Display device

Abstract

One embodiment of the present invention provides a display device comprising a display area and a non-display area outside the display area, the display device comprising: a plurality of pixels disposed in the display area, each including a transistor and a light emitting diode electrically connected to the transistor; connection wiring disposed in the display area and electrically connecting adjacent pixels from among the plurality of pixels; and peripheral wiring disposed in the non-display area, wherein the modulus of a conductive layer included in the transistor is greater than the modulus of the connection wiring, and the modulus of the connection wiring is greater than the modulus of the peripheral wiring.

Description

display device

[0001] Embodiments of the present invention relate to a display device, for example, a flexible display device.

[0002] As display devices that visually display electrical signals evolve, a variety of display devices with superior characteristics, such as thinness, lightness, and low power consumption, are being introduced. For example, flexible display devices that can be folded or rolled are being introduced. Recently, active research and development is underway on stretchable display devices capable of transforming into various forms.

[0003] Embodiments of the present invention seek to provide a display device that simultaneously (e.g., simultaneously) possesses high mechanical stability and excellent stretchability. However, these tasks are exemplary and do not limit the scope of the present invention.

[0004] One embodiment of the present invention provides a display device including a display area and a non-display area outside the display area, the display device including: a plurality of pixels each including a transistor and a light-emitting diode electrically connected to the transistor, the pixels being arranged in the display area; a connecting wire being arranged in the display area, the connecting wire electrically connecting adjacent pixels among the plurality of pixels; and a peripheral wire being arranged in the non-display area; wherein a modulus of a conductive layer included in the transistor is greater than a modulus of the connecting wire, and a modulus of the connecting wire is greater than a modulus of the peripheral wire.

[0005] In one embodiment, the conductive layer included in the transistor, the connecting wiring, and the peripheral wiring may each be made of different materials.

[0006] In one embodiment, the modulus of the conductive layer included in the transistor may be greater than 100 GPa and less than 1000 GPa.

[0007] In one embodiment, the conductive layer included in the transistor may include a metal thin film.

[0008] In one embodiment, the modulus of the connecting wire may be greater than 1 MPa and less than 100 MPa.

[0009] In one embodiment, the connecting wire may include a metal nanostructure and an elastic polymer.

[0010] In one embodiment, the metal nanostructure may include at least one of a silver nanoparticle, a silver nanoflake, and a silver nanowire.

[0011] In one embodiment, the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

[0012] In one embodiment, the connecting wire further comprises a carbon-based material, wherein the carbon-based material may comprise carbon nanotubes (CNTs), carbon fibers, graphene, and graphene oxide, or any combination thereof.

[0013] In one embodiment, the modulus of the peripheral wiring may be greater than 1 kPa and less than 100 kPa.

[0014] In one embodiment, the peripheral wiring may comprise liquid metal.

[0015] In one embodiment, the liquid metal may comprise a eutectic gallium-indium alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan).

[0016] In one embodiment, the conductive layer, the connecting wiring, and the peripheral wiring included in the transistor may each include a metal nanostructure and an elastic polymer.

[0017] In one embodiment, the concentration of the metal nanostructure in the conductive layer included in the transistor may be greater than the concentration of the metal nanostructure in the connecting wiring, and the concentration of the metal nanostructure in the connecting wiring may be greater than the concentration of the metal nanostructure in the peripheral wiring.

[0018] In one embodiment, the metal nanostructure may include at least one of a silver nanoparticle, a silver nanoflake, and a silver nanowire, and the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

[0019] In one embodiment, the connecting wiring includes a plurality of signal lines and a plurality of voltage lines, and the plurality of signal lines may include at least one of a data line, a light emission control line, a scan signal line, an initialization control line, and a bypass control line.

[0020] In one embodiment, the peripheral wiring may include at least one of a driving voltage supply wiring, a common voltage supply wiring, a fan-out wiring, a driving circuit input line, and a driving circuit output line.

[0021] In one embodiment, the device further includes a gate driving circuit included in the non-display area, and the modulus of the conductive layer included in the gate driving circuit may be smaller than the modulus of the connecting wire.

[0022] In one embodiment, the conductive layer included in the gate driving circuit may include a liquid metal.

[0023] Another embodiment of the present invention provides a display device including a display area and a non-display area outside the display area, the display device including: a plurality of pixels each including a transistor and a light-emitting diode electrically connected to the transistor, the pixels being arranged in the display area; a connecting wire disposed in the display area, the connecting wire electrically connecting adjacent pixels among the plurality of pixels; and a peripheral wire disposed in the non-display area; wherein a conductive layer included in the transistor includes a metal thin film, the connecting wire includes a metal nanostructure and an elastic polymer, and the peripheral wire includes a liquid metal.

[0024] In one embodiment, the modulus of the conductive layer included in the transistor may be greater than the modulus of the connecting wiring, and the modulus of the connecting wiring may be greater than the modulus of the peripheral wiring.

[0025] In one embodiment, the modulus of the conductive layer included in the transistor may have a value in the range of 100 GPa to 1000 GPa, the modulus of the connecting wiring may have a value in the range of 1 MPa to 100 MPa, and the modulus of the peripheral wiring may have a value in the range of 1 kPa to 100 kPa.

[0026] In one embodiment, the metal nanostructure may include at least one of a silver nanoparticle, a silver nanoflake, and a silver nanowire, and the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

[0027] In one embodiment, the liquid metal may comprise a eutectic gallium-indium alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan).

[0028] According to one embodiment of the present invention, a display device can be provided that prevents damage due to concentrated stress and can be stretched in various directions. The aforementioned effects are exemplary and should not be construed as limiting the scope of the present invention.

[0029] FIG. 1 is a perspective view schematically showing a display device according to one embodiment of the present invention.

[0030] FIG. 2a and FIG. 2b are perspective views showing the display device of FIG. 1 extended in the first direction.

[0031] Figure 2c is a perspective view showing the display device of Figure 1 extended in the second direction.

[0032] Figure 2d is a perspective view showing the display device of Figure 1 extended in the first direction and the second direction.

[0033] Figure 2e is a perspective view showing the display device of Figure 1 extended in the third direction.

[0034] Figure 3 is a schematic plan view of a display device according to one embodiment of the present invention.

[0035] FIG. 4A is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0036] FIG. 4b is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0037] FIG. 4c is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0038] FIG. 5 is a cross-sectional view schematically showing a main island portion and a main bridge portion arranged in a display area of ​​a display device according to one embodiment of the present invention.

[0039] FIGS. 6A to 6C are equivalent circuit diagrams of subpixels of a display device according to one embodiment of the present invention, respectively.

[0040] FIG. 7a and FIG. 7b are cross-sectional views schematically showing a light-emitting element of a display device according to one embodiment of the present invention, respectively.

[0041] Figure 8a is a schematic diagram of a display device according to one embodiment of the present invention.

[0042] FIG. 8b is a schematic diagram illustrating a gate driving circuit of a display device according to one embodiment of the present invention.

[0043] FIG. 9a is an enlarged plan view of the main island portion of a display device according to one embodiment of the present invention.

[0044] FIG. 9b is a plan view showing the arrangement of wiring on the main bridge section of a display device according to one embodiment of the present invention.

[0045] FIG. 9c is an enlarged plan view of the peripheral island portion and peripheral bridge portion of a display device according to one embodiment of the present invention.

[0046] Figure 10 shows a cross-section along line Ⅰ-Ⅰ' of Figure 9a, a cross-section along line Ⅱ-Ⅱ' of Figure 9b, and a cross-section along line Ⅲ-Ⅲ' of Figure 9c.

[0047] Fig. 11 is a cross-sectional view schematically showing a display device according to another embodiment of the present invention.

[0048] Fig. 12 is a schematic plan view of a display device according to another embodiment of the present invention.

[0049] FIGS. 13A to 13G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention, respectively.

[0050] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0052] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0053] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0054] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0055] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0056] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0057] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0058] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. In addition, “at least one of A or B” refers to the case where it is A, or B, or both A and B.

[0059] In the following examples, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0060] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0061] Based on the disclosure throughout this specification, those skilled in the art will appreciate that each suitable feature of the various embodiments of this specification may be partially or fully combined or inter-connected with one another, and may be technically interconnected and operated in various suitable ways. Furthermore, unless explicitly stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0062] Fig. 1 is a perspective view schematically illustrating a display device (1) according to one embodiment of the present invention. Figs. 2a and 2b are perspective views illustrating the display device (1) of Fig. 1 in a state extended in a first direction. Fig. 2c is a perspective view illustrating the display device (1) of Fig. 1 in a state extended in a second direction. Fig. 2d is a perspective view illustrating the display device of Fig. 1 in a state extended in the first and second directions. Fig. 2e is a perspective view illustrating the display device (1) of Fig. 1 in a state extended in a third direction.

[0063] Referring to FIG. 1, a display device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display device (1) may provide a predetermined image using light emitted from the plurality of pixels. The non-display area (NDA) may be arranged outside the display area (DA). The non-display area (NDA) may entirely surround the display area (DA).

[0064] The display device (1) can be extended or contracted in various directions. The display device (1) can be extended in a first direction (e.g., the x direction and / or the -x direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIGS. 2A and 2B, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be extended in the first direction (e.g., the x direction and / or the -x direction). For example, as illustrated in FIG. 2A, the display device (1) can be extended along the x direction and the -x direction, or as illustrated in FIG. 2B, one side of the display device (1) can be fixed and the display device (1) can be extended along the x direction.

[0065] The display device (1) can be stretched in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIG. 2 c, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be stretched in the y direction and the -y direction. In another embodiment, one side of the display device (1) can be fixed while being stretched in the y direction or the -y direction.

[0066] The display device (1) can be stretched in a plurality of directions, for example, a first direction (e.g., the x direction and / or the -x direction) and a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a part of a human body. As illustrated in Fig. 2d, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be stretched in the ±x direction and the ±y direction.

[0067] The display device (1) can be stretched in a third direction (e.g., in the z direction or the -z direction) (e.g., in the thickness direction of the display device (1)) by an external force applied by an external object or a part of a human body. In one embodiment, FIG. 2e illustrates that a part of the display device (1), for example, a part of the display area (DA), protrudes in the z direction. In another embodiment, a part of the display device (1), for example, a part of the display area (DA), can protrude along the z direction (or be sunken along the -z direction).

[0068] Although FIGS. 2A to 2E illustrate that the display device (1) is elongated in a first direction (e.g., the x direction and / or the -x direction), a second direction (e.g., the y direction and / or the -y direction) and / or a third direction (e.g., the z direction or the -z direction), the present invention is not limited thereto. In another embodiment, the display device (1) may be variously deformed into an irregular shape, such as being bent or twisted along two or more axes.

[0069] Figure 3 is a plan view schematically showing a display device (1) according to one embodiment of the present invention.

[0070] Referring to Fig. 3, various components forming a display device (1) are arranged on a substrate (100). The substrate (100) may include a display area (DA) and a non-display area (NDA) surrounding the edge or periphery of the display area (DA). The display area (DA) may be covered with a sealing member to protect it from external air or moisture.

[0071] Subpixels (P) are arranged in the display area (DA) of the substrate (100). Each subpixel (P) can display an image using light emitted from a light-emitting element such as a light-emitting diode. Each light-emitting diode can emit red, green, or blue light, for example.

[0072] Each light emitting diode may be electrically connected to a subpixel circuit, and each subpixel circuit may include transistors and a storage capacitor. Each of the subpixel circuits may be electrically connected to peripheral circuits arranged in a non-display area (NDA). The peripheral circuits arranged in the non-display area (NDA) may include a gate driving circuit (GDC), a terminal portion (PAD), and peripheral wiring (PW). The peripheral wiring (PW) may include a driving voltage supply wiring (W11), a common voltage supply wiring (W13), and a fan-out wiring (FW).

[0073] The gate driving circuit (GDC) may include drivers for providing electrical signals to the gate electrodes of each of the transistors electrically connected to the light-emitting elements. Specifically, the gate driving circuit (GDC) may apply a scan signal to each of the sub-pixel circuits corresponding to the sub-pixels (P) through a gate line (GL). In addition, the gate driving circuit (GDC) may apply an emission control signal to each of the sub-pixel circuits through an emission control line (EML). At this time, the gate line (GL) may include a scan signal line (GWL), an initialization control line (GIL), and a bypass control line (GBL) which will be described later with reference to FIGS. 6B and 6C.

[0074] The gate driving circuit (GDC) may include a first gate driving circuit (GDC1) and a second gate driving circuit (GDC2) arranged on both sides of the display device (1) with the display area (DA) interposed therebetween. The second gate driving circuit (GDC2) may be positioned on the opposite side of the first gate driving circuit (GDC1) with the display area (DA) as the center, and may be approximately parallel to the first gate driving circuit (GDC1). Some of the subpixel circuits may be electrically connected to the first gate driving circuit (GDC1), and the rest may be electrically connected to the second gate driving circuit (GDC2). In some embodiments, the second gate driving circuit (GDC2) may be omitted.

[0075] A terminal portion (PAD) may be placed on one side of the substrate (100). The terminal portion (PAD) is exposed and not covered by an insulating layer and is connected to a display circuit board (30). A display driver (32) may be placed on the display circuit board (30).

[0076] The display driver (32) can generate a control signal to be transmitted to the first gate driver circuit (GDC1) and the second gate driver circuit (GDC2). The display driver (32) generates a data signal, and the generated data signal can be transmitted to the subpixel circuits of the subpixels (P) through the fan-out wiring (FW) and the data line (DL) connected to the fan-out wiring (FW).

[0077] The display driver (32) can supply a first power voltage (VDD, FIGS. 6A to 6C) to the driving voltage supply wire (W11) and can supply a first power voltage (VSS, FIGS. 6A to 6C) to the common voltage supply wire (W13). The first power voltage (VDD) is applied to a subpixel circuit of a subpixel (P) through a driving voltage line (PL) connected to the driving voltage supply wire (W11), and the second power voltage (VSS) can be applied to the opposite electrode of the light emitting element by being connected to the common voltage supply wire (W13).

[0078] The driving voltage supply wiring (W11) may be provided to extend along the x-direction from the lower side of the display area (DA). The common voltage supply wiring (W13) may have a loop shape with one side open, so as to partially surround the display area (DA).

[0079] FIG. 4A is an enlarged plan view of part A of FIG. 3 as part of a display device (1) according to one embodiment of the present invention.

[0080] The display device (1) may include main island portions (11) spaced apart from each other along a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a display area (DA), and main bridge portions (12) connecting adjacent main island portions (11).

[0081] Each main island unit (11) may be connected to a plurality of main bridge units (12). For example, each main island unit (11) may be connected to four main bridge units (12). Two main bridge units (12) may be arranged on both sides of the main island unit (11) along a first direction (e.g., x direction or -x direction), and the remaining two main bridge units (12) may be arranged on both sides of the main island unit (11) along a second direction (e.g., y direction or -y direction). In one embodiment, four main bridge units (12) may be connected to four sides of the main island unit (11), respectively. Each of the four main bridge units (12) may be adjacent to each corner of the main island unit (11).

[0082] The main bridge parts (12) can be spaced apart from each other by first openings (CS1) located between the main bridge parts (12). In one embodiment, the first openings (CS1) having an approximately H shape and the first openings (CS1) having an approximately I shape obtained by rotating the aforementioned H shape by 90 degrees can be alternately and repeatedly arranged along a first direction (e.g., an x-direction or a -x-direction) and a second direction (e.g., a y-direction or a -y-direction), respectively. Both ends of each main bridge part (12) are connected to each of the adjacent main island parts (11), and one side of each main bridge part (12) can be spaced apart from one side of the adjacent main island part (11) and / or one side of another main bridge part (12) by the first openings (CS1).

[0083] The display device (1) may include peripheral island portions (21) spaced apart from each other in a non-display area (NDA) and peripheral bridge portions (22) connecting adjacent peripheral island portions (21).

[0084] Each peripheral island portion (21) may extend along a first direction (e.g., x-direction or -x-direction). The peripheral island portions (21) may be spaced apart from each other along a second direction (e.g., y-direction or -y-direction) intersecting the first direction (e.g., x-direction or -x-direction). Each peripheral island portion (21) may include drivers of the gate driving circuit (GDC) described with reference to FIG. 3.

[0085] The peripheral bridge portion (22) may have a serpentine shape. The length of the peripheral bridge portion (22) may be greater than the shortest distance between adjacent peripheral island portions (21) along the second direction (e.g., the y direction or the -y direction). In one embodiment, the peripheral bridge portion (22) may have a shape of approximately omega (Ω) that is convex toward the first direction (e.g., the x direction or the -x direction). The peripheral bridge portions (22) may be arranged between adjacent peripheral island portions (21), but may be spaced apart from each other.

[0086] The peripheral bridge portions (22) between adjacent peripheral island portions (21) can be spaced apart from each other by the second opening portion (CS2). Between the adjacent peripheral island portions (21), the second opening portions (CS2) and the peripheral bridge portions (22) can be alternately arranged along a first direction (e.g., the x-direction or the -x-direction). The second opening portions (CS2) can have the same shape. Both ends of each peripheral bridge portion (22) are connected to the adjacent peripheral island portions (21), but one side of each peripheral bridge portion (22) can be spaced apart from one side of the adjacent peripheral island portion (21) and / or one side of another peripheral bridge portion (22) by the second opening portion (CS2).

[0087] Any one peripheral island (21) arranged in the non-display area (NDA) can correspond to the main islands (11) of a plurality of rows arranged in the display area (DA). For example, any one peripheral island (21) arranged in the non-display area (NDA) can correspond to the main islands (11) arranged in the (i)-th row and the main islands (11) arranged in the (i+1)-th row in the display area (DA) (wherein, i is a positive integer greater than 0). Although Fig. 4a illustrates that one peripheral island (21) corresponds to two rows of the main islands (11), the present invention is not limited thereto. In another embodiment, any one peripheral island (21) arranged in the non-display area (NDA) can correspond to n rows of the main islands (11) arranged in the display area (DA) (wherein, n is a positive integer greater than or equal to 3).

[0088] The non-display area (NDA) may include a first sub-non-display area (SNDA1) in which the aforementioned peripheral island portions (21) and peripheral bridge portions (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). Sub-bridge portions (23) may be arranged in the second sub-non-display area (SNDA2) to connect the display area (DA) and the first sub-non-display area (SNDA1). One end of the sub-bridge portion (23) may be connected to the peripheral island portion (21) and / or the peripheral bridge portion (22), and the other end of the sub-bridge portion (23) may be connected to the main island portion (11) and / or the main bridge portion (12).

[0089] The sub-bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the sub-bridge portion (23) may be different from the shapes of the main bridge portion (12) and the peripheral bridge portions (22). In one embodiment, as illustrated in FIG. 4A, the sub-bridge portion (23) may have a shape of approximately omega (Ω) that is convex in the second direction (e.g., the y direction or the -y direction). One of the adjacent sub-bridge portions (23) arranged along the second direction (e.g., the y direction or the -y direction) may have a structure that is symmetrical to each other, such as one being convex in the y direction and the other being convex in the -y direction. Between the sub-bridge portions (23), a third opening (CS3) and a fourth opening (CS4) of different shapes may have a structure in which they are repeated. The width of the sub-bridge section (23) may be different from the width of the main bridge section (12) and the width of the peripheral bridge section (22). In one embodiment, the width of the sub-bridge section (23) may be larger than the width of the main bridge section (12) and smaller than the width of the peripheral bridge section (22).

[0090] FIG. 4a shows that the peripheral island portion (21) and the peripheral bridge portion (22) of the non-display area (NDA) have different shapes from the main island portion (11) and the main bridge portion (12) of the display area (DA), respectively. In another embodiment of the present invention, the peripheral island portion (21) and the peripheral bridge portion (22) of the non-display area (NDA) may have the same shapes as the main island portion (11) and the main bridge portion (12) of the display area (DA), respectively.

[0091] FIG. 4b is an enlarged plan view of part A of FIG. 3 as part of a display device (1) according to one embodiment of the present invention.

[0092] Referring to Fig. 4b, the display device (1) includes main island portions (11) spaced apart from each other in the display area (DA) and main bridge portions (12) connecting adjacent main island portions (11) spaced apart from each other by a first opening (CS1). The structure of the display area (DA) of Fig. 4b may be the same as the structure of the display area (DA) described above with reference to Fig. 4a.

[0093] The display device (1) may include peripheral islands (21) and peripheral bridges (22) arranged in a non-display area (NDA). In one embodiment, the peripheral islands (21) and peripheral bridges (22) may have substantially the same shape as the main islands (11) and main bridges (12), respectively.

[0094] The peripheral island portions (21) can be spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a non-display area (NDA). Each of the peripheral bridge portions (22) can connect adjacent peripheral island portions (21). The peripheral bridge portions (22) can be spaced apart from each other by a second opening (CS2) located between the peripheral bridge portions (22).

[0095] The second opening (CS2) may have substantially the same shape as the first opening (CS1). For example, the second opening (CS2) having an approximately H shape and the second opening (CS2) having an approximately I shape may be alternately and repeatedly arranged in a non-display area, for example, a non-display area (NDA). The two ends of each peripheral bridge portion (22) are connected to each of the adjacent peripheral island portions (21), and one side of each peripheral bridge portion (22) may be spaced apart from one side of the adjacent peripheral island portion (21) and / or one side of another peripheral bridge portion (22) by the second opening (CS2).

[0096] Each peripheral island section (21) can be connected to four peripheral bridge sections (22). Each peripheral island section (21) can include drivers of the gate drive circuit (GDC) described with reference to FIG. 3.

[0097] The peripheral islands (21) of any one row arranged in the non-display area (NDA) may correspond to the main islands (11) of any one row arranged in the display area (DA). For example, the peripheral islands (21) arranged in the (i)th row along the first direction (e.g., the x-direction or the -x-direction) in the non-display area (NDA) may correspond to the main islands (11) arranged in the same row, e.g., the (i)th row, in the display area (DA) (wherein, i is a positive number greater than 0).

[0098] The display device (1) may include sub-bridge units (23) arranged in a second sub-non-display area (SNDA2) for connecting a display area (DA) and a first sub-non-display area (SNDA1). The non-display area (NDA) may include a first sub-non-display area (SNDA1) in which peripheral island units (21) and peripheral bridge units (22) are arranged, and a second sub-non-display area (SNDA2) including sub-bridge units (23) and positioned between the first sub-non-display area (SNDA1) and the display area (DA). The sub-bridge unit (23) may be substantially the same as the main bridge unit (12) and the peripheral bridge unit (22). For example, the width of the sub-bridge unit (23) may be the same as the width of the main bridge unit (12) and the width of the peripheral bridge unit (22).

[0099] FIG. 4c is an enlarged plan view of part A of FIG. 3 as part of a display device (1) according to one embodiment of the present invention.

[0100] Referring to FIG. 4c, the display device (1) may include main island portions (11) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in the display area (DA) and main bridge portions (12) connecting adjacent main island portions (11).

[0101] The main bridge parts (12) may be arranged to be spaced apart from each other by a first opening (CS1) located between the main bridge parts (12). The main bridge parts (12) may have a winding shape. For example, as illustrated in Fig. 4c, the main bridge parts (12) may have a shape roughly similar to the letter 'S'.

[0102] Each main island unit (11) may be connected to a plurality of main bridge units (12). For example, each main island unit (11) may be connected to four main bridge units (12). Two main bridge units (12) may be arranged on both sides of the main island unit (11) along a first direction (e.g., x direction or -x direction), and the remaining two main bridge units (12) may be arranged on both sides of the main island unit (11) along a second direction (e.g., y direction or -y direction). The four main bridge units (12) may be connected to each of the four sides of the main island unit (11). Each of the four main bridge units (12) may be adjacent to each corner of the main island unit (11).

[0103] The display device (1) may include peripheral island portions (21) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a non-display area (NDA) as shown in FIG. 4c, and peripheral bridge portions (22) connecting adjacent peripheral island portions (21).

[0104] The peripheral bridge portions (22) may be spaced apart from each other by a second opening (CS2) located between the peripheral bridge portions (22). The peripheral bridge portions (22) may have a winding shape. For example, as illustrated in FIG. 4C, the peripheral bridge portions (22) may have approximately the shape of the letter 'S'. The size and / or width of the peripheral bridge portions (22) may be different from the size and / or width of the main bridge portion (12). For example, the size and / or width of the peripheral bridge portions (22) may be larger than the size and / or width of the main bridge portion (12). The radius of curvature of the rounded portion of the peripheral bridge portions (22) may be different from the radius of curvature of the rounded portion of the main bridge portion (12). For example, the radius of curvature of the rounded portion of the peripheral bridge portion (22) may be larger than the radius of curvature of the rounded portion of the main bridge portion (12).

[0105] Each peripheral island portion (21) can be connected to a plurality of peripheral bridge portions (22). Each peripheral island portion (21) can be connected to four peripheral bridge portions (22). Two peripheral bridge portions (22) can be arranged on both sides of the peripheral island portion (21) along a first direction (e.g., x direction or -x direction), and the remaining two peripheral bridge portions (22) can be arranged on both sides of the peripheral island portion (21) along a second direction (e.g., y direction or -y direction). In one embodiment, the four peripheral bridge portions (22) can be respectively connected to the four sides of the peripheral island portion (21). Each peripheral bridge portion (22) can be connected to the central portion of each side of the peripheral island portion (21).

[0106] The peripheral islands (21) of a row arranged in the non-display area (NDA) may correspond to the main islands (11) of a plurality of rows arranged in the display area (DA). For example, the peripheral islands (21) of a row arranged in the non-display area (NDA) may correspond to the main islands (11) arranged in the (i)-th row of the display area (DA) and the main islands (11) arranged in the (i+1)-th row (wherein, i is a positive integer greater than 0). In another embodiment, the peripheral islands (21) of a row may correspond to n rows of the main islands (11) (wherein, n is a positive integer greater than 3).

[0107] The non-display area (NDA) may include a first sub-non-display area (SNDA1) in which the aforementioned peripheral islands (21) and peripheral bridges (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). Sub-bridges (23) for connecting the display area (DA) and the first sub-non-display area (SNDA1) may be arranged in the second sub-non-display area (SNDA2). One end of the sub-bridge (23) may be connected to the peripheral island (21), and the other end of the sub-bridge (23) may be connected to the main island (11). For example, one end of the sub-bridge (23) may be connected to a central portion of one side of the peripheral island (21), and the other end of the sub-bridge (23) may be connected to a central portion of one side of the main island (11).

[0108] The sub-bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the sub-bridge portion (23) may be different from the shapes of the main bridge portion (12) and the peripheral bridge portions (22). The width of the sub-bridge portion (23) may be different from the width of the main bridge portion (12) and the width of the peripheral bridge portions (22). The width of the sub-bridge portion (23) may be larger than the width of the main bridge portion (12) and smaller than the width of the peripheral bridge portions (22). Third openings (CS3) and fourth openings (CS4) of different shapes may be alternately arranged between the sub-bridge portions (23) in the second direction (e.g., the y direction or the -y direction).

[0109] FIG. 5 is a cross-sectional view schematically showing a main island portion and a main bridge portion arranged in a display area of ​​a display device according to one embodiment of the present invention.

[0110] Referring to Fig. 5, the main island portion (11) and the main bridge portion (12) arranged in the display area (DA) may be spaced apart from each other with a first opening (CS1) therebetween. The main island portion (11) includes light-emitting elements (LEDs) and a circuit for driving the light-emitting elements (LEDs) electrically connected thereto, for example, a pixel driving circuit portion (PC), and the main bridge portion (12) may include a connection wire (WL) electrically connected to the pixel driving circuit portions (PC) arranged in each of the adjacent main island portions (11).

[0111] Looking at the main island portion (11), a buffer layer (111) including an inorganic insulator is disposed on a substrate (100), and a pixel driver circuit (PC) may be disposed on the buffer layer (111). An insulating layer (ISL) including an inorganic insulator and / or an organic insulator may be disposed between the pixel driver circuit (PC) and the light emitting element (LED). The light emitting element (LED) is disposed on the insulating layer (ISL) and may be electrically connected to a corresponding pixel driver circuit (PC). The light emitting elements (LED) may emit light of different colors or the same color. In one embodiment, the light emitting elements (LED) may emit red, green, and blue light, respectively. In some embodiments, the light emitting elements (LED) may emit white light. In another embodiment, the light emitting elements (LED) may emit red, green, blue, and white light, respectively.

[0112] The substrate (100) may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In one embodiment, the substrate (100) may be a single layer including the aforementioned polymer resin. In another embodiment, the substrate (100) may be a multilayer structure including a base layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material. The substrate (100) including the polymer resin may have flexible, rollable, and bendable properties.

[0113] In one embodiment, FIG. 5 illustrates three pixel driver circuits (PCs) arranged in each main island unit (11) and three light-emitting elements (LEDs) connected to each pixel driver circuit unit (PC), but the present invention is not limited thereto. In another embodiment, the number of pixel driver circuits (PCs) and light-emitting elements (LEDs) arranged in the main island unit (11) may be one, two, four or more.

[0114] The encapsulation layer (300) may be disposed on a light-emitting element (LED) and may protect the light-emitting element (LED) from external force and / or moisture permeation. The encapsulation layer (300) may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer (300) may include a structure in which an inorganic encapsulation layer including an inorganic insulating material, an organic encapsulation layer including an organic insulating material, and an inorganic encapsulation layer including an inorganic insulating material are laminated. In other embodiments, the encapsulation layer (300) may include an organic material such as a resin. In some embodiments, the encapsulation layer (300) may include urethane epoxy acrylate. The encapsulation layer (300) may include a photosensitive material, for example, a material such as a photoresist.

[0115] Looking at the main bridge portion (12), an insulating layer (ISL) including an organic insulating material may be placed on the substrate (100). When the display device (1) is extended, the main bridge portion (12), which is subject to relatively large deformation, may not have a layer including an inorganic insulating material that is prone to cracking, unlike the main island portion (11).

[0116] In one embodiment, the substrate (100) corresponding to the main bridge portion (12) may have the same laminated structure as the substrate (100) corresponding to the main island portion (11). In one embodiment, the substrate (100) corresponding to the main bridge portion (12) and the substrate (100) corresponding to the main island portion (11) may be polymer resin layers formed together in the same process. In another embodiment, the substrate (100) corresponding to the main bridge portion (12) may have a different laminated structure from the substrate (100) corresponding to the main island portion (11). In some embodiments, the substrate (100) corresponding to the main island portion (11) may have a multilayer structure including a base layer including a polymer resin and a barrier layer including an inorganic insulating material, and the substrate (100) corresponding to the main bridge portion (12) may have a structure of a polymer resin layer without a layer including an inorganic insulating material.

[0117] As described above, the connection wires (WL) of the main bridge unit (12) may be signal lines (e.g., gate lines, data lines, etc.) for providing electrical signals to transistors included in the pixel driving circuit unit (PC) of the main island unit (11) or voltage lines (e.g., driving voltage lines, initialization voltage lines, etc.) for providing voltage. An encapsulation layer (300) may also be arranged in the main bridge unit (12). In another embodiment, the encapsulation layer (300) may not exist in the main bridge unit (12).

[0118] Referring to FIGS. 4A to 4C and FIG. 5, the substrate (100) corresponding to the main island portion (11) and the substrate (100) corresponding to the main bridge portion (12) may be connected to each other. In other words, the plan views illustrated in FIGS. 4A to 4C may be substantially the same as the plan view of the substrate (100) of FIG. 5. In other words, the substrate (100) may include an area corresponding to the main island portion (11), an area corresponding to the main bridge portion (12), and an opening (100OP1) having the same shape as the first opening (CS1).

[0119] Similarly, the sealing layer (300) corresponding to the main island portion (11) and the sealing layer (300) corresponding to the main bridge portion (12) may be connected to each other. For example, the plan views illustrated in FIGS. 4A to 4C above may be substantially identical to the plan views of the sealing layer (300). In other words, the sealing layer (300) may include an area corresponding to the main island portion (11), an area corresponding to the main bridge portion (12), and an opening (300OP1) having the same shape as the first opening (CS1).

[0120] The circuit-light-emitting element layer (200) between the substrate (100) and the encapsulation layer (300) may include a buffer layer (111), a pixel driver circuit (PC), a connection wire (WL), an insulating layer (ISL), and a light-emitting element (LED). Similar to the substrate (100), the plan views illustrated in FIGS. 4A to 4C may be substantially the same as the plan views of the circuit-light-emitting element layer (200). In other words, the circuit-light-emitting element layer (200) may include an opening (200OP1) having the same shape as the first opening (CS1).

[0121] Figures 6a to 6c are equivalent circuit diagrams of subpixels of a display device (1) according to one embodiment of the present invention, respectively.

[0122] Referring to FIG. 6a, a light emitting element (LED) corresponding to a subpixel is electrically connected to a pixel driver circuit (PC), and the pixel driver circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel driver circuit (PC) may be electrically connected to a signal line and a voltage line. The signal line may include a gate line (GL, FIG. 3), such as a scan signal line (GWL), and a data line (DL), and the voltage line may include a first voltage line (VDDL). At this time, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 3), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 3).

[0123] The second transistor (T2) can be electrically connected to a scan signal line (GWL) and a data line (DL). The scan signal line (GWL) can provide a scan signal (GW) to a gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from a data line (DL) to the first transistor (T1) according to a scan signal (GW) input from the scan signal line (GWL).

[0124] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power supply voltage (VDD) supplied by the first voltage line (VDDL).

[0125] A first transistor (T1) is a driving transistor and can control a driving current flowing through a light-emitting element (LED). One electrode of the first transistor (T1) can be connected to a first voltage line (VDDL) and a storage capacitor (Cst). The other electrode of the first transistor (T1) can be connected to a light-emitting element (LED). The first transistor (T1) can control a driving current flowing through the light-emitting element (LED) from the first voltage line (VDDL) in response to a voltage value stored in the storage capacitor (Cst). The light-emitting element (LED) can emit light having a predetermined brightness by the driving current. A first electrode of the light-emitting element (LED) can be electrically connected to the first transistor (T1), and a second electrode can be electrically connected to a second voltage line (VSSL) that supplies a second power voltage (VSS).

[0126] Although FIG. 6a illustrates that the pixel driver circuit (PC) includes two transistors and one storage capacitor, in other embodiments, the pixel driver circuit (PC) may include three or more transistors.

[0127] Referring to FIG. 6b, the pixel driving circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0128] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include a gate line (GL, FIG. 3), such as a scan signal line (GWL), a bypass control line (GBL), an initialization control line (GIL), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a first voltage line (VDDL), and a second voltage line (VSSL). At this time, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 3), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 3).

[0129] The first voltage line (VDDL) can transmit the first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit the first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit the second initialization voltage (Vaint) that initializes the first electrode of the light-emitting element (LED) to the pixel driver circuit (PC).

[0130] The first transistor (T1) may be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and may be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and receives a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0131] The second transistor (T2) is a data write transistor and is electrically connected to the scan signal line (GWL) and the data line (DL). The second transistor (T2) can be connected between the data line (DL) and a first node (N1) connected to one electrode of the first transistor (1). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0132] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light emitting element (LED) via the sixth transistor (T6). The third transistor (T3) can be connected between the gate electrode of the first transistor (T1) and another electrode. The third transistor (T3) can be turned on according to the scan signal (GW) received through the scan signal line (GWL) to diode-connect the first transistor (T1).

[0133] The fourth transistor (T4) is a first initialization transistor and is electrically connected to an initialization control line (GIL) and a first initialization voltage line (VIL1). The fourth transistor (T4) may be connected between the gate electrode of the first transistor (T1) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to an initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel driving circuit unit arranged in a previous row of the corresponding pixel driving circuit unit (PC).

[0134] The fifth transistor (T5) may be a motion control transistor, and the sixth transistor (T6) may be a light-emitting control transistor. The fifth transistor (T5) and the sixth transistor (T6) have their respective gate electrodes electrically connected to the light-emitting control line (EML), and are simultaneously turned on in response to the light-emitting control signal (EM) received through the light-emitting control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting element (LED).

[0135] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to a bypass control line (GBL), a second initialization voltage line (VIL2), and a sixth transistor (T6), or a first electrode of a light-emitting element (LED). The seventh transistor (T7) is turned on according to a bypass control signal (GB) received through the bypass control line (GBL), and can transmit a second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0136] A storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain a voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to a difference between the voltages across the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0137] Referring to FIG. 6c, the pixel driving circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0138] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a scan signal line (GWL), a bypass control line (GBL), an initialization control line (GIL), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a sustain voltage line (VSL), a first voltage line (VDDL), and a second voltage line (VSSL). At this time, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 3), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 3).

[0139] The first voltage line (VDDL) can transmit a first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) for initializing the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) for initializing the first electrode of the light emitting element (LED) to the pixel driver circuit (PC). The sustain voltage line (VSL) can provide a sustain voltage (VSUS) to the second node (N2) (e.g., the second electrode (CE2) of the storage capacitor (Cst)) and the auxiliary capacitor (Ca) during the initialization period and the data writing period.

[0140] A first transistor (T1) may be connected between a first electrode (N1) and a sixth transistor (T6). The first transistor (T1) may be electrically connected to a first voltage line (VDDL) via a fifth transistor (T5) and an eighth transistor (T8), and may be electrically connected to a light-emitting element (LED) via a sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and may receive a data signal (Dm) according to a switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0141] The second transistor (T2) can be connected between the data line (DL) and the first node (N1). The second transistor (T2) is electrically connected to the scan signal line (GWL) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0142] The third transistor (T3) can be connected between the gate electrode of the first transistor (T1) and another electrode, which is connected to the sixth transistor (T6). The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) to diode-connect the first transistor (T1), thereby compensating for the threshold voltage of the first transistor (T1).

[0143] The fourth transistor (T4) may be connected between the gate electrode of the first transistor (T1) and the first initialization voltage line (VIL1). The fourth transistor (T4) is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1), and is turned on according to the initialization control signal (GI) transmitted through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel driving circuit unit arranged in a previous row of the corresponding pixel driving circuit unit (PC).

[0144] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the light emission control line (EML), and are simultaneously turned on in response to the light emission control signal (EM) transmitted through the light emission control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) in the direction of the light emitting element (LED).

[0145] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to a bypass control line (GBL), a second initialization voltage line (VIL2), and a sixth transistor (T6). The seventh transistor (T7) is turned on according to a bypass control signal (GB) received through the bypass control line (GBL) to transmit a second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light emitting element (LED) to initialize the first electrode of the light emitting element (LED).

[0146] The ninth transistor (T9) can be electrically connected to the second electrode (CE2) of the storage capacitor (Cst) and the holding voltage line (VSL) through the bypass control line (GBL), the second node (N2). The ninth transistor (T9) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can transmit the holding voltage (VSUS) to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst), during the initialization section and the data writing section.

[0147] The eighth transistor (T8) and the ninth transistor (T9) may be electrically connected to a second node (N2), for example, a second electrode (CE2) of a storage capacitor (Cst), respectively. In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on in the initialization period and the data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off in the light emitting period. Since the sustain voltage (VSUS) is transmitted to the second node (N2) in the initialization period and the data writing period, the uniformity of the luminance (e.g., LRU, Long Range Uniformity) of the display device according to the voltage drop of the first voltage line (VDDL) may be improved.

[0148] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the ninth transistor (T9) via the eighth transistor (T8) and the second node (N2).

[0149] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSL), and the first electrode of the light-emitting element (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to a voltage difference between the first electrode of the light-emitting element (LED) and the sustain voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, thereby reducing or preventing the problem of black luminance increasing when the sixth transistor (T6) is turned off.

[0150] FIG. 7a is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0151] Referring to FIG. 7A, a light-emitting element according to one embodiment of the present invention may include an organic light-emitting diode (220) including an organic material. The organic light-emitting diode (220) may include a first electrode (221) disposed on an insulating layer, a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) interposed between the first electrode (221) and the second electrode (225). A first functional layer (222) may be disposed between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be disposed between the light-emitting layer (223) and the second electrode (225).

[0152] The edge of the first electrode (221) may be covered with a bank layer (BKL) including an insulating material. The bank layer (BKL) may include an opening (B-OP) overlapping the central portion of the first electrode (221).

[0153] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode (221) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer.

[0154] The light-emitting layer (223) may include a polymer or low-molecular organic material that emits light of a predetermined color. The first functional layer (222) may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer (224) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0155] The second electrode (225) may be formed of a conductive material having a low work function. For example, the second electrode (225) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0156] FIG. 7b is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0157] Referring to FIG. 7B, in one embodiment of the present invention, a light-emitting element may include an inorganic light-emitting diode (230) including an inorganic material. The inorganic light-emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the inorganic light-emitting diode (230) may be electrically connected to a first electrode pad (241) and a second electrode pad (242), respectively, which are disposed on the same layer.

[0158] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.

[0159] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with an n-type dopant such as Si, Ge, or Sn.

[0160] The intermediate layer (233) is a region where electrons and holes recombine, and as the electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) may be formed by including, for example, a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and may be formed as a single quantum well structure or a multi-quantum well structure (MQW: Multi Quantum Well). In addition, the intermediate layer (223) may also include a quantum wire structure or a quantum dot structure.

[0161] Although Fig. 7b illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0162] Figure 8a is a schematic diagram of a display device according to one embodiment of the present invention.

[0163] Referring to FIG. 8A, a display area (DA) may include a plurality of subpixels (P) and signal lines capable of applying electrical signals to the plurality of subpixels (P). The signal lines capable of applying electrical signals to each of the subpixels (P) may include a plurality of data lines (DL), a plurality of emission control lines (EML), a plurality of scan signal lines (GWL), a plurality of initialization control lines (GIL), and a plurality of bypass control lines (GBL).

[0164] A driving circuit (DC) for supplying a signal to drive subpixels (P) may be positioned outside a display area (DA). The driving circuit (DC) may include a data driving circuit (DDC) and a gate driving circuit (GDC, FIG. 3), and the gate driving circuit (GDC, FIG. 3) may include an emission control driving circuit (EMDC), a bypass driving circuit (GBDC), an initialization driving circuit (GIDC), and a data write driving circuit (GWDC). The data driving circuit (DDC) may be positioned adjacent to a lower side of the display area (DA), connected to data lines (DL), and output a data signal (Dm) to the data lines (DL).

[0165] An emission control driving circuit (EMDC), a bypass driving circuit (GBDC), an initialization driving circuit (GIDC), and a data write driving circuit (GWDC) may be arranged adjacent to a left side or a right side of a display area (DA). The emission control driving circuit (EMDC) is connected to emission control lines (EML) and can output an emission control signal (EM) to the emission control lines (EML). The bypass driving circuit (GBDC) is connected to bypass control lines (GBL) and can output a bypass control signal (GB) to the bypass control lines (GBL). The initialization driving circuit (GIDC) is connected to initialization control lines (GIL) and can output an initialization control signal (GI) to the initialization control lines (GIL). The data write driving circuit (GWDC) is connected to scan signal lines (GWL) and can output a scan signal (GW).

[0166] Fig. 8b is a schematic diagram of a gate driving circuit according to one embodiment of the present invention. Fig. 8b is a diagram schematically showing the configuration of an emission control driving circuit (EMDC), a bypass driving circuit (GBDC), an initialization driving circuit (GIDC), and a data write driving circuit (GWDC).

[0167] Referring to FIG. 8b, the light emission control driving circuit (EMDC) can be implemented as a shift register including a plurality of light emission control stages (EMST1, EMST2, EMST3, ...). Each of the light emission control stages (EMST1, EMST2, EMST3, ...) can be a sub-driving circuit. Each of the light emission control stages (EMST1, EMST2, EMST3, ...) is connected to a corresponding light emission control line (EML) and can output a light emission control signal (EM) to the corresponding light emission control line (EML). The first light emission control stage (EMST1) outputs the light emission control signal (EM) in response to an external start signal (STV), and each of the remaining light emission control stages (EMST2, EMST3, ...) other than the first light emission control stage (EMST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the light emission control stages (EMST1, EMST2, EMST3, ...) can be connected to a plurality of input lines (IL) arranged outside the light emission control stages (EMST1, EMST2, EMST3, ...).

[0168] A bypass driving circuit (GBDC) can be implemented as a shift register including a plurality of bypass stages (GBST1, GBST2, GBST3, 쪋). Each of the bypass stages (GBST1, GBST2, GBST3, 쪋) can be a sub-driving circuit. Each of the bypass stages (GBST1, GBST2, GBST3, 쪋) is connected to a corresponding bypass control line (GBL) and can output a bypass control signal (GB) to the corresponding bypass control line (GBL). The first bypass stage (GBST1) outputs the bypass control signal (GB) in response to an external start signal (STV), and each of the remaining bypass stages (GBST1, GBST2, GBST3, 쪋) other than the first bypass stage (GBST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the bypass stages (GBST1, GBST2, GBST3, 쪋) can be connected to a plurality of input lines (IL) arranged outside the bypass stages (GBST1, GBST2, GBST3, 쪋).

[0169] An initialization driving circuit (GIDC) can be implemented as a shift register including a plurality of initialization stages (GIST1, GIST2, GIST3, ...). Each of the initialization stages (GIST1, GIST2, GIST3, ...) can be a sub-driving circuit. Each of the initialization stages (GIST1, GIST2, GIST3, ...) is connected to an initialization control line (GIL) and can output an initialization control signal (GI) to a corresponding initialization control line (GIL). The first initialization stage (GIST1) outputs the initialization control signal (GI) in response to an external start signal (STV), and each of the remaining stages (GIST2, GIST3, ...) other than the first initialization stage (GIST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the initialization stages (GIST1, GIST2, GIST3, ...) can be connected to a plurality of input lines (IL) arranged outside the initialization stages (GIST1, GIST2, GIST3, ...).

[0170] A data write drive circuit (GWDC) can be implemented as a shift register including a plurality of data write stages (GWST1, GWST2, GWST3, ...). Each of the data write stages (GWST1, GWST2, GWST3, ...) can be a sub-drive circuit. Each of the data write stages (GWST1, GWST2, GWST3, ...) is connected to a corresponding scan signal line (GWL) and can output a scan signal (GW) to the corresponding scan signal line (GWL). The first data write stage (GWST1) outputs the scan signal (GW) in response to an external start signal (STV), and each of the remaining data write stages (GWST2, GWST3, ...) other than the first data write stage (GWST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the data writing stages (GWST1, GWST2, GWST3, ...) can be connected to a plurality of input lines (IL) arranged outside the data writing stages (GWST1, GWST2, GWST3, ...).

[0171] The plurality of input lines (IL) may be signal lines including a plurality of voltage lines and a plurality of clock lines. In Fig. 8b, only one input line is illustrated for convenience of illustration. The plurality of input lines (IL) may include a gate high voltage line, a gate low voltage line, a start signal line, a first clock line, a second clock line, a carry line, and a reset signal line.

[0172] FIG. 9a is an enlarged plan view of the main island portion of a display device according to one embodiment of the present invention, and FIG. 9b is a plan view showing the arrangement of wiring on the main bridge portion of the display device according to one embodiment of the present invention. FIG. 9c is an enlarged plan view of the peripheral island portion and peripheral bridge portion of the display device according to one embodiment of the present invention.

[0173] Referring to Fig. 9a, the main island portion (11) arranged in the display area (DA) may include light-emitting elements and a pixel driver circuit portion (PC) electrically connected thereto. The pixel driver circuit portion (PC) may include transistors and at least one capacitor, as described above. Fig. 9a illustrates three pixel driver circuit portions (PC) arranged in the main island portion (11), but the present invention is not limited thereto. In another embodiment, the number of pixel driver circuit portions (PC) and light-emitting elements arranged in the main island portion (11) may be one, two, four or more.

[0174] Referring to FIG. 9b, the main bridge unit (12) may include a plurality of connection wires (WL) electrically connected to pixel driver circuit units (PC) arranged in each of the adjacent main island units (11). As described above, the connection wires (WL) may be signal lines for providing electrical signals to transistors included in the pixel driver circuit units (PC) of the main island unit (11) or voltage lines for providing voltage. For example, the connection wires (WL) may include at least one of a data line (DL, FIG. 8b), a scan signal line (GWL, FIG. 8b), an initialization control line (GIL, FIG. 8b), a bypass control line (GBL, FIG. 8b), an initialization control line (GIL, FIG. 8b), and an emission control line (EML, FIG. 8b). Alternatively, the connecting wires (WL) may include at least one of a first voltage line (VDDL, FIG. 6b), a second voltage line (VSSL, FIG. 6b), a first initialization voltage line (VIL1, FIG. 6b), and a second initialization voltage line (VIL2, FIG. 6b). FIG. 9b illustrates that a plurality of connecting wires (WL), for example, the first to third connecting wires (WL1, WL2, WL3), are arranged on the main bridge unit (12), but the present invention is not limited thereto. In another embodiment, one connecting wire (WL) may be arranged on the main bridge unit (12), or four or more connecting wires (WL) may be arranged.

[0175] Referring to Fig. 9c, a peripheral island portion (21) and a peripheral bridge portion (22) may be arranged in a non-display area (NDA). A plurality of peripheral island portions (21) may be arranged spaced apart from each other, and a peripheral bridge portion (22) may connect adjacent peripheral island portions (21) to each other. A gate driving circuit (GDC, Fig. 3) and a plurality of peripheral wirings (PW) may be arranged on the peripheral island portion (21) and the peripheral bridge portion (22).

[0176] As described above, the gate drive circuit (GDC, FIG. 3) may include an emission control drive circuit (EMDC, FIG. 8a), a bypass drive circuit (GBDC, FIG. 8a), an initialization drive circuit (GIDC, FIG. 8a), and a data write drive circuit (GWDC, 8a). At this time, each drive circuit may include a plurality of driver stages. For example, the data write drive circuit (GWDC) may include a plurality of data write stages (GWSTn, GWSTn+1, GWSTn+2, GWSTn+3). In some of the plurality of peripheral islands (21), an n-th data write stage (GWSTn), an n+1-th data write stage (GWSTn+1), an n+2-th data write stage (GWSTn+2), and an n+3-th data write stage (GWSTn+3) may be arranged, as shown in FIG. 9c. At this time, each driver stage may include multiple transistors and capacitors for generating an output signal.

[0177] In addition, a plurality of peripheral wirings (PW) may be arranged on the peripheral island portion (21) and the peripheral bridge portion (22). The peripheral wiring (PW) may be a wiring arranged in a non-display area (NDA) where sub-pixels are not arranged. Specifically, the peripheral wiring (PW) may include a driving voltage supply wiring (W11), a common voltage supply wiring (W13), and a fan-out wiring (FW), as described above with reference to FIG. 3. In addition, the peripheral wiring (PW) may include a plurality of input lines (IL) for inputting a signal to a gate driving circuit (GDC, FIG. 3) and a plurality of output wirings (OL) for transmitting an output signal generated from the gate driving circuit (GDC, FIG. 3).

[0178] Figure 10 shows a cross-section along line Ⅰ-Ⅰ' of Figure 9a, a cross-section along line Ⅱ-Ⅱ' of Figure 9b, and a cross-section along line Ⅲ-Ⅲ' of Figure 9c.

[0179] Referring to FIG. 9, the substrate (100) corresponding to the main island portion (11) may include a first base layer (101), a first barrier layer (102), a second base layer (103), and a second barrier layer (104). The first base layer (101) and the second base layer (103) may each include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. The first barrier layer (102) and the second barrier layer (104) may each include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0180] A buffer layer (111) is disposed on a substrate (100), and a pixel driving circuit (PC) (including a thin film transistor (TFT) and a first storage capacitor (Cst)) may be disposed on the buffer layer (111). The buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0181] A thin film transistor (TFT) may include a first semiconductor layer (Act), a first gate electrode (GE), a first source electrode (SE), and a first drain electrode (DE). FIG. 10 illustrates a top gate type in which the first gate electrode (GE) is disposed on the first semiconductor layer (Act) with a gate insulating layer (113) therebetween, but according to another embodiment, the thin film transistor (TFT) may be a bottom gate type.

[0182] The first semiconductor layer (Act) may include polysilicon. Alternatively, the first semiconductor layer (Act) may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The first gate electrode (GE) may include a metal thin film made of a low-resistance metal material. The first gate electrode (GE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials. For example, the first gate electrode (GE) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0183] The gate insulating layer (113) between the first semiconductor layer (Act) and the first gate electrode (GE) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or a multilayer including the aforementioned material. The gate insulating layer (113) may be disposed on the buffer layer (111) and the first semiconductor layer (Act). The first gate electrode (GE) of the thin film transistor (TFT) may be disposed on the gate insulating layer (113) to overlap the first semiconductor layer (Act). The first gate electrode (GE) may be a first electrode (CE1) of the first storage capacitor (Cst). The first interlayer insulating layer (115) may be disposed on the gate insulating layer (113) and the first gate electrode (GE). The second electrode (CE2) of the first storage capacitor (Cst) may be disposed on the first interlayer insulating layer (115). The second interlayer insulating layer (117) may be disposed on the first interlayer insulating layer (115) and the second electrode (CE2) of the first storage capacitor (Cst).

[0184] The first source electrode (SE) and the first drain electrode (DE) may be positioned on the same layer, for example, the second interlayer insulating layer (117), and may include the same material. The first source electrode (SE) and the first drain electrode (DE) may be connected to the first semiconductor layer (Act) through respective contact holes penetrating the gate insulating layer (113), the first interlayer insulating layer (115), and the second interlayer insulating layer (117). The first source electrode (SE) and the first drain electrode (DE) may include a metal thin film made of a low-resistance metal material. The first source electrode (SE) and the first drain electrode (DE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials. For example, the first source electrode (SE) and the first drain electrode (DE), like the gate electrode (GE), may be formed of a metal thin film formed as a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure. The second interlayer insulating layer (117) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or multilayer including the aforementioned materials.

[0185] The first storage capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2) that overlap with a first interlayer insulating layer (115) therebetween. The first storage capacitor (Cst) may overlap with a thin film transistor (TFT). In this regard, FIG. 10 illustrates that the first gate electrode (GE) of the thin film transistor (TFT) is the first electrode (CE1) of the first storage capacitor (Cst). In another embodiment, the first storage capacitor (Cst) may not overlap with the thin film transistor (TFT). The first storage capacitor (Cst) may be covered with a second interlayer insulating layer (117).

[0186] The first interlayer insulating layer (115) may be disposed between the gate insulating layer (113) and the second interlayer insulating layer (117). The first interlayer insulating layer (115) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or multilayer including the aforementioned materials.

[0187] The second electrode (CE2) of the first storage capacitor (Cst) may include a conductive material and may be formed in a multilayer or single layer. The second electrode (CE2) may include a metal thin film made of a low-resistance metal material. The second electrode (CE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and may be formed in a multilayer or single layer including the above materials. For example, the second electrode (CE2) may be provided as a metal thin film formed in a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0188] The inorganic insulating layer (IOL) on the substrate (100) may include, for example, a buffer layer (111), a gate insulating layer (113), a first interlayer insulating layer (115), and a second interlayer insulating layer (117).

[0189] The first organic insulating layer (119) may be disposed on the second interlayer insulating layer (117), the first source electrode (SE), and the first drain electrode (DE), and the second organic insulating layer (121) may be disposed on the first organic insulating layer (119). The first organic insulating layer (119) and the second organic insulating layer (121) may each include an organic insulating material such as polyimide.

[0190] A first connection electrode (CM1) may be disposed on a first organic insulating layer (119), and a second connection electrode (CM2) may be disposed on a second organic insulating layer (121). The first connection electrode (CM1) and the second connection electrode (CM2) may electrically connect a thin film transistor (TFT) and an inorganic light-emitting diode (230). The first connection electrode (CM1) may be connected to a first source electrode (SE) or a first drain electrode (DE) through a contact hole penetrating the first organic insulating layer (119). The second connection electrode (CM2) may be connected to the first connection electrode (CM1) through a contact hole penetrating the second organic insulating layer (121). The first connection electrode (CM1) and the second connection electrode (CM2) may include a metal thin film made of a low-resistance metal material. The first connection electrode (CM1) and the second connection electrode (CM2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the first connection electrode (CM1) and the second connection electrode (CM2) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0191] A second voltage line (VSSL) is disposed on a second organic insulating layer (121), and a third organic insulating layer (123) may be disposed on the second organic insulating layer (121) and the second voltage line (VSSL). The third organic insulating layer (123) may include an organic insulating material such as polyimide. The second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 3) to transmit a second power voltage (VSS, FIG. 6a) to a second electrode (238) of an inorganic light-emitting diode (230). The second voltage line (VSSL) may include a conductive material and may be formed in a multilayer or a single layer. However, in this case, the second voltage line (VSSL) may be formed of a different material from the second connection electrode (CM2) disposed on the same layer. The material of the second voltage line (VSSL) will be described in detail later.

[0192] The first electrode pad (241) and the second electrode pad (242) may be disposed on the third organic insulating layer (123). The first electrode pad (241) may be electrically connected to a thin film transistor (TFT) through a first connection electrode (CM1) between the first organic insulating layer (119) and the second organic insulating layer (121) and a second connection electrode (CM2) between the second organic insulating layer (121) and the third organic insulating layer (123). The inorganic light-emitting diode (230) on the first electrode pad (241) and the second electrode pad (242) is as described above with reference to FIG. 7b. A light emitting diode, for example, an inorganic light emitting diode (230), may be protected by an encapsulating layer (300), and the encapsulating layer (300) may include an inorganic encapsulating layer and / or an organic encapsulating layer, or may include an organic material such as a resin. FIG. 10 illustrates that the light emitting diode is an inorganic light emitting diode (230) described with reference to FIG. 7b, but as another embodiment, the light emitting diode may be an organic light emitting diode (220) described with reference to FIG. 7a.

[0193] To summarize, a thin film transistor (TFT) included in a pixel driver circuit (PC) may include a plurality of conductive layers. Specifically, the plurality of conductive layers included in the thin film transistor (TFT) may include the first gate electrode (GE), the first source electrode (SE), the first drain electrode (DE), the first electrode (CE1) of the first storage capacitor (Cst), and the second electrode (CE2) as described above. The plurality of conductive layers, the first connection electrode (CM1), and the second connection electrode (CM2) included in the thin film transistor (TFT) may be formed of a metal thin film material. For example, the plurality of conductive layers, the first connection electrode (CM1), and the second connection electrode (CM2) included in the thin film transistor (TFT) may be formed of a metal thin film formed of a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure. Accordingly, the modulus of each of the plurality of conductive layers included in the thin film transistor (TFT), the first connection electrode (CM1), and the second connection electrode (CM2) may be greater than 100 Ga and less than 1000 GPa. In other words, the modulus of the conductive layers of the thin film transistor (TFT) may be greater than the modulus of the connection wiring (WL) and the peripheral wiring (PW) described later.

[0194] Next, referring to the main bridge portion (12) of FIG. 10, the substrate (100) corresponding to the main bridge portion (12) may have the same laminated structure as the substrate (100) corresponding to the main island portion (11). In one embodiment, the substrate (100) corresponding to the main bridge portion (12) may include a first base layer (101), a first barrier layer (102), a second base layer (103), and a second barrier layer (104). In another embodiment, the substrate (100) corresponding to the main bridge portion (12) may have a different laminated structure from the substrate (100) corresponding to the main island portion (11). The substrate (100) corresponding to the main bridge portion (12) may have a structure of a first base layer (101) and a second base layer (103).

[0195] On the substrate (100), an inorganic insulating layer (IOL) may not be disposed, and an insulating layer (OSL), a first organic insulating layer (119), and a second organic insulating layer (121) may be disposed. The insulating layer (OSL) may include an organic insulating material such as polyimide. In one embodiment, the insulating layer (OSL) may have a thickness corresponding to the inorganic insulating layer (IOL). In some embodiments, the insulating layer (OSL) may be omitted.

[0196] A plurality of connection wires (WL) may be arranged on the main bridge unit (12). The plurality of connection wires (WL), for example, the first to third connection wires (WL1, WL2, WL3), may be arranged on different layers but may be electrically connected to the same pixel driver circuit unit (PC). For example, the first connection wire (WL1) may be arranged between the second organic insulating layer (121) and the third organic insulating layer (123), the second connection wire (WL2) may be arranged between the first organic insulating layer (119) and the second organic insulating layer (121), and the third connection wire (WL3) may be arranged between the insulating layer (OSL) and the first organic insulating layer (119). However, the present invention is not limited thereto, and in another embodiment, at least some of the first to third connection wires (WL1, WL2, WL3) may be arranged on the same layer.

[0197] At this time, the plurality of connecting wires (WL) may be signal lines for providing electrical signals to a thin film transistor (TFT) included in a pixel driver circuit (PC), or may be low-voltage lines for providing voltage. For example, the connecting wires (WL) may include at least one of a data line (DL, FIG. 8b), a scan signal line (GWL, FIG. 8b), an initialization control line (GIL, FIG. 8b), a bypass control line (GBL, FIG. 8b), and an emission control line (EML, FIG. 8b). Alternatively, the connecting wires (WL) may include at least one of a first voltage line (VDDL, FIG. 6b), a second voltage line (VSSL), a first initialization voltage line (VIL1, FIG. 6b), and a second initialization voltage line (VIL2, FIG. 6b).

[0198] However, even if the plurality of connecting wires (WL) are arranged on the same layer as the conductive layers of the thin film transistor (TFT), the first connecting electrode (CM1), and the second connecting electrode (CM2), they may include a different material from the conductive layers of the thin film transistor (TFT), the first connecting electrode (CM1), and the second connecting electrode (CM2). In one embodiment, the plurality of connecting wires (WL) may be formed of a material having a lower modulus than the conductive layers of the thin film transistor (TFT), the first connecting electrode (CM1), and the second connecting electrode (CM2). For example, the modulus of the plurality of connecting wires (WL) may be greater than 1 MPa and less than 100 MPa.

[0199] Specifically, the plurality of connecting wires (WL) may include a metal nanostructure and an elastic polymer. The metal nanostructure is, for example, a nano-scale structure including an inorganic, organic, or organic-inorganic material, and may be a nanostructure having a one-dimensional, two-dimensional, and / or three-dimensional shape. The metal nanostructure may include, but is not limited to, a nanoparticle, a nanorod, a nanoplate, a nanowire, a nanoflake, a nanotube, a nanocapsule, or a combination thereof. For example, the nanostructure may be, but is not limited to, an inorganic nanoparticle, an inorganic nanorod, an inorganic nanoplate, an inorganic nanowire, an inorganic nanoflake, an inorganic nanotube, an inorganic nanocapsule, or a combination thereof.

[0200] The metal nanostructure may be, for example, an oxide, a nitride, or an oxynitride, and may be, for example, a metal oxide, a metalloid oxide, a metal nitride, a metalloid nitride, a metal oxynitride, or a metalloid oxynitride. In one embodiment, the metal nanostructure may include at least one of a silver nanoparticle, a silver nanoflake, and a silver nanowire.

[0201] The metal nanostructure may have a major diameter of, for example, about 200 nm or less, for example, about 5 nm to 100 nm, for example, about 5 nm to 80 nm, for example, about 5 nm to 50 nm. Here, the major diameter may be the diameter if it is spherical, and may be the length of the longest part among the height, width, and thickness if it is not spherical.

[0202] Meanwhile, the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex. However, the elastic polymer is not limited thereto, and may be a material that is easily composited with a metal nanostructure.

[0203] The plurality of connecting wires (WL) may further include metal nanostructures, elastic polymers, and other conductive additives. In one embodiment, the plurality of connecting wires (WL) may further include a carbon-based material including carbon nanotubes (CNTs), carbon fibers, graphene, and graphene oxide, or any combination thereof. In one embodiment, the concentration of the metal nanostructures in the plurality of connecting wires (WL) may be 60 wt% to 80 wt%, and the concentration of the carbon-based material in the plurality of connecting wires (WL) may be 1 wt% to 10 wt%. Accordingly, the minimum electrical conductivity of the plurality of connecting wires (WL) is 10 -3 It can satisfy the Ωcm level.

[0204] Next, referring to the peripheral island portion (21) of FIG. 10, a gate driving circuit (GDC) and a plurality of peripheral wirings (PW) may be arranged on the peripheral island portion (21). The substrate (100) corresponding to the peripheral island portion (21) may have the same laminated structure as the substrate (100) corresponding to the main island portion (11). A buffer layer (111) may be arranged on the substrate (100), and the gate driving circuit (GDC) may be arranged on the buffer layer (111).

[0205] The gate driving circuit (GDC) may include a plurality of driver stages, and each of the plurality of driver stages may include a plurality of transistors and capacitors. For example, the gate driving circuit (GDC) may include a peripheral thin film transistor (TFT') as shown in FIG. 10. The peripheral thin film transistor (TFT') may include a second semiconductor layer (Act'), a second gate electrode (GE'), a second source electrode (SE'), a second drain electrode (DE'), and a second storage capacitor (Cst'). The second semiconductor layer (Act'), like the first semiconductor layer (Act), may include polysilicon, amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like.

[0206] In contrast, the second gate electrode (GE') may be disposed on the gate insulating layer (113) like the first gate electrode (GE), but may have a different material from the first gate electrode (GE). In one embodiment, the second gate electrode (GE') may be composed of a material having a lower modulus than the first gate electrode (GE) and the connecting wire (WL). For example, the modulus of the second gate electrode (GE') may be greater than 1 kPa and less than 100 kPa.

[0207] Specifically, the second gate electrode (GE') may include a liquid metal. In one embodiment, the second gate electrode (GE') may include a liquid metal including a eutectic gallium-indium alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan). That is, the second gate electrode (GE') may include at least one of gallium (Ga), indium (In), or tin (Sn). In particular, in the case of the eutectic gallium-indium alloy (EGaIn), which is a eutectic alloy of gallium (Ga) and indium (In), the melting point thereof is lower than room temperature, and thus the eutectic gallium-indium alloy can have a low resistivity while remaining in a liquid state at room temperature.

[0208] Similarly, the second electrode (CE2'), the second source electrode (SE'), and the second drain electrode (DE') of the second storage capacitor (Cst') may include the same material as the second gate electrode (GE'). Specifically, the second electrode (CE2'), the second source electrode (SE'), and the second drain electrode (DE') of the second storage capacitor (Cst') may include a liquid metal. In one embodiment, the second electrode (CE2'), the second source electrode (SE'), and the second drain electrode (DE') of the second storage capacitor (Cst') may include a liquid metal including a eutectic gallium-indium alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan). In other words, the second electrode (CE2') of the second storage capacitor (Cst') may be disposed on the first interlayer insulating layer (115), but may include a material having a smaller modulus than the second electrode (CE2) of the first storage capacitor (Cst) and the connecting wire (WL). The second source electrode (SE') and the second drain electrode (DE') may also be disposed on the second interlayer insulating layer (117), but may include a material having a smaller modulus than the first source electrode (SE), the first drain electrode (DE), and the connecting wire (WL).

[0209] A first organic insulating layer (119) may be disposed on the peripheral thin film transistor (TFT), and a plurality of peripheral wirings (PW) may be disposed on the first organic insulating layer (119). For example, as shown in FIG. 10, an input line (IL) for transmitting an electrical signal to a gate driving circuit (GDC) and an output wiring (OL) for transmitting an output signal of the gate driving circuit (GDC) may be disposed on the first organic insulating layer (119). In addition, although not shown in FIG. 10, a driving voltage supply wiring (W11) and a common voltage supply wiring (W13) that may be included in the peripheral wiring (PW) may also be disposed on the first organic insulating layer (119) and the second organic insulating layer (121).

[0210] At this time, the plurality of peripheral wirings (PW) may include a material having a lower modulus than the conductive layers of the thin film transistor (TFT) and the connecting wiring (WL), similar to the conductive layers of the peripheral thin film transistor (TFT). Specifically, the plurality of peripheral wirings (PW) may include a liquid metal. In one embodiment, the plurality of peripheral wirings (PW) may include a liquid metal including a eutectic gallium-indium alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan).

[0211] To summarize, the conductive layers included in the thin film transistor (TFT) of the pixel driver circuit (PC) may be formed of a metal thin film, the connecting wire (WL) may be formed of a composite material of a metal nanostructure and an elastic polymer, and the conductive layers included in the peripheral wire (PW) and the peripheral thin film transistor (TFT') may be formed of a liquid metal. Accordingly, the modulus of the conductive layers included in the thin film transistor (TFT) of the pixel driver circuit (PC) may be greater than the modulus of the connecting wire (WL), and the modulus of the connecting wire (WL) may be greater than the modulus of the conductive layers included in the peripheral wire (PW) and the peripheral thin film transistor (TFT'). For example, the modulus of the conductive layers of a thin film transistor (TFT) may differ by 100 to 1000 times from the modulus of the connecting wire (WL), and the modulus of the connecting wire (WL) may differ by 100 to 1000 times from the modulus of the conductive layers of the peripheral wire (PW) and the peripheral thin film transistor (TFT').

[0212] Typically, the larger the modulus of a material layer, the better the recovery rate, and the smaller the modulus, the better the elongation. In this case, since the connecting wire (WL) has a smaller modulus than the conductive layers included in the thin film transistor (TFT), it may have relatively better elasticity than the conductive layers included in the thin film transistor (TFT). Similarly, the conductive layers and the peripheral wire (PW) included in the peripheral thin film transistor (TFT') have smaller moduli than the connecting wire (WL), and thus may have relatively better elasticity than the unconnected wire (WL).

[0213] In the case of a display device (1) that is stretchable, high stress may be formed at the outer portion of the display device (1) during stretching, and low stress may be formed at the center portion of the display device (1). At this time, as in the display device (1) according to one embodiment of the present invention, when wiring is formed with a material having a low modulus in the non-display area (NDA) corresponding to the outer portion of the display device (1) and wiring is formed with a material having a high modulus in the pixel driving circuit unit (PC) of the display area (DA), deformation of the display area (DA) when stress is applied can be minimized, thereby ensuring the stability of the elements within the display device. Specifically, by disposing a material having a low modulus and excellent stretchability, such as a liquid metal, in the non-display area (NDA) where high stress is formed, the high stress can be alleviated, and a material having a high modulus and excellent recovery rate and electrical characteristics, such as a metal thin film, can be disposed in the pixel driving circuit unit (PC) of the display area (DA) where electrical characteristics and element stability are important. In addition, the connecting wire (WL) connecting multiple subpixels (P) in the display area (DA) can be made of a material having both excellent elasticity and electrical properties, such as a composite material of a metal nanostructure and an elastic polymer, thereby simultaneously implementing the stretchability and mechanical stability of the display device (1).

[0214] In addition, in another embodiment of the present invention, even though all of the conductive layers of the thin film transistor (TFT), the connecting wire (WL), the peripheral wire (PW), and the conductive layers of the peripheral thin film transistor (TFT') use the same material, the stretchability and mechanical stability of the display device (1) can be implemented simultaneously. Specifically, in another embodiment, all of the conductive layers of the thin film transistor (TFT), the connecting wire (WL), the peripheral wire (PW), and the conductive layers of the peripheral thin film transistor (TFT') can include a metal nanostructure and an elastic polymer. At this time, the metal nanostructure can include at least one of silver nanoparticles (Ag nanoparticles), silver nanoflakes (Ag nanoflake), and silver nanowires (Ag nanowire), and the elastic polymer can include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

[0215] However, the conductive layers of the thin film transistor (TFT), the connecting wire (WL), the peripheral wire (PW), and the conductive layers of the peripheral thin film transistor (TFT') may have different moduli even though they are composed of the same material. That is, the conductive layers of the thin film transistor (TFT), the connecting wire (WL), the peripheral wire (PW), and the conductive layers of the peripheral thin film transistor (TFT') may all be formed of a composite material of a metal nanostructure and an elastic polymer, but may have different concentrations of the metal nanostructure. For example, the conductive layers of the thin film transistor (TFT) may have a higher concentration of the metal nanostructure than the connecting wire (WL), and the connecting wire (WL) may have a higher concentration of the metal nanostructure than the peripheral wire (PW) and the conductive layers of the peripheral thin film transistor (TFT'). Alternatively, the conductive layers of the thin film transistor (TFT) may have a higher concentration of carbon-based material than the connecting wire (WL), and the connecting wire (WL) may have a higher concentration of carbon-based material than the conductive layers of the peripheral wire (PW) and the peripheral thin film transistor (TFT'). The concentration of the metal nanostructure may be controlled in the range of 60 wt% to 80 wt%, and the concentration of the carbon-based material may be controlled in the range of 1 wt% to 10 wt%.

[0216] Accordingly, the modulus of the conductive layers of the thin film transistor (TFT) may be greater than the modulus of the connecting wire (WL), and the modulus of the connecting wire (WL) may be greater than the modulus of the conductive layers of the surrounding thin film transistor (TFT') and the peripheral wire (PW). For example, the modulus of the conductive layers of the thin film transistor (TFT) may have a difference of 100 to 1000 times from the modulus of the connecting wire (WL), and the modulus of the connecting wire (WL) may have a difference of 100 to 1000 times from the modulus of the conductive layers of the surrounding wire (PW) and the surrounding thin film transistor (TFT').

[0217] In another embodiment, that is, the conductive layers of the thin film transistor (TFT), the connecting wire (WL), the peripheral wire (PW), and the conductive layers of the peripheral thin film transistor (TFT') can all be formed of a composite material of a metal nanostructure and an elastic polymer, but the moduli can be formed differently by making a difference in the thermal curing or UV curing process. For example, in the case of the conductive layers of the thin film transistor (TFT), the modulus characteristic of the material itself can be modified to be high by increasing the thermal curing process time or the UV curing process time. Similarly, in the case of the conductive layers of the peripheral thin film transistor (TFT') and the peripheral wire (PW), the modulus characteristic of the material itself can be modified to be low by decreasing the thermal curing process time or the UV curing process time. Even through the process modification described above, the modulus of the conductive layers of the thin film transistor (TFT) can be formed to be greater than the modulus of the connecting wiring (WL), and the modulus of the connecting wiring (WL) can be formed to be greater than the modulus of the conductive layers of the surrounding thin film transistor (TFT') and the surrounding wiring (PW).

[0218] In conclusion, in a display device according to another embodiment of the present invention and also in a display device according to another embodiment, excellent elasticity and mechanical stability can be secured simultaneously by arranging materials having different moduli in each area.

[0219] Fig. 11 is a cross-sectional view schematically illustrating a display device according to another embodiment of the present invention. Fig. 12 is a plan view schematically illustrating a display device according to another embodiment of the present invention.

[0220] First, referring to FIG. 11, the substrate (100') of the display device (1) may be formed integrally without being partitioned so as to be spaced apart from each other. However, the substrate (100') may be a flexible substrate so that the display device (1) can be elongated. For example, the substrate (100') may include at least a portion of an elastic region. The elastic region may have a property of being elongated in at least one direction by an external force and returning to an initial state when the external force is removed. Accordingly, the elastic region included in the substrate (100') may be manufactured from a polymer material having a predetermined elasticity. Specifically, the substrate (100') may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0221] A buffer layer (111) may be disposed on the substrate (100'). As described above, the buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, for the flexibility of the display device (1), the buffer layer (111) may be omitted or may include an organic insulating material.

[0222] A plurality of pixel driving circuits (PC) may be arranged on a buffer layer (111). An insulating layer (ISL) including an inorganic insulator and / or an organic insulator may be arranged between the pixel driving circuits (PC) and the light emitting elements (LED). The light emitting elements (LED) are arranged on the insulating layer (ISL) and may be electrically connected to the corresponding pixel driving circuits (PC). An encapsulation layer (300) may be arranged on the light emitting elements (LED) and may protect the light emitting elements (LED) from external force and / or moisture penetration.

[0223] A plurality of pixel driver circuit units (PC) may be arranged to be spaced apart from each other. At this time, a connecting wire (WL) may be arranged between the pixel driver circuit units (PC) that are spaced apart from each other. The connecting wire (WL) may be a signal line (e.g., a gate line, a data line, etc.) for providing an electrical signal to a transistor included in the pixel driver circuit unit (PC) or a voltage line (e.g., a driving voltage line, an initialization voltage line, etc.) for providing a voltage. At this time, the connecting wire (WL) may be formed of a material having a lower modulus than the conductive layers arranged in the pixel driver circuit unit (PC). That is, since the connecting wire (WL) is formed of a material having excellent stretchability, the display device (1) as in FIG. 11 can be stretched by utilizing the stretchability of the material itself, even though it is not divided into an island portion and a bridge portion.

[0224] Next, referring to FIG. 12, a plurality of display units (PU) may be arranged in the display area (DA). Each display unit (PU) may include a first sub-pixel (SP1) emitting red light, a second sub-pixel (SP2) emitting green light, and a third sub-pixel (SP3) emitting blue light. Adjacent display units (PU) may be electrically connected to each other through a connection wire (WL). In addition, within one display unit (PU), adjacent sub-pixels (P) (e.g., SP1, SP2, SP3) may be electrically connected to each other through a connection wire (WL). However, as shown in FIG. 12, the distance between adjacent display units (PU) may be greater than the distance between adjacent sub-pixels (P) (e.g., SP1, SP2, SP3) within one display unit (PU).

[0225] A gate driving circuit (GDC) may be arranged in a non-display area (NDA). The gate driving circuit (GDC) may include an emission control driving circuit (EMDC, FIG. 8a), a bypass driving circuit (GBDC, FIG. 8a), an initialization driving circuit (GIDC), and a data writing driving circuit (GWDC), as described above. Each driving circuit may include a plurality of driver stages. For example, the initialization driving circuit (GIDC) may include an n-th initialization stage (GISTn) and an n+1-th initialization stage (GISTn+1), and the data writing driving circuit (GWDC) may include an n-th data writing stage (GWSTn) and an n+1-th data writing stage (GWSTn+1). Each of the driver stages may include a plurality of transistors and capacitors.

[0226] Additionally, peripheral wiring (PW) may be arranged in the non-display area (NDA). The peripheral wiring (PW) may include input lines (IL) that can input electrical signals to the gate driving circuit (GDC), and output wiring (OL) that transmits output signals of the gate driving circuit (GDC), as illustrated in FIG. 12. Although not illustrated in FIG. 12, the peripheral wiring (PW) may further include a driving voltage supply wiring (W11), a common voltage supply wiring (W13), a fan-out wiring (FW, FIG. 3), etc.

[0227] Even in structures such as those in FIGS. 11 and 12, materials having different moduli can be arranged in the display area (DA) and the non-display area (NDA), respectively. Specifically, the conductive layers arranged in the pixel driver circuit (PC) can be formed of a material having a higher modulus than the connecting wire (WL), and the connecting wire (WL) can be formed of a material having a higher modulus than the conductive layers included in the gate driver circuit (GDC) and the peripheral wire (PW).

[0228] In one embodiment, the conductive layers disposed in the pixel driver circuit (PC) may include a metal thin film. For example, the conductive layers disposed in the pixel driver circuit (PC) may be formed of a metal thin film formed as a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure. The connecting wire (WL) may include a composite material of a metal nanostructure and an elastic polymer. For example, the metal nanostructure included in the connecting wire (WL) may include at least one of silver nanoparticles (Ag nanoparticles), silver nanoflakes (Ag nanoflake), and silver nanowires (Ag nanowire), and the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex. The conductive layers and the peripheral wire (PW) included in the gate driver circuit (GDC) may include a liquid metal. For example, the conductive layers and peripheral wiring (PW) included in the gate drive circuit (GDC) may include a liquid metal including a eutectic gallium-indium alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan).

[0229] In another embodiment, the conductive layers disposed in the pixel driver circuit (PC), the connecting wire (WL), the peripheral wire (PW), and the conductive layers disposed in the gate driver circuit (GDC) may have different moduli even though they are composed of the same material. For example, the conductive layers disposed in the pixel driver circuit (PC), the connecting wire (WL), the peripheral wire (PW), and the conductive layers disposed in the gate driver circuit (GDC) may all be formed of a composite material of a metal nanostructure and an elastic polymer, but may have different concentrations of the metal nanostructure.

[0230] A display device (1) such as that shown in FIGS. 11 and 12 may require both mechanical stability of a transistor included in a pixel driver circuit unit (PC) and elasticity of other connection wiring (WL) and peripheral wiring (PW) since the entire display device (1) can be stretched. Accordingly, in a display device according to another embodiment of the present invention, conductive layers included in a pixel driver circuit unit (PC) are formed of a material having a higher modulus and superior recovery rate than the connection wiring (WL), thereby ensuring stability and electrical characteristics of the transistor. In addition, the connection wiring (WL) connecting a plurality of subpixels (P) is formed of a composite material of a metal nanostructure and an elastic polymer that can secure both stretchability and electrical characteristics, thereby stably transmitting electrical signals to a plurality of subpixels (P) and alleviating stress applied to the display device (1) during stretching. The conductive layers of the gate drive circuit (GDC) and the peripheral wiring (PW) arranged in the outermost non-display area (NDA) are made of liquid metal having a lower modulus than the connecting wiring (WL), thereby significantly alleviating the stress in the outermost region, which is subject to the highest stress among the display devices (1) during stretching, thereby improving the stretchability of the display device. In conclusion, the display device according to another embodiment of the present invention can simultaneously secure excellent stretchability and mechanical stability of the device by arranging materials having different moduli in each region.

[0231] FIGS. 13A to 13G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention, respectively.

[0232] Referring to FIG. 13A, a display device according to an embodiment of the present invention may be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body portion (3110) and a display portion (3120) provided on the body portion (3110). The display device according to embodiments of the present invention may be utilized as the display portion (3120) of the wearable electronic device (3100). As illustrated in FIG. 13A, the wearable electronic device (3100) may be deformable. In one embodiment, the wearable electronic device (3100) may be utilized as a smart watch or a smartphone, depending on the user's selection.

[0233] FIG. 13B illustrates a medical electronic device (3200). In one embodiment, the medical electronic device (3200) may include a body portion (3210) and a light-emitting portion (3220). A display device according to embodiments of the present invention may be used as the light-emitting portion (3220) of the medical electronic device (3200). The light-emitting portion (3220) may emit light of a certain wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body portion (3210) may have a stretchable fiber material, and the light-emitting portion (3220) may have a structure that can be worn on the body of a user.

[0234] FIG. 13C illustrates an educational electronic device (3300). In one embodiment, the educational electronic device (3300) may include a display unit (3320) provided within a frame (3310). The display unit (3320) may utilize a display device according to embodiments of the present invention. The display unit (3320) may provide images such as a sea with crashing waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may expand in the height direction (e.g., the z-direction) to reflect the height of the wave, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of lava flow, thereby displaying the movement of lava in three dimensions. The educational electronic device (3300) may include a plurality of pins (or stroke units, 3330) arranged on the back surface of the display unit (3320) so that the display unit (3320) extends in the height direction. The pins (3330) may be implemented so that an image displayed on the display unit (3320) has a three-dimensional height as the pins move along a third direction (e.g., the z direction or the -z direction). Although FIG. 13C illustrates the educational electronic device (3300), its use is not limited as long as it provides certain image information.

[0235] While the electronic devices illustrated in FIGS. 13A through 13C are described as electronic devices whose shapes can be varied, the present invention is not limited thereto. As described in the embodiments below, display devices according to embodiments of the present invention can be used in electronic devices in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0236] FIG. 13D illustrates a robot (3400) as another electronic device according to one embodiment of the present invention. The robot (3400) can recognize movement or objects using a camera unit (3440), and can display a predetermined image to a user through a display unit (3420, 3430). In some embodiments, since the display devices according to one embodiment of the present invention can extend in various directions as described above, they can be assembled into a body frame having a hemispherical shape, and thus the robot (3400) can include a hemispherical display unit (3420, 3430).

[0237] FIG. 13E illustrates a vehicle display device (3500) as another electronic device according to one embodiment of the present invention. The vehicle display device (3500) may include a cluster (3510), a center information display (CID) (3520), and / or a passenger display (3530). Since the display device according to the embodiment of the present invention can be extended in various directions, it may be used in the cluster (3510), the center information display (CID) (3520), and / or the co-driver display regardless of the shape of the internal frame of the vehicle.

[0238] Although FIG. 13e illustrates that the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display (3530) are each separate, the present invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected integrally.

[0239] In some embodiments, a vehicle display device (3500) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 13E, the hemispherical button (3540) may include an object (3542) that provides a user experience of the button while moving in the z-direction or the -z-direction, and a display device positioned on the object (3542). In some embodiments, when the object (3542) has a three-dimensionally rounded surface, the display device may also have a three-dimensionally rounded surface.

[0240] FIG. 13F illustrates an electronic device according to one embodiment of the present invention, which is an electronic device (3600) for advertising or display purposes. In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on a fixed structure (3610), such as a wall or a pillar. If the structure (3610) includes a recessed surface as illustrated in FIG. 13F, the electronic device (3600) for advertising or display purposes may also be positioned along the recessed surface of the structure (3610). In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on the structure (3610) using a heat shrink film or the like.

[0241] FIG. 13G illustrates an electronic device according to one embodiment of the present invention as a controller (3700). The controller (3700) may include an image-type button. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display unit (3710) protrudes in the z direction or protrudes in the -z direction (or is sunken in the z direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z direction, and the second button area (3730) may protrude in the -z direction (or is sunken in the z direction).

[0242] While the present invention has been described with reference to one embodiment illustrated in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and variations of the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A display device including a display area and a non-display area outside the display area, A plurality of pixels each including a transistor and a light-emitting diode electrically connected to the transistor, arranged in the display area; A connecting wire arranged in the above display area, electrically connecting adjacent pixels among the plurality of pixels; and Peripheral wiring arranged in the above non-display area; including; The modulus of the conductive layer included in the above transistor is greater than the modulus of the above connecting wiring, A display device in which the modulus of the above connecting wiring is greater than the modulus of the above peripheral wiring.

2. In paragraph 1, A display device in which the conductive layer included in the transistor, the connecting wiring, and the peripheral wiring are each made of different materials.

3. In paragraph 1, A display device in which the modulus of the conductive layer included in the above transistor is greater than 100 GPa and less than 1000 GPa.

4. In paragraph 1, A display device, wherein the conductive layer included in the above transistor includes a metal thin film.

5. In paragraph 1, The modulus of the above connecting wire is greater than 1 MPa and less than 100 MPa, the display device.

6. In paragraph 1, The above connecting wiring is a display device including a metal nanostructure and an elastic polymer.

7. In paragraph 6, A display device, wherein the metal nanostructure comprises at least one of silver nanoparticles, silver nanoflakes, or silver nanowires.

8. In paragraph 6, A display device, wherein the elastic polymer comprises at least one of polydimethylsiloxane (PDMS), polyurethane (PU), or Ecoflex.

9. In paragraph 6, The above connecting wiring further includes a carbon-based material, A display device, wherein the carbon-based material comprises carbon nanotubes (CNTs), carbon fibers, graphene, and graphene oxide, or any combination thereof.

10. In paragraph 1, The modulus of the above peripheral wiring is greater than 1 kPa and less than 100 kPa, the display device.

11. In paragraph 1, A display device wherein the peripheral wiring includes liquid metal.

12. In paragraph 11, A display device, wherein the liquid metal comprises a eutectic gallium-indium alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan).

13. In paragraph 1, A display device, wherein the conductive layer included in the transistor, the connecting wiring, and the peripheral wiring each include a metal nanostructure and an elastic polymer.

14. In paragraph 13, The concentration of the metal nanostructure in the conductive layer included in the above transistor is greater than the concentration of the metal nanostructure in the above connecting wiring, A display device wherein the concentration of the metal nanostructure in the above connecting wiring is greater than the concentration of the metal nanostructure in the peripheral wiring.

15. In paragraph 13, The above metal nanostructure comprises at least one of silver nanoparticles, silver nanoflakes, and silver nanowires, A display device, wherein the elastic polymer comprises at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

16. In paragraph 1, The above connecting wiring includes a plurality of signal lines and a plurality of voltage lines, A display device, wherein the plurality of signal lines include at least one of a data line, a light emission control line, a scan signal line, an initialization control line, and a bypass control line.

17. In paragraph 1, A display device, wherein the peripheral wiring includes at least one of a driving voltage supply wiring, a common voltage supply wiring, a fan-out wiring, a driving circuit input line, and a driving circuit output line.

18. In paragraph 1, Further comprising a gate driving circuit included in the above non-display area; A display device in which the modulus of the conductive layer included in the above gate driving circuit is smaller than the modulus of the above connecting wiring.

19. In paragraph 18, A display device, wherein the conductive layer included in the above gate driving circuit includes liquid metal.

20. A display device including a display area and a non-display area outside the display area, A plurality of pixels each including a transistor and a light-emitting diode electrically connected to the transistor, arranged in the display area; A connecting wire arranged in the above display area, electrically connecting adjacent pixels among the plurality of pixels; and Peripheral wiring arranged in the above non-display area; including; The conductive layer included in the above transistor includes a metal thin film, The above connecting wiring includes a metal nanostructure and an elastic polymer, The above peripheral wiring is a display device including liquid metal.

21. In paragraph 20, The modulus of the conductive layer included in the above transistor is greater than the modulus of the above connecting wiring, A display device in which the modulus of the above connecting wiring is greater than the modulus of the above peripheral wiring.

22. In paragraph 21, The modulus of the conductive layer included in the above transistor has a value in the range of 100 GPa to 1000 GPa, The modulus of the above connecting wire has a value in the range of 1 MPa to 100 MPa, A display device, wherein the modulus of the peripheral wiring has a value in the range of 1 kPa to 100 kPa.

23. In paragraph 20, The above metal nanostructure comprises at least one of silver nanoparticles, silver nanoflakes, and silver nanowires, The elastic polymer comprises at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex. Display device.

24. In paragraph 20, A display device wherein the liquid metal comprises a molten gallium-indium alloy (eutectic gallium-indium alloy, EGaIn) or a gallium-indium-tin alloy (gallium-indium-tin alloy, Galinstan).

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