Multilevel inverter

Abstract

According to the present invention, a rise in temperature of a first clamp diode and a second clamp diode is suppressed. A control device (6) selects a first voltage vector, a second voltage vector, and a third voltage vector, respectively corresponding to the vertices of a regular triangle surrounding a command voltage vector, as a plurality of voltage vectors to be used in a control cycle among a group of voltage vectors, and determines a first distribution time of the first voltage vector, a second distribution time of the second voltage vector, and a third distribution time of the third voltage vector to match a composite vector of the first voltage vector, the second voltage vector, and the third voltage vector with the command voltage vector. When the command voltage vector is within a range of a reference hexagon defined by 12 voltage vectors, the control device (6) selects a first zero vector, a second zero vector, and a third zero vector as one among the first voltage vector, the second voltage vector, and the third voltage vector within the control cycle.

Description

Multilevel Inverter

[0001] The present disclosure relates to a multilevel inverter, and more particularly to a multilevel inverter with a bootstrap circuit.

[0002] Patent Document 1 discloses a three-level power conversion system (multilevel inverter). The three-level power conversion system disclosed in Patent Document 1 includes two DC terminals, two capacitors connected in series between the two DC terminals, a three-level switching network, three AC terminals, and a space vector modulation switch control device. The three-level switching network includes three switch sets (inverter circuits). Each of the three switch sets includes four switching devices (a first switching element, a second switching element, a third switching element, and a fourth switching element) and two diodes (a first clamp diode and a second clamp diode). Each of the four switching devices is, for example, an IGBT. Each of the four switching devices includes a freewheel diode. The three AC terminals are connected to, for example, a Y-connected three-phase load (AC load). The Y-connected three-phase load includes three phase loads. Each of the three phase loads is a motor winding.

[0003] US Patent Application Publication No. 2006 / 0245216

[0004] In the three-level power conversion system disclosed in Patent Document 1, for example, when a motor, which is an AC load, locks up, the currents in each phase become approximately constant, and the temperature of the first clamp diode or the second clamp diode is likely to rise. For example, if the polarities of the currents in the U, V, and W phases when the motor locks up are negative, positive, and negative, respectively, the temperature of the first clamp diode through which current flows in the switch set corresponding to the V phase is likely to rise, shortening the time it takes for the temperature of the first clamp diode to reach an allowable temperature. Also, for example, if the polarities of the currents in the U, V, and W phases when the motor locks up are positive, negative, and positive, respectively, the temperature of the second clamp diode through which V-phase current flows in the switch set corresponding to the V phase is likely to rise, shortening the time it takes for the temperature of the second clamp diode to reach an allowable temperature.

[0005] An object of the present disclosure is to provide a multilevel inverter capable of suppressing a temperature rise in the first clamp diode and the second clamp diode.

[0006] A multilevel inverter according to one aspect of the present disclosure includes a DC power supply unit, multiple inverter circuits, and a control device. The DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point. The multiple inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The control device controls the multiple inverter circuits using space vector modulation. Each of the multiple inverter circuits includes a switching circuit, a first clamp diode, and a second clamp diode. The switching circuit includes a first switching element, a second switching element, a third switching element, and a fourth switching element. In the switching circuit, the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element. The cathode of the first clamp diode is connected to a first connection point between the first switching element and the second switching element, and the anode is connected to the intermediate potential point. The second clamp diode has an anode connected to a second connection point between the third switching element and the fourth switching element, and a cathode connected to an intermediate potential point. The switching circuit has an output point between the second switching element and the third switching element. The control device stores a group of voltage vectors determined by a combination of potential levels of a plurality of output points. The group of voltage vectors includes 12 voltage vectors each having a reference magnitude, 6 voltage vectors each having a magnitude twice the reference magnitude, and 3 voltage vectors each having a magnitude three times the reference magnitude. １／２The control device includes six voltage vectors, each having a magnitude twice the magnitude of the first voltage vector, a first zero vector resulting from a combination in which the potential levels of the multiple output points are all positive, a second zero vector resulting from a combination in which the potential levels of the multiple output points are all at an intermediate potential point, and a third zero vector resulting from a combination in which the potential levels of the multiple output points are all negative. The control device selects, from the group of voltage vectors, a first voltage vector, a second voltage vector, and a third voltage vector corresponding to each vertex of an equilateral triangle surrounding a command voltage vector as multiple voltage vectors to be used within a control period, and determines a first allocation time for the first voltage vector, a second allocation time for the second voltage vector, and a third allocation time for the third voltage vector so that a composite vector of the first voltage vector, the second voltage vector, and the third voltage vector coincides with the command voltage vector. When the command voltage vector is within a range of a reference hexagon defined by the 12 voltage vectors, the control device selects the first zero vector, the second zero vector, and the third zero vector as any of the first voltage vector, the second voltage vector, and the third voltage vector within the control period.

[0007] The multilevel inverter of the present disclosure has an effect of being able to suppress a temperature rise in the first clamp diode and the second clamp diode.

[0008] FIG. 1 is a circuit diagram of a system including a multilevel inverter according to a first embodiment. FIG. 2 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the first embodiment is in a first switching state. FIG. 3 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter according to the first embodiment is in the first switching state. FIG. 4 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the first embodiment is in a second switching state. FIG. 5 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter according to the first embodiment is in the second switching state. FIG. 6 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the first embodiment is in a third switching state. FIG. 7 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter according to the first embodiment is in the third switching state. FIG. 8 is an explanatory diagram of a voltage command value for each phase in the multilevel inverter according to the first embodiment. FIG. 9 is a space vector modulation diagram for explaining a group of voltage vectors related to the multilevel inverter according to the first embodiment. FIG. 10 is a more detailed space vector modulation diagram for explaining a group of voltage vectors related to the multilevel inverter according to the first embodiment. Fig. 11 is an explanatory diagram of a command voltage vector, a first voltage vector, a second voltage vector, and a third voltage vector in a first example in which the command voltage vector is located outside the range of a reference hexagon of a three-level space vector diagram (space vector modulation diagram) for the multilevel inverter according to embodiment 1. Fig. 12 is a time chart of switching states of each phase in a first example in which the command voltage vector is located outside the range of a reference hexagon of a three-level space vector diagram for the multilevel inverter according to embodiment 1. Fig. 13 is a time chart of on / off states of first to fourth switching elements corresponding to the U-phase in a first example in which the command voltage vector is located outside the range of a reference hexagon of a three-level space vector diagram for the multilevel inverter according to embodiment 1.FIG. 14 is an explanatory diagram of a command voltage vector, a first voltage vector, a second voltage vector, and a third voltage vector in a second example in which the command voltage vector is located within the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter according to the first embodiment. FIG. 15 is a time chart of the switching states of each phase in a second example in which the command voltage vector is located within the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter according to the first embodiment. FIG. 16 is a time chart of the on / off states of first to fourth switching elements corresponding to the U phase in a second example in which the command voltage vector is located within the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter according to the first embodiment. FIG. 17 is a time chart of the switching states of each phase in a multilevel inverter according to a comparative example. FIG. 18 is a time chart of the on / off states of the first to fourth switching elements of the multilevel inverter according to the first embodiment. 19 is a characteristic diagram showing time changes in the current of each phase, the temperature of the first clamp diode, the second switching element, and the diode connected in anti-parallel to the second switching element of the inverter circuit corresponding to the V phase, and the switching state of the V phase when the motor is locked in the multilevel inverter according to the comparative example. Fig. 20 is a characteristic diagram showing time changes in the current of each phase, the temperature of the first clamp diode, the second switching element, and the diode connected in anti-parallel to the second switching element of the inverter circuit corresponding to the V phase, and the switching state of the V phase when the motor is locked in the multilevel inverter according to the first embodiment. Fig. 21 is an explanatory diagram of a command voltage vector, a first voltage vector, a second voltage vector, and a third voltage vector for the multilevel inverter according to a first modification of the first embodiment. Fig. 22 is a circuit diagram of a system including the multilevel inverter according to the second embodiment.

[0009] First Embodiment A multilevel inverter 100 according to a first embodiment will be described below with reference to FIGS.

[0010] (1) Overview FIG. 1 is a circuit diagram of a system including a multilevel inverter 100 according to a first embodiment. As shown in FIG. 1 , the multilevel inverter 100 includes, for example, a DC power supply unit 3, a plurality of (e.g., three) inverter circuits 1, and a control device 6. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. Ideally, the "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. In the first embodiment, when the voltage across the DC power supply unit 3 is Vdc (e.g., 400 V), the potential of the positive electrode P1 is approximately Vdc, the potential of the negative electrode N1 is approximately 0 V, and the potential of the intermediate potential point M1 is approximately Vdc / 2.

[0011] The plurality of inverter circuits 1 are connected between a positive electrode P1 and a negative electrode N1 of the DC power supply unit 3. The control device 6 controls the plurality of inverter circuits 1 by space vector modulation.

[0012] The multilevel inverter 100 is a diode-clamped three-level, three-phase inverter. In the multilevel inverter 100, each of the multiple inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to the multiple output terminals (AC terminals) 41. The AC load RA1 is a Y-connected three-phase load in which three phase loads are Y-connected, and includes three phase loads. The AC load RA1 is, for example, a three-phase servo motor, and each of the three phase loads is a motor winding.

[0013] In the multilevel inverter 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining one is an inverter circuit 1W that outputs a W-phase voltage.

[0014] Each of the inverter circuits 1 has a first clamp diode D5 and a second clamp diode D6. In the multilevel inverter 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.

[0015] Each of the multiple inverter circuits 1 includes a switching circuit 10. Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive electrode P1 side to the negative electrode N1 side in this order.

[0016] The first clamp diode D5 has a cathode connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2, and an anode connected to the intermediate potential point M1. The second clamp diode D6 has an anode connected to a second connection point 12 between the third switching element Q3 and the fourth switching element Q4, and a cathode connected to the intermediate potential point M1.

[0017] In each of the plurality of inverter circuits 1, the switching circuit 10 has a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4.

[0018] The first diode D1 is connected in anti-parallel to the first switching element Q1. The second diode D2 is connected in anti-parallel to the second switching element Q2. The third diode D3 is connected in anti-parallel to the third switching element Q3. The fourth diode D4 is connected in anti-parallel to the fourth switching element Q4.

[0019] The multilevel inverter 100 further includes a plurality of (e.g., three) first gate drivers 61, a plurality of (e.g., three) second gate drivers 62, a plurality of (e.g., three) third gate drivers 63, a plurality of (e.g., three) fourth gate drivers 64, a plurality of (e.g., three) first bootstrap circuits 71, a plurality of (e.g., three) second bootstrap circuits 72, a plurality of (e.g., three) third bootstrap circuits 73, and a power supply unit 9. In this embodiment, a control system 60 including the control device 6 includes the plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the plurality of third bootstrap circuits 73, and the power supply unit 9.

[0020] The plurality of first gate drivers 61 drive the first switching elements Q1 of the plurality of inverter circuits 1. The plurality of second gate drivers 62 drive the second switching elements Q2 of the plurality of inverter circuits 1. The plurality of third gate drivers 63 drive the third switching elements Q3 of the plurality of inverter circuits 1. The plurality of fourth gate drivers 64 drive the fourth switching elements Q4 of the plurality of inverter circuits 1.

[0021] The plurality of first bootstrap circuits 71 are connected to the plurality of first gate drivers 61. The plurality of first bootstrap circuits 71 correspond one-to-one to the plurality of first gate drivers 61. The plurality of first bootstrap circuits 71 supply voltages to the corresponding first gate drivers 61.

[0022] The second bootstrap circuits 72 are connected to the second gate drivers 62. The second bootstrap circuits 72 correspond one-to-one to the second gate drivers 62. The second bootstrap circuits 72 supply voltages to the corresponding second gate drivers 62.

[0023] The third bootstrap circuits 73 are connected to the third gate drivers 63. The third bootstrap circuits 73 correspond one-to-one to the third gate drivers 63. The third bootstrap circuits 73 supply voltages to the corresponding third gate drivers 63.

[0024] The power supply unit 9 supplies a voltage to the plurality of fourth gate drivers 64 .

[0025] The control device 6 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64 .

[0026] (2) Details of the Multilevel Inverter The DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. In the DC power supply unit 3, a first end of the first capacitor C1 is connected to a first DC terminal 31, a second end of the first capacitor C1 is connected to a first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to a second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1. The DC power supply unit 3 further includes a first DC terminal 31 connected to a positive electrode P1 and a second DC terminal 32 connected to a negative electrode N1. A DC voltage source E1, for example, is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. The phrase "the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not necessarily mean that the capacitance of the second capacitor C2 exactly matches the capacitance of the first capacitor C1, but may mean that the capacitance of the second capacitor C2 is within a range of 95% to 105% of the capacitance of the first capacitor C1.

[0027] For convenience of explanation, in the following, with respect to the multiple switching circuits 10, the switching circuit 10 included in inverter circuit 1U will be referred to as switching circuit 10U, the switching circuit 10 included in inverter circuit 1V will be referred to as switching circuit 10V, and the switching circuit 10 included in inverter circuit 1W will be referred to as switching circuit 10W. Furthermore, of the multiple output terminals 41, the output terminal 41 included in inverter circuit 1U will be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V will be referred to as output terminal 41V, and the output terminal 41 included in inverter circuit 1W will be referred to as output terminal 41W. Furthermore, in the following, the polarities of load currents iU, iV, and iW flowing through the U, V, and W phases of AC load RA1, respectively, will be described as positive when flowing in the direction of the arrows in FIG. 1 and as negative when flowing in the direction opposite to the arrows in FIG.

[0028] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 each have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, insulated gate bipolar transistors (IGBTs). Therefore, the control terminal, the first main terminal, and the second main terminal of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, respectively, a gate terminal, a collector terminal, and an emitter terminal.

[0029] A control terminal of the first switching element Q1 of each switching circuit 10 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0030] In each switching circuit 10, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of the DC power supply 3, and a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2. In each switching circuit 10, a second main terminal of the second switching element Q2 is connected to a first main terminal of a third switching element Q3. In each switching circuit 10, a second main terminal of the third switching element Q3 is connected to a first main terminal of a fourth switching element Q4, and a second main terminal of the fourth switching element Q4 is connected to a negative electrode N1 of the DC power supply 3.

[0031] In the inverter circuit 1U, an output point (third connection point) 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10U is connected to the output terminal 41U. In the inverter circuit 1V, an output point (third connection point) 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10V is connected to the output terminal 41V. In the inverter circuit 1W, an output point (third connection point) 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10W is connected to the output terminal 41W. For example, a U-phase load of the AC load RA1 is connected to the output point 13 of the inverter circuit 1U via the output terminal 41U. For example, a V-phase load of the AC load RA1 is connected to the output point 13 of the inverter circuit 1V via the output terminal 41V. For example, a W-phase load of the AC load RA1 is connected to the output point 13 of the inverter circuit 1W via the output terminal 41W.

[0032] In each inverter circuit 1, the cathode of the first clamp diode D5 is connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the first clamp diode D5 is connected to an intermediate potential point M1 of the DC power supply unit 3. The cathode of the second clamp diode D6 is connected to the intermediate potential point M1. The anode of the second clamp diode D6 is connected to a second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0033] In each switching circuit 10, the anode of the first diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In each switching circuit 10, the anode of the second diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In each switching circuit 10, the anode of the third diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. In each switching circuit 10, the anode of the fourth diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0034] In each switching circuit 10, the first diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In each switching circuit 10, the second diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In each switching circuit 10, the third diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In each switching circuit 10, the fourth diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0035] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element Q1. The plurality of first gate drivers 61 are connected to a control device 6. The control device 6 outputs a plurality of first control signals S1 (see FIG. 2 ) that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0036] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of the corresponding second switching element Q2. Each of the second gate drivers 62 drives the corresponding second switching element Q2. The second gate drivers 62 are connected to a control device 6. The control device 6 outputs second control signals S2 (see FIG. 2 ) that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0037] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding third switching element Q3. Each of the plurality of third gate drivers 63 drives a corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control device 6. The control device 6 outputs a plurality of third control signals S3 (see FIG. 2 ) that correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0038] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding fourth switching element Q4. Each of the plurality of fourth gate drivers 64 drives a corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to a control device 6. The control device 6 outputs a plurality of fourth control signals S4 (see FIG. 2 ) that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0039] The first bootstrap circuits 71 correspond one-to-one to the first gate drivers 61. Each of the first bootstrap circuits 71 supplies a voltage to the corresponding first gate driver 61. Each of the first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (also referred to as a boost capacitor C17). In each first bootstrap circuit 71, the anode of the diode D17 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D17 is connected to a first end of the capacitor C17 via the resistor R17. The first end of the capacitor C17 is connected to a high-potential power supply terminal 61H (see FIG. 3 ) of the first gate driver 61, and the second end of the capacitor C17 is connected to a low-potential power supply terminal 61L (see FIG. 3 ) of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with a voltage required to turn on the first switching element Q1 in the first gate driver 61. Each of the plurality of first bootstrap circuits 71 further includes a Zener diode Z17 connected in parallel to the capacitor C17.

[0040] The second bootstrap circuits 72 correspond one-to-one to the second gate drivers 62. Each of the second bootstrap circuits 72 supplies a voltage to the corresponding second gate driver 62. Each of the second bootstrap circuits 72 includes a diode D27, a resistor R27, and a capacitor C27 (also referred to as a boost capacitor C27). In each second bootstrap circuit 72, the anode of the diode D27 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D27 is connected to a first end of the capacitor C27 via the resistor R27. The first end of the capacitor C27 is connected to a high-potential power supply terminal 62H (see FIG. 3 ) of the second gate driver 62, and the second end of the capacitor C27 is connected to a low-potential power supply terminal 62L (see FIG. 3 ) of the second gate driver 62. The second bootstrap circuit 72 supplies the second gate driver 62 with a voltage required to turn on the second switching element Q2 in the second gate driver 62. Each of the plurality of second bootstrap circuits 72 further includes a Zener diode Z27 connected in parallel with the capacitor C27.

[0041] The third bootstrap circuits 73 correspond one-to-one to the third gate drivers 63. Each of the third bootstrap circuits 73 supplies a voltage to the corresponding third gate driver 63. Each of the third bootstrap circuits 73 includes a diode D37, a resistor R37, and a capacitor C37 (also referred to as a boost capacitor C37). In each third bootstrap circuit 73, the anode of the diode D37 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D37 is connected to a first end of the capacitor C37 via the resistor R37. The first end of the capacitor C37 is connected to a high-potential power supply terminal 63H (see FIG. 3 ) of the third gate driver 63, and the second end of the capacitor C37 is connected to a low-potential power supply terminal 63L (see FIG. 3 ) of the third gate driver 63. The third bootstrap circuit 73 supplies the third gate driver 63 with a voltage required to turn on the third switching element Q3 in the third gate driver 63. Each of the plurality of third bootstrap circuits 73 further includes a Zener diode Z37 connected in parallel with the capacitor C37.

[0042] The power supply unit 9 supplies voltages to the plurality (three) of first bootstrap circuits 71, the plurality (three) of second bootstrap circuits 72, the plurality (three) of third bootstrap circuits 73, and the plurality (three) of fourth gate drivers 64. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. A positive terminal of the power supply unit 9 is connected to the high-potential power supply terminal 64H (see FIG. 3) of each of the plurality of fourth gate drivers 64, and a negative terminal of the power supply unit 9 is connected to the low-potential power supply terminal 64L (see FIG. 3) of each of the plurality of fourth gate drivers 64.

[0043] The control device 6 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control device 6 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control device 6 includes a computer system. The computer system has one or more computers. The computer system is mainly composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control device 6 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0044] FIG. 2 is an explanatory diagram of a current path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in a first switching state. FIG. 3 is an explanatory diagram of a discharge path and a charge path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in a first switching state. The control device 6 outputs a plurality of (three) first control signals S1 (see FIG. 2 ) for controlling a plurality of (three) first switching elements Q1, a plurality of (three) second control signals S2 (see FIG. 2 ) for controlling a plurality of (three) second switching elements Q2, a plurality of (three) third control signals S3 (see FIG. 2 ) for controlling a plurality of (three) third switching elements Q3, and a plurality of (three) fourth control signals S4 for controlling a plurality of (three) fourth switching elements Q4. Note that FIG. 2 illustrates only one of the three inverter circuits 1, and the remaining two inverter circuits 1 are not illustrated. 2 omits the illustration of the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, the plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the plurality of third bootstrap circuits 73, and the power supply unit 9. Also, in Fig. 3 , only one inverter circuit 1 of the three inverter circuits 1 is shown, and the illustration of the remaining two inverter circuits 1 is omitted. Also, in Fig. 3 , the illustration of the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, the two second bootstrap circuits 72, and the two third bootstrap circuits 73 is omitted.

[0045] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1W that controls the first switching element Q1 of the switching circuit 10W.

[0046] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2W that controls the second switching element Q2 of the switching circuit 10W.

[0047] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3W that controls the third switching element Q3 of the switching circuit 10W.

[0048] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W that controls the fourth switching element Q4 of the switching circuit 10W.

[0049] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) higher than the first potential level. The first potential level is, for example, 0 V, and the second potential level is a potential level higher than the gate threshold voltage of the IGBT. That is, in each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off a switching element corresponding to that control signal, and the second potential level is a potential level for turning on a switching element corresponding to that control signal.

[0050] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0051] In the multilevel inverter 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state differ from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Note that with regard to the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with one another.

[0052] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the ON state and both the third switching element Q3 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the output point 13 becomes the potential level (e.g., Vdc) of the positive electrode P1 of the DC power supply unit 3.

[0053] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state and both the second switching element Q2 and the third switching element Q3 are in the on state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the second switching state, the potential of the output point 13 becomes the potential level of the intermediate potential point M1 (e.g., Vdc / 2).

[0054] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the output point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., 0).

[0055] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in FIG. 2, a current flows through the path of the positive electrode P1 of the DC power supply unit 3 - the first switching element Q1 - the second switching element Q2 - the output point 13 - the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see FIG. 1) becomes approximately Vdc.

[0056] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the first gate driver 61 to turn on the first switching element Q1 is supplied from the capacitor C17 of the first bootstrap circuit 71 to the first gate driver 61. Therefore, as shown in FIG. 3 , the charge in the capacitor C17 of the first bootstrap circuit 71 is discharged through a discharge path Ru1 that connects the capacitor C17 to the high-potential power supply terminal 61H of the first gate driver 61, the low-potential power supply terminal 61L of the first gate driver 61, and the capacitor C17. As a result, in the first bootstrap circuit 71, the voltage across the capacitor C17 decreases over time.

[0057] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the second gate driver 62 to turn on the second switching element Q2 is supplied from capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62. Therefore, the charge in capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru2 that runs from capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62 to the low-potential power supply terminal 62L of the second gate driver 62 and back to capacitor C27. As a result, in the second bootstrap circuit 72, the voltage across capacitor C27 decreases over time.

[0058] 3 , if the voltage across capacitor C17 is Vo1, the voltage across capacitor C27 is Vo2, the voltage across diode D17 is Vd1, the voltage across resistor R17 is VR1, and the voltage across second switching element Q2 is Vf2, when switching circuit 10 of inverter circuit 1 is in the first switching state, capacitor C17 is charged by capacitor C27 if a first condition is met. The first condition is Vo2>(Vo1+Vd1+VR1+Vf2). A charging path Ru21 along which capacitor C17 is charged by capacitor C27 is the path of capacitor C27-resistor R27-diode D17-resistor R17-capacitor C1-first node 11-second switching element Q2-capacitor C27.

[0059] 4 is an explanatory diagram of a current path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the second switching state. When the switching circuit 10 of the inverter circuit 1 is in the second switching state, for example, as shown in FIG. 4 , a current flows through a path (indicated by a thick solid arrow) from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5, the second switching element Q2 of the switching circuit 10U, the output point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes approximately Vdc / 2. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, a current flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5, the second switching element Q2 of the switching circuit 10U, the output point 13, and the output terminal 41.

[0060] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, for example, as shown in Figure 4, a current flows through the path (indicated by the thick dashed arrow) of the output terminal 41-output point 13-third switching element Q3-second connection point 12-second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 may be approximately Vdc / 2. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the second switching state, and the first switching state, respectively, a current flows through the path (indicated by the thick dashed arrow) of the output terminal 41 of the inverter circuit 1U-output point 13-third switching element Q3-second connection point 12-second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 may be approximately Vdc / 2.

[0061] 5 is an explanatory diagram of the discharge path and charge path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the second switching state. When the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for turning on the second switching element Q2 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62 by the second gate driver 62. Therefore, as shown in FIG. 5, the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru2 that connects the capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62, the low-potential power supply terminal 62L of the second gate driver 62, and the capacitor C27. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for turning on the third switching element Q3 is supplied from the capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63 by the third gate driver 63. Therefore, the charge in the capacitor C37 of the third bootstrap circuit 73 is discharged through a discharge path Ru3 that runs from the capacitor C37 to the high potential power supply terminal 63H of the third gate driver 63 to the low potential power supply terminal 63L of the third gate driver 63 and back to the capacitor C37.

[0062] 5 , let Vo1, Vo2, and Vo3 be the voltages across capacitors C17, C27, and C37, VR1 and VR2 be the voltages across resistors R17 and R27, and Vf2 and Vf3 be the voltages across the second and third switching elements Q2 and Q3, respectively. When the switching circuit 10 of the inverter circuit 1 is in the second switching state, capacitor C27 is charged by capacitor C37 if a second condition is met, and capacitor C17 is charged by capacitor C27 if a third condition is met. The second condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). The third condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). A charging path Ru32 that charges capacitor C27 using capacitor C37 is a path of capacitor C37-resistor R37-diode D27-resistor R27-capacitor C27-output point 13-third switching element Q3-capacitor C37. A charging path Ru21 that charges capacitor C17 using capacitor C27 is a path of capacitor C27-resistor R27-diode D17-resistor R17-capacitor C17-first connection point 11-second switching element Q2-capacitor C27. A charging path Ru32 that charges capacitor C27 using capacitor C37 is a path of capacitor C37-resistor R37-diode D27-resistor R27-capacitor C27-output point 13-third switching element Q3-capacitor C37.

[0063] FIG. 6 is an explanatory diagram of a current path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the third switching state. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, as shown in FIG. 6, a current flows through the path from the negative pole N1 of the DC power supply unit 3 to the fourth switching element Q4, the third switching element Q3, the output point 13, and the output terminal 41U, and the voltage value of the output voltage to the AC load RA1 becomes zero. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C17 of the first bootstrap circuit 71 is charged, and the voltage of the capacitor C17 increases over time until the capacitor C17 is fully charged. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C27 of the second bootstrap circuit 72 (see FIG. 1) is charged, and the voltage of the capacitor C27 increases over time until the capacitor C27 is fully charged. 7 is an explanatory diagram of the discharge path and the charge path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the third switching state. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, a voltage required for turning on the third switching element Q3 is supplied from the capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63 by the third gate driver 63. Therefore, as shown in FIG. 7 , the charge in the capacitor C37 of the third bootstrap circuit 73 is discharged via a discharge path Ru3 that connects the capacitor C37 to the high-potential power supply terminal 63H of the third gate driver 63, the low-potential power supply terminal 63L of the third gate driver 63, and the capacitor C37. Furthermore, as shown in FIG. 7 , if the voltage across the power supply unit 9 is Voo, the voltages across capacitors C27 and C37 are Vo2 and Vo3, the voltages across resistors R27 and R37 are VR2 and VR3, and the voltages across the third switching element Q3 and the fourth switching element Q4 are Vf3 and Vf4, respectively, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, capacitor C37 is charged by the power supply unit 9 if the fourth condition is satisfied, and capacitor C27 is charged by capacitor C37 if the fifth condition is satisfied.The fourth condition is Voo > (Vo3 + Vd3 + VR3 + Vf4). The fifth condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). A charging path Ru93 along which the power supply unit 9 charges the capacitor C37 is a path from the positive terminal of the power supply unit 9 to the diode D37, the diode D27, the resistor R27, the capacitor C27, the output point 13, the third switching element Q3, the fourth switching element Q4, and the negative terminal of the power supply unit 9. A charging path Ru32 along which the capacitor C27 is charged by the capacitor C37 is a path from the capacitor C37 to the resistor R37, the diode D27, the resistor R27, the capacitor C27, the output point 13, the third switching element Q3, and the capacitor C37.

[0064] The control device 6 generates first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U, first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V, and first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W, based on voltage commands Vu, Vv, and Vw (see Figure 8) related to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0065] FIG. 8 is an explanatory diagram of voltage command values ​​for each phase in the multilevel inverter 100 according to the first embodiment. As shown in FIG. 8 , the voltage command Vu, voltage command Vv, and voltage command Vw are sinusoidal signals, each having a phase difference of 120°, and their respective values ​​(voltage command values) change over time. The voltage command Vu, voltage command Vv, and voltage command Vw have the same cycle length. The control device 6 may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detector 8 that detects the state of the AC load RA1. When the AC load RA1 is a three-phase servo motor, the information output from the detector 8 includes, for example, at least one of information on the detection results of a plurality of current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1 and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase motor.

[0066] The output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0067] The control device 6 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing space vector modulation (hereinafter also referred to as voltage vector control).

[0068] The voltage vector control by the control device 6 will be described in more detail below.

[0069] The control device 6 stores a group of voltage vectors in advance. Each of the group of voltage vectors is determined by a combination of the potential levels of the output points 13 between the second switching elements Q2 and the third switching elements Q3 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3. ３ = 27 pieces.

[0070] 9 is a space vector modulation diagram for explaining a group of voltage vectors related to the multilevel inverter 100 according to the first embodiment. The group of voltage vectors includes three zero vectors V0p, V0n, and V0z, each of which has a magnitude of zero, as shown in the three-level space vector diagram (space vector modulation diagram) in FIG. 9. The group of voltage vectors also includes three zero vectors V0p, V0n, and V0z, each of which has a magnitude of (2 / 3) １／２ The group of voltage vectors includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which is 2 Vdc and points in different directions. The magnitude of each of the voltage vectors is (2 / 3) １／２ The group of voltage vectors includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3) １／２ ・3 １／２Six voltage vectors V13, V14, V15, V16, V17, and V18 are Vdc and have different directions. １／２ Vdc is the reference magnitude. In Figure 9, the angle between two adjacent voltage vectors of the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between two adjacent voltage vectors of the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 9 is a three-level space vector diagram illustrating a group of voltage vectors on an orthogonal d-q coordinate system.

[0071] 10 is a more detailed space vector modulation diagram for explaining a group of voltage vectors related to the multilevel inverter 100 according to embodiment 1. The group of voltage vectors can be expressed as a three-level space vector diagram (space vector modulation diagram) shown in FIG. 10 when the first switching state, the second switching state, and the third switching state are represented by the symbols “P,” “0,” and “N,” respectively, and the U phase, V phase, and W phase are written in that order.

[0072] 10 , the three zero vectors V0p, V0z, and V0n can be expressed as V0p[PPP], V0z

[000] , and V0n[NNN], respectively. For example, V0p[PPP] represents that, with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P," the switching state of the V-phase switching circuit 10V is "P," and the switching state of the W-phase switching circuit 10W is "P." Furthermore, V0z

[000] represents that, with respect to the zero vector V0z, the switching state of the U-phase switching circuit 10U is "0," the switching state of the V-phase switching circuit 10V is "0," and the switching state of the W-phase switching circuit 10W is "0." Furthermore, V0n[NNN] represents that, with respect to the zero vector V0n, the switching state of the U-phase switching circuit 10U is "N", the switching state of the V-phase switching circuit 10V is "N", and the switching state of the W-phase switching circuit 10W is "N". When the switching state of the switching circuit 10 is "P", the potential of the output point 13 of the switching circuit 10 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "N", the potential of the output point 13 of the switching circuit 10 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "0", the potential of the output point 13 of the switching circuit 10 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0073] Furthermore, a voltage vector with a "p" suffix, such as V10p, includes a "P" but does not include an "N". This also applies below. Furthermore, a voltage vector with an "n" suffix, such as V10n, includes an "N" but does not include a "P". This also applies below.

[0074] The six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors without "p," "n," or "o" after the number attached to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases. A group of voltage vectors includes six voltage vectors, V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], each of which has a magnitude twice the reference magnitude.

[0075] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively. Therefore, the group of voltage vectors includes 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], each of which has a reference magnitude as a voltage vector (reference vector).

[0076] The six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively. １／２ The voltage vectors are twice as large as the voltage vectors V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0].

[0077] The control device 6 converts the instantaneous value of the command voltage related to the output voltage of each of the multiple inverter circuits 1 into a command voltage vector Vref (see FIGS. 11 and 14). If the α-axis component of the command voltage vector Vref on the orthogonal α-β coordinate system (see FIG. 9) is Vα and the β-axis component of the command voltage vector Vref on the orthogonal α-β coordinate system is Vβ, the command voltage vector Vref can be calculated using equation (1).

[0078]

[0079] The control device 6 selects a first voltage vector Va, a second voltage vector Vb, and a third voltage vector Vc corresponding to the vertices of an equilateral triangle surrounding the command voltage vector Vref as multiple voltage vectors to be used within a control period Ts (see Figures 12, 13, 15, and 16) from the group of voltage vectors, and determines a first allocation time T0 for the first voltage vector Va, a second allocation time T1 for the second voltage vector Vb, and a third allocation time T2 for the third voltage vector Vc so that the resultant vector of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc coincides with the command voltage vector Vref.

[0080] The control device 6 determines T0, T1, and T2 so as to satisfy equations (2) and (3), where the voltage vectors at the vertices of an equilateral triangle surrounding the command voltage vector Vref are the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc, and the magnitude and angle of the command voltage vector Vref are V and θ, respectively. "j" in equation (2) is an imaginary unit. The angle between the first voltage vector Va, which is closest to the command voltage vector Vref, and the command voltage vector Vref is smaller than 30 degrees.

[0081]

[0082]

[0083] In addition, the control device 6 distributes the first distribution time T0 to each first voltage vector Va based on the number of times the first voltage vector Va is used within the control period Ts, distributes the second distribution time T1 to each second voltage vector Vb based on the number of times the second voltage vector Vb is used within the control period Ts, and distributes the third distribution time T2 based on the number of times the third voltage vector Vc is used within the control period Ts.

[0084] Below, with regard to operation examples of the control device 6, a first control mode when the command voltage vector Vref is located outside the range of the reference hexagon A1 of the three-level space vector modulation diagram will be described based on the first example shown in Figures 11 to 13, and a second control mode when the command voltage vector Vref is located within the range of the reference hexagon A1 will be described based on the second example shown in Figures 14 to 16. In this embodiment, the reference hexagon A1 is a hexagon defined by 12 voltage vectors, each of which has a magnitude equal to that of the reference vector. "The reference hexagon A1 is defined by 12 voltage vectors, each of which has a magnitude equal to the magnitude of the reference vector" means that two voltage vectors out of the 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0] are located at each of the six vertices of the reference hexagon A1. Furthermore, an example of the operation of the control device for a multilevel inverter according to the comparative example will be described with reference to FIGS. 17 and 18.

[0085] 11 is an explanatory diagram of the command voltage vector, the first voltage vector, the second voltage vector, and the third voltage vector in a first example in which the command voltage vector is located outside the range of the reference hexagon of the three-level space vector diagram (space vector modulation diagram) for the multilevel inverter 100 according to the first embodiment. In the first example shown in FIG. 11, the first voltage vector Va is the voltage vector V8p[PP0] and the voltage vector V8n[00N], the second voltage vector Vb is the voltage vector V13[P0N], and the third voltage vector Vc is the voltage vector V7p[P00]. FIG. 12 is a time chart of the switching states of each phase in a first example in which the command voltage vector is located outside the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter 100 according to the first embodiment. FIG. 12 shows the switching states of the U phase, the V phase, and the W phase when the control device 6 sequentially uses eight voltage vectors within a control period Ts. FIG. 13 is a time chart showing the on / off states of the first to fourth switching elements corresponding to the U-phase in a first example in which the command voltage vector is located outside the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter 100 according to the first embodiment. FIG. 13 shows the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the U-phase when the control device 6 sequentially uses eight voltage vectors within a control period Ts. FIG. 12 illustrates a case in which, during the control period Ts, the allocation time of the first voltage vector Va (voltage vector V8p[PP0] and voltage vector V8n[00N]) is T0, the allocation time of the second voltage vector Vb (voltage vector V13[P0N]) is T1, and the allocation time of the third voltage vector Vc (voltage vector V7p[P00]) is T2. The control period Ts is one period of the carrier signal.

[0086] In the first control mode, when changing the switching states of two adjacent voltage vectors among eight voltage vectors arranged in time series within a control period Ts, the control device 6 changes the switching state of only one of the U, V, and W phases between "P" and "0" or between "0" and "N," and uses the same voltage vector twice. In Fig. 12, the control device 6 uses the voltage vectors in the following order: voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. 12 , the control device 6 uses the first voltage vector Va four times, and therefore the allocation time for each of the first voltage vector Va (voltage vector V8n[00N]) used first within the control period Ts, the first voltage vector Va (voltage vector V8p[PP0]) used fourth, the first voltage vector Va (voltage vector V8p[PP0]) used fifth, and the first voltage vector Va (voltage vector V8n[00N]) used eighth within the control period Ts is set to T0 / 4. Also, in the example of FIG. 12 , the control device 6 uses the second voltage vector Vb twice, and therefore the allocation time for each of the second voltage vector Vb (voltage vector V13[P0N]) used second within the control period Ts and the second voltage vector Vb (voltage vector V13[P0N]) used seventh within the control period Ts is set to T1 / 2. In addition, in the example of Figure 12, the control device 6 uses the third voltage vector Vc twice, so the allocation time of each of the third voltage vector Vc (voltage vector V7p[P00]) used third and the third voltage vector Vc (voltage vector V7p[P00]) used sixth within the control period Ts is T2 / 2.

[0087] The control device 6 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 within a predetermined control period Ts (see FIG. 12) so as to make the resultant vector of the first voltage vector Va (in the first example shown in FIG. 11, the voltage vector V8p[PP0] and the voltage vector V8n[00N]), the second voltage vector Vb (in the first example shown in FIG. 11, the voltage vector V13[P0N]), and the third voltage vector Vc (in the first example shown in FIG. 11, the voltage vector V7p[P00]) match the command voltage vector Vref.

[0088] In the multilevel inverter according to the comparative example, when one of the vertices of an equilateral triangle surrounding a command voltage vector is located at the origin of a three-level space vector diagram, only the zero vector V0z

[000] is selected as the second voltage vector among the first voltage vector, the second voltage vector, and the third voltage vector located at the vertices of the equilateral triangle. The selection of only the zero vector V0z

[000] is similar to the operation of the space vector modulation switch control device disclosed in Patent Document 1.

[0089] In contrast, the control device 6 operates in the second control mode when the command voltage vector Vref is located within the range of the reference hexagon A1 and one of the vertices of the equilateral triangle surrounding the command voltage vector Vref is located at the origin of the three-level space vector diagram. In the second control mode, the control device 6 selects, within a control period Ts, the zero vector V0p[PPP] (hereinafter also referred to as the first zero vector V0p[PPP]), the zero vector V0z

[000] (hereinafter also referred to as the second zero vector V0z

[000] ), or the zero vector V0n[NNN] (hereinafter also referred to as the third zero vector V0n[NNN]) as one of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc (in this embodiment, the second voltage vector Vb).

[0090] In the second example shown in Figures 14 to 16, the control device 6 selects the voltage vector V8p[PP0] and the voltage vector V8n[00N] as the first voltage vector Va, selects the first zero vector V0p[PPP], the second zero vector V0z

[000] , and the third zero vector V0n[NNN] as the second voltage vector Vb, and selects the voltage vector V7p[P00] and the voltage vector V7n[0NN] as the third voltage vector Vc.

[0091] 14 is an explanatory diagram of the command voltage vector, the first voltage vector, the second voltage vector, and the third voltage vector in a second example in which the command voltage vector is located within the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter 100 according to the first embodiment. In FIG. 14, the first voltage vector Va is the voltage vector V8p[PP0] and the voltage vector V8n[00N], the second voltage vector Vb is the first zero vector V0p[PPP], the second zero vector V0z

[000] , and the third zero vector V0n[NNN], and the third voltage vector Vc is the voltage vector V7p[P00] and the voltage vector V7n[0NN]. FIG. 15 is a time chart of the switching states of each phase in the second example in which the command voltage vector is located within the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter 100 according to the first embodiment. Fig. 15 shows the switching states of the U-phase, V-phase, and W-phase when the control device 6 sequentially uses eight voltage vectors within a control period Ts. Fig. 16 is a time chart showing the on / off states of the first to fourth switching elements corresponding to the U-phase in a second example in which the command voltage vector is located within the range of the reference hexagon of the three-level space vector diagram for the multilevel inverter 100 according to the first embodiment. Fig. 16 shows the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the U-phase when the control device 6 sequentially uses eight voltage vectors within a control period Ts. 15 illustrates an example in which, during a control period Ts, the allocated time of the first voltage vector Va (voltage vector V8p[PP0] and voltage vector V8n[00N]) is set to a first allocated time T0, the allocated time of the second voltage vector Vb (first zero vector V0p[PPP], second zero vector V0z

[000] , and third zero vector V0n[NNN]) is set to a second allocated time T1, and the allocated time of the third voltage vector Vc (voltage vector V7p[P00] and voltage vector V7n[0NN]) is set to a third allocated time T2. Here, in the second control mode, the second allocated time T1 is set to T1=T1p+T1z+T1n.T1p is the time allocated to the first zero vector V0p [PPP], T1z is the time allocated to the second zero vector V0z

[000] , and T1n is the time allocated to the third zero vector V0n [NNN].

[0092] The control period Ts is one period of the carrier signal. In the second control mode, when changing the switching states of two adjacent voltage vectors among eight voltage vectors arranged in time series within the control period Ts, the control device 6 changes the switching state of only one of the U phase, V phase, and W phase between “P” and “0” or between “0” and “N,” uses the first voltage vector Va and the third voltage vector Vc twice each, and uses the first zero vector V0p [PPP], the second zero vector V0z

[000] , and the third zero vector V0n [NNN] as the second voltage vector Vb. 15, the control device 6 uses the first zero vector V0p[PPP] → voltage vector V8p[PP0] → voltage vector V7p[P00] → second zero vector V0z

[000] → second zero vector V0z

[000] → voltage vector V8n[00N] → voltage vector V7n[0NN] → third zero vector V0n[NNN] in this order. In the example of Fig. 15, the control device 6 uses the first voltage vector Va twice, and therefore, the allocation time of each of the first voltage vector Va (voltage vector V8p[PP0]) used second and the first voltage vector Va (voltage vector V8n[00N]) used sixth within the control period Ts is T0 / 2. 15 , the control device 6 uses the second voltage vector Vb four times, and the allocation time of the second voltage vector Vb (first zero vector V0p[PPP]) used first within the control period Ts is T1p, the allocation time of the second voltage vector Vb (second zero vector V0z

[000] ) used fourth and the second voltage vector Vb (second zero vector V0z

[000] ) used fifth are each set to T1z / 2, and the allocation time of the second voltage vector Vb (third zero vector V0n[NNN]) used eighth is set to T1n. Also, in the example of FIG. 15 , the control device 6 uses the third voltage vector Vc twice, and therefore the allocation time of the third voltage vector Vc (voltage vector V7p[P00]) used third and the third voltage vector Vc (voltage vector V7n[0NN]) used seventh within the control period Ts is T2 / 2.

[0093] The control device 6 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 within a predetermined control period Ts (see FIG. 15) so that a resultant vector of a first voltage vector Va (in the second example shown in FIG. 14, the voltage vector V8p[PP0] and the voltage vector V8n[00N]), a second voltage vector Vb (in the second example shown in FIG. 14, the first zero vector V0p[PPP], the second zero vector V0z

[000] , and the third zero vector V0n[NNN]), and a third voltage vector Vc (in the second example shown in FIG. 14, the voltage vector V7p[P00] and the voltage vector V7n[0NN]) matches the command voltage vector Vref.

[0094] In the multilevel inverter according to the comparative example, when one of the vertices of an equilateral triangle surrounding the command voltage vector is located at the origin of the three-level space vector diagram, the control device selects only the zero vector V0z

[000] as the second voltage vector among the first voltage vector, second voltage vector, and third voltage vector located at the vertices of the equilateral triangle. Note that the operation of the control device for the multilevel inverter according to the comparative example is the same as in the first control mode of the control device 6, regardless of the position of the command voltage vector.

[0095] Therefore, when the command voltage vector is the same as the command voltage vector in Figure 14, the control device for the multilevel inverter of the comparative example selects the voltage vector V8p[PP0] and the voltage vector V8n[00N] as the first voltage vector, selects the zero vector V0z

[000] as the second voltage vector, and selects the voltage vector V7p[P00] as the third voltage vector within the control period Ts (see Figures 17 and 18).

[0096] Fig. 17 is a time chart showing the switching states of each phase of the multilevel inverter 100 according to the comparative example. Fig. 17 shows the switching states of the U phase, V phase, and W phase when the control device of the comparative example sequentially uses eight voltage vectors within a control period Ts. Fig. 18 is a time chart showing the on / off states of the first switching element Q1 to the fourth switching element Q4 of the multilevel inverter 100 according to the first embodiment. Fig. 18 shows the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the U phase when the control device of the comparative example sequentially uses eight voltage vectors within a control period Ts. 17 illustrates a case where the control device of the comparative example allocates the first voltage vector (voltage vector V8p[PP0] and voltage vector V8n[00N]) time T0, the second voltage vector Vb (zero vector V0z

[000] ) time T1, and the third voltage vector Vc (voltage vector V7p[P00]) time T2 during a control period Ts. The control period Ts is one period of the carrier signal.

[0097] In the control device of the comparative example, when changing the switching states of two adjacent voltage vectors among the eight voltage vectors arranged in time series within a control period Ts, the switching state of only one of the U, V, and W phases is changed between "P" and "0" or between "0" and "N," and the same voltage vector is used twice. In Fig. 17, the control device of the comparative example uses the voltage vector V8n[00N] → zero vector V0z

[000] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → zero vector V0z

[000] → voltage vector V8n[00N] in this order. 17, the control device uses the first voltage vector four times, and therefore the allocation time for each of the first voltage vector (voltage vector V8n[00N]) used first within the control period Ts, the fourth voltage vector (voltage vector V8p[PP0]), the fifth voltage vector (voltage vector V8p[PP0]), and the eighth voltage vector (voltage vector V8n[00N]) is set to T0 / 4. Also, in the example of FIG. 17, the control device of the comparative example uses the second voltage vector twice, and therefore the allocation time for each of the second voltage vector (zero vector V0z

[000] ) used second within the control period Ts and the seventh voltage vector (zero vector V0z

[000] ) is set to T1 / 2. In addition, in the example of Figure 17, the control device of the comparative example uses the third voltage vector twice, so the allocation time of each of the third voltage vector (voltage vector V7p[P00]) used third and the third voltage vector (voltage vector V7p[P00]) used sixth within the control period Ts is T2 / 2.

[0098] As can be seen from Figures 15 and 17, the control device 6 of this embodiment replaces the two zero vectors V0z

[000] of the second allocation time T1 within the control period Ts in the comparative example with a first zero vector V0p[PPP], a second zero vector V0z

[000] , and a third zero vector V0n[NNN], and divides the second allocation time T1 into allocation time T1p, allocation time T1z, and allocation time T1n.

[0099] In the multilevel inverter 100 according to the first embodiment, the control device 6 also uses the third zero vector V0n in the second control mode. Therefore, as shown in FIG. 15 , a period in which the switching state of the U phase is “N”, a period in which the switching state of the V phase is “N”, and a period in which the switching state of the W phase is “N” can be generated. As a result, the multilevel inverter 100 according to the first embodiment can generate a third switching state in which, for example, as shown in FIG. 16 , the first switching element Q1 and the second switching element Q2 of the switching circuit 10U are both in the OFF state and the third switching element Q3 and the fourth switching element Q4 are both in the ON state. Therefore, the multilevel inverter 100 according to the first embodiment can suppress a voltage drop across the capacitor C27 of the second bootstrap circuit 72. Furthermore, because there are periods in which the switching state of the V phase and the switching state of the W phase are both “N”, the capacitor C27 of the second bootstrap circuit 72 corresponding to each of the switching circuits 10V and 10W is charged and maintains its voltage. Therefore, the second control mode of the control device 6 of the multilevel inverter 100 according to the first embodiment also serves as a charging mode in which the capacitor C27 of the second bootstrap circuit 72 of each of the three switching circuits 10U, 10V, and 10W can be charged.

[0100] (3) Characteristics In the multilevel inverter according to the comparative example, for example, when a three-phase servo motor serving as an AC load locks, the U-phase load current iU, the V-phase load current iV, and the W-phase load current iW each remain substantially constant, and the temperature of the first clamp diode or the second clamp diode tends to rise. Figure 19 is a characteristic diagram showing the time variations of the currents of each phase, the temperatures of the first clamp diode, the second switching element, and the diode connected in anti-parallel to the second switching element in the inverter circuit corresponding to the V-phase, and the switching state of the V-phase switching circuit when the motor locks in the multilevel inverter according to the comparative example. Figure 19 also shows the temperatures of the first clamp diode, the second switching element, and the second diode in the inverter circuit corresponding to the V-phase, and the switching state of the V-phase switching circuit when, for example, the polarity of the U-phase load current iU is negative, the polarity of the V-phase load current iV is positive, and the polarity of the W-phase load current iW is negative when the three-phase servo motor locks. In Figure 19, the timing when the three-phase servo motor locks is represented as 0 on the time axis. In the comparative example, the V-phase switching state changes between "0" and "N" and is mainly "0." Therefore, the current flowing through the first V-phase clamp diode increases the loss in the first clamp diode, and the temperature of the first clamp diode is more likely to rise than the temperatures of the second switching element and the second diode. From Figure 19, it can be seen that the temperature of the first clamp diode rises to the allowable temperature Ta (125°C) of the first clamp diode in approximately 1.4 ms and continues to rise. The allowable temperature Ta is the allowable junction temperature of the first clamp diode.

[0101] In the multilevel inverter 100 according to the first embodiment, for example, when a three-phase servo motor serving as the AC load RA1 is locked, the U-phase load current iU, the V-phase load current iV, and the W-phase load current iW each become substantially constant, as in the multilevel inverter according to the comparative example. Fig. 20 is a characteristic diagram showing the time variations of the currents of each phase, the first clamp diode D5, the second switching element Q2, and the diode D2 connected in anti-parallel to the second switching element Q2 in the inverter circuit corresponding to the V-phase when the motor is locked in the multilevel inverter 100 according to the first embodiment. Fig. 20 shows the temperatures of the first clamp diode D5, the second switching element Q2, and the second diode D2 in the inverter circuit 1V corresponding to the V-phase, and the switching state of the V-phase switching circuit 10V, for example, when the polarity of the U-phase load current iU is negative, the polarity of the V-phase load current iV is positive, and the polarity of the W-phase load current iW is negative when the three-phase servo motor is locked. In FIG. 20, the timing at which the three-phase servo motor is locked is set as 0 on the time axis.

[0102] However, in the multilevel inverter 100 according to the first embodiment, when the command voltage vector V is within the range of the reference hexagon A1, the control device 6 operates in the second control mode. Therefore, the switching state changes between "P," "0," and "N," thereby reducing loss in the first clamp diode D5 of the V phase. This allows the multilevel inverter 100 according to the first embodiment to suppress a temperature rise in the first clamp diode D5. In FIG. 20 , the temperature of the first clamp diode D5 rises to the allowable temperature Ta (125° C.) of the first clamp diode D5 in approximately 40 ms. The allowable temperature Ta is the allowable junction temperature of the first clamp diode D5. Furthermore, in the multilevel inverter 100 according to the first embodiment, the temperature of the first clamp diode D5 is reduced compared to the comparative example, while the temperature of the second diode D2 increases. As a result, the temperatures of the first clamp diode D5, the second switching element Q2, and the second diode D2 of the V phase are substantially the same. In this embodiment, the first clamp diode D5, the second switching element Q2, and the second diode D2 are all Si-based devices, and therefore the allowable temperatures of the second switching element Q2 and the second diode D2 are the same as the allowable temperature Ta of the first clamp diode D5.

[0103] Furthermore, in the multilevel inverter 100 according to the first embodiment, for example, when the three-phase servo motor that is the AC load RA1 is locked, if the polarity of the load current iU in the U phase is negative, the polarity of the load current iV in the V phase is negative, and the polarity of the load current iW in the W phase is positive, it is possible to suppress a temperature rise in the first clamp diode D5 in the inverter circuit 1W corresponding to the W phase.

[0104] Furthermore, in the multilevel inverter 100 according to the first embodiment, for example, when the three-phase servo motor that is the AC load RA1 is locked, if the polarity of the load current iU in the U phase is positive, the polarity of the load current iV in the V phase is negative, and the polarity of the load current iW in the W phase is negative, it is possible to suppress a temperature rise in the first clamp diode D5 in the inverter circuit 1U corresponding to the U phase.

[0105] Furthermore, in the multilevel inverter 100 according to the first embodiment, for example, when the three-phase servo motor that is the AC load RA1 is locked, if the polarity of the load current iU in the U phase is positive, the polarity of the load current iV in the V phase is negative, and the polarity of the load current iW in the W phase is positive, it is possible to suppress a temperature rise in the second clamp diode D6 in the inverter circuit 1V corresponding to the V phase.

[0106] Furthermore, in the multilevel inverter 100 according to the first embodiment, for example, when the three-phase servo motor that is the AC load RA1 is locked, if the polarity of the load current iU in the U phase is positive, the polarity of the load current iV in the V phase is positive, and the polarity of the load current iW in the W phase is negative, it is possible to suppress a temperature rise in the second clamp diode D6 in the inverter circuit 1W corresponding to the W phase.

[0107] Furthermore, in the multilevel inverter 100 according to the first embodiment, for example, when the three-phase servo motor serving as the AC load RA1 is locked, if the polarity of the U-phase load current iU is negative, the polarity of the V-phase load current iV is positive, and the polarity of the W-phase load current iW is positive, it is possible to suppress a temperature rise in the second clamp diode D6 in the inverter circuit 1U corresponding to the U-phase. The allowable temperature of the second clamp diode D6 is the same as the allowable temperature Ta of the first clamp diode D5.

[0108] (4) Advantages In the multilevel inverter 100 according to the first embodiment, the control device 6 stores a group of voltage vectors determined by a combination of potential levels of a plurality of output points 13. The group of voltage vectors includes 12 voltage vectors, each of which has a reference magnitude, 6 voltage vectors, each of which has a magnitude twice the reference magnitude, and 3 voltage vectors, each of which has a magnitude three times the reference magnitude. １／２The control unit 6 selects six voltage vectors, each having a magnitude twice the magnitude of the first voltage vector Va, a first zero vector V0p [PPP] representing a combination in which the potential levels of the plurality of output points 13 are all at the potential of the positive pole P1, a second zero vector V0z

[000] representing a combination in which the potential levels of the plurality of output points 13 are all at the potential of the intermediate potential point M1, and a third zero vector V0n [NNN] representing a combination in which the potential levels of the plurality of output points 13 are all at the potential of the negative pole N1 from the group of voltage vectors. The control unit 6 selects a first voltage vector Va, a second voltage vector Vb, and a third voltage vector Vc corresponding to the vertices of an equilateral triangle surrounding the command voltage vector Vref as the plurality of voltage vectors to be used within the control period Ts, and determines a first allocated time T0 for the first voltage vector Va, a second allocated time T1 for the second voltage vector Vb, and a third allocated time T2 for the third voltage vector Vc so that a composite vector of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc coincides with the command voltage vector Vref. When the command voltage vector Vref is within the range of the reference hexagon A1 defined by the above 12 voltage vectors, the control device 6 selects the first zero vector V0p [PPP], the second zero vector V0z

[000] , and the third zero vector V0n [NNN] as one of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc within the control period Ts.

[0109] According to the above configuration, it is possible to suppress the temperature rise of the first clamp diode D5 and the second clamp diode D6.

[0110] Furthermore, in the multilevel inverter 100 according to the first embodiment, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to the plurality of fourth gate drivers 64 and the plurality of third bootstrap circuits 73 .

[0111] According to the above configuration, it is possible to achieve miniaturization.

[0112] (4) Modification of Embodiment 1 Hereinafter, a description will be given of a modification of Embodiment 1. The circuit configuration of the multilevel inverter 100 according to the modification is the same as the circuit configuration of the multilevel inverter 100 according to Embodiment 1 (see FIG. 1 ), and therefore, illustration and description thereof will be omitted.

[0113] 21 is an explanatory diagram of a command voltage vector, a first voltage vector, a second voltage vector, and a third voltage vector for the multilevel inverter 100 according to the first modification of the first embodiment. In the multilevel inverter 100 according to the first modification of the first embodiment, a second reference hexagon A2 smaller than the first reference hexagon A1 is used instead of the first reference hexagon A1 (see FIG. 14). The second reference hexagon A2 is a hexagon set inside the first reference hexagon A1.

[0114] The operation of the control device 6 is the same as in the first embodiment, except that the second reference hexagon A2 is used instead of the first reference hexagon A1 when determining whether to switch between the first control mode and the second control mode.

[0115] The multilevel inverter 100 according to the modified example also has the same advantages as the multilevel inverter 100 according to the first embodiment.

[0116] (Embodiment 2) A multilevel inverter 100A according to embodiment 2 will be described with reference to Fig. 22. Fig. 22 is a circuit diagram of a system including the multilevel inverter 100A according to embodiment 2. Regarding the multilevel inverter 100A according to embodiment 2, components similar to those of the multilevel inverter 100 according to embodiment 1 (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0117] (1) Configuration The multilevel inverter 100A according to the second embodiment differs from the multilevel inverter 100 according to the first embodiment in that the power supply unit 9 includes a plurality of (for example, three) DC-DC converters 91.

[0118] The plurality of DC-DC converters 91 correspond one-to-one to the plurality of (three) fourth gate drivers 64 , and supply voltages to the corresponding fourth gate drivers 64 .

[0119] In the multilevel inverter 100A according to the second embodiment, in each of the first bootstrap circuits 71, an anode of a diode D17 is connected to the positive terminal of a corresponding one of the plurality of DC-DC converters 91. In each of the second bootstrap circuits 72, an anode of a diode D27 is connected to the positive terminal of a corresponding one of the plurality of DC-DC converters 91. In each of the third bootstrap circuits 73, an anode of a diode D37 is connected to the positive terminal of a corresponding one of the plurality of DC-DC converters 91.

[0120] (2) Operation The operation of the control device 6 is the same as in the first embodiment, and therefore a description thereof will be omitted.

[0121] (3) Advantages Like the multilevel inverter 100 according to the first embodiment, the multilevel inverter 100A according to the second embodiment can suppress the temperature rise of the first clamp diode D5 and the second clamp diode D6.

[0122] (Other Modifications) The above-described first and second embodiments are merely examples of various embodiments of the present disclosure. The above-described first and second embodiments can be modified in various ways depending on the design and the like as long as the object of the present disclosure can be achieved.

[0123] For example, each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 is not limited to an IGBT but may be a MOSFET. In this case, the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are a gate terminal, a drain terminal, and a source terminal, respectively. In each switching circuit 10, the MOSFETs constituting each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are, for example, normally-off n-channel MOSFETs. Note that although the MOSFETs are Si-based MOSFETs, they are not limited to Si-based MOSFETs and may be, for example, SiC-based MOSFETs.

[0124] Furthermore, the multilevel inverter 100 may be configured without including the plurality of first bootstrap circuits 71 , the plurality of second bootstrap circuits 72 , the plurality of third bootstrap circuits 73 , and the power supply unit 9 .

[0125] Furthermore, each of the first bootstrap circuits 71 includes a resistor R17 but may not include the resistor R17. Each of the second bootstrap circuits 72 includes a resistor R27 but may not include the resistor R27. Each of the third bootstrap circuits 73 includes a resistor R37 but may not include the resistor R37.

[0126] Furthermore, each of the plurality of first bootstrap circuits 71 includes the Zener diode Z17, but may not include the Zener diode Z17. Furthermore, each of the plurality of second bootstrap circuits 72 includes the Zener diode Z27, but may not include the Zener diode Z27. Furthermore, each of the plurality of third bootstrap circuits 73 includes the Zener diode Z37, but may not include the Zener diode Z37.

[0127] (Aspects) The following aspects are disclosed in this specification.

[0128] A multilevel inverter (100; 100A) according to a first aspect includes a DC power supply unit (3), a plurality of inverter circuits (1), and a control device (6). The DC power supply unit (3) has a positive pole (P1), a negative pole (N1), and an intermediate potential point (M1). The plurality of inverter circuits (1) are connected between the positive pole (P1) and the negative pole (N1) of the DC power supply unit (3). The plurality of inverter circuits (1) are connected between the positive pole (P1) and the negative pole (N1) of the DC power supply unit (3). The control device (6) controls the plurality of inverter circuits (1) by space vector modulation. Each of the plurality of inverter circuits (1) includes a switching circuit (10), a first clamp diode (D5), and a second clamp diode (D6). The switching circuit (10) includes a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4). In the switching circuit (10), the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4) are connected in series from the positive electrode (P1) side to the negative electrode (N1) side in the order of the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4). The first clamp diode (D5) has a cathode connected to a first connection point (11) between the first switching element (Q1) and the second switching element (Q2), and an anode connected to an intermediate potential point (M1). The second clamp diode (D6) has an anode connected to a second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4), and a cathode connected to the intermediate potential point (M1). The switching circuit (10) has an output point (13) between the second switching element (Q2) and the third switching element (Q3). The control device (6) stores a group of voltage vectors determined by a combination of potential levels of the plurality of output points (13). The group of voltage vectors includes 12 voltage vectors each having a reference magnitude, 6 voltage vectors each having a magnitude twice the reference magnitude, and 3 voltage vectors each having a magnitude three times the reference magnitude. １／２The vector includes six voltage vectors each twice as large as the vector of the voltages of the output points (13), a first zero vector (V0p[PPP]) of a combination in which the potential levels of the multiple output points (13) are all at a positive potential (P1), a second zero vector (V0z

[000] ) of a combination in which the potential levels of the multiple output points (13) are all at a potential of an intermediate potential point (M1), and a third zero vector (V0n[NNN]) of a combination in which the potential levels of the multiple output points (13) are all at a negative potential (N1). The control device (6) selects a first voltage vector (Va), a second voltage vector (Vb), and a third voltage vector (Vc) corresponding to the vertices of an equilateral triangle surrounding a command voltage vector (Vref) as a plurality of voltage vectors to be used within a control period (Ts) from the group of voltage vectors, and determines a first allocation time (T0) of the first voltage vector (Va), a second allocation time (T1) of the second voltage vector (Vb), and a third allocation time (T2) of the third voltage vector (Vc) so that a composite vector of the first voltage vector (Va), the second voltage vector (Vb), and the third voltage vector (Vc) matches the command voltage vector (Vref). When the command voltage vector (Vref) is within the range of a reference hexagon (A1) defined by the above-mentioned 12 voltage vectors, the control device (6) selects the first zero vector (V0p[PPP]), the second zero vector (V0z

[000] ), and the third zero vector (V0n[NNN]) as any of the first voltage vector (Va), the second voltage vector (Vb), and the third voltage vector (Vc) within the control period (Ts).

[0129] According to this aspect, it is possible to suppress the temperature rise of the first clamp diode (D5) and the second clamp diode (D6).

[0130] In the multilevel inverter (100; 100A) according to the second aspect, the control device (6) selects the first zero vector (V0p[PPP]), the second zero vector (V0z

[000] ), and the third zero vector (V0n[NNN]) as any one of the first voltage vector (Va), the second voltage vector (Vb), and the third voltage vector (Vc) within the control period (Ts) only when the command voltage vector (Vref) is within the range of a second reference hexagon (A2) that is smaller than the first reference hexagon (A1), which is the reference hexagon (A1).

[0131] The multilevel inverter (100; 100A) according to the third aspect is the same as that according to the first or second aspect, and further includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a plurality of third bootstrap circuits (73), and a power supply unit (9). The plurality of first gate drivers (61) drive first switching elements (Q1) of the plurality of inverter circuits (1). The plurality of second gate drivers (62) drive second switching elements (Q2) of the plurality of inverter circuits (1). The plurality of third gate drivers (63) drive third switching elements (Q3) of the plurality of inverter circuits (1). The plurality of fourth gate drivers (64) drive fourth switching elements (Q4) of the plurality of inverter circuits (1). The plurality of first bootstrap circuits (71) are connected to the plurality of first gate drivers (61). The plurality of second bootstrap circuits (72) are connected to the plurality of second gate drivers (62). The plurality of third bootstrap circuits (73) are connected to the plurality of third gate drivers (63). The power supply unit (9) supplies voltage to the plurality of fourth gate drivers (64). The control device (6) controls the plurality of first gate drivers (61), the plurality of second gate drivers (62), the plurality of third gate drivers (63), and the plurality of fourth gate drivers (64) within a control period (Ts) so as to match a composite vector of the first voltage vector, the second voltage vector, and the third voltage vector with a command voltage vector.

[0132] According to this aspect, since the power supply unit (9) includes a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a plurality of third bootstrap circuits (73), and a power supply unit (9), it is possible to achieve a smaller size compared to a case where a DC-DC converter is provided instead of each of the plurality of first bootstrap circuits (71), the plurality of second bootstrap circuits (72), and the plurality of third bootstrap circuits (73). Also, according to this aspect, the control device (6) controls the plurality of first gate drivers (61), the plurality of second gate drivers (62), the plurality of third gate drivers (63), and the plurality of fourth gate drivers (64) within the control period (Ts) so as to make the resultant vector of the first voltage vector, the second voltage vector, and the third voltage vector coincide with the command voltage vector, thereby making it possible to suppress a decrease in the output voltage of each of the plurality of second bootstrap circuits (72).

[0133] In a multilevel inverter (100; 100A) according to a fourth aspect, in the third aspect, each of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) includes a capacitor (C17) and a diode (D17), and the diode (D17) is connected in series with the capacitor (C17).

[0134] In the multilevel inverter (100; 100A) according to a fifth aspect, in the fourth aspect, each of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) further includes a resistor (R17), which is connected in series with the capacitor (C17).

[0135] In a multilevel inverter (100) according to a sixth aspect, in any one of the third to fifth aspects, the power supply unit (9) includes a DC-DC converter (91). The DC-DC converter (91) supplies voltage to the plurality of fourth gate drivers (64) and the plurality of third bootstrap circuits (73).

[0136] According to this aspect, it is possible to reduce the size of the multilevel inverter (100).

[0137] The multilevel inverter of the present disclosure can suppress the temperature rise of the first clamp diode and the second clamp diode, and is thus industrially useful.

[0138] REFERENCE SIGNS LIST 1 Inverter circuit 3 DC power supply unit 6 Control device 61 First gate driver 62 Second gate driver 63 Third gate driver 64 Fourth gate driver 9 Power supply unit 91 DC-DC converter 10 Switching circuit 11 First connection point 12 Second connection point 13 Output point (third connection point) 71 First bootstrap circuit 72 Second bootstrap circuit 73 Third bootstrap circuit 100, 100A Multilevel inverter C17, C27, C37 Capacitor A1 Reference hexagon (first reference hexagon) A2 Second reference hexagon D1 First diode D2 Second diode D3 Third diode D4 Fourth diode D5 First clamp diode D6 Second clamp diode D17, D27, D37 Diode P1 Positive electrode Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element M1 Midpoint potential point N1 Negative pole R17, R27, R37 Resistor Ts Control period V0 to V18 Voltage vector Vref Command voltage vector

Claims

1. A device comprising: a DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point; a plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; and a control device that controls the plurality of inverter circuits by space vector modulation, wherein each of the plurality of inverter circuits has a first switching element, a second switching element, a third switching element, and a fourth switching element, and the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element; a first clamp diode having a cathode connected to a first connection point between the first switching element and the second switching element and an anode connected to the intermediate potential point; and a second clamp diode having an anode connected to a second connection point between the third switching element and the fourth switching element and a cathode connected to the intermediate potential point, wherein an output point is between the second switching element and the third switching element, and the control device A group of voltage vectors determined by a combination of potential levels of a plurality of the output points is stored, and the group of voltage vectors includes 12 voltage vectors each having a reference magnitude, 6 voltage vectors each having a magnitude twice the reference magnitude, and 3 voltage vectors each having a magnitude three times the reference magnitude. １／２ a first zero vector of a combination in which the potential levels of the plurality of output points all become the positive potential; a second zero vector of a combination in which the potential levels of the plurality of output points all become the potential of the intermediate potential point; and a third zero vector of a combination in which the potential levels of the plurality of output points all become the negative potential, wherein the control device selects a first voltage vector, a second voltage vector, and a third voltage vector corresponding to each of the vertices of an equilateral triangle surrounding a command voltage vector as a plurality of voltage vectors to be used within a control period from the group of voltage vectors; and determines a first allocation time of the first voltage vector, a second allocation time of the second voltage vector, and a third allocation time of the third voltage vector so that a composite vector of the first voltage vector, the second voltage vector, and the third voltage vector coincides with the command voltage vector. a multilevel inverter, wherein when the command voltage vector is within a range of a reference hexagon defined by the 12 voltage vectors, the first zero vector, the second zero vector, and the third zero vector are selected as any of the first voltage vector, the second voltage vector, and the third voltage vector within the control period.

2. The multilevel inverter according to claim 1, wherein the control device selects the first zero vector, the second zero vector, and the third zero vector as one of the first voltage vector, the second voltage vector, and the third voltage vector within the control period only when the command voltage vector is within a range of a second reference hexagon that is smaller than the first reference hexagon.

3. The multilevel inverter according to claim 1 or 2, further comprising: a plurality of first gate drivers that drive the first switching elements of the respective plurality of inverter circuits; a plurality of second gate drivers that drive the second switching elements of the respective plurality of inverter circuits; a plurality of third gate drivers that drive the third switching elements of the respective plurality of inverter circuits; a plurality of fourth gate drivers that drive the fourth switching elements of the respective plurality of inverter circuits; a plurality of first bootstrap circuits connected to the respective plurality of first gate drivers; a plurality of second bootstrap circuits connected to the respective plurality of second gate drivers; a plurality of third bootstrap circuits connected to the respective plurality of third gate drivers; and a power supply unit that supplies voltages to the respective plurality of fourth gate drivers, wherein the control device controls the respective plurality of first gate drivers, the respective plurality of second gate drivers, the respective plurality of third gate drivers, and the respective plurality of fourth gate drivers within the control period so as to make a composite vector of the first voltage vector, the second voltage vector, and the third voltage vector coincide with the command voltage vector.

4. The multilevel inverter according to claim 3, wherein each of the plurality of first bootstrap circuits and the plurality of second bootstrap circuits includes a capacitor and a diode connected in series with the capacitor.

5. The multilevel inverter according to claim 4, wherein each of the plurality of first bootstrap circuits and the plurality of second bootstrap circuits further includes a resistor connected in series with the capacitor.

6. The multilevel inverter according to any one of claims 3 to 5, wherein the power supply unit includes a DC-DC converter that supplies voltage to the plurality of fourth gate drivers and the plurality of third bootstrap circuits.

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