Array substrate, display panel, display device, and driving method

Abstract

An array substrate, a display panel, a display device, and a driving method. The array substrate comprises: a plurality of pixel electrode units (P). Each pixel electrode unit (P) comprises: a plurality of first-type pixel electrodes (PA) and a plurality of second-type pixel electrodes (PB). At least some of the second-type pixel electrodes (PB) each comprise: a plurality of first sub-pixel electrodes (PB1) and a plurality of second sub-pixel electrodes (PB2). A first-type pixel electrode (PA) is electrically connected to the same data line (2) as a first sub-pixel electrode (PB1) and is electrically connected to a gate line (10) above the first-type pixel electrode (PA), and a second-type pixel electrode (PB) is electrically connected to the same data line (2) as a second sub-pixel electrode (PB2) and is electrically connected to a gate line (10) above the second-type pixel electrode (PB). At least some of the first sub-pixel electrodes (PB1) and the second sub-pixel electrodes (PB2) are alternately arranged in a first direction, and at least some of the first sub-pixel electrodes (PB1) and the second sub-pixel electrodes (PB2) are alternately arranged in a second direction.

Description

Array substrate, display panel, display device and driving method Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, a display device, and a driving method. Background Art

[0002] Dual-gate display product design can halve the number of data lines required for display panels, thereby reducing the number of source chip-on-film (COF) used, significantly lowering panel production costs. As a result, it has attracted widespread attention in recent years.

[0003] In existing Dual Gate display products, sub-pixels have brightness differences in the row (or column) direction, which leads to stripe (horizontal, vertical or grid lines, etc.) defects.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, a display device, and a driving method. The array substrate includes:

[0006] substrate;

[0007] A plurality of transistors; located on one side of the substrate;

[0008] A plurality of gate line groups are located on one side of the substrate, at least one of the plurality of gate line groups comprises: two gate lines extending along the first direction;

[0009] a plurality of data lines, located on one side of the substrate, and extending along a second direction;

[0010] A plurality of pixel electrode units, wherein the plurality of pixel electrode units are periodically and repeatedly arranged on the substrate; the pixel electrode units include: a plurality of first-type pixel electrodes and a plurality of second-type pixel electrodes; the light-emitting wavelength range of the region where the first-type pixel electrodes are located is different from the light-emitting wavelength range of the region where the second-type pixel electrodes are located;

[0011] Among them, at least part of the second type of pixel electrodes includes: multiple first sub-pixel electrodes and multiple second sub-pixel electrodes; the first type of pixel electrodes are electrically connected to the same data line as the first sub-pixel electrodes and electrically connected to the previous gate line, and the second type of pixel electrodes are electrically connected to the same data line as the second sub-pixel electrodes and electrically connected to the previous gate line; at least part of the first sub-pixel electrodes and the second sub-pixel electrodes are alternately arranged in the first direction, and at least part of the first sub-pixel electrodes and the second sub-pixel electrodes are alternately arranged in the second direction.

[0012] In one possible embodiment, the plurality of first-type pixel electrodes include: a plurality of first pixel electrodes; the plurality of second-type pixel electrodes include: a plurality of second pixel electrodes, and a plurality of third pixel electrodes; the light-emitting wavelength range of the region where the second pixel electrodes are located is greater than the light-emitting wavelength range of the region where the third pixel electrodes are located; the first pixel electrodes, the second pixel electrodes, and the third pixel electrodes are arranged sequentially along the first direction;

[0013] The multiple third pixel electrodes include the multiple first sub-pixel electrodes and the multiple second sub-pixel electrodes; in at least a partial area of ​​the pixel electrode unit, the first sub-pixel electrodes and the second sub-pixel electrodes of the multiple third pixel electrodes are alternately arranged in the first direction and alternately arranged in the second direction.

[0014] In one possible embodiment, the multiple second pixel electrodes include the multiple first sub-pixel electrodes and the multiple second sub-pixel electrodes; the first sub-pixel electrodes and the second sub-pixel electrodes of the multiple second pixel electrodes are alternately arranged in the first direction and alternately arranged in the second direction.

[0015] In a possible implementation, the plurality of first sub-pixel electrodes of the third pixel electrode include: a first electrode and a second electrode; the plurality of second sub-pixel electrodes of the third pixel electrode include: a third electrode and a fourth electrode;

[0016] The first electrode is electrically connected to the Mth gate line and the N+1th data line; the second electrode is electrically connected to the M+2th gate line and the N+3th data line;

[0017] The third electrode is electrically connected to the (M+1)th gate line and the (N+2)th data line; the fourth electrode is electrically connected to the (M+2)th gate line and the (N+2)th data line.

[0018] In a possible implementation, the plurality of first sub-pixel electrodes of the second pixel electrode include: a fifth electrode and a sixth electrode; the plurality of second sub-pixel electrodes of the second pixel electrode include: a seventh electrode and an eighth electrode;

[0019] The fifth electrode is electrically connected to the Mth gate line and the N+2th data line; the sixth electrode is electrically connected to the M+2th gate line and the N+1th data line;

[0020] The seventh electrode is electrically connected to the Mth gate line and the Nth data line; the eighth electrode is electrically connected to the M+3th gate line and the N+3th data line.

[0021] In a possible implementation, the plurality of first pixel electrodes include: a ninth electrode, a tenth electrode, an eleventh electrode, and a twelfth electrode;

[0022] The ninth electrode is electrically connected to the Mth gate line and the Nth data line; the tenth electrode is electrically connected to the M+1th gate line and the N+1th data line; the eleventh electrode is electrically connected to the M+3th gate line and the N+1th data line; and the twelfth electrode is electrically connected to the M+3th gate line and the N+2th data line.

[0023] In a possible implementation, the ninth electrode, the seventh electrode, the first electrode, the tenth electrode, the fifth electrode, and the third electrode are located between the Mth gate line and the M+1th gate line; the eleventh electrode, the sixth electrode, the fourth electrode, the twelfth electrode, the eighth electrode, and the second electrode are located between the M+2th gate line and the M+3th gate line;

[0024] The ninth electrode, the seventh electrode, the eleventh electrode, and the sixth electrode are located between the Nth data line and the N+1th data line; the first electrode, the tenth electrode, the fourth electrode, and the twelfth electrode are located between the N+1th data line and the N+2th data line; the fifth electrode, the third electrode, the eighth electrode, and the second electrode are located between the N+2th data line and the N+3th data line.

[0025] In a possible implementation manner, the seventh electrode is located on a side of the ninth electrode away from the Nth data line;

[0026] The sixth electrode is located on a side of the eleventh electrode away from the (N+1)th data line;

[0027] The tenth electrode is located at a side of the first electrode away from the (N+1)th data line;

[0028] The fourth electrode is located at a side of the twelfth electrode away from the (N+2)th data line;

[0029] The third electrode is located at a side of the fifth electrode away from the (N+2)th data line;

[0030] The eighth electrode is located on a side of the second electrode away from the (N+3)th data line.

[0031] In a possible implementation, in the first region of the pixel electrode unit, the first sub-pixel electrodes and the second sub-pixel electrodes of the plurality of third pixel electrodes are alternately arranged in the first direction and alternately arranged in the second direction; in a region outside the first region of the pixel electrode unit, the first sub-pixel electrodes of the plurality of third pixel electrodes are sequentially arranged in the first direction and sequentially arranged in the second direction;

[0032] The plurality of second pixel electrodes include: the plurality of second sub-pixel electrodes; the second sub-pixel electrodes of the plurality of second pixel electrodes are sequentially arranged in the first direction and sequentially arranged in the second direction.

[0033] In a possible implementation, the plurality of first sub-pixel electrodes of the third pixel electrode include: a thirteenth electrode, a fourteenth electrode, a fifteenth electrode, a sixteenth electrode, a seventeenth electrode, and an eighteenth electrode; the plurality of second sub-pixel electrodes of the third pixel electrode include: a nineteenth electrode and a twentieth electrode;

[0034] The thirteenth electrode is electrically connected to the J+1th gate line and the K+1th data line; the fourteenth electrode is electrically connected to the Jth gate line and the K+2th data line; the fifteenth electrode is electrically connected to the J+3th gate line and the K+2th data line; the sixteenth electrode is electrically connected to the J+2th gate line and the K+3th data line; the seventeenth electrode is electrically connected to the J+5th gate line and the K+1th data line; and the eighteenth electrode is electrically connected to the J+6th gate line and the K+3th data line.

[0035] The nineteenth electrode is electrically connected to the J+5th gate line and the K+2th data line; the twentieth electrode is electrically connected to the J+6th gate line and the K+2th data line.

[0036] In a possible implementation manner, the plurality of second sub-pixel electrodes of the second pixel electrode include: a twenty-first electrode, a twenty-second electrode, a twenty-third electrode, a twenty-fourth electrode, a twenty-fifth electrode, a twenty-sixth electrode, a twenty-seventh electrode, and a twenty-eighth electrode;

[0037] The twenty-first electrode is electrically connected to the J-th gate line and the K-th data line; the twenty-second electrode is electrically connected to the J+1-th gate line and the K+2-th data line; the twenty-third electrode is electrically connected to the J+2-th gate line and the K+1-th data line; the twenty-fourth electrode is electrically connected to the J+3-th gate line and the K+3-th data line; the twenty-fifth electrode is electrically connected to the J+4-th gate line and the K-th data line; the twenty-sixth electrode is electrically connected to the J+4-th gate line and the K+2-th data line; the twenty-seventh electrode is electrically connected to the J+6-th gate line and the K+1-th data line; and the twenty-eighth electrode is electrically connected to the J+7-th gate line and the K+3-th data line.

[0038] In a possible implementation, the plurality of first electrodes include: a twenty-ninth electrode, a thirtieth electrode, a thirty-first electrode, a thirty-second electrode, a thirty-third electrode, a thirty-fourth electrode, a thirty-fifth electrode, and a thirty-sixth electrode;

[0039] The twenty-ninth electrode is electrically connected to the J+1th gate line and the Kth data line; the 30th electrode is electrically connected to the Jth gate line and the K+1th data line; the thirty-first electrode is electrically connected to the J+3th gate line and the K+1th data line; the thirty-second electrode is electrically connected to the J+2th gate line and the K+2th data line; the thirty-third electrode is electrically connected to the J+5th gate line and the Kth data line; the thirty-fourth electrode is electrically connected to the J+4th gate line and the K+1th data line; the thirty-fifth electrode is electrically connected to the J+7th gate line and the K+1th data line; and the thirty-sixth electrode is electrically connected to the J+7th gate line and the K+2th data line.

[0040] In a possible implementation manner, the thirteenth electrode, the fourteenth electrode, the twenty-first electrode, the twenty-second electrode, the twenty-ninth electrode, and the thirtieth electrode are located between the J-th gate line and the J+1-th gate line; the fifteenth electrode, the sixteenth electrode, the twenty-third electrode, the twenty-fourth electrode, the thirty-first electrode, and the thirty-second electrode are located between the J+2-th gate line and the J+3-th gate line; the seventeenth electrode, the nineteenth electrode, the twenty-fifth electrode, the twenty-sixth electrode, the thirty-third electrode, and the thirty-fourth electrode are located between the J+4-th gate line and the J+5-th gate line; the eighteenth electrode, the twentieth electrode, the twenty-seventh electrode, the twenty-eighth electrode, the thirty-fifth electrode, and the thirty-sixth electrode are located between the J+6-th gate line and the J+7-th gate line;

[0041] The twenty-ninth electrode, the twenty-first electrode, the thirty-first electrode, the twenty-third electrode, the thirty-third electrode, the twenty-fifth electrode, the thirty-fifth electrode, and the twenty-seventh electrode are located between the K-th data line and the K+1-th data line; the thirteenth electrode, the thirtieth electrode, the fifteenth electrode, the thirty-second electrode, the seventeenth electrode, the thirty-fourth electrode, the twentieth electrode, and the thirty-sixth electrode are located between the K+1-th data line and the K+2-th data line; the twenty-second electrode, the fourteenth electrode, the twenty-fourth electrode, the sixteenth electrode, the twenty-sixth electrode, the nineteenth electrode, the twenty-eighth electrode, and the eighteenth electrode are located between the K+2-th data line and the K+3-th data line.

[0042] In a possible implementation, the twenty-first electrode is located on a side of the twenty-ninth electrode away from the Kth data line; the thirty-first electrode is located on a side of the twenty-third electrode away from the K+1th data line; the twenty-fifth electrode is located on a side of the thirty-third electrode away from the Kth data line; and the thirty-fifth electrode is located on a side of the twenty-seventh electrode away from the K+1th data line.

[0043] The 30th electrode is located on a side of the 13th electrode away from the (K+1)th data line; the 15th electrode is located on a side of the 32nd electrode away from the (K+2)th data line; the 34th electrode is located on a side of the 17th electrode away from the (K+1)th data line; and the 20th electrode is located on a side of the 36th electrode away from the (K+2)th data line.

[0044] The fourteenth electrode is located on the side of the twenty-second electrode away from the K+2 data line; the twenty-fourth electrode is located on the side of the sixteenth electrode away from the K+3 data line; the nineteenth electrode is located on the side of the twenty-sixth electrode away from the K+2 data line; and the twenty-eighth electrode is located on the side of the eighteenth electrode away from the K+3 data line.

[0045] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0046] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0047] The present disclosure further provides a method for driving the array substrate provided in the present disclosure, wherein the driving method includes:

[0048] Control the loading of scanning signals to each gate line in sequence;

[0049] During a period in which the current gate line is turned on, the next gate line is controlled to be turned on, so that the pixel electrode electrically connected to the next gate line is precharged.

[0050] In a possible implementation, when displaying a preset image, controlling the next gate line to be turned on during a period in which the current gate line is turned on, so as to pre-charge the pixel electrode electrically connected to the next gate line, includes:

[0051] In a first time period, controlling the M-th gate line to load a valid scan signal, and controlling the N-th, N+1-th, and N+2-th data lines to load a first data signal;

[0052] In the second period, the Mth and M+1th gate lines are controlled to load valid scan signals, the Nth and N+1th data lines are controlled to load second data signals, and the N+2th data line is controlled to load the first data signal;

[0053] In a third period, controlling the Mth, M+1th, and M+2th gate lines to load valid scan signals, controlling the Nth and N+1th data lines to load first data signals, and controlling the N+2th data line to load second data signals;

[0054] In the fourth period, the M+1th, M+2th, and M+3th gate lines are controlled to load valid scan signals, the Nth and N+2th data lines are controlled to load first data signals, and the N+1th data line is controlled to load second data signals.

[0055] In a possible implementation, when the picture is preset, the driving method further includes:

[0056] In a first period, controlling the J-th gate line to load a valid scan signal, controlling the K-th and K+2-th data lines to load a first data signal, and controlling the K+1-th data line to load a second data signal;

[0057] In the second period, the J-th and J+1-th gate lines are controlled to load valid scan signals, the K+1-th and K+2-th data lines are controlled to load first data signals, and the K-th data line is controlled to load second data signals;

[0058] In a third period, the Jth, J+1th, and J+2th gate lines are controlled to load valid scan signals, the Kth and K+1th data lines are controlled to load first data signals, and the K+2th data line is controlled to load second data signals;

[0059] In a fourth period, the J+1th, J+2th, and J+3th gate lines are controlled to load valid scan signals, the Kth and K+2th data lines are controlled to load first data signals, and the K+1th data line is controlled to load second data signals;

[0060] In a fifth period, the J+2, J+3, and J+4 gate lines are controlled to load valid scan signals, the K and K+2 data lines are controlled to load first data signals, and the K+1 data line is controlled to load second data signals;

[0061] In a sixth period, the J+3, J+4, and J+5 gate lines are controlled to load valid scan signals, the K+1 and K+2 data lines are controlled to load first data signals, and the Kth data line is controlled to load second data signals;

[0062] In the seventh period, the J+4th, J+5th, and J+6th gate lines are controlled to load valid scan signals, and the Kth, K+1th, and K+2th data lines are controlled to load first data signals;

[0063] In an eighth time period, the J+5th, J+6th, and J+7th gate lines are controlled to load valid scan signals, the Kth data line is controlled to load the first data signal, and the K+1th and K+2th data lines are controlled to load the second data signal;

[0064] In a ninth period, the J+6th and J+7th gate lines are controlled to load valid scan signals, the Kth and K+2th data lines are controlled to load first data signals, and the K+1th data line is controlled to load second data signals;

[0065] In the tenth period, the J+7th gate line is controlled to load a valid scan signal, the Kth, K+1th, and K+2th data lines are controlled to load a first data signal, and the Kth data line is controlled to load a second data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] FIG1A is a schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0067] FIG1B is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0068] FIG1C is a third schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0069] FIG1D is a fourth schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0070] FIG1E is a fifth schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0071] FIG1F is a sixth schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0072] FIG1G is a seventh schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0073] FIG2 is a timing signal diagram corresponding to the pixel architecture shown in FIG1A ;

[0074] FIG3A is a schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0075] FIG3B is a second schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0076] FIG3C is a third schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0077] FIG3D is a fourth schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0078] FIG3E is a fifth schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0079] FIG3F is a sixth schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0080] FIG4 is a timing signal diagram corresponding to the pixel architecture shown in FIG3A;

[0081] FIG5 is a schematic flow chart of a driving method according to an embodiment of the present disclosure;

[0082] FIG6 is a schematic diagram of a Dual Gate pixel architecture of the related art;

[0083] FIG7A is a schematic diagram showing the mechanism of occurrence of sky blue vertical streaks;

[0084] FIG7B is a diagram of the timing signals loaded when the sky blue vertical streak defect occurs. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0086] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0087] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0088] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0089] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0090] Because Dual Gate products have double the number of grid lines compared to Single Gate products, charging speed is difficult, which manifests itself macroscopically as streaks (horizontal, vertical, or grid patterns) on the mixed-color screen. For example, during Dual Gate product development, grid patterns appeared when the frequency was adjusted to 120Hz. This is primarily due to the difficulty in charging at high refresh rates, resulting in differences in brightness between G and B sub-pixels in both the row and column directions, leading to grid patterns.

[0091] In view of this, an embodiment of the present disclosure provides an array substrate. Referring to FIG1A , the array substrate includes:

[0092] substrate;

[0093] A plurality of transistors T are located on one side of the substrate;

[0094] A plurality of gate line groups 1 are located on one side of the substrate, and at least one gate line group 1 among the plurality of gate line groups 1 includes: two gate lines 10 extending along a first direction X;

[0095] A plurality of data lines 2 are located on one side of the substrate, and the plurality of data lines 2 extend along a second direction Y;

[0096] Multiple pixel electrode units P, the multiple pixel electrode units P are periodically and repeatedly arranged on the substrate; the pixel electrode units P include: multiple first-type pixel electrodes PA, and multiple second-type pixel electrodes PB; the light-emitting wavelength range of the region where the first-type pixel electrodes PA are located is different from the light-emitting wavelength range of the region where the second-type pixel electrodes PB are located; specifically, for example, the region where the first-type pixel electrodes PA are located emits red light, and the region where the second-type pixel electrodes PB are located emits green light or blue light;

[0097] Among them, at least part of the second type of pixel electrodes PB includes: a plurality of first sub-pixel electrodes PB1 and a plurality of second sub-pixel electrodes PB2. For example, as shown in FIG1A , the second type of pixel electrode PB emitting blue light B includes a plurality of first sub-pixel electrodes PB1 and a plurality of second sub-pixel electrodes PB2; for another example, as shown in FIG1B , the second type of pixel electrode PB emitting green light G includes a plurality of first sub-pixel electrodes PB1 and a plurality of second sub-pixel electrodes PB2; for another example, as shown in FIG1C , the second type of pixel electrode PB emitting blue light B includes a plurality of first sub-pixel electrodes PB1 and a plurality of second sub-pixel electrodes PB2, and the second type of pixel electrode PB emitting green light G includes a plurality of first sub-pixel electrodes PB1 and a plurality of second sub-pixel electrodes PB2; the first sub-pixel electrode PB1 and the second sub-pixel electrode PB of the second type of pixel electrodes PB of the same light emitting color have the same light emitting color (i.e., wavelength band) range; and the first sub-pixel electrode PB1 and the second sub-pixel electrode PB have the same light emitting color (i.e., wavelength band) range. The electrode PB1 is electrically connected to the same data line 2 and electrically connected to the previous gate line 1, which is a first-type pixel electrode PA. For example, as shown in FIG1B , the pixel electrode in the second row and the second column is electrically connected to the M+2th gate line and the N+1th data line, and the pixel electrode electrically connected to the same data line 2 and electrically connected to the previous gate line 1 is the first-type pixel electrode PA in the fourth column of the first row. Then the pixel electrode in the second row and the second column can serve as the first sub-pixel electrode PB1; the pixel electrode electrically connected to the same data line 2 and electrically connected to the previous gate line 1 is the second-type pixel electrode PB. For example, as shown in FIG1B , the pixel electrode in the second row and the fifth column is electrically connected to the M+3th gate line and the N+3th data line, and the pixel electrode electrically connected to the same data line 2 and electrically connected to the previous gate line 1 is the second-type pixel electrode PB in the sixth column of the second row. Then the pixel electrode in the second row and the fifth column can serve as the second sub-pixel electrode PB2. At least part of the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 are alternately arranged in the first direction X, and at least part of the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 are alternately arranged in the second direction Y.

[0098] In the embodiment of the present disclosure, in the repeating unit pixel electrode unit P, at least part of the second type pixel electrodes PB include: multiple first sub-pixel electrodes PB1 and multiple second sub-pixel electrodes PB2, the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 are alternately arranged in the first direction X, and the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 are alternately arranged in the second direction Y, which can avoid vertical stripes caused by the alternating distribution of one column of bright and one column of dark sub-pixels of the same color, and avoid horizontal stripes caused by the alternating distribution of one row of bright and one row of dark sub-pixels of the same color, and avoid the occurrence of intricate horizontal and vertical stripes, i.e., grid patterns, in the case of high refresh rate when the sub-pixels of the same color are viewed from the row direction, in which the bright and dark sub-pixels in one row are alternately distributed, and the sub-pixels in the adjacent rows are all brighter sub-pixels, while in which the bright and dark sub-pixels in one column are alternately distributed, and the sub-pixels in the adjacent columns are all brighter sub-pixels when viewed from the column direction.

[0099] In the embodiment of the present disclosure, referring to FIG. 1A to FIG. 1C and FIG. 2 , FIG. 2 is a timing signal diagram loaded by the pixel architecture shown in FIG. 1A to FIG. 1C . In the mixed color screen displayed by the G and B sub-pixels, the G and B sub-pixels are turned on, the R sub-pixel is turned off, and the data signals written by the Nth data line (the same as the N+3th data line) at different time periods and the brightness and darkness of the corresponding electrically connected sub-pixels are as follows: high (the G sub-pixel in the first row and second column is bright), low (the R sub-pixel in the first row and first column is off), high (the sub-pixel in the second row connected to the N data line is off), and the brightness and darkness of the corresponding electrically connected sub-pixels are as follows: The data signals written by the N+1 data line at different time periods and the brightness and darkness of the corresponding electrically connected sub-pixels are as follows: high (the B sub-pixel in the first row and third column is on), low (the R sub-pixel in the first row and fourth column is off), high (the G sub-pixel in the second row and second column is on), and low (the R sub-pixel in the second row and first column is off); the data signals written by the N+2 ... The brightness and darkness of the sub-pixels are as follows: high (the G sub-pixel in the first row and fifth column is bright), high (the B sub-pixel in the first row and sixth column is bright), high (the B sub-pixel in the second row and third column is bright), low (the R sub-pixel in the second row and fourth column is off), and the cycle continues; as shown in FIG1C , in one cycle, taking the M+2th gate line turning on the G sub-pixel in the second row and second column as an example, the signal is provided by the N+1th data line. When the M+1th gate line in the previous row is turned on, the N+1th data line writes a low-level data signal of the R sub-pixel in the first row and fourth column. Therefore, the formal data signal is written into the G sub-pixel in the second row and second column. Before the signal is written, the pre-charged signal is a low-level data signal of the R sub-pixel in the first row and the fourth column. When the data signal is officially written, the voltage of the pixel electrode will be lower than the preset voltage, and the brightness will be dim, so it is marked as poor (pre-charged poor). Similarly, the charging conditions of the G sub-pixels in the second column are distributed as good and poor, respectively; the charging conditions of the G sub-pixels in the fifth column are distributed as poor and good, respectively; similarly, the charging conditions of the B sub-pixels in the third column are distributed as poor and good, respectively, and the charging conditions of the B sub-pixels in the sixth column are distributed as good and poor, respectively; the charging conditions of the G sub-pixels in the first row are distributed as good and poor, respectively; the charging conditions of the G sub-pixels in the second row are distributed as poor and good, respectively;Ultimately, for the B sub-pixels, the charging conditions in the first row are poor and good, while the charging conditions in the second row are good and poor. This pixel architecture maintains the same charging conditions for the B sub-pixels in both the row and column directions. At high refresh rates, this ensures consistent charging of the B sub-pixels, resulting in no pixel brightness differences. Similarly, the charging conditions for the G sub-pixels are consistent in both the row and column directions. At high refresh rates, this ensures consistent charging of the G sub-pixels, resulting in no pixel brightness differences. Therefore, in mixed-color images of G and B sub-pixels (water-blue images), no grid pattern defects occur. This fundamentally addresses the grid pattern defects that can occur in dual-gate pixel architecture displays at high frequencies.

[0100] FIG6 shows a Dual Gate pixel architecture design of the related art, which is the minimum period of the Dual Gate pixel arrangement and adopts a Z-inversion pixel structure. The thin film transistors (TFTs) connected to the first to fourth gate lines respectively adopt a short-long-long-long-short-long-short-short-long-long connection method (wherein, a long connection can be understood as the sub-pixel bypassing a sub-pixel to be electrically connected to the data line, and a short connection can be understood as the sub-pixel being directly electrically connected to the adjacent data line, or it can be said that if one pole electrically connected to the data line by the transistor is defined as the first pole, then the length of the first pole of the long connection is longer than the length of the first pole of the short connection). For Gate1, Data1 is short connected, Data2 is long connected, and Data3 is long connected. For Gate2, Data1 is long connected, Data2 is short connected, and Data3 is short connected. For Gate3, Data1 is not connected, Data2 is long connected, Data3 is short connected, and Data4 is short connected. For Gate4, Data1 is not connected, Data2 is short connected, Data3 is long connected, and Data4 is long connected. The color resistance corresponding to a row of sub-pixels adopts RGBRGB sequence, and RGB is one cycle.

[0101] The Dual Gate pixel architecture shown in FIG6 has sky blue vertical stripes when the high-frequency charging time is reduced. The sky blue picture is mainly a GB mixed color grayscale picture (L127 or L255), as shown in FIG7A and FIG7B. The Dual Gate+GOA design can remove the chip on film (COF) on the Gate side. At the same time, the number of Gate rows is doubled and the number of Data is halved, thereby halving the COF on the source side (Data side). Only the source side has COF, thereby reducing costs and increasing the market competitiveness of the product. The current market has increasingly higher requirements for high frequencies, and currently there is a demand for 100Hz / 120Hz. Due to the doubling of the number of Gate rows, the Dual Gate design has a 1H charging time of 4.6us at 100Hz and a 1H charging time of 3.8us at 120Hz. The shorter the charging time, the more difficult it is to charge. In order to meet the requirements of Dual Gate charging, a pre-charge design is generally adopted, as shown in FIG7B. As shown in FIG7B, the normal Gate charging time is 1H, and the Dual Gate design has a pre-charge time of 3.8us at 120Hz. The Gate pixel structure is designed with 3H, and the pre-charge time of 2H is added. Taking Gate1 as an example, the extra 2H in the front is the pre-charge time. Taking G2 as an example, the 1H of G1 is the pre-charge time, and so on. Before the 1H time of writing the Data signal, the Gate is open for 2H, and the data of the first two rows are written. When G is turned on, G2 is opened for 1H, and the pre-charge is the Data data opened by G1. When G2 is turned on, G3 is opened for 2H. The subsequent Gates are basically opened for 2H as the Pre-charge time. The data written in advance is generally written by opening the previous row for 1H as the pre-charge data;

[0102] The principle of vertical stripes is as follows: in the data signal, V2 is a high level and V1 is a low level. In the mixed color screen where the G and B sub-pixels are bright, as shown in Figures 7A and 7B, the G and B sub-pixels are turned on, and the R sub-pixel is turned off. Taking one cycle as an example, the data signals written by D1 (same as D4) at different time periods and the brightness and darkness of the corresponding electrically connected sub-pixels are: low (R off in the first row and first column), high (G on in the first row and second column), high (the second row of sub-pixels connected to D1 is shown, and you can refer to the sub-pixels connected to D4, that is, B on the second row and sixth column is bright), high (same as before, G on the second row and fifth column is bright), and the sub-pixels in the subsequent rows are as follows: low (R off in the first row and first column), high (G on the first row and second column is bright ... and the sub-pixels in the subsequent rows are as follows: high (R off in the first row and first column), high (G on the first row and second column is bright), and the sub-pixels in the subsequent rows are as follows: high (R off in the first row and first column), high (G on the first row and second column is bright), and the sub-pixels in the subsequent rows are as follows: high (R on the first row and first column is off), high (G on the first row and second column is bright), and the sub-pixels in the subsequent rows are as follows: high (R on the first row and first column is off In this cycle, the D1 signal is shown in FIG2 ; the data signals written by D2 at different time periods and the brightness and darkness of the corresponding electrically connected sub-pixels are: low (R off in the first row, fourth column), high (B on in the first row, third column), low (R off in the second row, first column), high (G on in the second row, second column), and the sub-pixels in subsequent rows repeat this cycle, and the D2 signal is shown in FIG7B ; the data signals written by D3 at different time periods and the brightness and darkness of the corresponding electrically connected sub-pixels are: high (B on in the first row, sixth column), high (G on in the first row, fifth column), low (R off in the second row, fourth column), high (B on in the second row, third column), and the cycle continues;

[0103] In one cycle, taking G2 turning on the G sub-pixel in the first row and second column as an example, the electrically connected data line D1 writes the data signal of the R sub-pixel when G1 in the previous row is turned on, which is also a low-level signal. Therefore, before the data signal is written into the G sub-pixel in the first row and second column, the pre-charge is the low-level signal of the R sub-pixel, so it is marked as poor (pre-charge is poor); similarly, taking G4 turning on the G sub-pixel in the second row and second column as an example, the electrically connected data line D1 writes the data signal of the R sub-pixel when G3 in the previous row is turned on, which is also a low-level signal. Therefore, Before the data signal is written to the G sub-pixel in the second row and second column, the pre-charged signal is a low-level signal of the R sub-pixel, so it is marked as poor (pre-charge is poor). Similarly, all the G sub-pixels in the second column are poor. Taking G2 turning on the G sub-pixel in the first row and fifth column as an example, the electrically connected data line D3 writes the data signal of the B sub-pixel when G1 in the previous row is turned on, that is, a high-level signal. Therefore, before the data signal is written to the G sub-pixel in the first row and fifth column, the pre-charged signal is a high-level signal of the B sub-pixel, so it is marked as good (pre-charge is good). Similarly, take G4 as an example to open the G sub-pixel in the second row and the fifth column. When G3 in the previous row is opened, the electrically connected data line D4 writes the data signal of the B sub-pixel, which is also a high-level signal. Therefore, before the data signal is written to the G sub-pixel in the second row and the fifth column, the pre-charged signal is a high-level signal of the B sub-pixel, so it is marked as good (pre-charge is better). By analogy, all the G sub-pixels in the second column are good. By analogy with the same method, all the B sub-pixels in the second column are bad, and all the B sub-pixels in the fifth column are good. A column of R, G, and B sub-pixels constitutes a column of pixels, and one cycle There are two columns of pixels in the display panel, which are superimposed so that one column of pixels is dark and the other column of pixels is bright, and the following pixels are periodically continued. In particular, the human eye is more sensitive to G sub-pixels, so the entire display panel appears as one column bright and one column dark, resulting in vertical stripes in the sky blue screen (G and B sub-pixels display mixed colors); specifically, for example, A and B are two adjacent sub-pixels of the same color, and if the sub-pixel connected to the same data line as A and connected to the previous gate line is a red pixel (not displayed in the sky blue screen, and a low grayscale data signal needs to be loaded), due to the dual The pre-charging mechanism of the gate is that the A sub-pixel will be pre-charged with the low grayscale data voltage loaded by the previous red pixel in advance, resulting in the A sub-pixel being darker than normal when it is officially displayed; if the sub-pixel connected to the same data line as the B sub-pixel and connected to the previous gate line is a blue or green pixel (high grayscale data signal needs to be loaded for display under the sky blue screen), the B sub-pixel will be pre-charged with the high grayscale data voltage loaded by the previous blue or green pixel in advance, resulting in the B sub-pixel being brighter than normal when it is officially displayed; based on this principle, statistics on other pixel architectures of Dual Gate and the display process under the G and B sub-pixel mixed color screen also exist under high refresh rate conditions. There is also a phenomenon of intricate horizontal and vertical stripes, namely grid patterns, when observed in different directions.

[0104] In a possible implementation, in the embodiment of the present disclosure, under the same data voltage, the light emitting brightness of the area where the first sub-pixel electrode PB1 is located may be lower than the light emitting brightness of the area where the second sub-pixel electrode PB2 is located, that is, the second type of pixel electrodes PB emitting the same color may be divided into the first sub-pixel electrode PB1 emitting darker light and the second sub-pixel electrode PB2 emitting brighter light, and the difference in brightness between the two is related to the pre-charge voltage; specifically, for example, the second type of pixel electrodes PB emitting blue light may be divided into the first sub-pixel electrode PB1 emitting darker light and the second sub-pixel electrode PB2 emitting brighter light; for another example, the second type of pixel electrodes PB emitting green light may be divided into the first sub-pixel electrode PB1 emitting darker light and the second sub-pixel electrode PB2 emitting brighter light; the determination of the first sub-pixel electrode PB1 and the second sub-pixel electrode PB2 is related to the pixel electrodes electrically connected to the same data line 2 and electrically connected to the previous gate line 10, that is, if they are electrically connected to the same data line 2 and electrically connected to the previous gate line 1 0 is a first-type pixel electrode PA, then it serves as the first sub-pixel electrode PB1; if the pixel electrode electrically connected to the same data line 2 and electrically connected to the previous gate line 10 is a second-type pixel electrode PB, then it serves as the second sub-pixel electrode PB2; specifically, for example, the pixel electrode in the second row and second column and the pixel electrode in the second row and fifth column in FIG1A are both pixel electrodes that emit blue light, wherein the pixel electrode in the first row and fourth column is electrically connected to the same data line 2 and electrically connected to the previous gate line 10 as the pixel electrode in the second row and second column, and the pixel electrode in the first row and fourth column is the first-type pixel electrode PA that emits red light, then the pixel electrode in the second row and second column can be used as the darker first sub-pixel electrode PB1; and the pixel electrode in the second row and sixth column is electrically connected to the same data line 2 and electrically connected to the previous gate line 10 as the pixel electrode in the second row and sixth column, and the pixel electrode in the second row and sixth column is the second-type pixel electrode PB that emits blue light, then the pixel electrode in the second row and fifth column can be used as the brighter second sub-pixel electrode PB2.

[0105] Specifically, the first type of pixel electrode PA is electrically connected to the same data line 2 as the first sub-pixel electrode PB1 and is electrically connected to the previous gate line 10. It can be understood that the first sub-pixel electrode PB1 and the first type of pixel electrode PA are electrically connected to the same data line 2, but the gate line 1 to which the first type of pixel electrode PA is electrically connected is the previous gate line of the gate line 1 electrically connected to the first sub-pixel electrode PB1, that is, for example, the first sub-pixel electrode PB1 is electrically connected to the N+2th data line and the M+2th gate line, then the pixel electrode electrically connected to the same data line 2 as the first sub-pixel electrode PB1 and is electrically connected to the previous gate line 1 is the pixel electrode electrically connected to the N+2th data line and the M+1th gate line; wherein, "previous" can be the "previous" gate line along the direction of the gate scan signal, that is, the gate scan signal loaded on the "previous" gate line is earlier than the gate scan signal loaded on the current gate line.

[0106] Specifically, the array substrate provided in the embodiment of the present disclosure can be applied to a liquid crystal display panel. The liquid crystal display panel has a backlight module, and an array substrate and a color film substrate located on the light-emitting side of the backlight module. The light-emitting band of the area where the first type of pixel electrode PA is located can be understood as the light emitted by the backlight module after being filtered by the color film substrate.

[0107] In one possible embodiment, the plurality of first-type pixel electrodes PA include: a plurality of first pixel electrodes, for example, the first pixel electrode can be a pixel electrode of a red sub-pixel R; the plurality of second-type pixel electrodes PB include: a plurality of second pixel electrodes, and a plurality of third pixel electrodes; the light-emitting band range of the area where the second pixel electrode is located is greater than the light-emitting band range of the area where the third pixel electrode is located, for example, the second pixel electrode can be a pixel electrode of a green sub-pixel G, and the third pixel electrode can be a pixel electrode of a blue sub-pixel B; the first pixel electrode, the second pixel electrode, and the third pixel electrode are arranged in sequence along the first direction X; the plurality of third pixel electrodes include a plurality of first sub-pixel electrodes PB1, and a plurality of second sub-pixel electrodes PB2; in at least a portion of the pixel electrode unit P, the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 of the plurality of third pixel electrodes are alternately arranged in the first direction X, and alternately arranged in the second direction Y. In the disclosed embodiment, the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 of the plurality of third pixel electrodes are alternately arranged in the first direction X and alternately arranged in the second direction Y. This can prevent vertical stripes caused by an alternating distribution of one column of light and one column of dark in the sub-pixels emitting blue light, and avoid horizontal stripes caused by an alternating distribution of one row of light and one row of dark in the sub-pixels emitting blue light, and avoid grid pattern defects of both horizontal and vertical stripes in the sub-pixels emitting blue light.

[0108] In one possible embodiment, the plurality of second pixel electrodes include a plurality of first sub-pixel electrodes PB1 and a plurality of second sub-pixel electrodes PB2; the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 of the plurality of second pixel electrodes are alternately arranged in a first direction X and alternately arranged in a second direction Y. In the disclosed embodiment, the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 of the plurality of second pixel electrodes are alternately arranged in the first direction X and alternately arranged in the second direction Y. This can prevent vertical stripes caused by an alternating arrangement of one bright column and one dark column in sub-pixels emitting green light, avoid horizontal stripes caused by an alternating arrangement of one bright column and one dark column in sub-pixels emitting green light, and avoid grid stripes caused by a grid stripe pattern of both horizontal and vertical stripes in sub-pixels emitting green light.

[0109] In a possible embodiment, referring to FIG1D , the multiple first sub-pixel electrodes PB1 of the third pixel electrode (i.e., the blue sub-pixel B) include: a first electrode P1 and a second electrode P2; the multiple second sub-pixel electrodes PB2 of the third pixel electrode (i.e., the blue sub-pixel B) include: a third electrode P3 and a fourth electrode P4; the first electrode P1 is electrically connected to the M-th gate line and the N+1-th data line; the second electrode P2 is electrically connected to the M+2-th gate line and the N+3-th data line; the third electrode P3 is electrically connected to the M+1-th gate line and the N+2-th data line; and the fourth electrode P4 is electrically connected to the M+2-th gate line and the N+2-th data line.

[0110] In a possible embodiment, referring to FIG1D , the multiple first sub-pixel electrodes PB1 of the second pixel electrode (i.e., the green sub-pixel G) include: a fifth electrode P5 and a sixth electrode P6; the multiple second sub-pixel electrodes PB2 of the second pixel electrode (i.e., the green sub-pixel G) include: a seventh electrode P7 and an eighth electrode P8; the fifth electrode P5 is electrically connected to the M-th gate line and the N+2-th data line; the sixth electrode P6 is electrically connected to the M+2-th gate line and the N+1-th data line; the seventh electrode P7 is electrically connected to the M-th gate line and the N-th data line; and the eighth electrode P8 is electrically connected to the M+3-th gate line and the N+3-th data line.

[0111] In a possible embodiment, referring to FIG1D , a plurality of first pixel electrodes (i.e., red sub-pixels R) include: a ninth electrode P9, a tenth electrode P10, an eleventh electrode P11, and a twelfth electrode P12; the ninth electrode P9 is electrically connected to the Mth gate line and the Nth data line; the tenth electrode P10 is electrically connected to the M+1th gate line and the N+1th data line; the eleventh electrode P11 is electrically connected to the M+3th gate line and the N+1th data line; and the twelfth electrode P12 is electrically connected to the M+3th gate line and the N+2th data line.

[0112] In a possible embodiment, referring to FIG. 1D , the ninth electrode P9, the seventh electrode P7, the first electrode P1, the tenth electrode P10, the fifth electrode P5, and the third electrode P3 are located between the M-th gate line and the M+1-th gate line; the eleventh electrode P11, the sixth electrode P6, the fourth electrode P4, the twelfth electrode P12, the eighth electrode P8, and the second electrode P2 are located between the M+2-th gate line and the M+3-th gate line;

[0113] The ninth electrode P9, the seventh electrode P7, the eleventh electrode P11, and the sixth electrode P6 are located between the Nth data line and the N+1th data line; the first electrode P1, the tenth electrode P10, the fourth electrode P4, and the twelfth electrode P2 are located between the N+1th data line and the N+2th data line; the fifth electrode P5, the third electrode P3, the eighth electrode P8, and the second electrode P2 are located between the N+2th data line and the N+3th data line.

[0114] In a possible implementation, referring to FIG. 1D , the seventh electrode P7 is located on a side of the ninth electrode P9 away from the Nth data line;

[0115] The sixth electrode P6 is located on a side of the eleventh electrode P11 away from the (N+1)th data line;

[0116] The tenth electrode P10 is located at a side of the first electrode P1 away from the (N+1)th data line;

[0117] The fourth electrode P4 is located at a side of the twelfth electrode P12 away from the (N+2)th data line;

[0118] The third electrode P3 is located at a side of the fifth electrode P5 away from the (N+2)th data line;

[0119] The eighth electrode P8 is located on a side of the second electrode P2 away from the (N+3) th data line.

[0120] In the embodiment of the present disclosure, as shown in Figure 1D, it is a Dual Gate pixel architecture, which is a 2dot-Z Inversion pixel architecture. The pixel architecture is arranged by long and short TFT connections. For the Mth gate line, the Nth data line is a long connection, the N+1th data line is a short connection, and the N+2th data line is a short connection; for the M+1th gate line, the Nth data line is a short connection, the N+1th data line is a long connection, and the N+2th data line is a long connection; for the M+2th gate line, the N+1th data line is a short connection, the N+2th data line is a long connection, and the N+3th data line is a short connection; for the M+3th gate line, the N+1th data line is a long connection, the N+2th data line is a short connection, and the N+3th data line is a long connection. 2 rows and 6 columns are a minimum period, and multiple periods are repeatedly arranged in the array substrate.

[0121] 1D , optionally, a common electrode line or a touch line may be provided between two adjacent data lines, for example, between R and G pixels, between B and R, between G and B, etc., which is not limited here.

[0122] In a possible embodiment, a variation of the embodiment of the present disclosure, for example, as shown in Figure 1E, includes 2 rows and 6 columns of pixels, and in the first row of sub-pixels, the distributed sub-pixels may be in the order of blue, green, red, blue, green, and red; in the second row of sub-pixels, the distributed sub-pixels may be in the order of blue, green, red, blue, green, and red; wherein, the green pixel in the second column of the first row is a long connection, the red pixel in the third column of the first row is a short connection, and the red pixel in the sixth column of the first row is a long connection, and they are all electrically connected to the first gate line; the blue pixel in the first column of the first row is a short connection, the blue pixel in the fourth column of the first row is a long connection, and the green pixel in the fifth column of the first row is a short connection, and they are all electrically connected to the second gate line; the blue pixel in the first column of the second row is a long connection, the red pixel in the third column of the second row is a long connection, and the red pixel in the sixth column of the second row is a short connection, and they are all electrically connected to the third gate line; the green pixel in the second column of the second row is a short connection, the blue pixel in the fourth column of the second row is a short connection, and the green pixel in the fifth column of the second row is a long connection, and they are all electrically connected to the fourth gate line.

[0123] For another example, as shown in Figure 1F, it includes 2 rows and 6 columns of pixels. In the first row of sub-pixels, the distributed sub-pixels can be: red, green, blue, red, green, blue, and in the second row of sub-pixels, the distributed sub-pixels can be: red, green, blue, red, green, blue; among them, the red pixels in the first row and the first column are long connections, the red pixels in the first row and the fourth column are short connections, and the green pixels in the first row and the fifth column are long connections, and they are all electrically connected to the first gate line; the green pixels in the first row and the second column are short connections, the blue pixels in the first row and the third column are long connections, and the blue pixels in the first row and the sixth column are short connections, and they are all electrically connected to the second gate line; the red pixels in the second row and the first column are short connections, the red pixels in the second row and the fourth column are long connections, and the blue pixels in the second row and the sixth column are long connections, and they are all electrically connected to the third gate line; the red pixels in the second row and the second column are long connections, the blue pixels in the second row and the third column are short connections, and the blue pixels in the second row and the fifth column are short connections, and they are all electrically connected to the fourth gate line.

[0124] For another example, as shown in Figure 1G, it includes 2 rows and 6 columns of pixels. In the first row of sub-pixels, the distributed sub-pixels can be: blue, green, red, blue, green, red, and in the second row of sub-pixels, the distributed sub-pixels can be: blue, green, red, blue, green, red; among them, the green pixel in the second column of the first row is a short connection, the blue pixel in the fourth column of the first row is a short connection, and the green pixel in the fifth column of the first row is a long connection, and they are all electrically connected to the first gate line; the blue pixel in the first column of the first row is a long connection, the red pixel in the third column of the first row is a long connection, and the red pixel in the sixth column of the first row is a short connection, and they are all electrically connected to the second gate line; the blue pixel in the first column of the second row is a short connection, the blue pixel in the fourth column of the second row is a long connection, and the green pixel in the fifth column of the second row is a short connection, and they are all electrically connected to the third gate line; the green pixel in the second column of the second row is a long connection, the red pixel in the third column of the second row is a short connection, and the red pixel in the sixth column of the second row is a long connection, and they are all electrically connected to the fourth gate line.

[0125] In a possible embodiment, referring to FIG3A , in the first region S1 of the pixel electrode unit P, the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 of the plurality of third pixel electrodes (i.e., blue sub-pixels B) are alternately arranged in the first direction X and in the second direction Y; in the region outside the first region S1 of the pixel electrode unit P, the first sub-pixel electrodes PB1 of the plurality of third pixel electrodes (i.e., blue sub-pixels B) are sequentially arranged in the first direction X and in the second direction Y, that is, in the region outside the first region S1 of the pixel electrode unit P, the plurality of third pixel electrodes (i.e., blue sub-pixels B) are all first sub-pixel electrodes PB1; the plurality of second pixel electrodes (i.e., green sub-pixels G) include: a plurality of second sub-pixel electrodes PB2; the second sub-pixel electrodes PB2 of the plurality of second pixel electrodes (i.e., green sub-pixels G) are sequentially arranged in the first direction X and in the second direction Y, that is, the plurality of second pixel electrodes (i.e., green sub-pixels G) are all second sub-pixel electrodes PB2.

[0126] For the pixel architecture shown in FIG3A, when the timing signal shown in FIG4 is loaded, in the mixed color screen displayed by the G and B sub-pixels, the G and B sub-pixels are turned on, and the R sub-pixel is turned off. Taking the period of one pixel electrode unit P as an example, the data signals written in different time periods by the K-th data line (the same as the K+3-th data line) and the brightness and darkness of the corresponding electrically connected sub-pixels are as follows: high (the first row and second column G sub-pixel is on), low (the first row and first column R sub-pixel is off), high (the second row sub-pixel connected to the K-th data line is off), .... =The sub-pixel connected to the 3rd data line, that is, the B sub-pixel in the second row and the sixth column is bright), high (the sub-pixel connected to the second row of the Kth data line is shown, and you can refer to the sub-pixel connected to the K+3th data line, that is, the G sub-pixel in the second row and the fifth column is bright), high (the G sub-pixel in the third row and the second column is bright), low (the R sub-pixel in the third row and the first column is off), high (the sub-pixel in the fourth row of the Kth data line is shown, and you can refer to the sub-pixel connected to the K+3th data line, that is, the B sub-pixel in the fourth row and the sixth column is bright), high (the sub-pixel in the fourth row of the Kth data line is shown, and you can refer to the sub-pixel in the K+3th data line, that is, the B sub-pixel in the fourth row and the sixth column is bright), high (the sub-pixel in the fourth row of the Kth data line is shown, and you can refer to the Referring to the sub-pixel connected to the K+3 data line, that is, the G sub-pixel in the fourth row and fifth column is bright), the following cycle is repeated; the data signals written to the K+1 data line at different time periods and the brightness and darkness of the corresponding electrically connected sub-pixels are as follows: low (the R sub-pixel in the first row and fourth column is off), high (the B sub-pixel in the first row and third column is on), high (the G sub-pixel in the second row and second column is on), low (the R sub-pixel in the second row and first column is off), low (the R sub-pixel in the third row and fourth column is off), high (the B sub-pixel in the third row and third column is on), high (the G sub-pixel in the fourth row and second column is on), Low (the R sub-pixel in the fourth row and first column is off), and the cycle continues; the data signals written to the K+2th data line at different time periods and the brightness and darkness of the corresponding electrically connected sub-pixels are: high (the B sub-pixel in the first row and sixth column is on), high (the G sub-pixel in the first row and fifth column is on), low (the R sub-pixel in the second row and fourth column is off), high (the B sub-pixel in the second row and third column is on), high (the G sub-pixel in the third row and fifth column is on), high (the B sub-pixel in the third row and sixth column is on), high (the B sub-pixel in the fourth row and third column is on), low (the R sub-pixel in the fourth row and fourth column is off), and the cycle continues;

[0127] As shown in FIG3B , within one cycle, taking the J+2 gate line turning on the second row and second column G sub-pixel as an example, the K+1 data line provides a signal. When the J+1 gate line of the previous row is turned on, the K+1 data line writes a high-level data signal of the first row and third column B sub-pixel. Therefore, before the second row and second column G sub-pixel is written with a formal data signal, the pre-charged signal is a high-level data signal of the first row and third column R sub-pixel. When the data signal is formally written, the voltage of the pixel electrode will be higher than the preset voltage, and the brightness will be high, so it is marked as good (pre-charged good), and so on. Similarly, it can be judged that the J gate line, the J+2 gate line, and the J+4 gate line are good. The G sub-pixels turned on by the J+1th gate line and the K+1th gate line are all pre-charged good; by analogy with the same method, the B sub-pixels in the first row and the third column are turned on by the J+1th gate line and the K+1th gate line, and the R sub-pixels controlled by the Jth gate line in the previous row are low level, so the pre-charge of the B sub-pixels is also low level, so the B sub-pixels in the first row and the third column are marked as poor (indicating pre-charge poor), and so on, the pre-charge of the B sub-pixels in the third column is: poor, poor, poor, and good; the B sub-pixels in the sixth column are also three poor and one good, so the brightness difference of the two columns of B sub-pixels is the same, and the brightness of the two columns of G sub-pixels is also the same, which fundamentally solves the problem of vertical stripes under the mixed color display of G and B sub-pixels.

[0128] In one possible implementation, referring to FIG3C , the plurality of first sub-pixel electrodes PB1 of the third pixel electrode (i.e., the blue sub-pixel B) include: a thirteenth electrode P13, a fourteenth electrode P14, a fifteenth electrode P15, a sixteenth electrode P16, a seventeenth electrode P17, and an eighteenth electrode P18; the plurality of second sub-pixel electrodes PB2 of the third pixel electrode (i.e., the blue sub-pixel B) include: a nineteenth electrode P9 and a twentieth electrode P12;

[0129] The thirteenth electrode P13 is electrically connected to the J+1th gate line and the K+1th data line; the fourteenth electrode P14 is electrically connected to the Jth gate line and the K+2th data line; the fifteenth electrode P15 is electrically connected to the J+3th gate line and the K+2th data line; the sixteenth electrode P16 is electrically connected to the J+2th gate line and the K+3th data line; the seventeenth electrode P17 is electrically connected to the J+5th gate line and the K+1th data line; the eighteenth electrode P18 is electrically connected to the J+6th gate line and the K+3th data line; the nineteenth electrode P19 is electrically connected to the J+5th gate line and the K+2th data line; and the twentieth electrode P20 is electrically connected to the J+6th gate line and the K+2th data line.

[0130] In a possible implementation, as shown in FIG3C , the plurality of second sub-pixel electrodes PB2 of the second pixel electrode (i.e., the green sub-pixel G) include: a twenty-first electrode P21, a twenty-second electrode P22, a twenty-third electrode P23, a twenty-fourth electrode P24, a twenty-fifth electrode P25, a twenty-sixth electrode P26, a twenty-seventh electrode P27, and a twenty-eighth electrode P28;

[0131] The twenty-first electrode P21 is electrically connected to the J-th gate line and the K-th data line; the twenty-second electrode P22 is electrically connected to the J+1-th gate line and the K+2-th data line; the twenty-third electrode P23 is electrically connected to the J+2-th gate line and the K+1-th data line; the twenty-fourth electrode P24 is electrically connected to the J+3-th gate line and the K+3-th data line; the twenty-fifth electrode P25 is electrically connected to the J+4-th gate line and the K-th data line; the twenty-sixth electrode P26 is electrically connected to the J+4-th gate line and the K+2-th data line; the twenty-seventh electrode P27 is electrically connected to the J+6-th gate line and the K+1-th data line; and the twenty-eighth electrode P28 is electrically connected to the J+7-th gate line and the K+3-th data line.

[0132] In one possible implementation, referring to FIG. 3C , the plurality of first electrodes (i.e., pixel electrodes of the red sub-pixel R) include: a twenty-ninth electrode P29, a thirtieth electrode P30, a thirty-first electrode P31, a thirty-second electrode P32, a thirty-third electrode P33, a thirty-fourth electrode P34, a thirty-fifth electrode P35, and a thirty-sixth electrode P36;

[0133] The twenty-ninth electrode P29 is electrically connected to the J+1th gate line and the Kth data line; the 30th electrode P30 is electrically connected to the Jth gate line and the K+1th data line; the thirty-first electrode P31 is electrically connected to the J+3th gate line and the K+1th data line; the thirty-second electrode P32 is electrically connected to the J+2th gate line and the K+2th data line; the thirty-third electrode P33 is electrically connected to the J+5th gate line and the Kth data line; the thirty-fourth electrode P34 is electrically connected to the J+4th gate line and the K+1th data line; the thirty-fifth electrode P35 is electrically connected to the J+7th gate line and the K+1th data line; and the thirty-sixth electrode P36 is electrically connected to the J+7th gate line and the K+2th data line.

[0134] In a possible embodiment, referring to FIG3C , the thirteenth electrode P13, the fourteenth electrode P14, the twenty-first electrode P21, the twenty-second electrode P22, the twenty-ninth electrode P29, and the thirtieth electrode P30 are located between the J-th gate line and the J+1-th gate line; the fifteenth electrode P15, the sixteenth electrode P16, the twenty-third electrode P23, the twenty-fourth electrode P24, the thirty-first electrode P31, and the thirty-second electrode P32 are located between the J+2-th gate line and the J+3-th gate line; the seventeenth electrode P17, the nineteenth electrode P19, the twenty-fifth electrode P25, the twenty-sixth electrode P26, the thirty-third electrode P33, and the thirty-fourth electrode P34 are located between the J+4-th gate line and the J+5-th gate line; the eighteenth electrode P18, the twentieth electrode P20, the twenty-seventh electrode P27, the twenty-eighth electrode P28, the thirty-fifth electrode P35, and the thirty-sixth electrode P36 are located between the J+6-th gate line and the J+7-th gate line;

[0135] The twenty-ninth electrode P29, the twenty-first electrode P21, the thirty-first electrode P31, the twenty-third electrode P23, the thirty-third electrode P33, the twenty-fifth electrode P25, the thirty-fifth electrode P35, and the twenty-seventh electrode P27 are located between the K-th data line and the K+1-th data line; the thirteenth electrode P13, the thirtieth electrode P30, the fifteenth electrode P15, the thirty-second electrode P32, the seventeenth electrode P17, the thirty-fourth electrode P34, the twentieth electrode P20, and the thirty-sixth electrode P36 are located between the K+1-th data line and the K+2-th data line; the twenty-second electrode P22, the fourteenth electrode P14, the twenty-fourth electrode P24, the sixteenth electrode P16, the twenty-sixth electrode P26, the nineteenth electrode P19, the twenty-eighth electrode P28, and the eighteenth electrode P18 are located between the K+2-th data line and the K+3-th data line.

[0136] In a possible implementation, referring to FIG3C , the twenty-first electrode P21 is located on a side of the twenty-ninth electrode P19 away from the K-th data line; the thirty-first electrode P31 is located on a side of the twenty-third electrode P23 away from the K+1-th data line; the twenty-fifth electrode P25 is located on a side of the thirty-third electrode P33 away from the K-th data line; and the thirty-fifth electrode P35 is located on a side of the twenty-seventh electrode P27 away from the K+1-th data line.

[0137] The 30th electrode P30 is located on a side of the 13th electrode P13 away from the (K+1)th data line; the 15th electrode P15 is located on a side of the 32nd electrode P32 away from the (K+2)th data line; the 34th electrode P34 is located on a side of the 17th electrode P17 away from the (K+1)th data line; the 20th electrode P20 is located on a side of the 36th electrode P36 away from the (K+2)th data line;

[0138] The fourteenth electrode P14 is located on the side of the twenty-second electrode P22 away from the K+2 data line; the twenty-fourth electrode P24 is located on the side of the sixteenth electrode P16 away from the K+3 data line; the nineteenth electrode P19 is located on the side of the twenty-sixth electrode P26 away from the K+2 data line; and the twenty-eighth electrode P28 is located on the side of the eighteenth electrode P18 away from the K+3 data line.

[0139] The Dual Gate pixel architecture shown in FIG3A to FIG3C provided by the embodiment of the present disclosure adopts a 2dot Z-inversion pixel structure. For the J-th gate line, the K-th data line is a long connection, the K+1-th data line is a long connection, and the K+2-th data line is a long connection; for the J+1-th gate line, the K-th data line is a short connection, the K+1-th data line is a short connection, and the K+2-th data line is a short connection; for the J+2-th gate line, the K-th data line is not connected, the K+1-th data line is a short connection, the K+2-th data line is a short connection, and the K+3-th data line is a short connection; for the J+3-th gate line, the K-th data line is not connected, the K+1-th data line is a long connection, and the K+ The 2 data lines are long connected, and the K+3 data line is long connected; for the J+4 gate line, the K data line is long connected, the K+1 data line is long connected, and the K+2 data line is short connected; for the J+5 gate line, the K data line is short connected, the K+1 data line is short connected, and the K+2 data line is long connected; for the J+6 gate line, the K data line is not connected, the K+1 data line is short connected, the K+2 data line is long connected, and the K+3 data line is short connected; for the J+7 gate line, the K data line is not connected, the K+1 data line is long connected, the K+2 data line is short connected, and the K+3 data line is long connected. Such a pixel structure and arrangement can improve the problem of poor vertical stripes; the minimum period of pixel arrangement is 4 rows and 6 columns, and the CF side color resistance adopts RGB arrangement order.

[0140] In a possible embodiment, variations of the disclosed embodiment, such as the horizontal flipping, vertical flipping, and mirror flipping architecture of the architecture shown in FIG3A, are also within the scope of protection of this case. Specifically, for example, the pixel architecture shown in architecture FIG3A is horizontally flipped to obtain the pixel architecture shown in FIG3D. For another example, the pixel architecture shown in architecture FIG3A is vertically flipped to obtain the pixel architecture shown in FIG3E. The pixel architecture shown in architecture FIG3A is horizontally and vertically flipped to obtain the pixel architecture shown in FIG3F.

[0141] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0142] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0143] Based on the same inventive concept, as shown in FIG5 , an embodiment of the present disclosure further provides a driving method for driving the array substrate provided in the embodiment of the present disclosure, wherein the driving method includes:

[0144] Step S100, controlling the loading of scanning signals to each gate line in sequence;

[0145] Step S200 : controlling the next gate line to be turned on within a period in which the current gate line is turned on, so as to pre-charge the pixel electrode electrically connected to the next gate line.

[0146] In one possible implementation, for the pixel architecture shown in FIG. 1A to FIG. 1D , when displaying a preset image (e.g., a sky blue image when only G and B sub-pixels are displayed), in conjunction with the timing diagram shown in FIG. 2 , step S200 includes controlling the next gate line to be turned on during the period in which the current gate line is turned on, so as to precharge the pixel electrode electrically connected to the next gate line.

[0147] In the first time period T1, the Mth gate line is controlled to load an effective scanning signal, and the Nth, N+1th, and N+2th data lines are controlled to load a first data signal; the effective scanning signal can be a signal for turning on the gate line, such as a high-level signal; the first data signal can be a high-level signal;

[0148] In the second period T2, the Mth and M+1th gate lines are controlled to load valid scan signals, the Nth and N+1th data lines are controlled to load second data signals, and the N+2th data line is controlled to load the first data signal; the second data signal can be a low-level signal;

[0149] In the third period T3, the Mth, M+1th, and M+2th gate lines are controlled to load valid scan signals, the Nth and N+1th data lines are controlled to load first data signals, and the N+2th data line is controlled to load second data signals;

[0150] In the fourth period T4, the M+1th, M+2th, and M+3th gate lines are controlled to load valid scan signals, the Nth and N+2th data lines are controlled to load first data signals, and the N+1th data line is controlled to load second data signals.

[0151] In one possible implementation, for the pixel architecture shown in FIG. 3A to FIG. 3C , when displaying a preset image (e.g., a sky blue image when only G and B sub-pixels are displayed), in conjunction with the timing diagram shown in FIG. 4 , step S200 includes controlling the next gate line to be turned on during the period in which the current gate line is turned on, so as to precharge the pixel electrode electrically connected to the next gate line.

[0152] In the first time period T1, the J-th gate line is controlled to load a valid scan signal, the K-th and K+2-th data lines are controlled to load a first data signal, and the K+1-th data line is controlled to load a second data signal;

[0153] In the second time period T2, the Jth and J+1th gate lines are controlled to load valid scan signals, the K+1th and K+2th data lines are controlled to load first data signals, and the Kth data line is controlled to load second data signals;

[0154] In the third time period T3, the Jth, J+1th, and J+2th gate lines are controlled to load valid scan signals, the Kth and K+1th data lines are controlled to load first data signals, and the K+2th data line is controlled to load second data signals;

[0155] In a fourth time period T4, the J+1th, J+2th, and J+3th gate lines are controlled to load valid scan signals, the Kth and K+2th data lines are controlled to load first data signals, and the K+1th data line is controlled to load second data signals;

[0156] In the fifth period T5, the J+2, J+3, and J+4 gate lines are controlled to load valid scan signals, the K and K+2 data lines are controlled to load first data signals, and the K+1 data line is controlled to load second data signals;

[0157] In the sixth period T6, the J+3, J+4, and J+5 gate lines are controlled to load valid scan signals, the K+1 and K+2 data lines are controlled to load first data signals, and the K data line is controlled to load second data signals;

[0158] In the seventh period T7, the J+4th, J+5th, and J+6th gate lines are controlled to load valid scan signals, and the Kth, K+1th, and K+2th data lines are controlled to load first data signals;

[0159] In the eighth period T8, the J+5th, J+6th, and J+7th gate lines are controlled to load valid scan signals, the Kth data line is controlled to load the first data signal, and the K+1th and K+2th data lines are controlled to load the second data signal;

[0160] In a ninth period T9, the J+6th and J+7th gate lines are controlled to load valid scan signals, the Kth and K+2th data lines are controlled to load first data signals, and the K+1th data line is controlled to load second data signals.

[0161] In the tenth period T10, the J+7th gate line is controlled to load the valid scan signal, the Kth, K+1th, and K+2th data lines are controlled to load the first data signal, and the Kth data line is controlled to load the second data signal.

[0162] In the embodiment of the present disclosure, in the repeating unit pixel electrode unit P, at least part of the second type pixel electrodes PB include: multiple first sub-pixel electrodes PB1 and multiple second sub-pixel electrodes PB2, the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 are alternately arranged in the first direction X, and the first sub-pixel electrodes PB1 and the second sub-pixel electrodes PB2 are alternately arranged in the second direction Y, which can avoid vertical stripes caused by the alternating distribution of one column of bright and one column of dark sub-pixels of the same color, and avoid horizontal stripes caused by the alternating distribution of one row of bright and one row of dark sub-pixels of the same color, and avoid the occurrence of intricate horizontal and vertical stripes, i.e., grid patterns, in the case of high refresh rate when the sub-pixels of the same color are viewed from the row direction, in which the bright and dark sub-pixels in one row are alternately distributed, and the sub-pixels in the adjacent rows are all brighter sub-pixels, while in which the bright and dark sub-pixels in one column are alternately distributed, and the sub-pixels in the adjacent columns are all brighter sub-pixels when viewed from the column direction.

[0163] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0164] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; multiple transistors; Located on one side of the substrate; A plurality of gate line groups are located on one side of the substrate, at least one of the plurality of gate line groups comprises: two gate lines extending along the first direction; a plurality of data lines, located on one side of the substrate, and extending along a second direction; A plurality of pixel electrode units, wherein the plurality of pixel electrode units are periodically and repeatedly arranged on the substrate; the pixel electrode units include: a plurality of first-type pixel electrodes and a plurality of second-type pixel electrodes; the light-emitting wavelength range of the region where the first-type pixel electrodes are located is different from the light-emitting wavelength range of the region where the second-type pixel electrodes are located; Among them, at least part of the second type of pixel electrodes includes: multiple first sub-pixel electrodes and multiple second sub-pixel electrodes; the first type of pixel electrodes are electrically connected to the same data line as the first sub-pixel electrodes and electrically connected to the previous gate line, and the second type of pixel electrodes are electrically connected to the same data line as the second sub-pixel electrodes and electrically connected to the previous gate line; at least part of the first sub-pixel electrodes and the second sub-pixel electrodes are alternately arranged in the first direction, and at least part of the first sub-pixel electrodes and the second sub-pixel electrodes are alternately arranged in the second direction.

2. The array substrate according to claim 1, wherein: The plurality of first-type pixel electrodes include: a plurality of first pixel electrodes; the plurality of second-type pixel electrodes include: a plurality of second pixel electrodes, and a plurality of third pixel electrodes; the light-emitting wavelength range of the region where the second pixel electrodes are located is greater than the light-emitting wavelength range of the region where the third pixel electrodes are located; the first pixel electrodes, the second pixel electrodes, and the third pixel electrodes are arranged in sequence along the first direction; The plurality of third pixel electrodes include the plurality of first sub-pixel electrodes and the plurality of second sub-pixel electrodes; in at least a portion of the pixel electrode unit, the first sub-pixel electrodes and the second sub-pixel electrodes of the plurality of third pixel electrodes are alternately arranged in the first direction. and arranged alternately in the second direction.

3. The array substrate according to claim 2, wherein: The plurality of second pixel electrodes include the plurality of first sub-pixel electrodes and the plurality of second sub-pixel electrodes; the first sub-pixel electrodes and the second sub-pixel electrodes of the plurality of second pixel electrodes are alternately arranged in the first direction and alternately arranged in the second direction.

4. The array substrate according to claim 3, wherein: The plurality of first sub-pixel electrodes of the third pixel electrode include: a first electrode and a second electrode; the plurality of second sub-pixel electrodes of the third pixel electrode include: a third electrode and a fourth electrode; The first electrode is electrically connected to the Mth gate line and the N+1th data line; the second electrode is electrically connected to the M+2th gate line and the N+3th data line; The third electrode is electrically connected to the (M+1)th gate line and the (N+2)th data line; the fourth electrode is electrically connected to the (M+2)th gate line and the (N+2)th data line.

5. The array substrate according to claim 3 or 4, wherein: The plurality of first sub-pixel electrodes of the second pixel electrode include: a fifth electrode and a sixth electrode; the plurality of second sub-pixel electrodes of the second pixel electrode include: a seventh electrode and an eighth electrode; The fifth electrode is electrically connected to the Mth gate line and the N+2th data line; the sixth electrode is electrically connected to the M+2th gate line and the N+1th data line; The seventh electrode is electrically connected to the Mth gate line and the Nth data line; the eighth electrode is electrically connected to the M+3th gate line and the N+3th data line.

6. The array substrate according to any one of claims 3 to 5, wherein: The plurality of first pixel electrodes include: a ninth electrode, a tenth electrode, an eleventh electrode, and a twelfth electrode; The ninth electrode is electrically connected to the Mth gate line and the Nth data line; the tenth electrode is electrically connected to the M+1th gate line and the N+1th data line; the eleventh electrode is electrically connected to the M+3th gate line and the N+1th data line; and the twelfth electrode is electrically connected to the M+3th gate line and the N+2th data line.

7. The array substrate according to any one of claims 3 to 6, wherein: The ninth electrode, the seventh electrode, the first electrode, the tenth electrode, the fifth electrode, and the third electrode are located between the Mth gate line and the M+1th gate line; the eleventh electrode, the sixth electrode, the fourth electrode, the twelfth electrode, the eighth electrode, and the second electrode are located between the M+2th gate line and the M+3th gate line; The ninth electrode, the seventh electrode, the eleventh electrode, and the sixth electrode are located between the Nth data line and the N+1th data line; the first electrode, the tenth electrode, the fourth electrode, and the twelfth electrode are located between the N+1th data line and the N+2th data line; the fifth electrode, the third electrode, the eighth electrode, and the second electrode are located between the N+2th data line and the N+3th data line.

8. The array substrate according to claim 7, wherein: The seventh electrode is located at a side of the ninth electrode away from the Nth data line; The sixth electrode is located on a side of the eleventh electrode away from the (N+1)th data line; The tenth electrode is located at a side of the first electrode away from the (N+1)th data line; The fourth electrode is located at a side of the twelfth electrode away from the (N+2)th data line; The third electrode is located at a side of the fifth electrode away from the (N+2)th data line; The eighth electrode is located on a side of the second electrode away from the (N+3)th data line.

9. The array substrate according to claim 2, wherein: In the first area of ​​the pixel electrode unit, the first sub-pixel electrodes and the second sub-pixel electrodes of the plurality of third pixel electrodes are alternately arranged in the first direction and alternately arranged in the second direction; in an area other than the first area of ​​the pixel electrode unit, the first sub-pixel electrodes of the plurality of third pixel electrodes are sequentially arranged in the first direction and sequentially arranged in the second direction; The plurality of second pixel electrodes include: the plurality of second sub-pixel electrodes; the second sub-pixel electrodes of the plurality of second pixel electrodes are sequentially arranged in the first direction and sequentially arranged in the second direction.

10. The array substrate according to claim 9, wherein: The plurality of first sub-pixel electrodes of the third pixel electrode include: a thirteenth electrode, a fourteenth electrode, a fifteenth electrode, a sixteenth electrode, a seventeenth electrode, and an eighteenth electrode; the plurality of second sub-pixel electrodes of the third pixel electrode include: a nineteenth electrode and a twentieth electrode; The thirteenth electrode is electrically connected to the J+1th gate line and the K+1th data line; the fourteenth electrode is electrically connected to the Jth gate line and the K+2th data line; the fifteenth electrode is electrically connected to the J+3th gate line and the K+2th data line; the sixteenth electrode is electrically connected to the J+2th gate line and the K+3th data line; the seventeenth electrode is electrically connected to the J+5th gate line and the K+1th data line; and the eighteenth electrode is electrically connected to the J+6th gate line and the K+3th data line. The nineteenth electrode is electrically connected to the J+5th gate line and the K+2th data line; the twentieth electrode is electrically connected to the J+6th gate line and the K+2th data line.

11. The array substrate according to claim 10, wherein: The plurality of second sub-pixel electrodes of the second pixel electrode include: a twenty-first electrode, a twenty-second electrode, a twenty-third electrode, a twenty-fourth electrode, a twenty-fifth electrode, a twenty-sixth electrode, a twenty-seventh electrode, and a twenty-eighth electrode; The twenty-first electrode is electrically connected to the J-th gate line and the K-th data line; the twenty-second electrode is electrically connected to the J+1-th gate line and the K+2-th data line; the twenty-third electrode is electrically connected to the J+2-th gate line and the K+1-th data line; the twenty-fourth electrode is electrically connected to the J+3-th gate line and the K+3-th data line; the twenty-fifth electrode is electrically connected to the J+4-th gate line and the K-th data line; the twenty-sixth electrode is electrically connected to the J+4-th gate line and the K+2-th data line; the twenty-seventh electrode is electrically connected to the J+6-th gate line and the K+1-th data line; and the twenty-eighth electrode is electrically connected to the J+7-th gate line and the K+3-th data line.

12. The array substrate according to claim 11, wherein: The plurality of first electrodes include: a twenty-ninth electrode, a thirtieth electrode, a thirty-first electrode, a thirty-second electrode, a thirty-third electrode, a thirty-fourth electrode, a thirty-fifth electrode, and a thirty-sixth electrode; The twenty-ninth electrode is electrically connected to the J+1th gate line and the Kth data line; the thirtieth electrode is electrically connected to the Jth gate line and the K+1th data line; the thirty-first electrode is electrically connected to the J+3th gate line and the K+1th data line; the thirty-second electrode is electrically connected to the J+2th gate line and the K+2th data line; the thirty-third electrode is electrically connected to the J+3rd gate line and the K+2th data line; The thirty-fourth electrode is electrically connected to the J+5th gate line and the Kth data line; the thirty-fifth electrode is electrically connected to the J+7th gate line and the K+1th data line; the thirty-sixth electrode is electrically connected to the J+7th gate line and the K+2th data line.

13. The array substrate according to claim 12, wherein: the thirteenth electrode, the fourteenth electrode, the twenty-first electrode, the twenty-second electrode, the twenty-ninth electrode, and the thirtieth electrode are located between the J-th gate line and the J+1-th gate line; the fifteenth electrode, the sixteenth electrode, the twenty-third electrode, the twenty-fourth electrode, the thirty-first electrode, and the thirty-second electrode are located between the J+2-th gate line and the J+3-th gate line; the seventeenth electrode, the nineteenth electrode, the twenty-fifth electrode, the twenty-sixth electrode, the thirty-third electrode, and the thirty-fourth electrode are located between the J+4-th gate line and the J+5-th gate line; the eighteenth electrode, the twentieth electrode, the twenty-seventh electrode, the twenty-eighth electrode, the thirty-fifth electrode, and the thirty-sixth electrode are located between the J+6-th gate line and the J+7-th gate line; The twenty-ninth electrode, the twenty-first electrode, the thirty-first electrode, the twenty-third electrode, the thirty-third electrode, the twenty-fifth electrode, the thirty-fifth electrode, and the twenty-seventh electrode are located between the K-th data line and the K+1-th data line; the thirteenth electrode, the thirtieth electrode, the fifteenth electrode, the thirty-second electrode, the seventeenth electrode, the thirty-fourth electrode, the twentieth electrode, and the thirty-sixth electrode are located between the K+1-th data line and the K+2-th data line; the twenty-second electrode, the fourteenth electrode, the twenty-fourth electrode, the sixteenth electrode, the twenty-sixth electrode, the nineteenth electrode, the twenty-eighth electrode, and the eighteenth electrode are located between the K+2-th data line and the K+3-th data line.

14. The array substrate according to claim 13, wherein: The twenty-first electrode is located on a side of the twenty-ninth electrode away from the Kth data line; the thirty-first electrode is located on a side of the twenty-third electrode away from the K+1th data line; the twenty-fifth electrode is located on a side of the thirty-third electrode away from the Kth data line; and the thirty-fifth electrode is located on a side of the twenty-seventh electrode away from the K+1th data line. The 30th electrode is located on a side of the 13th electrode away from the (K+1)th data line; the 15th electrode is located on a side of the 32nd electrode away from the (K+2)th data line; the 34th electrode is located on a side of the 17th electrode away from the (K+1)th data line; and the 20th electrode is located on a side of the 36th electrode away from the (K+2)th data line. The fourteenth electrode is located on the side of the twenty-second electrode away from the K+2 data line; the twenty-fourth electrode is located on the side of the sixteenth electrode away from the K+3 data line; the nineteenth electrode is located on the side of the twenty-sixth electrode away from the K+2 data line; and the twenty-eighth electrode is located on the side of the eighteenth electrode away from the K+3 data line.

15. A display panel, wherein: Comprising the array substrate according to any one of claims 1 to 14.

16. A display device, wherein: Comprising the display panel as claimed in claim 15.

17. A method for driving the array substrate according to any one of claims 1 to 14, wherein: The driving method includes: Control the loading of scanning signals to each gate line in sequence; During a period in which the current gate line is turned on, the next gate line is controlled to be turned on, so that the pixel electrode electrically connected to the next gate line is precharged.

18. The driving method according to claim 17, wherein: When displaying a preset image, the control controls the next gate line to be turned on during the period when the current gate line is turned on, so as to pre-charge the pixel electrode electrically connected to the next gate line, including: In a first time period, controlling the M-th gate line to load a valid scan signal, and controlling the N-th, N+1-th, and N+2-th data lines to load a first data signal; In the second period, the Mth and M+1th gate lines are controlled to load valid scan signals, the Nth and N+1th data lines are controlled to load second data signals, and the N+2th data line is controlled to load the first data signal; In a third period, controlling the Mth, M+1th, and M+2th gate lines to load valid scan signals, controlling the Nth and N+1th data lines to load first data signals, and controlling the N+2th data line to load second data signals; In the fourth period, the gate lines M+1, M+2 and M+3 are controlled to load effective scanning. Scanning signal, and controls the Nth and N+2th data lines to load the first data signal, and loads the second data signal to the N+1th data line.

19. The driving method according to claim 17, wherein: When the picture is preset, the driving method further includes: In a first period, controlling the J-th gate line to load a valid scan signal, controlling the K-th and K+2-th data lines to load a first data signal, and controlling the K+1-th data line to load a second data signal; In the second period, the J-th and J+1-th gate lines are controlled to load valid scan signals, the K+1-th and K+2-th data lines are controlled to load first data signals, and the K-th data line is controlled to load second data signals; In a third period, the Jth, J+1th, and J+2th gate lines are controlled to load valid scan signals, the Kth and K+1th data lines are controlled to load first data signals, and the K+2th data line is controlled to load second data signals; In a fourth period, the J+1th, J+2th, and J+3th gate lines are controlled to load valid scan signals, the Kth and K+2th data lines are controlled to load first data signals, and the K+1th data line is controlled to load second data signals; In a fifth period, the J+2, J+3, and J+4 gate lines are controlled to load valid scan signals, the K and K+2 data lines are controlled to load first data signals, and the K+1 data line is controlled to load second data signals; In a sixth period, the J+3, J+4, and J+5 gate lines are controlled to load valid scan signals, the K+1 and K+2 data lines are controlled to load first data signals, and the Kth data line is controlled to load second data signals; In the seventh period, the J+4th, J+5th, and J+6th gate lines are controlled to load valid scan signals, and the Kth, K+1th, and K+2th data lines are controlled to load first data signals; In an eighth time period, the J+5th, J+6th, and J+7th gate lines are controlled to load valid scan signals, the Kth data line is controlled to load the first data signal, and the K+1th and K+2th data lines are controlled to load the second data signal; In a ninth period, the J+6th and J+7th gate lines are controlled to load valid scan signals, the Kth and K+2th data lines are controlled to load first data signals, and the K+1th data line is controlled to load second data signals; In the tenth period, the J+7th gate line is controlled to load a valid scan signal, the Kth, K+1th, and K+2th data lines are controlled to load a first data signal, and the Kth data line is controlled to load a second data signal.

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