Display panel and preparation method therefor, and display device

Abstract

A display panel (00) and a preparation method therefor, and a display device. The display panel (00) comprises an array substrate (0) and an opposing substrate (1) arranged opposite to each other. A gate conductive layer (GATE) in the array substrate (0) can be used for forming a gate line (G1) connected to pixels (02), and a first common electrode (COM1) located in a spacer region (B1) of at least two adjacent pixels (02), and the orthographic projection of a reflecting layer (REF) on a substrate (01) overlaps with the orthographic projection of the first common electrode (COM1) on the substrate (01). A light blocking structure replacing a black matrix (BM) can be formed in the spacer region (B1). The black matrix (BM) does not need to be arranged at the side of the opposing substrate (1) corresponding to the spacer region (B1), so that it is ensured that the reflection aperture ratio of the display panel (00) is large while light leakage is avoided.

Description

Display panel and manufacturing method thereof, and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] A semi-transmissive and semi-reflective display panel is one of the common display panels, which can display in a reflective mode in a high-brightness environment and a transmissive mode in a low-brightness environment, respectively, to better match display power consumption and display brightness.

[0003] In related art, a transflective display panel typically includes an array substrate and a counter substrate facing each other, and a liquid crystal layer located between the two substrates. The liquid crystal layer is driven by voltages applied to the array and counter substrates, allowing the display panel to display images. Furthermore, a large amount of black matrix is ​​typically provided on one side of the counter substrate to shield the light leakage areas of the array substrate and prevent light leakage.

[0004] However, the provision of the black matrix will reduce the aperture ratio of the display panel, thereby resulting in poor display effect of the display panel.

[0005] Summary of the Invention

[0006] Provided are a display panel, a method for manufacturing the same, and a display device. The technical solution is as follows:

[0007] In one aspect, a display panel is provided, comprising: an array substrate and an opposing substrate disposed opposite to each other; the array substrate comprising:

[0008] substrate;

[0009] A plurality of gate lines, a plurality of data lines, and a plurality of pixels are all located on a side of the substrate close to the counter substrate, the plurality of pixels are spaced apart and arranged in an array, each pixel is connected to one of the gate lines and one of the data lines, and each pixel has an adjacent transmissive region and a reflective region, each pixel includes a transparent conductive layer located on one side of the substrate in the transmissive region and the reflective region, and each pixel includes a reflective layer located on a side of the transparent conductive layer away from the substrate in the reflective region;

[0010] A source-drain conductive layer and a gate conductive layer are located between the substrate and the transparent conductive layer and are stacked in sequence, the source-drain conductive layer is used to form the data line, and the gate conductive layer is used to form the gate line and a first common electrode, and the first common electrode is located in a space between at least two adjacent pixels;

[0011] The orthographic projection of the reflective layer on the substrate satisfies the following requirements: overlapping with the orthographic projection of the first common electrode on the substrate, covering the orthographic projection of the gate line on the substrate, and covering the orthographic projection of at least part of the data line segment on the substrate.

[0012] Optionally, the first common electrode includes: a first electrode pattern, and the first electrode pattern is located in the interval between every two adjacent pixels in the same column;

[0013] The source-drain conductive layer is also used to form a second common electrode, and the second common electrode is located in the interval area between at least two adjacent pixels in the same row, and the orthographic projection of the reflective layer on the substrate also meets the requirement of overlapping with the orthographic projection of the second common electrode on the substrate.

[0014] Optionally, the plurality of pixels include a plurality of groups of pixels, each group of pixels includes two adjacent pixels located in the same row, and two data lines connected to the two adjacent pixels are located between the two adjacent pixels;

[0015] The second common electrode includes a second electrode pattern, and the second electrode pattern is located in the interval area of ​​each group of pixels.

[0016] Optionally, each of the two data lines includes a first line segment and a second line segment extending along a pixel column direction;

[0017] The width of the first line segment is greater than the width of the second line segment, and the line segments of the two data lines with different widths are arranged axially symmetrically about a symmetry axis extending along the pixel column direction;

[0018] The orthographic projection of the reflective layer on the substrate satisfies: overlapping with the orthographic projection of the first line segment of the data line on the substrate, and covering the orthographic projection of the second line segment of the data line on the substrate.

[0019] Optionally, the display panel further includes:

[0020] A first black matrix is ​​located on a side of the counter substrate close to the array substrate, and an orthographic projection of the first black matrix on the substrate covers an orthographic projection of a portion of the first line segment that does not overlap with the reflective layer on the substrate.

[0021] Optionally, the width of each portion of each of the two data lines is equal;

[0022] The second common electrode further includes: a third electrode pattern, and the third electrode pattern is located in a space between two adjacent pixels in each group of pixels and between the two data lines;

[0023] The orthographic projection of the reflective layer on the substrate satisfies: covering the orthographic projection of the data line on the substrate.

[0024] Optionally, the first common electrode further includes: a fourth electrode pattern, and the fourth electrode pattern is located on a side of at least one of the second electrode pattern and the third electrode pattern close to the substrate;

[0025] Furthermore, the orthographic projection of the fourth electrode pattern on the substrate covers the orthographic projection of the at least one electrode pattern on the substrate.

[0026] Optionally, the first common electrode includes: a first electrode pattern and a fifth electrode pattern, and the first electrode pattern is located in the space between every two adjacent pixels in the same column, and the fifth electrode pattern is located in the space between every two adjacent pixels in the same row.

[0027] Optionally, among the plurality of pixels, two data lines connecting two adjacent pixels in the same row are respectively located on two sides of one of the pixels;

[0028] Furthermore, each of the two data lines includes a transfer line segment and a main line segment, the transfer line segment is connected to the pixel, and an orthographic projection of the transfer line segment on the substrate overlaps with an orthographic projection of the gate line and the first common electrode on the substrate, and at least a portion of the main line segment is located between the fifth electrode pattern and the pixel connected to the transfer line segment;

[0029] The orthographic projection of the reflective layer on the substrate satisfies: covering the orthographic projection of the main line segment on the substrate, and overlapping with the orthographic projection of the transition line segment on the substrate.

[0030] Optionally, each portion of the main line segment is located between the fifth electrode pattern and the pixel connected to the adapter line segment;

[0031] Furthermore, the main body line segment and the fifth electrode pattern are parallel to each other.

[0032] Optionally, a portion of the main line segment is located between the fifth electrode pattern and a pixel connected to the adapter line segment, and another portion of the main line segment is located between pixels adjacent to the pixel connected to the fifth electrode pattern and the adapter line segment;

[0033] Furthermore, the main body segment and the fifth electrode pattern intersect each other, and a length of a portion of the main body segment is the same as a length of another portion of the main body segment.

[0034] Optionally, the display panel further includes:

[0035] The second black matrix is ​​located on a side of the counter substrate close to the array substrate, and the orthographic projection of the second black matrix on the substrate covers the orthographic projection of the adapter segment on the substrate.

[0036] Optionally, the line width of the gate line and the line width of at least part of the line segment of the data line are both smaller than a line width threshold, so that the orthographic projection of the reflective layer on the substrate satisfies: covering the orthographic projection of the gate line on the substrate, and covering the orthographic projection of at least part of the line segment of the data line on the substrate; the display panel further includes:

[0037] a supporting column, located between the array substrate and the counter substrate;

[0038] The third black matrix is ​​located on a side of the counter substrate close to the array substrate, and the orthographic projection of the third black matrix on the substrate overlaps with the orthographic projection of the supporting pillar on the substrate.

[0039] In another aspect, a method for manufacturing a display panel is provided, for manufacturing the display panel according to the above aspect; the method comprising:

[0040] forming a counter substrate;

[0041] forming a substrate on a side opposite to the counter substrate;

[0042] A plurality of gate lines, a plurality of data lines, and a plurality of pixels are formed on a side of the substrate close to the counter substrate, wherein the plurality of pixels are spaced apart and arranged in an array, each pixel is connected to one of the gate lines and one of the data lines, and each pixel has an adjacent transmission area and a reflection area, each pixel includes a transparent conductive layer located on one side of the substrate in the transmission area and the reflection area, and each pixel includes a reflection layer located on a side of the transparent conductive layer away from the substrate in the reflection area;

[0043] forming a source-drain conductive layer and a gate conductive layer stacked in sequence between the substrate and the transparent conductive layer, wherein the source-drain conductive layer is used to form the data line, and the gate conductive layer is used to form the gate line and a first common electrode, and the first common electrode is located in a space between at least two adjacent pixels;

[0044] Moreover, the orthographic projection of the formed reflective layer on the substrate satisfies: overlapping with the orthographic projection of the first common electrode on the substrate, covering the orthographic projection of the gate line on the substrate, and covering the orthographic projection of at least part of the data line segment on the substrate.

[0045] In another aspect, a display device is provided, comprising: a power supply component, and the display panel according to the above aspect;

[0046] The power supply component is coupled to the display panel and is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] FIG1 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0049] FIG2 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0050] FIG3 is a cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application;

[0051] FIG4 is a schematic top view of an array substrate provided in an embodiment of the present application;

[0052] FIG5 is a schematic cross-sectional view of the structure shown in FIG4 taken along the line AA';

[0053] FIG6 is a schematic cross-sectional view of the structure shown in FIG4 taken along the BB' direction;

[0054] FIG7 is a schematic cross-sectional view of the structure shown in FIG4 along the CC' direction;

[0055] FIG8 is a schematic cross-sectional view of the structure shown in FIG4 along the DD' direction;

[0056] FIG9 is a schematic top view of a display panel based on the structure shown in FIG4 ;

[0057] FIG10 is a schematic top view of another array substrate provided in an embodiment of the present application;

[0058] FIG11 is a schematic cross-sectional view of the structure shown in FIG10 taken along the BB' direction;

[0059] FIG12 is a schematic cross-sectional view of the structure shown in FIG10 in the CC' direction;

[0060] FIG13 is a schematic cross-sectional view of the structure shown in FIG10 in the DD' direction;

[0061] FIG14 is a schematic top view of another array substrate provided in an embodiment of the present application;

[0062] FIG15 is a schematic cross-sectional view of the structure shown in FIG14 taken along the BB' direction;

[0063] FIG16 is a schematic cross-sectional view of the structure shown in FIG14 in the CC' direction;

[0064] FIG17 is a schematic cross-sectional view of the structure shown in FIG14 taken along the DD' direction;

[0065] FIG18 is a schematic top view of another array substrate provided in an embodiment of the present application;

[0066] FIG19 is a schematic cross-sectional view of the structure shown in FIG18 taken along the BB' direction;

[0067] FIG20 is a schematic cross-sectional view of the structure shown in FIG18 taken along the CC' direction;

[0068] FIG21 is a schematic cross-sectional view of the structure shown in FIG18 taken along the DD' direction;

[0069] FIG22 is a schematic top view of another array substrate provided in an embodiment of the present application;

[0070] FIG23 is a schematic cross-sectional view of the structure shown in FIG22 along the CC' direction;

[0071] FIG24 is a schematic cross-sectional view of the structure shown in FIG22 taken along the DD' direction;

[0072] FIG25 is a schematic top view of another display panel based on the structure shown in FIG18 ;

[0073] FIG26 is a schematic top view of yet another display panel based on the structure shown in FIG22 ;

[0074] FIG27 is a schematic top view of yet another display panel based on the structure shown in FIG10 ;

[0075] FIG28 is a schematic top view of yet another display panel based on the structure shown in FIG14 ;

[0076] FIG29 is a schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0077] FIG30 is a schematic diagram of a manufacturing process of a display panel based on the structure shown in FIG4 ;

[0078] FIG31 is a schematic diagram of another process for manufacturing a display panel based on the structure shown in FIG10 ;

[0079] FIG32 is a schematic diagram of a manufacturing process of another display panel based on the structure shown in FIG14;

[0080] FIG33 is a schematic diagram of a manufacturing process of another display panel based on the structure shown in FIG18 ;

[0081] FIG34 is a schematic diagram of a manufacturing process of another display panel based on the structure shown in FIG23;

[0082] Figure 35 is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0083] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0084] At present, the traditional transmissive display panel does not display clearly when displayed outdoors because the ambient light is too bright (i.e., in a high-brightness environment). The display effect is usually improved by increasing the screen brightness, but increasing the brightness will increase the display power consumption. Although the traditional reflective display panel can clearly reflect and display when the ambient light brightness is very high, thereby reducing the display power consumption, it cannot achieve a clear display effect when the ambient light brightness is low or in a dark scene (i.e., in a low-brightness environment). Therefore, a semi-transmissive and semi-reflective display panel with both reflective and transmissive functions has come into being. The semi-transmissive and semi-reflective display panel can use the reflective mode to display clearly in a high-brightness environment, and can use the transmissive mode to display in a low-brightness environment to reduce power consumption, thereby achieving a low power consumption and clear display effect. However, for the semi-transmissive and semi-reflective display panel, a large amount of black matrix (BM) needs to be set to block light leakage, resulting in a low reflective aperture ratio.

[0085] Based on this, the embodiment of the present application provides a novel semi-transmissive and semi-reflective display panel, which can block light leakage by changing the pixel design and reduce the setting of the black matrix BM, thereby improving the reflective aperture ratio.

[0086] FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in FIG1 , the display panel includes an array substrate 0 and an opposing substrate 1 that are arranged opposite to each other.

[0087] Optionally, the counter substrate 1 may be a color filter (CF) substrate. Furthermore, referring to FIG1 , the display panel may further include: a liquid crystal layer 2 located between the array substrate 0 and the counter substrate 1. The liquid crystal layer may include liquid crystal molecules. Driven by the array substrate 0 and the counter substrate 1, the liquid crystal molecules in the liquid crystal layer 2 may be deflected, thereby allowing light to pass through or not pass through, thereby achieving light transmission or opacity. It is understood that one side of the counter substrate 1 may include a common electrode, and one side of the array substrate 0 may include a pixel electrode. The liquid crystal molecules may be deflected by the voltage difference between the common electrode and the pixel electrode.

[0088] Based on FIG1 , referring to FIG2 , it can be seen that the array substrate 0 includes:

[0089] Substrate 01.

[0090] Multiple gate lines G1, multiple data lines D1, and multiple pixels 02 are all located on a side of the substrate 01 close to the opposing substrate 1. The multiple pixels 02 are spaced apart and arranged in an array. Each pixel 02 is connected to a gate line G1 and a data line D1, and each pixel 02 has an adjacent transmissive area A1 and a reflective area A2. Therefore, it can be determined that the display panel provided in the embodiment of the present application is a semi-transmissive and semi-reflective display panel.

[0091] Among them, the interval and array arrangement can refer to the arrangement of multiple pixels 02 in rows and columns, that is, the array substrate 0 can include multiple rows of pixels 02 arranged along the pixel row direction X1, and multiple pixels 02 arranged along the pixel column direction Y1. Multiple pixels 02 located in the same row can be connected to the same gate line G1, and multiple pixels 02 located in the same column can be connected to the same data line D1. The transmission area A1 and the reflection area A2 of each pixel 02 can be adjacent along the pixel column direction Y1 as shown in Figure 2. Of course, the arrangement, connection method and position relationship here are only schematic illustrations. In addition, each pixel 02 can include a pixel circuit and a pixel electrode described above. The pixel circuit can provide a driving voltage to the pixel electrode based on the gate drive signal provided by the gate line G1 and the data signal provided by the data line D1, so that the pixel electrode forms a voltage difference with the common voltage on the common electrode on one side of the opposing substrate 1, driving the liquid crystal molecules to deflect.

[0092] Based on Figure 2, it can be seen from Figure 3 that in the transmission area A1 and the reflection area A2, each pixel 02 includes a transparent conductive layer located on one side of the substrate 01. For example, the material of the transparent conductive layer can be indium tin oxide (ITO), and accordingly, the transparent conductive layer can also be called an ITO layer. Of course, the materials here are only schematic illustrations. In the reflection area A2, each pixel 02 includes a reflective layer (reflector, REF) REF located on the side of the transparent conductive layer ITO away from the substrate 01. The reflective layer REF can overlap with the transparent conductive layer ITO to form a pixel electrode, but the reflective layer REF does not completely cover the transparent conductive layer ITO. That is, as shown in Figure 3, in the transmission area A1, the transparent conductive layer ITO is farthest from the substrate 01 to achieve transmission display; in the reflection area A2, the reflective layer REF is farthest from the substrate 01 to achieve reflection display.

[0093] Furthermore, referring to FIG. 3 , it can be seen that the array substrate 0 further includes:

[0094] The source and drain (SD) conductive layer SD and the gate conductive layer GATE are located between the substrate 01 and the transparent conductive layer ITO and are stacked in sequence. For example, the gate conductive layer GATE and the source and drain conductive layer SD can be stacked in sequence in a direction away from the substrate 01 as shown in FIG3 . Alternatively, in some other embodiments, the gate conductive layer GATE and the source and drain conductive layer SD can also be stacked in sequence in a direction close to the substrate 01 . Furthermore, the source and drain conductive layer SD is used to form the data line D1 (not shown in FIG3 ), and the gate conductive layer GATE is used to form the gate line G1 (not shown in FIG3 ) and the first common electrode COM1, and the first common electrode COM1 is located in the spacer area B1 of at least two adjacent pixels 02. Of course, the gate conductive layer GATE is also used to form the gate in the pixel 02, as well as other common electrodes COM0 located in the non-spacer area B1. The source and drain conductive layer SD is also used to form the source and drain in the pixel 02.

[0095] Among them, the orthographic projection of the reflective layer REF on the substrate 01 satisfies: overlapping with (i.e., partially overlapping) the orthographic projection of the first common electrode COM1 on the substrate 01, covering the orthographic projection of the gate line G1 on the substrate 01, and covering the orthographic projection of at least part of the line segment of the data line D1 on the substrate 01.

[0096] It can be understood that since the reflective layer REF and the first common electrode COM1 are generally non-transparent conductive layers. For example, the material of the reflective layer REF and the material of the first common electrode COM1 are generally metal aluminum (Al), metal silver (Ag) or molybdenum aluminum alloy (MoAl), and since the first common electrode COM1 is located in the spacer area B1, the overlapping portion of the reflective layer REF and the first common electrode COM1 can form a light-shielding structure located in the spacer area B1 to block light leakage in the spacer area B1. Accordingly, there is no need to form a black matrix BM on the opposing substrate 1 located on one side of the light-shielding structure. That is, in one embodiment, the black matrix BM can be replaced by the first common electrode COM1 formed by overlapping REF and the gate conductive layer GATE to block light leakage.

[0097] It is also understood that in the embodiments of the present application, the voltages on the common electrodes (e.g., the first common electrode and the common electrode on the opposite substrate) can be equal. For example, the common electrodes can be connected at the outermost periphery of the display panel and connected together to a peripheral integrated circuit (IC) to receive the same and constant common voltage provided by the IC.

[0098] Currently, to replace the black matrix BM to block light leakage, an embodiment has been proposed in which a reflective layer REF overlaps with the gate line G1 and / or the data line D1 to form a light-shielding structure. However, because the voltage on the gate line G1 is relatively high for a long time, such as 15 volts (V) or -10V, the voltage on the data line D1 will fluctuate, typically fluctuating between 5V and -5V, while the voltage on the common electrode on the opposite substrate 1 side is constant. Therefore, when the reflective layer REF overlaps with the gate line G1 or the data line D1 to form a light-shielding structure, and there is a gap between adjacent pixels O2 above, below, and on the left and right sides, the gate line G1 or the data line D1 cannot be effectively covered by the reflective layer REF. This, in turn, causes a large vertical electric field to form between the gate line G1 or the data line D1 and the common electrode on the opposite substrate 1 side, causing the liquid crystal molecules to be mis-deflected, thereby causing reflected light leakage.

[0099] In the embodiment of the present application, since the voltages on the common electrodes are all constant and the same voltage, for example, the voltage of the first common electrode COM1 is the same as the voltage of the common electrode on the side of the opposing substrate 1, the formation of a vertical electric field can be avoided on the basis of setting the reflective layer REF and the first common electrode COM1 to overlap to form a light-shielding structure, thereby avoiding the mis-deflection of the liquid crystal molecules and better shielding the light leakage.

[0100] In addition, when the reflective layer REF and the first common electrode COM1 formed by the gate conductive layer GATE overlap to form a light shielding structure, as described above, the reflective layer REF can effectively cover all gate lines G1 and at least part of the data line D1, thereby effectively reducing the occurrence of vertical electric fields.

[0101] It is understood that for the data line D1 not covered by the reflective layer REF and located in the spacer area B1, a black matrix BM can be further provided at the corresponding position on the counter substrate 1 to block light leakage and ensure a better display effect. Based on this, it can also be seen that compared to the current solution of overlapping the reflective layer REF and the data line D1 to form a light-shielding structure, the overlapping area of ​​the reflective layer REF and the data line D1 is significantly reduced, thereby reducing the coupling capacitance on the data line D1.

[0102] In summary, an embodiment of the present disclosure provides a display panel. In this display panel, an array substrate includes an array substrate and an opposing substrate. The gate conductive layer in the array substrate can be used to form a gate line connecting pixels and a common electrode located in the spacer area, and the reflective layer overlaps with the common electrode. In this way, a light-shielding structure that replaces the black matrix can be formed in the spacer area to avoid light leakage in the spacer area. In other words, there is no need to set a black matrix at the position corresponding to the spacer area on the side of the opposing substrate. In this way, while avoiding light leakage, the reflective aperture ratio of the display panel can be ensured to be large, thereby ensuring a good display effect.

[0103] In addition, since the light-shielding structure is formed by overlapping the reflective layer and the common electrode, the common electrode and the common electrode on the opposite substrate side generally have the same potential, so it can avoid the formation of a vertical electric field that causes the liquid crystal molecules in the display panel to be misdeflected and cause reflected light leakage, which can further ensure a better display effect.

[0104] Optionally, as can be seen from FIG. 3 , the array substrate 0 described in the embodiment of the present application may further include: a gate insulator (GI) layer GI and an active (ACT) layer located between the gate conductive layer GATE and the source / drain conductive layer SD and stacked sequentially in a direction away from the substrate 01; a passivation (PVX) layer PVX located between the source / drain conductive layer SD and the transparent conductive layer ITO; and a concave-convex layer located between the transparent conductive layer ITO and the reflective layer REF. For example, the concave-convex layer may be made of acrylic (ACR), and accordingly, the concave-convex layer may also be referred to as an ACR layer.

[0105] In the transmission area A1, the concave-convex layer ACR may have an ACR macropore K0 exposing the transparent conductive layer ITO, and the reflective layer REF may overlap with the transparent conductive layer ITO at the position of the ACR macropore K0. Here, the reflective layer REF can be used as a metal pixel electrode, and the transparent conductive layer ITO can be used as a transparent pixel electrode, that is, the metal pixel electrode and the transparent pixel electrode can be used as the pixel electrode described above after overlapping. The passivation layer PVX may have a via exposing the source and drain conductive layer SD, and the transparent conductive layer ITO can overlap with the source and drain conductive layer SD through the via, and the pixel voltage can be provided to the pixel electrode including the transparent conductive layer ITO through the source and drain conductive layer SD.

[0106] It is understood that the portion of the reflective area A2 including the active layer ACT can be divided into the channel region of the pixel circuit. Referring to Figure 3, in the channel region of the reflective area A2, the array substrate 0 can include at least: a gate conductive layer GATE, a gate insulating layer GI, an active layer ACT, a source-drain conductive layer SD, a passivation layer PVX, a concave-convex layer ACR, and a reflective layer REF, stacked in sequence. In the area of ​​the reflective area A2 excluding the channel region, the array substrate 0 can include at least: a gate conductive layer GATE, a gate insulating layer GI, a source-drain conductive layer SD, a passivation layer PVX, a concave-convex layer ACR, and a reflective layer REF, stacked in sequence. Of course, a transparent conductive layer ITO can also be included between the concave-convex layer ACR and the passivation layer PVX. In the transmissive area A1, the array substrate 0 can include at least: a gate insulating layer GI, a passivation layer PVX, a transparent conductive layer ITO, and a portion of the concave-convex layer ACR, stacked in sequence. It can be seen from this that the array substrate 0 includes different numbers of film layers in the transmissive area A1 and the reflective area A2. Accordingly, there is a certain difference in film thickness between the transmissive area A1 and the reflective area A2, forming two cell thicknesses.

[0107] Optionally, in a first embodiment, as shown in FIG4 :

[0108] The first common electrode COM1 may include a first electrode pattern COM11, and the first electrode pattern COM11 may be located in the spacer B1 between every two adjacent pixels 02 in the same column. That is, the first electrode pattern COM11 may extend along the pixel row direction X1. In other words, the gate conductive layer GATE may at least form a horizontal common electrode (i.e., the first electrode pattern COM11) that overlaps with the reflective layer REF, thereby forming a light shielding structure in the spacer B1 between two adjacent pixels 02 in the same column to block light leakage.

[0109] Optionally, Figure 5 shows a schematic cross-sectional view of the structure shown in Figure 4 in the A-A' direction, Figure 6 shows a schematic cross-sectional view of the structure shown in Figure 4 in the BB' direction, Figure 7 shows a schematic cross-sectional view of the structure shown in Figure 4 in the C-C' direction, and Figure 8 shows a schematic cross-sectional view of the structure shown in Figure 4 in the D-D' direction.

[0110] Continuing with reference to FIG. 4 and the corresponding cross-sectional view, it can be seen that the source-drain conductive layer SD can also be used to form a second common electrode COM2. This second common electrode COM2 can be located in the spacer B1 between at least two adjacent pixels 02 in the same row. That is, the second common electrode COM2 can extend along the pixel column direction Y1. In other words, the source-drain conductive layer SD can also form a vertical common electrode. Furthermore, the orthographic projection of the reflective layer REF on the substrate 01 can also overlap with the orthographic projection of the second common electrode COM2 on the substrate 01. Combined with the aforementioned description, the overlapping portion of the reflective layer REF and the second common electrode COM2 can also form a light shielding structure to block light leakage. In other words, the source-drain conductive layer SD can form a vertical common electrode that overlaps with the reflective layer REF, forming a light shielding structure between the spacer B1 between two adjacent pixels 02 in the same row. Because the common electrode formed by the source-drain conductive layer SD has the same potential as the common electrode on the opposing substrate 1, it can also prevent the formation of a vertical electric field, thereby preventing mis-deflection of liquid crystal molecules and effectively blocking light leakage.

[0111] In other words, in this first embodiment, in the space B1 between two adjacent pixels 02 in the same column, a common electrode can be formed using the gate conductive layer GATE, and a reflective layer REF can be provided to overlap the common electrode formed by the gate conductive layer GATE to form a light-shielding structure, thereby achieving a horizontal reflective light-shielding effect. In the space B1 between two adjacent pixels 02 in the same row, a common electrode can be formed using the source / drain conductive layer SD, and a reflective layer REF can be provided to overlap the common electrode formed by the source / drain conductive layer SD to form a light-shielding structure, thereby achieving a vertical reflective light-shielding effect.

[0112] It can be understood that by forming shading structures in both the horizontal and vertical spacing areas B1, the display panel can be free of not only horizontal reflection light leakage but also vertical reflection light leakage, that is, it can better block light leakage and ensure a better display effect of the semi-transmissive and semi-reflective display panel.

[0113] Optionally, it can be seen from FIG4 that in the first embodiment:

[0114] The plurality of pixels 02 may include a plurality of groups of pixels 02Z, each group of pixels 02Z may include two adjacent pixels 02 located in the same row, and the two data lines D1 connected to the two adjacent pixels 02 may be located between the two adjacent pixels 02. That is, the plurality of pixels 02 included in the array substrate 0 may be divided into a plurality of groups of pixels 02Z, with two adjacent columns of pixels forming a group, and the two data lines D1 connected to the two columns of pixels being located between the two columns of pixels, with the two data lines D1 being adjacent to each other.

[0115] For example, in the pixel row direction X1, the spacing between two adjacent data lines D1 between two columns of pixels may be approximately 4 micrometers (μm). It is understood that "approximately" or "approximately" in the embodiments of the present application may mean floating and variable within a certain range.

[0116] Based on this configuration, with continued reference to FIG. 4 and the corresponding cross-sectional view, it can be seen that the second common electrode COM2 described in the embodiment of the present disclosure may include: a second electrode pattern COM21, and the second electrode pattern COM21 may be located in the spacing region B1 of each group of pixels 02. That is, based on dividing the plurality of pixels 02 into a plurality of groups of pixels 02Z, the source-drain conductive layer SD can at least form a vertical common electrode (i.e., the second electrode pattern COM21) located in the spacing region B1 of each group of pixels 02Z, overlapping with the reflective electrode REF, thereby forming a light shielding structure in the spacing region B1 of two adjacent pixels 02 in the same row.

[0117] Optionally, in an implementation of the first embodiment, further referring to FIG4 , it can be seen that:

[0118] Each of the two data lines D1 may include a first line segment D11 and a second line segment D12 extending along the pixel column direction Y1 .

[0119] The width of the first line segment D11 can be greater than the width of the second line segment D12, and the line segments of different widths in the two data lines D1 can be arranged symmetrically about an axis of symmetry extending along the pixel column direction Y1. That is, as shown in Figure 4, in each of the two data lines D1, half (i.e., the first line segment D11) can have a wide line width, and the other half (i.e., the second line segment D12) can have a narrow line width; and along the same direction (e.g., from top to bottom), one data line D1 can transform from a wide line width to a narrow line width, and the other data line D1 can transform from a narrow line width to a wide line width; and the width-to-narrow transformation positions of the two data lines D1 are the same. It will be understood that the width direction in the embodiment of the present application can be the pixel row direction X1.

[0120] For example, the width of the first line segment D11 may be approximately 9 μm, and the width of the second line segment D12 may be approximately between 3 μm and 5 μm. That is, each data line D1 may be reduced from 9 μm to 3 μm to 5 μm.

[0121] Based on this implementation, the orthographic projection of the reflective layer REF on the substrate 01 can satisfy the following requirements: it overlaps with the orthographic projection of the first line segment D11 of the data line D1 on the substrate 01, and covers the orthographic projection of the second line segment D12 of the data line D1 on the substrate 01. That is, for the spacing region B1 between two adjacent pixels 02 in each group of pixels 02Z, the reflective layer REF can overlap with the wide line width of the data line D1 to form a light-shielding structure, and can also cover the narrow line width of the data line D1. Accordingly, it can be seen that the wide line width has a portion of the film layer not covered by the reflective layer REF. That is, in this implementation, the reflective layer REF covers a portion of the data line D1, including portions of both the narrow and wide line widths of the data line D1.

[0122] Optionally, for the portion of the film layer with a wide line width that is not covered by the reflective layer REF, there will still be reflected light leakage. Therefore, based on FIG4 and FIG9 , it can be seen that the display panel described in the embodiment of the present disclosure may further include:

[0123] A first black matrix BM1 is located on the side of the counter substrate 1 close to the array substrate 0, and the orthographic projection of the first black matrix BM1 on the substrate 01 covers the orthographic projection of the portion of the first line segment D11 that does not overlap with the reflective layer REF on the substrate 01. In other words, the first black matrix BM1 can be used to block the portion of the wide line width of the data line D1 that is not covered by the reflective layer REF, thereby further reducing reflected light leakage.

[0124] Optionally, in another implementation of the first embodiment, as shown in FIG10 :

[0125] The width of each portion of each of the two data lines D1 can be equal. That is, the width of each data line D1 at any point is fixed, and there is no width-to-narrow conversion as shown in Figure 4. A cross-sectional schematic diagram of the structure shown in Figure 10 along the A-A' direction can be referenced to Figure 5. Figure 11 also shows a cross-sectional schematic diagram of the structure shown in Figure 10 along the B-B' direction. Figure 12 also shows a cross-sectional schematic diagram of the structure shown in Figure 10 along the C-C' direction. Figure 13 also shows a cross-sectional schematic diagram of the structure shown in Figure 10 along the D-D' direction.

[0126] In this alternative implementation, as can be seen from FIG. 10 and the corresponding cross-sectional view, the second common electrode COM2 may further include a third electrode pattern COM22, and the third electrode pattern COM22 may be located in the spacer B1 between two adjacent pixels 02 in each group of pixels 02, and may be located between two data lines D1. That is, in addition to forming a vertical common electrode (i.e., the second electrode pattern COM21) located in the spacer B1 between each group of pixels 02Z, the source-drain conductive layer SD may also form a vertical common electrode (i.e., the third electrode pattern COM22) located in the spacer B1 between two adjacent columns of pixels 02 in each group of pixels 02, overlapping with the reflective layer REF to form a light-shielding structure in the spacer B1 between two adjacent pixels 02 in the same row. That is, relative to the one implementation shown in FIG4 above, in the other implementation shown in FIG10 , not only is the spacer area B1 of each group of pixels 02Z provided with a common electrode formed by the source-drain conductive layer SD to overlap with the reflective layer REF to form a shading structure to block light leakage from the spacer area B1 of each group of pixels 02Z, but the spacer area B1 of two adjacent pixels 02 in each group of pixels 02Z is ​​also similarly provided with a common electrode formed by the source-drain conductive layer SD to overlap with the reflective layer REF to form a shading structure to block light leakage from the spacer area B1 of two adjacent pixels 02 in each group of pixels 02Z.

[0127] Therefore, in this alternative implementation, the orthographic projection of the reflective layer REF on the substrate 01 can satisfy the requirement of covering the orthographic projection of the data line D1 on the substrate 01. In other words, the reflective layer REF can cover all, but not just part, of the data line D1. This way, because no portion of the data line D1 is exposed, it will not form a perpendicular electric field with the common electrode on the opposing substrate 1 side, thereby preventing reflected light leakage. Furthermore, there is no need to additionally provide the first black matrix BM1 shown in FIG. 9 to shield reflected light leakage from the data line D1, further improving the reflective aperture ratio.

[0128] Optionally, between two adjacent pixels 02 in each pixel group 02Z, the distance between the common electrode formed by the source-drain conductive layer SD (ie, the third electrode pattern COM22) and the adjacent data line D1 may be approximately 4 μm. Furthermore, the line width of the third electrode pattern COM22 may be greater than or equal to 9 μm.

[0129] Optionally, based on FIG10 , with reference to FIG14 , it can be seen that in yet another implementation of the first embodiment:

[0130] The first common electrode COM1 may further include a fourth electrode pattern COM12, and the fourth electrode pattern COM12 may be located on a side of at least one of the second electrode pattern COM21 and the third electrode pattern COM22 that is closer to the substrate 01. Furthermore, the orthographic projection of the fourth electrode pattern COM12 on the substrate 01 may overlap the orthographic projection of the at least one electrode pattern on the substrate 01. That is, in the embodiment of the present application, in addition to forming a horizontal common electrode (i.e., the first electrode pattern COM11) in the gap B1 between every two adjacent pixels 02 in the same column, the gate conductive layer GATE may also form a vertical common electrode (i.e., the fourth electrode pattern COM12) extending along the pixel column direction Y1 below the third electrode pattern COM22 (i.e., the gap B1 between two adjacent pixels 02 in each group of pixels 02Z) and / or below the second electrode pattern COM21 (i.e., the gap B1 between each group of pixels 02Z). This formed common electrode may overlap the third electrode pattern COM22 formed at that location by the source / drain conductive layer SD.

[0131] In other words, in the spacing area B1 of each group of pixels 02Z and / or the spacing area B1 of two adjacent pixels 02 in each group of pixels 02Z, the gate conductive layer GATE and the source-drain conductive layer SD can be used simultaneously to form a common electrode. In this way, the film thickness of the spacing area B1 can be larger relative to the position of other spacing areas B1, and the concave-convex layer ACR can be made to have obvious concave-convex changes in the spacing area B1, thereby ensuring better uniformity of the film layer below the reflective layer REF.

[0132] For example, taking the third electrode pattern COM22 as an example, in some embodiments, the width of the fourth electrode pattern COM12 can be the same as the width of the third electrode pattern COM22, such as approximately 9 μm. In other words, the orthographic projection of the fourth electrode pattern COM12 on the substrate 01 can exactly overlap with the orthographic projection of the third electrode pattern COM22 on the substrate 01.

[0133] Alternatively, the schematic cross-sectional view of the structure shown in FIG14 along the AA' direction may refer to FIG5. FIG15 also shows a schematic cross-sectional view of the structure shown in FIG14 along the BB' direction. FIG16 also shows a schematic cross-sectional view of the structure shown in FIG14 along the C-C' direction. FIG17 also shows a schematic cross-sectional view of the structure shown in FIG14 along the D-D' direction.

[0134] Alternatively, in a second embodiment, as shown in FIG18 :

[0135] The first common electrode COM1 may include: a first electrode pattern COM11 and a fifth electrode pattern COM13, and the first electrode pattern COM11 may be located in the spacer B1 between every two adjacent pixels 02 in the same column, and the fifth electrode pattern COM13 may be located in the spacer B1 between every two adjacent pixels 02 in the same row. That is, the first electrode pattern COM11 may extend along the pixel row direction X1, and the fifth electrode pattern COM13 may extend along the pixel column direction Y1. In other words, the gate conductive layer GATE can not only form a horizontal common electrode (i.e., the first electrode pattern COM11) overlapping with the reflective layer REF to form a light-shielding structure in the spacer B1 between two adjacent pixels 02 in the same column, but can also form a vertical common electrode (i.e., the fifth electrode pattern COM13) overlapping with the reflective layer REF to form a light-shielding structure in the spacer B1 between two adjacent pixels 02 in the same row.

[0136] In other words, in this second embodiment, in the spacer region B1 between two adjacent pixels 02 in the same column, a common electrode can be formed using the gate conductive layer GATE, and a reflective layer REF can be provided to overlap the common electrode formed by the gate conductive layer GATE to form a light-shielding structure, thereby achieving a horizontal reflective light-shielding effect. Similarly, in the spacer region B1 between two adjacent pixels 02 in the same row, a common electrode can be formed using the gate conductive layer GATE, and a reflective layer REF can be provided to overlap the common electrode formed by the gate conductive layer GATE to form a light-shielding structure, thereby achieving a vertical reflective light-shielding effect. Accordingly, there is no need to use the source / drain conductive layer SD to form a vertical common electrode.

[0137] Optionally, it can be seen from FIG. 18 that in this second embodiment:

[0138] Among the multiple pixels 02, the two data lines D1 connected to two adjacent pixels 02 in the same row may be located on either side of one of the pixels 02. That is, the two data lines D1 connected to two adjacent columns of pixels 02 may not be adjacent. For example, referring to FIG. 18 , the data lines D1 connected to each column of pixels 02 are all located on the left side of the pixel 02 in that column.

[0139] Furthermore, each of the two data lines D1 may include a patch line segment D1-1 and a main line segment D1-2. The patch line segment D1-1 may be connected to the pixel 02, and the orthographic projection of the patch line segment D1-1 on the substrate 01 may overlap with the orthographic projections of both the gate line G1 and the first common electrode COM1 on the substrate 01. At least a portion of the main line segment D1-2 may be located between the fifth electrode pattern COM13 and the pixel 02 connected to the patch line segment D1-1. That is, as shown in FIG18 , the patch line segment D1-1 may be located at the portion where the gate line G1 overlaps with the first common electrode COM1, and the main line segment D1-2 may be connected to the patch line segment D1-1 to connect to the pixel 02.

[0140] Based on this embodiment, referring to FIG. 18 , it can be seen that the orthographic projection of the reflective layer REF on substrate 01 satisfies the following requirements: it covers the orthographic projection of the main line segment D1-2 on substrate 01 and overlaps with the orthographic projection of the patch line segment D1-1 on substrate 01. Therefore, it can be seen that patch line segment D1-1 has a portion of the film layer that is not covered by the reflective layer REF. That is, in this second embodiment, the reflective layer REF covers a portion of the data line D1, including the main line segment D1-2 and the portion of the patch line segment D1.

[0141] Optionally, in an implementation of the second embodiment, further referring to FIG. 18 , it can be seen that:

[0142] Each portion of the main line segment D1-2 may be located between the fifth electrode pattern COM13 and the pixel 02 connected to the patch line segment D1-1. For example, referring to FIG18 , the main line segment D1-2 is shown to be located on the right side of the fifth electrode pattern COM13, that is, on the left side of the connected pixel 02.

[0143] Furthermore, the main line segment D1 - 2 and the fifth electrode pattern COM13 may be parallel to each other, that is, the main line segment D1 - 2 and the fifth electrode pattern COM13 may both extend along the pixel column direction Y1 .

[0144] Alternatively, the schematic cross-sectional view of the structure shown in FIG18 along the AA' direction may refer to FIG5. FIG19 also shows a schematic cross-sectional view of the structure shown in FIG18 along the BB' direction. FIG20 also shows a schematic cross-sectional view of the structure shown in FIG18 along the C-C' direction. FIG21 also shows a schematic cross-sectional view of the structure shown in FIG18 along the D-D' direction.

[0145] Optionally, in another implementation of the second embodiment, as shown in FIG22 :

[0146] A portion of the main line segment D1-2 may be located between the fifth electrode pattern COM13 and the pixel 02 connected to the adapter line segment D1-1, and another portion of the main line segment D1-2 may be located between pixels 02 adjacent to the pixel 02 connected to the fifth electrode pattern COM13 and the adapter line segment D1-1.

[0147] Furthermore, the main line segment D1-2 and the fifth electrode pattern COM13 can intersect, and the length of a portion of the main line segment D1-2 can be the same as the length of another portion of the main line segment D1-2. That is, as shown in Figure 22, in the pixel column direction Y1, both the main line segment D1-2 and the fifth electrode pattern COM13 can be divided into two halves. Furthermore, one half of the main line segment D1-2 can be located to the left of one half of the fifth electrode pattern COM13, and the other half of the main line segment D1-2 can be located to the right of the other half of the fifth electrode pattern COM13. In other words, the data line D1 can bypass the vertical fifth electrode pattern COM13 formed by the gate conductive layer GATE in the middle of the connected pixel O2. Alternatively, the vertical fifth electrode pattern COM13 formed by the gate conductive layer GATE can bypass the data line D1 in the middle of the connected pixel O2. In other words, the data line D1 and the fifth electrode pattern COM13 are both designed to bend and intersect, with the same bending point located in the middle of the pixel O2 in the pixel column direction Y1.

[0148] In this way, the spacing between each data line D1 and the pixel 02 to which it is connected, as well as the spacing between another pixel 02 adjacent to the connected pixel 02, can be made the same. Furthermore, the coupling capacitance Cdp formed between each data line D1 and the pixel 02 to which it is connected, as well as the coupling capacitance Cdpother formed between each data line D1 and another pixel 02 adjacent to the connected pixel 02, can be made consistent, ensuring good display uniformity of each pixel 02.

[0149] Alternatively, for a cross-sectional schematic diagram of the structure shown in FIG22 along the AA' direction, reference may be made to FIG5. For a cross-sectional schematic diagram of the structure shown in FIG22 along the BB' direction, reference may be made to FIG19. FIG23 also shows a cross-sectional schematic diagram of the structure shown in FIG22 along the C-C' direction. FIG24 also shows a cross-sectional schematic diagram of the structure shown in FIG22 along the D-D' direction.

[0150] Optionally, for the portion of the film layer of the adapter line segment D1-1 not covered by the reflective layer REF, that is, the data line D1 at the position of the seam between the common electrode formed by the gate conductive layer GATE and the gate line G1, reflected light leakage will still occur. Therefore, referring to Figures 25 and 26, it can be seen that the display panel described in the embodiment of the present disclosure may also include:

[0151] The second black matrix BM2 can be located on the side of the counter substrate 1 close to the array substrate 0, and the orthographic projection of the second black matrix BM2 on the substrate 01 can cover the orthographic projection of the transfer line segment D1-1 on the substrate 01. In other words, the second black matrix BM2 can be used to shield the portion of the transfer line segment D1-1 not covered by the reflective layer REF, thereby further reducing reflected light leakage.

[0152] It can be understood that Fig. 25 shows another display panel based on the structure shown in Fig. 18. Fig. 26 shows another display panel based on the structure shown in Fig. 22.

[0153] Optionally, in the embodiment of the present application, the line width of the gate line G1 and the line width of at least a portion of the data line D1 can both be smaller than a line width threshold, so that the orthographic projection of the reflective layer REF on the substrate 01 can satisfy the following requirements: covering the orthographic projection of the gate line G1 on the substrate 01 and covering the orthographic projection of at least a portion of the data line D1 on the substrate 01. For example, in combination with the above description, for the structure shown in FIG4 , at least a portion of the data line D1 can refer to the narrow line width portion of the data line D1, that is, the second segment D12.

[0154] For example, in some embodiments, the line width threshold can be 5μm. That is, the line width of the gate line G1 or the data line D1, which is traditionally about 10μm wide, can be reduced to less than 5μm. Of course, the setting of the line width of the gate line G1 or the data line D1 also needs to take into account factors such as resistance, capacitance, and broken lines, so the line width of the gate line G1 or the data line D1 can usually be set to be greater than or equal to 3μm. For example, in an embodiment of the present application, the line width of the gate line G1 and the line width of at least part of the line segment of the data line D1 (such as the second line segment D12) can be approximately 3μm.

[0155] On the basis of reducing the line width, as previously mentioned, the reflective layer REF can cover the gate line G1 and data line D1 as much as possible, preventing the gate line G1 and data line D1 from forming a perpendicular electric field with the common electrode on the opposite substrate 1, which could cause erroneous deflection of the liquid crystal molecules. Furthermore, the coupling capacitance on the gate line G1 and data line D1 can be reduced, thereby reducing the load. This ensures a better display effect.

[0156] Optionally, as can be seen from FIG. 1 , the display panel described in the embodiment of the present application may further include:

[0157] Point supporting (PS) posts PS can be located between the array substrate 0 and the counter substrate 1. The support posts PS can be used to support the array substrate 0 and the counter substrate 1. Furthermore, as shown in FIG1 , there are no liquid crystal molecules at the location of the support posts PS, which can result in light leakage.

[0158] In the embodiment of the present application, referring to FIG. 9 and FIG. 25 to FIG. 28 , it can be seen that the display panel may further include:

[0159] The third black matrix BM3 can be located on the side of the counter substrate 1 close to the array substrate 0, and the orthographic projection of the third black matrix BM3 on the substrate 01 overlaps with the orthographic projection of the support pillars PS on the substrate 01. That is, at the location of the support pillars PS, light leakage can be blocked by adding the third black matrix BM3 on the side of the counter substrate 1.

[0160] It can be understood that Fig. 27 is another display panel based on the structure shown in Fig. 10. Fig. 28 is another display panel based on the structure shown in Fig. 14.

[0161] Optionally, the black matrix BM is a choice of light shielding layer. In some other embodiments, a black pixel defining layer can be provided instead of the black matrix BM as the light shielding layer. Here, the black matrix includes any one of the first black matrix BM1, the second black matrix BM2, and the third black matrix BM3 described above.

[0162] As can be seen from the foregoing, the embodiments of the present application provide multiple implementation methods to block light leakage by adjusting pixel arrangement and changing pixel design, thereby ensuring a better display effect of the semi-transmissive and semi-reflective display panel:

[0163] In the first implementation, in conjunction with FIG4 , the embodiment of the present application adjusts the pixel arrangement so that the data line D1 connecting two adjacent pixels 02 is arranged in close proximity, and the data line D1 is set to have half the narrow line width and half the wide line width. The wide line width overlaps with the reflective layer REF to form a light-shielding structure to reduce reflected light leakage above the data line D1. At the same time, a gate conductive layer GATE is also provided to form a common electrode located laterally in the spacer B1, and the reflective layer REF is provided to overlap with the common electrode to form a light-shielding structure to prevent lateral reflected light leakage. In this implementation, a black matrix is ​​added to the wide line width side of the data line D1 formed by the source and drain conductive layer SD, and / or a black matrix is ​​added to the side supporting the PS to block the remaining reflected light leakage. In this way, reflective display light leakage can be effectively reduced without increasing the process difficulty. In addition, the coupling capacitance can be reduced based on the reduction of the overlapping area between the reflective layer REF and the data line D1.

[0164] In the second implementation, in conjunction with Figure 10, the embodiment of the present application adjusts the pixel arrangement, arranges the data line D1 connecting two adjacent pixels O2 in close proximity, reduces the line width of the data line D1, adds a common electrode formed by the source and drain conductive layer SD between the adjacent data lines D1, and arranges a reflective layer REF to overlap with the common electrode to form a light-shielding structure to prevent vertical reflection light leakage. At the same time, a gate conductive layer GATE is also provided to form a common electrode located horizontally in the spacer area B1, and a reflective layer REF is provided to overlap with the common electrode to form a light-shielding structure to prevent horizontal reflection light leakage. In this implementation, a black matrix is ​​added to the position where the source and drain conductive layer SD leaks light, and / or a black matrix is ​​added to the side supporting the PS to block the remaining reflection light leakage. In this way, reflective display light leakage can be effectively reduced without increasing the process difficulty.

[0165] In a third implementation, as shown in Figure 14 , the present embodiment adjusts the pixel arrangement, arranging the data lines D1 connecting two adjacent pixels O2 in close proximity. This reduces the width of data line D1, adds a common electrode formed by a source / drain conductive layer SD between adjacent data lines D1, and overlaps a reflective layer REF with the common electrode to form a light-shielding structure, thereby eliminating vertical reflected light leakage. Furthermore, a gate conductive layer GATE is provided to form a common electrode positioned laterally within the spacer B1, overlapping the reflective layer REF with the common electrode to form a light-shielding structure, thereby eliminating horizontal reflected light leakage. Furthermore, a gate conductive layer GATE is provided to form a vertical common electrode positioned below the common electrode formed by the source / drain conductive layer SD, thereby enhancing the uniformity of the concave-convex layer ACR at the corresponding position. In this implementation, black matrix is ​​added at locations where light leaks from the source / drain conductive layer SD, and / or at the side supporting the PS to block any remaining reflected light leakage. This effectively reduces reflective display light leakage without increasing process complexity.

[0166] In the fourth implementation, in conjunction with FIG18 , the embodiment of the present application reduces the width of the data line D1 by changing the pixel design, and at the same time sets a gate conductive layer GATE to form a horizontal common electrode and a vertical common electrode located in the spacer B1, and sets a reflective layer REF to overlap with both the horizontal common electrode and the vertical common electrode to form a light-shielding structure, so that there is no horizontal reflected light leakage and no vertical reflected light leakage. In this implementation, a black matrix is ​​added at the position where the source-drain conductive layer SD overlaps with the reflective layer REF, and / or a black matrix is ​​added on the side supporting the PS to block the remaining reflected light leakage. In this way, reflective display light leakage can be effectively reduced without increasing the process difficulty.

[0167] In a fourth implementation, in conjunction with FIG22 , the embodiment of the present application reduces the line width of the data line D1 by changing the pixel design, and at the same time sets the gate conductive layer GATE to form a horizontal common electrode and a vertical common electrode located in the spacer B1, and sets the reflective layer REF to overlap with the horizontal common electrode and the vertical common electrode to form a light-shielding structure, so that there is no horizontal reflection leakage and no vertical reflection leakage. In addition, by changing the data line D1 design, the data line D1 and the vertical common electrode formed by the gate conductive layer GATE are arranged to intersect with each other, so that the coupling capacitance Cdp formed by each data line D1 and the connected pixel 02, and the coupling capacitance Cdpother formed by another pixel 02 adjacent to the connected pixel 02 are consistent, ensuring that the display uniformity of each pixel 02 is good. In this implementation, a black matrix is ​​added at the position where the source and drain conductive layer SD overlaps with the reflective layer REF, and / or a black matrix is ​​added on the side supporting the PS to block the remaining reflected light leakage. In this way, the reflected display light leakage can be effectively reduced without increasing the process difficulty.

[0168] In summary, an embodiment of the present disclosure provides a display panel. In this display panel, an array substrate includes an array substrate and an opposing substrate. The gate conductive layer in the array substrate can be used to form a gate line connecting pixels and a common electrode located in the spacer area, and the reflective layer overlaps with the common electrode. In this way, a light-shielding structure that replaces the black matrix can be formed in the spacer area to avoid light leakage in the spacer area. In other words, there is no need to set a black matrix at the position corresponding to the spacer area on the side of the opposing substrate. In this way, while avoiding light leakage, the reflective aperture ratio of the display panel can be ensured to be large, thereby ensuring a good display effect.

[0169] In addition, since the light-shielding structure is formed by overlapping the reflective layer and the common electrode, the common electrode and the common electrode on the opposite substrate side generally have the same potential, so it can avoid the formation of a vertical electric field that causes the liquid crystal molecules in the display panel to be misdeflected and cause reflected light leakage, which can further ensure a better display effect.

[0170] The present application also provides a method for manufacturing a display panel, which is used to manufacture the display panel described above. As shown in FIG29 , the method includes:

[0171] Step 2901: Form an opposing substrate.

[0172] Optionally, in combination with the above description, the formed opposing substrate may be a color filter substrate, and one side of the formed opposing substrate may include a common electrode.

[0173] Step 2902: Form a substrate on the side opposite to the counter substrate.

[0174] Optionally, in conjunction with FIG. 2 , the formed substrate 01 may be a glass substrate or a flexible substrate.

[0175] Step 2903: forming a plurality of gate lines, a plurality of data lines, and a plurality of pixels on a side of the substrate close to the counter substrate.

[0176] 2 and 3 , it can be seen that the multiple pixels 02 formed can be spaced apart and arranged in an array, and each pixel 02 can be connected to a gate line G1 and a data line D1 respectively, and each pixel 02 has an adjacent transmission area A1 and a reflection area A2. In the transmission area A1 and the reflection area A2, each pixel 02 can include a transparent conductive layer ITO located on one side of the substrate 01, and in the reflection area A2, each pixel 02 can include a reflection layer REF located on the side of the transparent conductive layer ITO away from the substrate 01.

[0177] Step 2904 : forming a source-drain conductive layer and a gate conductive layer stacked in sequence between the substrate and the transparent conductive layer.

[0178] Continuing with reference to FIG. 2 and FIG. 3 , it can be seen that the formed source-drain conductive layer SD can be used to form a data line D1, and the formed gate conductive layer GATE can be used to form a gate line G1 and a first common electrode COM1, and the first common electrode COM1 can be located in the spacer B1 between at least two adjacent pixels 02. Furthermore, the orthographic projection of the formed reflective layer REF on the substrate 01 can satisfy the following requirements: overlap with the orthographic projection of the first common electrode COM1 on the substrate 01, cover the orthographic projection of the gate line G1 on the substrate 01, and cover the orthographic projection of at least a portion of the data line D1 on the substrate 01.

[0179] In one implementation of the first embodiment, the manufacturing process of the display panel is described as follows with reference to the process flow diagrams shown in FIG4 and FIG30 :

[0180] (1) First, a gate metal material can be deposited on one side of a provided substrate 01 (e.g., a glass substrate), and the gate metal material is processed using a gate metal mask GATE Mask to form a gate line G1, a gate electrode, other common electrodes COM0, and a first electrode pattern COM11 included in the first common electrode COM1 at different locations on the same layer at one time. The formed first electrode pattern COM11 extends along the pixel row direction X1 and is located in the interval B1 between two adjacent pixels 02 in the same column.

[0181] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an active layer mask ACT Mask to form an active layer ACT in the channel region of the reflective region A2.

[0182] (3) Then, a source-drain metal material can be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal mask SD Mask can be used to process the source-drain metal material to form the data line D1, the source-drain electrode, and the second electrode pattern COM21 included in the second common electrode COM2 located in the same layer at different positions at one time. The formed second electrode pattern COM21 extends along the pixel column direction Y1 and is located in the spacing area B1 between two adjacent groups of pixels 02Z. In addition, referring to FIG30, it can be seen that among the multiple data lines D1 formed, the two data lines D1 connecting the two adjacent pixels 02 included in each group of pixels 02Z are arranged closely together, and half (the first line segment D11) has a narrow line width and the other half (the second line segment D12) has a wide line width.

[0183] (4) Then, a passivation material can be deposited on the side of the source-drain metal layer SD away from the substrate 01 to form a passivation layer PVX, and the passivation layer PVX can be processed using a passivation layer mask plate PVX Mask to form a transfer hole K1 at the transition between the gate metal layer GATE and the source-drain metal layer SD, and to punch a hole at the position where the source-drain metal layer SD transitions to the transparent conductive layer ITO.

[0184] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed using an indium tin oxide mask ITO Mask to form a transparent conductive layer ITO. The transparent conductive layer ITO can be used as a transparent pixel electrode, and the transparent conductive layer ITO can be overlapped with the source and drain metal layer SD through the via hole on the passivation layer PVX.

[0185] (6) Then, a concave-convex layer material (e.g., acrylic ACR) can be deposited on the side of the transparent conductive layer ITO away from the substrate O1 to form the concave-convex layer ACR, and the portion of the concave-convex layer ACR located in the transmissive area A1 is removed to form an ACR macrohole K0 to expose the transparent conductive layer ITO. Since the concave-convex layer ACR is generally a thick organic material layer with a flattening effect, the film thickness of the reflective area A2 and the transmissive area A1 can be made different, thereby forming two cell thicknesses.

[0186] (7) Then, a reflective metal material (such as Al, Ag or MoAl) can be deposited on the side of the concave-convex layer ACR away from the substrate 01 to form a reflective layer REF. Moreover, at the position of the ACR macrohole K0, the formed reflective layer REF can be overlapped with the exposed transparent conductive layer ITO along the ACR macrohole K0, so that the reflective layer REF as a metal pixel electrode is connected to the ITO layer as a transparent pixel electrode to form a pixel electrode on one side of the array substrate 0. Moreover, the formed reflective layer REF can also overlap with the first electrode pattern COM11 formed by the gate conductive layer GATE to form a light-shielding structure in the lateral spacing area B1 to block lateral light leakage. In addition, as shown in Figure 4, the formed reflective layer REF also covers the gate line G1 formed by the gate conductive layer GATE, so that no light leaks at the gate line G1. The formed reflective layer REF also overlaps with the wide line width of the data line D1 to block vertical light leakage. And, the formed reflective layer REF also overlaps with the second electrode pattern COM21 formed by the source and drain conductive layer SD to form a light-shielding structure to block vertical light leakage.

[0187] (8) Finally, considering that there will be some light leakage at the PS support and the wide line width of the data line D1, as shown in FIG9 , a third black matrix BM3 can be set on one side of the opposing substrate 1 to block the light leakage at the PS support, and a first black matrix BM1 can be set on one side of the opposing substrate 1 to block the light leakage at the wide line width of the data line D1.

[0188] In another implementation of the first embodiment, the manufacturing process of the display panel is described as follows with reference to the process flow diagrams shown in FIG10 and FIG31 :

[0189] (1) First, a gate metal material can be deposited on one side of a provided substrate 01 (e.g., a glass substrate), and the gate metal material is processed using a gate metal mask GATE Mask to form a gate line G1, a gate electrode, other common electrodes COM0, and a first electrode pattern COM11 included in the first common electrode COM1 at different locations on the same layer at one time. The formed first electrode pattern COM11 extends along the pixel row direction X1 and is located in the interval B1 between two adjacent pixels 02 in the same column.

[0190] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an active layer mask ACT Mask to form an active layer ACT in the channel region of the reflective region A2.

[0191] (3) Then, a source-drain metal material can be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal mask plate SD Mask can be used to process the source-drain metal material to form the data line D1, source-drain electrode, and the second electrode pattern COM21 and the third electrode pattern COM22 included in the second common electrode COM2 at different positions at one time. The formed second electrode pattern COM21 and the third electrode pattern COM22 both extend along the pixel column direction Y1, and the second electrode pattern COM21 is located in the spacing area B1 between two adjacent groups of pixels 02Z, and the third electrode pattern COM22 is located in the spacing area B1 between two adjacent pixels 02 in each group of pixels 02Z. In addition, referring to Figure 31, it can be seen that among the multiple data lines D1 formed, the two data lines D1 connecting the two adjacent pixels 02 included in each group of pixels 02Z are arranged closely together and have equal widths.

[0192] (4) Then, a passivation material can be deposited on the side of the source-drain metal layer SD away from the substrate 01 to form a passivation layer PVX, and the passivation layer PVX can be processed using a passivation layer mask plate PVX Mask to form a transfer hole K1 at the transition between the gate metal layer GATE and the source-drain metal layer SD, and to punch a hole at the position where the source-drain metal layer SD transitions to the transparent conductive layer ITO.

[0193] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed using an indium tin oxide mask ITO Mask to form a transparent conductive layer ITO. The transparent conductive layer ITO can be used as a transparent pixel electrode, and the transparent conductive layer ITO can be overlapped with the source and drain metal layer SD through the via hole on the passivation layer PVX.

[0194] (6) Then, a concave-convex layer material (e.g., acrylic ACR) can be deposited on the side of the transparent conductive layer ITO away from the substrate O1 to form the concave-convex layer ACR, and the portion of the concave-convex layer ACR located in the transmissive area A1 is removed to form an ACR macrohole K0 to expose the transparent conductive layer ITO. Since the concave-convex layer ACR is generally a thick organic material layer with a flattening effect, the film thickness of the reflective area A2 and the transmissive area A1 can be made different, thereby forming two cell thicknesses.

[0195] (7) Then, a reflective metal material (such as Al, Ag or MoAl) can be deposited on the side of the concave-convex layer ACR away from the substrate 01 to form a reflective layer REF. Moreover, at the position of the ACR macrohole K0, the formed reflective layer REF can be overlapped with the exposed transparent conductive layer ITO along the ACR macrohole K0, so that the reflective layer REF as a metal pixel electrode is connected to the ITO layer as a transparent pixel electrode to form a pixel electrode on one side of the array substrate 0. Moreover, the formed reflective layer REF can also overlap with the first electrode pattern COM11 formed by the gate conductive layer GATE to form a light-shielding structure in the horizontal spacing area B1 to block horizontal light leakage. And the formed reflective layer REF can also overlap with the second electrode pattern COM21 and the third electrode pattern COM22 formed by the source-drain conductive layer SD to form a light-shielding structure in the vertical spacing area B1 to block vertical light leakage. In addition, as shown in Figure 10, the formed reflective layer REF also covers the gate line G1 formed by the gate conductive layer GATE, so that no light leaks at the gate line G1. The formed reflective layer REF also covers the data line D1 formed by the source-drain conductive layer SD, so that no light leaks from the data line D1.

[0196] (8) Finally, considering that there will be some light leakage at the PS support, as shown in FIG27 , a third black matrix BM3 may be provided on one side of the counter substrate 1 to block the light leakage at the PS support.

[0197] In another implementation of the first embodiment, the manufacturing process of the display panel is described as follows with reference to the process flow diagrams shown in FIG14 and FIG32 :

[0198] (1) First, a gate metal material can be deposited on one side of a provided substrate 01 (e.g., a glass substrate), and the gate metal material can be processed using a gate metal mask GATE Mask to form a gate line G1, a gate, other common electrodes COM0, and a first electrode pattern COM11 and a fourth electrode pattern COM12 included in the first common electrode COM1 at different positions at one time. The formed first electrode pattern COM11 extends along the pixel row direction X1 and is located in the spacing area B1 between two adjacent pixels 02 in the same column. The formed fourth electrode pattern COM12 extends along the pixel column direction Y1 and is located in the spacing area B1 between two adjacent pixels 02 in each group of pixels 02Z.

[0199] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an active layer mask ACT Mask to form an active layer ACT in the channel region of the reflective region A2.

[0200] (3) Then, a source / drain metal material can be deposited on the side of the active layer ACT away from the substrate 01, and the source / drain metal mask SD Mask can be used to process the source / drain metal material to form the data line D1, the source / drain electrode, and the second electrode pattern COM21 and the third electrode pattern COM22 included in the second common electrode COM2 at different positions at one time. The formed second electrode pattern COM21 and the third electrode pattern COM22 both extend along the pixel column direction Y1, and the second electrode pattern COM21 is located in the spacing area B1 between two adjacent groups of pixels 02Z, and the third electrode pattern COM22 is located in the spacing area B1 between two adjacent pixels 02 in each group of pixels 02Z. In addition, referring to FIG. 32 , it can be seen that among the multiple data lines D1 formed, the two data lines D1 connecting the two adjacent pixels 02 included in each group of pixels 02Z are arranged closely together and have equal widths.

[0201] (4) Then, a passivation material can be deposited on the side of the source-drain metal layer SD away from the substrate 01 to form a passivation layer PVX, and the passivation layer PVX can be processed using a passivation layer mask plate PVX Mask to form a transfer hole K1 at the transition between the gate metal layer GATE and the source-drain metal layer SD, and to punch a hole at the position where the source-drain metal layer SD transitions to the transparent conductive layer ITO.

[0202] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed using an indium tin oxide mask ITO Mask to form a transparent conductive layer ITO. The transparent conductive layer ITO can be used as a transparent pixel electrode, and the transparent conductive layer ITO can be overlapped with the source and drain metal layer SD through the via hole on the passivation layer PVX.

[0203] (6) Then, a concave-convex layer material (e.g., acrylic ACR) can be deposited on the side of the transparent conductive layer ITO away from the substrate O1 to form the concave-convex layer ACR, and the portion of the concave-convex layer ACR located in the transmissive area A1 is removed to form an ACR macrohole K0 to expose the transparent conductive layer ITO. Since the concave-convex layer ACR is generally a thick organic material layer with a flattening effect, the film thickness of the reflective area A2 and the transmissive area A1 can be made different, thereby forming two cell thicknesses.

[0204] (7) Then, a reflective metal material (such as Al, Ag or MoAl) can be deposited on the side of the concave-convex layer ACR away from the substrate 01 to form a reflective layer REF. Moreover, at the position of the ACR macrohole K0, the formed reflective layer REF can be overlapped with the exposed transparent conductive layer ITO along the ACR macrohole K0, so that the reflective layer REF as a metal pixel electrode is connected to the ITO layer as a transparent pixel electrode to form a pixel electrode on one side of the array substrate 0. Moreover, the formed reflective layer REF can also overlap with the first electrode pattern COM11 formed by the gate conductive layer GATE to form a shading structure in the horizontal spacing area B1 to block horizontal light leakage. And the formed reflective layer REF can also overlap with the second electrode pattern COM21 and the third electrode pattern COM22 formed by the source-drain conductive layer SD to form a shading structure in the vertical spacing area B1 to block vertical light leakage. Moreover, the fourth electrode pattern COM12 also covers the third electrode pattern COM22, so that the concave-convex layer ACR at the corresponding position has better concave-convexity and improves the uniformity of the film layer. 14 , the formed reflective layer REF also covers the gate line G1 formed by the gate conductive layer GATE, so that light does not leak from the gate line G1 . The formed reflective layer REF also covers the data line D1 formed by the source / drain conductive layer SD, so that light does not leak from the data line D1 .

[0205] (8) Finally, considering that there will be some light leakage at the PS support, as shown in FIG28 , a third black matrix BM3 may be provided on one side of the counter substrate 1 to block the light leakage at the PS support.

[0206] In one implementation of the second embodiment, the manufacturing process of the display panel is described as follows with reference to the process flow diagrams shown in FIG18 and FIG33 :

[0207] (1) First, a gate metal material can be deposited on one side of a provided substrate 01 (e.g., a glass substrate), and the gate metal material can be processed using a gate metal mask GATE Mask to form a gate line G1, a gate, other common electrodes, and a first electrode pattern COM11 and a fifth electrode pattern COM13 included in the first common electrode COM1 at different positions at one time. The formed first electrode pattern COM11 extends along the pixel row direction X1 and is located in the spacing area B1 between two adjacent pixels 02 in the same column. The formed fifth electrode pattern COM13 extends along the pixel column direction Y1 and is located in the spacing area B1 between two adjacent pixels 02 in the same row.

[0208] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an active layer mask ACT Mask to form an active layer ACT in the channel region of the reflective region A2.

[0209] (3) Then, a source-drain metal material can be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal material can be processed using a source-drain metal mask plate SD Mask to form a data line D1 and a source-drain electrode located on the same layer at different positions at one time. In addition, referring to Figure 33, it can be seen that among the multiple data lines D1 formed, each data line D1 is located on the left side of the pixel 02 to which it is connected, and each data line D1 includes a transfer line segment D1-1 and a main line segment D1-2. Moreover, each part of the main line segment D1-2 is located between the fifth electrode pattern COM13 and the pixel 02 connected to the transfer line segment D1-1.

[0210] (4) Then, a passivation material can be deposited on the side of the source-drain metal layer SD away from the substrate 01 to form a passivation layer PVX, and the passivation layer PVX can be processed using a passivation layer mask plate PVX Mask to form a transfer hole K1 at the transition between the gate metal layer GATE and the source-drain metal layer SD, and to punch a hole at the position where the source-drain metal layer SD transitions to the transparent conductive layer ITO.

[0211] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed using an indium tin oxide mask ITO Mask to form a transparent conductive layer ITO. The transparent conductive layer ITO can be used as a transparent pixel electrode, and the transparent conductive layer ITO can be overlapped with the source and drain metal layer SD through the via hole on the passivation layer PVX.

[0212] (6) Then, a concave-convex layer material (e.g., acrylic ACR) can be deposited on the side of the transparent conductive layer ITO away from the substrate O1 to form the concave-convex layer ACR, and the portion of the concave-convex layer ACR located in the transmissive area A1 is removed to form an ACR macrohole K0 to expose the transparent conductive layer ITO. Since the concave-convex layer ACR is generally a thick organic material layer with a flattening effect, the film thickness of the reflective area A2 and the transmissive area A1 can be made different, thereby forming two cell thicknesses.

[0213] (7) Then, a reflective metal material (such as Al, Ag or MoAl) can be deposited on the side of the concave-convex layer ACR away from the substrate 01 to form a reflective layer REF. Moreover, at the position of the ACR macrohole K0, the formed reflective layer REF can be overlapped with the exposed transparent conductive layer ITO along the ACR macrohole K0, so that the reflective layer REF as a metal pixel electrode is connected to the ITO layer as a transparent pixel electrode to form a pixel electrode on one side of the array substrate 0. Moreover, the formed reflective layer REF can also overlap with the first electrode pattern COM11 and the fifth electrode pattern COM15 formed by the gate conductive layer GATE to form a shading structure in the horizontal spacer area B1 to block horizontal light leakage, and to form a shading structure in the vertical spacer area B1 to block vertical light leakage. In addition, as shown in FIG18 , the formed reflective layer REF also covers the gate line G1 formed by the gate conductive layer GATE, so that no light leaks at the gate line G1. The formed reflective layer REF also covers the main line segment D1 - 2 of the data line D1 formed by the source-drain conductive layer SD, so that no light leaks from the main line segment D1 - 2 .

[0214] (8) Finally, considering that there will be some light leakage at the support PS and the transfer line segment D1-1 of the data line D1, as shown in FIG25 , a third black matrix BM3 can be set on one side of the opposing substrate 1 to block the light leakage at the support PS, and a second black matrix BM2 can be set on one side of the opposing substrate 1 to block the light leakage at the transfer line segment D1-1 of the data line D1.

[0215] In another implementation of the second embodiment, the manufacturing process of the display panel is described as follows with reference to the process flow diagrams shown in FIG22 and FIG34 :

[0216] (1) First, a gate metal material can be deposited on one side of a provided substrate 01 (e.g., a glass substrate), and the gate metal material can be processed using a gate metal mask GATE Mask to form a gate line G1, a gate, other common electrodes COM0, and a first electrode pattern COM11 and a fifth electrode pattern COM13 included in the first common electrode COM1 at different positions at one time. The formed first electrode pattern COM11 extends along the pixel row direction X1 and is located in the spacing region B1 between two adjacent pixels 02 in the same column. The formed fifth electrode pattern COM13 is located in the spacing region B1 between two adjacent pixels 02 in the same row.

[0217] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an active layer mask ACT Mask to form an active layer ACT in the channel region of the reflective region A2.

[0218] (3) Then, a source-drain metal material can be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal material can be processed using a source-drain metal mask plate SD Mask to form a data line D1 and a source-drain electrode located in the same layer at different positions at one time. In addition, referring to Figure 33, it can be seen that among the multiple data lines D1 formed, each data line D1 is located on the left side of the pixel 02 to which it is connected, and each data line D1 includes a transfer line segment D1-1 and a main line segment D1-2. And a portion of the main line segment D1-2 is located between the fifth electrode pattern COM13 and the pixel 02 connected to the transfer line segment D1-1, and another portion of the main line segment D1-2 is located between the fifth electrode pattern COM13 and the pixel 02 adjacent to the pixel 02 connected to the transfer line segment D1-1. The fifth electrode pattern COM13 and the main line segment D1-2 intersect with each other. And the length of a portion of the main line segment D1-2 is the same as the length of another portion of the main line segment D1-2. That is, in this implementation, the data line D1 can bypass the fifth electrode pattern COM13 formed by the gate conductive layer GATE in the middle of the pixel. In this way, as described above, the coupling capacitance Cdp formed between each data line D1 and the pixel 02 to which it is connected, as well as the coupling capacitance Cdpother formed with another pixel 02 adjacent to the connected pixel 02, can be kept consistent, ensuring good display uniformity across all pixels 02.

[0219] (4) Then, a passivation material can be deposited on the side of the source-drain metal layer SD away from the substrate 01 to form a passivation layer PVX, and the passivation layer PVX can be processed using a passivation layer mask plate PVX Mask to form a transfer hole K1 at the transition between the gate metal layer GATE and the source-drain metal layer SD, and to punch a hole at the position where the source-drain metal layer SD transitions to the transparent conductive layer ITO.

[0220] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed using an indium tin oxide mask ITO Mask to form a transparent conductive layer ITO. The transparent conductive layer ITO can be used as a transparent pixel electrode, and the transparent conductive layer ITO can be overlapped with the source and drain metal layer SD through the via hole on the passivation layer PVX.

[0221] (6) Then, a concave-convex layer material (e.g., acrylic ACR) can be deposited on the side of the transparent conductive layer ITO away from the substrate O1 to form the concave-convex layer ACR, and the portion of the concave-convex layer ACR located in the transmissive area A1 is removed to form an ACR macrohole K0 to expose the transparent conductive layer ITO. Since the concave-convex layer ACR is generally a thick organic material layer with a flattening effect, the film thickness of the reflective area A2 and the transmissive area A1 can be made different, thereby forming two cell thicknesses.

[0222] (7) Then, a reflective metal material (such as Al, Ag or MoAl) can be deposited on the side of the concave-convex layer ACR away from the substrate 01 to form a reflective layer REF. Moreover, at the position of the ACR macrohole K0, the formed reflective layer REF can be overlapped with the exposed transparent conductive layer ITO along the ACR macrohole K0, so that the reflective layer REF as a metal pixel electrode is connected to the ITO layer as a transparent pixel electrode to form a pixel electrode on one side of the array substrate 0. Moreover, the formed reflective layer REF can also overlap with the first electrode pattern COM11 and the fifth electrode pattern COM15 formed by the gate conductive layer GATE to form a shading structure in the horizontal spacer area B1 to block horizontal light leakage, and to form a shading structure in the vertical spacer area B1 to block vertical light leakage. In addition, as shown in FIG18 , the formed reflective layer REF also covers the gate line G1 formed by the gate conductive layer GATE, so that no light leaks at the gate line G1. The formed reflective layer REF also covers the main line segment D1 - 2 of the data line D1 formed by the source-drain conductive layer SD, so that no light leaks from the main line segment D1 - 2 .

[0223] (8) Finally, considering that there will be some light leakage at the support PS and the transfer line segment D1-1 of the data line D1, as shown in FIG26 , a third black matrix BM3 can be set on one side of the opposing substrate 1 to block the light leakage at the support PS, and a second black matrix BM2 can be set on one side of the opposing substrate 1 to block the light leakage at the transfer line segment D1-1 of the data line D1.

[0224] It is understandable that the above-mentioned mask processing process may include a one-time patterning process, which includes: coating, exposure, and development.

[0225] Since the method for preparing the display panel can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the preparation method will not be repeatedly described here for the purpose of brevity.

[0226] FIG35 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. As shown in FIG35 , the display device includes: a power supply component J1 and a display panel 00 as described in the above embodiment.

[0227] The power supply component J1 is coupled to the display panel 00 and is used to supply power to the display panel 00 .

[0228] Optionally, the display device may be an LCD display device, and the display device may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0229] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0230] It should be noted that the terms used in the examples of this application are only used to explain the examples and are not intended to limit this application. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this application should have the common meanings understood by people with ordinary skills in the field to which this application belongs.

[0231] For example, the words “first”, “second” or “third” and similar words used in the specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “a” or “an” do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as “include” or “comprise” mean that the elements or objects appearing before “include” or “comprises” include the elements or objects listed after “include” or “comprises” and their equivalents, and do not exclude other elements or objects. “Up”, “down”, “left” or “right” and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. “Connected” or “coupled” refers to an electrical connection.

[0232] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, comprising: An array substrate and a counter substrate arranged opposite to each other; The array substrate includes: substrate; A plurality of gate lines, a plurality of data lines, and a plurality of pixels are all located on a side of the substrate close to the counter substrate, the plurality of pixels are spaced apart and arranged in an array, each pixel is connected to one of the gate lines and one of the data lines, and each pixel has an adjacent transmissive region and a reflective region, each pixel includes a transparent conductive layer located on one side of the substrate in the transmissive region and the reflective region, and each pixel includes a reflective layer located on a side of the transparent conductive layer away from the substrate in the reflective region; A source-drain conductive layer and a gate conductive layer are located between the substrate and the transparent conductive layer and are stacked in sequence, the source-drain conductive layer is used to form the data line, and the gate conductive layer is used to form the gate line and a first common electrode, and the first common electrode is located in a space between at least two adjacent pixels; The orthographic projection of the reflective layer on the substrate satisfies the following requirements: overlapping with the orthographic projection of the first common electrode on the substrate, covering the orthographic projection of the gate line on the substrate, and covering the orthographic projection of at least part of the data line segment on the substrate.

2. The display panel according to claim 1, wherein The first common electrode includes: a first electrode pattern, and the first electrode pattern is located in the interval between every two adjacent pixels in the same column; The source-drain conductive layer is also used to form a second common electrode, and the second common electrode is located in the interval area between at least two adjacent pixels in the same row, and the orthographic projection of the reflective layer on the substrate also meets the requirement of overlapping with the orthographic projection of the second common electrode on the substrate.

3. The display panel according to claim 2, wherein: The plurality of pixels include a plurality of groups of pixels, each group of pixels includes two adjacent pixels located in the same row, and two data lines connected to the two adjacent pixels are located between the two adjacent pixels; The second common electrode includes a second electrode pattern, and the second electrode pattern is located in the interval area of ​​each group of pixels.

4. The display panel according to claim 3, wherein: Each of the two data lines includes a first line segment and a second line segment extending along a pixel column direction; The width of the first line segment is greater than the width of the second line segment, and the line segments of the two data lines with different widths are arranged axially symmetrically about a symmetry axis extending along the pixel column direction; The orthographic projection of the reflective layer on the substrate satisfies: overlapping with the orthographic projection of the first line segment of the data line on the substrate, and covering the orthographic projection of the second line segment of the data line on the substrate.

5. The display panel according to claim 4, wherein: The display panel further includes: A first black matrix is ​​located on a side of the counter substrate close to the array substrate, and an orthographic projection of the first black matrix on the substrate covers an orthographic projection of a portion of the first line segment that does not overlap with the reflective layer on the substrate. The display panel according to claim 3 , wherein: The width of each portion of each of the two data lines is equal; The second common electrode further includes: a third electrode pattern, and the third electrode pattern is located in a space between two adjacent pixels in each group of pixels and between the two data lines; The orthographic projection of the reflective layer on the substrate satisfies: covering the orthographic projection of the data line on the substrate.

7. The display panel according to claim 6, wherein: The first common electrode further includes: a fourth electrode pattern, and the fourth electrode pattern is located on a side of at least one of the second electrode pattern and the third electrode pattern close to the substrate; Furthermore, the orthographic projection of the fourth electrode pattern on the substrate covers the orthographic projection of the at least one electrode pattern on the substrate.

8. The display panel according to claim 1, wherein: The first common electrode includes a first electrode pattern and a fifth electrode pattern. The first electrode pattern is located in the interval between every two adjacent pixels in the same column, and the fifth electrode pattern is located in the interval between every two adjacent pixels in the same row.

9. The display panel according to claim 8, wherein: Among the plurality of pixels, two data lines connecting two adjacent pixels in the same row are respectively located on two sides of one of the pixels; Furthermore, each of the two data lines includes a transfer line segment and a main line segment, the transfer line segment is connected to the pixel, and an orthographic projection of the transfer line segment on the substrate overlaps with an orthographic projection of the gate line and the first common electrode on the substrate, and at least a portion of the main line segment is located between the fifth electrode pattern and the pixel connected to the transfer line segment; The orthographic projection of the reflective layer on the substrate satisfies: covering the orthographic projection of the main line segment on the substrate, and overlapping with the orthographic projection of the transition line segment on the substrate.

10. The display panel according to claim 9, wherein: Each portion of the main line segment is located between the fifth electrode pattern and the pixel connected to the adapter line segment; Furthermore, the main body line segment and the fifth electrode pattern are parallel to each other.

11. The display panel according to claim 9, wherein: A portion of the main line segment is located between the fifth electrode pattern and the pixel connected to the adapter line segment, and another portion of the main line segment is located between pixels adjacent to the pixel connected to the fifth electrode pattern and the adapter line segment; Furthermore, the main body segment and the fifth electrode pattern intersect each other, and a length of a portion of the main body segment is the same as a length of another portion of the main body segment.

12. The display panel according to any one of claims 9 to 11, wherein: The display panel further includes: The second black matrix is ​​located on a side of the counter substrate close to the array substrate, and the orthographic projection of the second black matrix on the substrate covers the orthographic projection of the adapter segment on the substrate.

13. The display panel according to any one of claims 1 to 12, wherein: The line width of the gate line and the line width of at least part of the line segment of the data line are both smaller than a line width threshold, so that the orthographic projection of the reflective layer on the substrate satisfies: covering the orthographic projection of the gate line on the substrate, and covering the orthographic projection of at least part of the line segment of the data line on the substrate; The display panel further includes: a supporting column, located between the array substrate and the counter substrate; The third black matrix is ​​located on a side of the counter substrate close to the array substrate, and the orthographic projection of the third black matrix on the substrate overlaps with the orthographic projection of the supporting pillar on the substrate.

14. A method for manufacturing a display panel, for manufacturing the display panel according to any one of claims 1 to 13; the method comprising: forming a counter substrate; forming a substrate on a side opposite to the counter substrate; A plurality of gate lines, a plurality of data lines, and a plurality of pixels are formed on a side of the substrate close to the counter substrate, wherein the plurality of pixels are spaced apart and arranged in an array, each pixel is connected to one of the gate lines and one of the data lines, and each pixel has an adjacent transmission area and a reflection area, each pixel includes a transparent conductive layer located on one side of the substrate in the transmission area and the reflection area, and each pixel includes a reflection layer located on a side of the transparent conductive layer away from the substrate in the reflection area; forming a source-drain conductive layer and a gate conductive layer stacked in sequence between the substrate and the transparent conductive layer, wherein the source-drain conductive layer is used to form the data line, and the gate conductive layer is used to form the gate line and a first common electrode, and the first common electrode is located in a space between at least two adjacent pixels; Moreover, the orthographic projection of the formed reflective layer on the substrate satisfies: overlapping with the orthographic projection of the first common electrode on the substrate, covering the orthographic projection of the gate line on the substrate, and covering the orthographic projection of at least part of the data line segment on the substrate.

15. A display device, comprising: A power supply component, and a display panel according to any one of claims 1 to 13; The power supply component is coupled to the display panel and is used to supply power to the display panel.

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