Display panel and display device

Abstract

Provided is a display panel. The display panel is provided with a plurality of sub-pixels. The display panel comprises a substrate, a light-emitting device layer and a plurality of connecting portions. The substrate is provided with a circuit layer. The light-emitting device layer is disposed on one side of the substrate. The light-emitting device layer comprises a cathode layer and an anode layer disposed opposite each other, and a light-emitting layer disposed between the cathode layer and the anode layer. The cathode layer is further away from the substrate than the anode layer. The cathode layer comprises a plurality of mutually independent cathodes, each cathode corresponding to at least one sub-pixel. The connecting portions are disposed on one side of the substrate. In the direction parallel to the plane where the substrate is located, the connecting portions are located on at least one side of the cathodes, and the cathodes are connected to the circuit layer by means of the connecting portions.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410354562.X filed on March 26, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) has been widely used in the display field due to its advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed and flexible display.

[0004] The power consumption of OLED needs to be further optimized.

[0005] Summary of the Invention

[0006] In one aspect, a display panel is provided. The display panel has multiple sub-pixels. The display panel includes a substrate, a light-emitting device layer, and multiple connecting portions. The substrate is provided with a circuit layer. The light-emitting device layer is provided on one side of the substrate and includes a cathode layer and an anode layer disposed opposite each other, and a light-emitting layer disposed between the cathode layer and the anode layer. The cathode layer is further away from the substrate than the anode layer, and the cathode layer includes multiple independent cathodes, each cathode corresponding to at least one sub-pixel. The connecting portion is provided on one side of the substrate. The connecting portion is located on at least one side of the cathode in a direction parallel to the plane of the substrate, and the cathode is connected to the circuit layer via the connecting portion.

[0007] In some embodiments, at least one of the plurality of connecting portions is a first connecting portion, the first connecting portion including a first connecting post disposed on one side of the substrate, the cathode connected to the first connecting post, and the first connecting post connected to the circuit layer.

[0008] In some embodiments, the first connecting column includes a first end away from the substrate and a second end close to the substrate, and an orthographic projection of the first end on the substrate is located within an orthographic projection of the second end on the substrate.

[0009] In some embodiments, at least one of the plurality of connecting portions is a second connecting portion, the second connecting portion comprising a second connecting group and a first connecting sub-portion. The second connecting column group comprises at least one second connecting column disposed on a side of the substrate. The first connecting sub-portion is disposed on a side of the second connecting column closer to the substrate. The cathode is connected to at least one of the second connecting column group and the first connecting sub-portion, and the second connecting portion is connected to the circuit layer.

[0010] In some embodiments, the second connecting post includes a third end distal from the substrate and a fourth end proximal to the substrate. When the cathode is connected to the second connecting post, the orthographic projection of the third end of the second connecting post connected to the cathode on the substrate is located within the orthographic projection of the fourth end on the substrate. When the cathode is connected to the first connecting sub-portion, the orthographic projection of the fourth end of the second connecting post connected to the cathode on the substrate is located within the orthographic projection of the third end on the substrate.

[0011] In some embodiments, an orthographic projection of the second connecting column closest to the cathode on the substrate is located within an orthographic projection of the first connecting sub-portion on the substrate.

[0012] In some embodiments, the display panel includes a plurality of pixels, each pixel including at least three sub-pixels. The cathode of each sub-pixel is independent of each other. The connecting portion includes a first connecting portion and / or a second connecting portion, wherein the connecting portion to which the cathode of at least one sub-pixel is connected is the first connecting portion, and / or the connecting portion to which the cathode of at least one sub-pixel is connected is the second connecting portion.

[0013] In some embodiments, the circuit layer includes a first signal line, a second signal line, and a third signal line, and the pixel includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel. The connection portion to which the cathode of the first sub-pixel is connected is connected to the first signal line. The connection portion to which the cathode of the second sub-pixel is connected is connected to the second signal line. The connection portion to which the cathode of the third sub-pixel is connected is connected to the third signal line.

[0014] In some embodiments, the anode layer includes a plurality of anodes, the circuit layer further includes a plurality of pixel circuits, the anodes are connected to the pixel circuits, and the pixel circuits are not in contact with the first signal line, the second signal line, and the third signal line.

[0015] In some embodiments, the display panel further includes a spacer. Along a direction parallel to the plane of the substrate, the spacer and the connecting portion are located on the same side of the cathode to which the connecting portion is connected. An orthographic projection of the spacer on the substrate does not overlap with an orthographic projection of the connecting portion on the substrate.

[0016] In some embodiments, the distance between the spacer and the cathode is greater than or equal to 2 μm.

[0017] In some embodiments, two adjacent cathodes among the plurality of cathodes are respectively a first cathode and a second cathode. The first cathode is located on one side of the second cathode in a direction parallel to the plane of the substrate. The connecting portion is connected to the first cathode, and the spacer portion is connected to the second cathode.

[0018] In some embodiments, the display panel further includes a pixel defining layer. The pixel defining layer is disposed on one side of the substrate. The pixel defining layer includes a plurality of pixel openings and a pixel defining body. The light-emitting devices of the sub-pixels are disposed corresponding to the pixel openings, and the connecting portion extends through the pixel defining body and connects to the circuit layer.

[0019] In some embodiments, the display panel further comprises an isolation layer. The isolation layer is disposed on a side of the pixel defining layer away from the substrate. The isolation layer comprises a plurality of isolation openings, each corresponding to a plurality of pixel openings, and each corresponding isolation opening having a size smaller than that of the pixel openings.

[0020] In another aspect, a display device is provided, comprising a display panel according to any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0022] FIG1 is a structural diagram of a display device provided by some embodiments of the present disclosure;

[0023] FIG2 is a structural diagram of a display panel provided by some embodiments of the present disclosure;

[0024] FIG3 is an enlarged view of the S region of the display panel shown in FIG2 ;

[0025] FIG4 is a structural diagram of a display panel provided by some embodiments of the present disclosure;

[0026] FIG5 is a cross-sectional view taken along section line A1-A2 in FIG4;

[0027] FIG6 is a diagram showing the relationship between the brightness and voltage of a sub-pixel;

[0028] FIG7 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0029] FIG8 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0030] FIG9A is an enlarged view of point B in FIG8 ;

[0031] FIG9B is an enlarged view of point C in FIG8 ;

[0032] FIG9C is an enlarged view of point D in FIG8 ;

[0033] FIG10 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0034] FIG11 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0035] FIG12 is a top view of the structure of an isolation layer and a pixel defining layer provided in some embodiments of the present disclosure;

[0036] FIG13 is a flow chart of a method for manufacturing a display panel according to one embodiment of the present disclosure;

[0037] 14A to 14N are structural diagrams of various steps of a method for manufacturing a display panel provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0042] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0043] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0044] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0045] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0048] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] The present disclosure provides a display device. The display device is an electronic device having an image (including: static image or dynamic image, wherein the dynamic image can be a video) display function. For example, the display device can be any one of a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a large-area wall, a home appliance, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, an electronic screen, a virtual reality (VR) display device, an augmented reality (AR) display device, and an in-vehicle display, but is not limited thereto.

[0051] In some examples, the display device may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0052] FIG1 is a structural diagram of a display device provided by some embodiments of the present disclosure.

[0053] 1 , the embodiment of the present disclosure is exemplified by using a mobile phone as the display device 1000. The display device 1000 includes a display panel 100. The display panel 100 can be any of an OLED display panel, a QLED display panel, or a micro-light-emitting diode (Mini LED or Micro LED) display panel.

[0054] The embodiment of the present disclosure is exemplified by taking the display panel 100 as an OLED display panel, but the embodiments of the present disclosure include but are not limited to this.

[0055] FIG2 is a structural diagram of a display panel provided by some embodiments of the present disclosure.

[0056] To facilitate the following description, an XYZ coordinate system is established. The first direction X and the second direction Y are both parallel to the plane on which the display side of the display panel 100 is located, and the two directions intersect. For example, the first direction X and the second direction Y are perpendicular to each other. The third direction Z is perpendicular to the plane on which the display side of the display panel 100 is located.

[0057] 2 , the display panel 100 may include a display area AA and a peripheral area BB. The display area AA corresponds to the area of ​​the display panel 100 used for displaying images, and the peripheral area BB corresponds to the area of ​​the display panel 100 other than the display area AA. The peripheral area BB may be located on at least one side (e.g., one side or multiple sides) of the display area AA. For example, the peripheral area BB may be disposed around the display area AA.

[0058] FIG. 3 is an enlarged view of the S region of the display panel shown in FIG. 2 .

[0059] A plurality of pixels P are disposed in the display area AA. In some examples, the first direction X may be a row direction of the pixels P, and the second direction Y may be a column direction of the pixels P. The peripheral area BB may include a cathode voltage signal bus.

[0060] 3 , each pixel P includes at least three sub-pixels SP. The sub-pixel SP is the smallest unit for displaying an image within the display panel 100. Each sub-pixel SP can emit a single color. For example, each pixel P includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein any one of the first, second, and third sub-pixels emits red light, one emits green light, and one emits blue light. For the convenience of description below, the embodiments of the present disclosure are described by taking the first sub-pixel as a red sub-pixel R, the second sub-pixel as a green sub-pixel G, and the third sub-pixel as a blue sub-pixel B as an example. Of course, the first sub-pixel can also be a green sub-pixel or a blue sub-pixel, the second sub-pixel can also be a red sub-pixel or a blue sub-pixel, and the third sub-pixel can also be a red sub-pixel or a green sub-pixel, and the same applies to the embodiments of the present disclosure.

[0061] There can be multiple arrangements of sub-pixels SP in the pixel P. For example, the sub-pixel arrangement is a real RGB arrangement, and the pixel P includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. For example, referring to Figure 3 again, the third sub-pixel, the second sub-pixel, and the first sub-pixel are arranged in an array along the first direction X. The rendering algorithm can adopt sub-pixel rendering (Sub Pixel Rendering, SPR). Another example is that the arrangement of sub-pixels SP is a GGRB arrangement, and the pixel P includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the fourth sub-pixel is a green sub-pixel G, and the fourth sub-pixel and the second sub-pixel both emit green light. It should be noted that the arrangement of sub-pixels SP in the pixel P also includes a pentile arrangement, a diamond arrangement, or a Delta arrangement, but is not limited thereto.

[0062] The sub-pixel SP includes a light-emitting device and a pixel circuit. The light-emitting device includes a cathode, an anode, and a light-emitting sublayer. The anode is connected to the pixel circuit, and the cathode is connected to a cathode voltage bus. The pixel circuit provides an anode voltage Vdd to the anode, and the cathode voltage signal bus provides a cathode voltage Vss to the cathode. The voltage difference between the anode voltage Vdd and the cathode voltage Vss is the voltage of the sub-pixel SP. The anode injects holes into the light-emitting sublayer, and the cathode injects electrons into the light-emitting sublayer. The resulting electrons and holes form excitons in the light-emitting sublayer. The excitons return to the ground state through radiative transitions, causing the light-emitting device to emit light, and the sub-pixel SP then emits light. By adjusting the voltage of the sub-pixel SP, the brightness of the light-emitting device can be adjusted, enabling the display of multiple colors.

[0063] The structure of the display panel 100 is described in detail below.

[0064] Fig. 4 is a structural diagram of a display panel provided by some embodiments of the present disclosure. Fig. 5 is a cross-sectional view taken along the section line A1-A2 in Fig. 4 .

[0065] 4 and 5 , the display panel 100 includes a substrate 10 and a light emitting device layer 20. The light emitting device layer 20 is disposed on one side of the substrate 10. The first direction X and the second direction Y are parallel to the plane of the substrate 10, and the third direction Z is perpendicular to the plane of the substrate 10.

[0066] The substrate 10 is provided with a circuit layer 12. The circuit layer 12 includes a plurality of pixel circuits. In some examples, the circuit layer 12 includes a thin film transistor (TFT) layer, a plurality of pixel circuits are provided in the TFT layer, and the pixel circuit includes a plurality of TFTs. Exemplarily, the TFT layer includes an active layer (Active) formed by a patterning process, a gate insulating layer (GI) formed on the active layer by a deposition process, a gate (Gate) of a thin film transistor formed on the gate insulating layer by a patterning process, a dielectric layer (Inter-Layer Dielectric, ILD) formed on the gate by deposition, etc., a source-drain metal layer formed on the dielectric layer, and a planar layer (PLN) covering the source-drain metal layer and the exposed dielectric layer, the source-drain metal layer forms the source (Source) and drain (Drain) of the thin film transistor, for example, the source is electrically connected to the active layer through a dielectric layer via. Among them, the active layer can be made of materials such as polysilicon and metal oxide, the gate insulating layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, and the dielectric layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. Gate materials include metals or alloy materials such as aluminum (Al), titanium (Ti), and cobalt (Co). The flat layer can be made of, for example, an organic material, or can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The flat layer has a flattening effect, which is beneficial to the quality of subsequent material deposition, reduces the surface differences of the subsequently formed anode layer, reflects more light, and has better luminous performance; and the flat layer is beneficial to blocking water and oxygen from the bottom from entering the sub-pixel light-emitting device formed later.

[0067] Continuing with FIG5 , the substrate 10 further includes a base substrate 11. The base substrate 11 is disposed on a side of the circuit layer 12 away from the light-emitting device layer 20 and supports other structures in the display panel 100. The base substrate 11 may be a rigid substrate, the material of which may be glass or polymethyl methacrylate (PMMA). The base substrate 11 may also be a flexible substrate, the material of which may be polyethylene terephthalate (PET), polyethylene naphthalate diformic acid glycol ester (PEN), ultra-thin glass, or polyimide (PI).

[0068] Continuing with Figures 4 and 5 , the light-emitting device layer 20 is disposed on one side of the substrate 10. For example, the light-emitting device layer 20 is disposed on the side of the circuit layer 12 away from the base substrate 11. The light-emitting device layer 20 includes a plurality of light-emitting devices L. The anodes of the plurality of light-emitting devices L form an anode layer 21, the light-emitting sublayers of the plurality of light-emitting devices L form a light-emitting layer 22, and the cathodes of the plurality of light-emitting devices form a cathode layer 23. The anode layer 21 and the cathode layer 23 are disposed opposite each other, with the light-emitting layer 22 located between the anode layer 21 and the cathode layer 23, and the cathode layer 23 is further away from the substrate 10 than the anode layer 21. That is, the anode layer 21, the light-emitting layer 22, and the cathode layer 23 are stacked in sequence in a direction away from the substrate 10, and the stacked anodes, light-emitting sublayers, and cathodes constitute a single light-emitting device L.

[0069] The luminescent colors of the multiple luminescent sublayers can be different. For example, the multiple luminescent sublayers include a first luminescent sublayer 221, a second luminescent sublayer 222, and a third luminescent sublayer 223, wherein any one of the first luminescent sublayer 221, the second luminescent sublayer 222, and the third luminescent sublayer 223 emits red light, one emits green light, and one emits blue light. For the convenience of the following description, the embodiments of the present disclosure are described by taking the first luminescent sublayer as a red luminescent sublayer, the second luminescent sublayer as a green luminescent sublayer, and the third luminescent sublayer as a blue luminescent sublayer as an example. The red luminescent sublayer is generally made of a red organic luminescent material, the green luminescent sublayer is generally made of a green organic luminescent material, and the blue luminescent sublayer is generally made of a blue organic luminescent material. Of course, the first luminescent sublayer can also be a green luminescent sublayer or a blue luminescent sublayer, the second luminescent sublayer can also be a red luminescent sublayer or a blue luminescent sublayer, and the third luminescent sublayer can also be a red luminescent sublayer or a green luminescent sublayer, and the same applies to the embodiments of the present disclosure.

[0070] In some examples, referring again to FIG5 , the light-emitting area of ​​the blue light-emitting sublayer can be greater than the light-emitting area of ​​the red light-emitting sublayer or the green light-emitting sublayer. For example, the orthographic projection area of ​​the third light-emitting sublayer 223 on the substrate 10 is greater than the orthographic projection area of ​​the first light-emitting sublayer 221 on the substrate 10, and the orthographic projection area of ​​the third light-emitting sublayer 223 on the substrate 10 is greater than the orthographic projection area of ​​the second light-emitting sublayer 222 on the substrate 10. The resistivity of blue organic light-emitting materials is generally greater than that of green and red organic light-emitting materials. By increasing the light-emitting area of ​​the blue light-emitting sublayer, the brightness uniformity of the light-emitting device L can be improved, thereby improving the uniformity of the display effect of the display panel 100.

[0071] In some examples, the light-emitting sublayer may further include an auxiliary light-emitting layer that helps the light-emitting sublayer emit light. The auxiliary light-emitting layer may include, for example, one or more film layers of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EIL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0072] Continuing to refer to Figures 4 and 5, the anode layer 21 includes a plurality of anodes 211 (Anode), which are connected to the circuit layer 12. Specifically, the anode 211 is connected to the pixel circuit of the circuit layer 12. Exemplarily, the anode 211 is connected to the pixel circuit through a via, for example, the anode 211 is connected to the drain of the source-drain metal layer through a via penetrating the flat layer. The light-emitting sublayer corresponds one-to-one with the anode 211. The material of the anode 211 is, for example, a metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal such as silver (Ag), aluminum (Al), molybdenum (Mo), or an alloy thereof.

[0073] The cathode layer 23 includes a plurality of cathodes 231. The cathode 231 may be made of a metal such as magnesium (Mg), calcium (Ca), lithium (Li), or aluminum (Al), or an alloy thereof, or a metal oxide such as IZO or ZTO, or an organic material having conductive properties such as PEDOT / PSS (poly (3,4-ethylenedioxythiophene) / polystyrene sulfonate).

[0074] FIG6 is a diagram showing the relationship between the brightness and voltage of a sub-pixel.

[0075] The brightness of a subpixel is related to the voltage applied to it. Specifically, as shown in Figure 6 , within a certain voltage range, the brightness of a subpixel SP is roughly positively correlated with the voltage. For example, for a red subpixel R, within a certain voltage range, the greater the voltage applied to the red subpixel, the greater the brightness of the red subpixel R; for a green subpixel G, within a certain voltage range, the greater the voltage applied to the green subpixel, the greater the brightness of the green subpixel G; and for a blue subpixel B, within a certain voltage range, the greater the voltage applied to the blue subpixel, the greater the brightness of the blue subpixel B.

[0076] In some implementations, multiple cathodes are interconnected to form coplanar cathodes. Since the cathodes are interconnected, the voltage signal of one cathode is transmitted to each cathode through the interconnected cathodes, so that the voltage signal of the cathode of each light-emitting device L is the same, resulting in the same cathode voltage Vss for sub-pixels with different luminous colors.

[0077] Continuing with FIG6 , sub-pixels SP of different luminous colors require different voltages for luminescence. When the luminance of each sub-pixel is the same, the voltage required for luminescence of the blue sub-pixel B is greater than the voltages required for luminescence of the red sub-pixel R and the green sub-pixel G. Therefore, when the cathodes of the cathode layer 23 are connected to each other, to cause the blue sub-pixel B to emit light, the cathode voltage Vss of the cathode layer 23 is relatively large. At this time, the voltage actually required for the red sub-pixel R and the green sub-pixel G is less than the cathode voltage Vss. The current Ivss of the red luminescent sub-layer corresponding to the red sub-pixel R and the green luminescent sub-layer corresponding to the green sub-pixel G is greater than the current required for luminescence, resulting in increased power consumption of the red sub-pixel R and the green sub-pixel G, thereby increasing the power consumption of the entire pixel P, and further increasing the power consumption of the display panel 100, thereby reducing the display performance of the display panel 100.

[0078] To solve the above problem, in some embodiments, the plurality of cathodes 231 are independent of each other, and each cathode 231 corresponds to at least one sub-pixel SP. Independence here means that the cathodes 231 are not connected to each other.

[0079] Each cathode 231 corresponds to at least one subpixel SP, meaning that each cathode serves as the cathode of the light-emitting device in at least one subpixel. Exemplarily, one cathode 231 corresponds to one subpixel SP, meaning that multiple subpixels SP do not share a common cathode 231. For example, the first, second, and third subpixels each correspond to a cathode 231. The cathodes of the light-emitting devices in the first, second, and third subpixels are independent cathodes, and the three cathodes 231 are independent and unconnected. Another exemplary embodiment is that one cathode 231 corresponds to multiple subpixels SP emitting the same luminous color, meaning that two or more subpixels SP emitting the same luminous color share a common cathode 231. For example, the multiple subpixels SP further include a fourth subpixel emitting the same luminous color as the first subpixel, and the first and fourth subpixels correspond to the same cathode 231. For another example, the display panel 100 includes multiple columns of subpixels, each column including multiple subpixels emitting the same luminous color, and the subpixels in the column correspond to the same cathode 231.

[0080] To connect to the circuit layer 12, the display panel 100 further includes a plurality of connecting portions 30. One cathode 231 is connected to the circuit layer 12 via at least one connecting portion 30. To prevent short circuits, the connecting portion 30 and the anode 211 are not in contact with each other.

[0081] Specifically, the connection portion 30 is provided on one side of the substrate 10. Along a direction parallel to the plane of the substrate 10 (e.g., the first direction X), the connection portion 30 is located on at least one side (e.g., one side, or multiple sides) of the cathode 231. For example, referring again to FIG4 , a connection portion 30 is provided on one side of the cathode 231, and each portion of the connection portion 30 is located on the same side of the cathode 231. For another example, a plurality of connection portions 30 are provided on one side of the cathode 231, and each portion of each of the plurality of connection portions 30 is located on the same side of the cathode 231. For another example, each portion of a connection portion 30 is located on either side of a cathode 231. For another example, a plurality of connection portions 30 are provided on either side of a cathode, and the cathode 231 is connected to the connection portions 30 on both sides, and the connection portions 30 on both sides are connected to the circuit layer 12. For another example, a connection portion 30 is provided around the cathode 231, and the cathode 231 is connected to the surrounding connection portions 30, and the surrounding connection portions 30 are connected to the circuit layer 12.

[0082] In the embodiment of the present disclosure, multiple cathodes 231 are independent of each other, each cathode 231 corresponding to at least one sub-pixel SP. A connecting portion 30 is provided to connect the cathodes 231 to the circuit layer 12. The voltage signal provided by the circuit layer 12 to each cathode 231 can also be independent of each other. In this way, the cathode voltage Vss corresponding to each cathode 231 can be different. The cathode voltage Vss of sub-pixels emitting different colors can be adjusted according to actual needs. This can achieve differentiation of the cathode voltage Vss of sub-pixels corresponding to different cathodes. The voltage of the sub-pixel SP can be approximately equal to the actual required voltage, and the brightness of the sub-pixel is adapted to the cathode voltage. For example, the actual voltage of the blue sub-pixel B can be greater than the actual voltage of the red sub-pixel R and the green sub-pixel G. This ensures that the current Ivss in the blue light-emitting sub-layer corresponding to the blue sub-pixel B, the red light-emitting sub-layer corresponding to the red sub-pixel R, and the green light-emitting sub-layer corresponding to the green sub-pixel G are all adapted to the required current, thereby reducing the power consumption of the sub-pixel SP, thereby reducing the power consumption of the pixel P, and further reducing the power consumption of the display panel 100, thereby improving the display performance of the display panel 100.

[0083] In some embodiments, referring to FIG5 , the circuit layer 12 further includes a plurality of signal lines, including a first signal line 121, a second signal line 122, and a third signal line 123. The first signal line 121, the second signal line 122, and the third signal line 123 are all configured to transmit cathode voltage signals, and the voltage magnitudes of the transmitted cathode voltage signals are different. The cathode 231 is connected to the connecting portion 30, the connecting portion 30 is connected to the signal line, the signal line is connected to the cathode voltage signal bus, and the cathode voltage bus is configured to transmit cathode voltage signals. The material of the signal line can be a conductive material such as titanium (Ti), aluminum (Al), copper (Cu), or molybdenum (Mo). The circuit layer 12 can include a metal layer, which is located on the side of the base substrate 11 close to the light-emitting device layer 20. For example, the first signal line 121, the second signal line 122, and the third signal line 123 are located in the same metal layer of the circuit layer 12. That is, multiple signal lines can be formed simultaneously in the same metal layer, reducing the number of metal film layers, thereby simplifying the process steps and improving product production efficiency. Moreover, since multiple signal lines are located in the same metal layer, there is no need to provide an insulating layer between adjacent metal layers, thereby reducing the number of film layers of the display panel 100 and further reducing the size of the display panel 100 in the third direction Z. The circuit layer 12 may also include multiple metal layers, with multiple signal lines located in the multiple metal layers. For example, any two of the first signal line 121, the second signal line 122, and the third signal line 123 are located in the same metal layer, and the first signal line 121, the second signal line 122, and the third signal line 123 are respectively connected to the cathode voltage signal bus. For another example, the multiple metal layers include a first metal layer, a second metal layer, and a third metal layer, the first signal line 121 is located in the first metal layer, the second signal line 122 is located in the second metal layer, and the third signal line 123 is located in the third metal layer, and the multiple signal lines are located in different metal layers. In some implementations, when the circuit layer 12 includes multiple metal layers, the multiple signal lines can also be located in the same metal layer.

[0084] In the same pixel P, sub-pixels emitting different colors are connected to different signal lines. For example, in a pixel P, the cathode 231 of the first sub-pixel is connected to the first signal line 121, the cathode 231 of the second sub-pixel is connected to the second signal line 122, and the cathode 231 of the third sub-pixel is connected to the third signal line 123. As another example, the pixel P further includes a fourth sub-pixel. If the fourth sub-pixel and the first sub-pixel both emit red light, the cathode of the fourth sub-pixel is connected to the first signal line 121, the cathode voltage signal bus transmits a voltage signal to the first signal line 121, the first signal line 121 transmits a signal to the cathodes of the first sub-pixel and the fourth sub-pixel, and the cathode voltage Vss of the first sub-pixel and the fourth sub-pixel are the same. If the fourth sub-pixel and the second sub-pixel both emit green light, the cathode of the fourth sub-pixel is connected to the second signal line 122, the cathode voltage signal bus transmits a voltage signal to the second signal line 122, the second signal line 122 transmits a signal to the cathodes of the second sub-pixel and the fourth sub-pixel, and the cathode voltage Vss of the second sub-pixel and the fourth sub-pixel are the same. If the fourth sub-pixel and the third sub-pixel both emit blue light, the cathode of the fourth sub-pixel is connected to the third signal line 123, the cathode voltage signal bus transmits a voltage signal to the third signal line 123, the third signal line 123 transmits a signal to the cathodes of the third sub-pixel and the fourth sub-pixel, and the cathode voltage Vss of the third sub-pixel and the fourth sub-pixel are the same.

[0085] Subpixels emitting light of the same color in different pixels P may be connected to the same signal line. For example, the plurality of pixels P include a first pixel P1 and a second pixel P2, wherein the red subpixel R of the first pixel P1 and the red subpixel R of the second pixel P2 are both connected to the first signal line 121, the green subpixel G of the first pixel P1 and the green subpixel G of the second pixel P2 are both connected to the second signal line 122, and the blue subpixel B of the first pixel P1 and the blue subpixel B of the second pixel P2 are both connected to the third signal line 123.

[0086] The cathodes 231 corresponding to the sub-pixels emitting the same color are connected to the same signal line. The same signal line controls the voltages of the sub-pixels emitting the same color at the same time, thereby improving signal transmission efficiency.

[0087] In some embodiments, referring again to FIG5 , the pixel circuit does not contact any of the plurality of signal lines. For example, the pixel circuit does not contact the first signal line 121, the second signal line 122, and the third signal line 123. Because the pixel circuit and the signal lines do not contact each other, the anode 211 is connected to the pixel circuit, and the cathode 231 is connected to the signal line. Therefore, the anode 211 cannot be connected to the cathode 231 through the pixel circuit, and the cathode 231 cannot be connected to the anode 211 through the signal line. This can reduce the problem of signal disorder caused by the interconnection of cathodes and anodes between sub-pixels.

[0088] For example, referring to Figure 5, the display panel 100 includes a base substrate 11, a gate layer 124 arranged on one side of the base substrate 11, a first source-drain metal layer 125 and a second source-drain metal layer 126. The gate layer 124 is, for example, the above-mentioned first metal layer, the first source-drain metal layer 125 is, for example, the above-mentioned second metal layer, and the second source-drain metal layer 126 is, for example, the above-mentioned third metal layer. In some examples, the third signal line 123 is located in the same layer as the gate of the thin film transistor, that is, both are located in the gate layer 124, the second signal line is located in the first source-drain metal layer, and the first signal line 121 is located in the same layer as the source (Source) and drain (Drain) of the thin film transistor, that is, both are located in the second source-drain metal layer.

[0089] FIG7 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0090] In some embodiments, at least one (e.g., one, or more) of the multiple connecting portions is a first connecting portion 31, and the cathode 231 is connected to the circuit layer 12 via the first connecting portion 31. Specifically, among the multiple sub-pixels SP of the display panel 100, the cathode 231 of at least one (e.g., one, or more) sub-pixel SP is connected to the circuit layer 12 via the first connecting portion 31.

[0091] Exemplarily, the display panel 100 includes a plurality of pixels P, each pixel P including a plurality of sub-pixels SP. The cathode 231 of at least one (e.g., one, or more) sub-pixel SP of a portion of the plurality of pixels P is connected to the circuit layer 12 via a first connection portion 31, while the sub-pixels SP of another portion of the pixels P are not connected to the circuit layer 12 via the first connection portion 31, but are connected, for example, via a second connection portion 32 (described in detail below). Furthermore, exemplarily, the display panel 100 includes a plurality of pixels P, each pixel P including a plurality of sub-pixels SP. The cathode 231 of at least one (e.g., one, or more) sub-pixel SP of each pixel P is connected to the circuit layer 12 via a first connection portion 31. For example, referring to Figures 4 and 7, a first pixel P1 (not shown in Figure 7) includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The cathode 231 of the first sub-pixel is connected to the first connection portion 31, which is connected to a signal line via a via in the circuit layer 12. The cathodes of the second sub-pixel and / or the third sub-pixel may also be connected to another first connection portion 31, respectively. Furthermore, the cathode 231 of at least one (eg, one, or a plurality of) sub-pixels SP in the second pixel P2 (not shown in FIG. 7 ) is also connected to the circuit layer 12 through the first connecting portion 31 .

[0092] The first connection portion 31 includes a first connection post 311. The first connection post 311 is disposed on one side of the substrate 10. The cathode 231 is connected to the first connection post 311, and the first connection post 311 is connected to the circuit layer 12. For example, referring to FIG. 7 , the first connection post 311 is connected to the cathode 231a, and the first connection post 311 is connected to the signal line in the metal layer through a via in the circuit layer 12. The material of the first connection post 311 can be a conductive material that can achieve signal transmission, such as titanium (Ti), aluminum (Al), copper (Cu), or molybdenum (Mo).

[0093] When forming the first connection portion 31, a via hole can be formed in the circuit layer 12 to expose the signal line to be connected. A thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) is then used to deposit a conductive material to form a connection layer laid on the circuit layer 12. The layer is then patterned through an etching process to form the first connection column 311. Due to the simple structure of the first connection portion 31, the process for forming the first connection portion 31 is simple and easy to form.

[0094] In some embodiments, referring again to FIG. 7 , the first connecting pillar 311 has an overall structure that is narrow at the top and wide at the bottom. Specifically, the first connecting pillar 311 includes a first end 3111 distal from the substrate 10 and a second end 3112 proximal to the substrate 10. The orthographic projection of the first end 3111 on the substrate 10 is located within the orthographic projection of the second end 3112 on the substrate 10. That is, along a direction parallel to the XY plane (e.g., the first direction X), the dimension of the first end 3111 is smaller than the dimension of the second end 3112. For example, the cross-section of the first connecting pillar 311 along the XZ plane can be a trapezoidal structure, and the dimension of the first connecting pillar 311 gradually increases from the first end 3111 to the second end 3112 along the direction proximal to the substrate 10. The boundary of the orthographic projection of the side of the first connecting pillar 311 away from the first end 3111 on the substrate 10 extends beyond the boundary of the orthographic projection of the first end 3111 on the substrate 10. When the cathode 231 is formed using a deposition process or an evaporation process, the conductive material is deposited from the side of the connecting portion 30 away from the substrate 10 toward between adjacent cathodes 231. The conductive material will first contact the side of the first connecting pillar 311 away from the first end 3111 to ensure the connection between the connecting portion 30 and the cathode 231. In some embodiments, referring again to FIG. 7 , at least one (e.g., one, or more) of the multiple connecting portions 30 is a second connecting portion 32, and the cathode 231 is connected to the circuit layer 12 via the second connecting portion 32. Specifically, among the multiple sub-pixels SP of the display panel 100, the cathode 231 of at least one (e.g., one, or more) sub-pixel SP is connected to the circuit layer 12 via the second connecting portion 32.

[0095] Exemplarily, the display panel 100 includes a plurality of pixels P, and the pixel P includes a plurality of sub-pixels SP. The cathode 231 of at least one (for example, one, or multiple) sub-pixel SP of a part of the pixels P among the plurality of pixels P is connected to the circuit layer 12 through the second connection portion 32, and the sub-pixels SP of another part of the pixels P are not connected to the circuit layer 12 through the second connection portion 32, for example, are connected to the circuit layer 12 through the first connection portion 31. Also exemplarily, the display panel 100 includes a plurality of pixels P, and the pixel P includes a plurality of sub-pixels SP. The cathode 231 of at least one (for example, one, or multiple) sub-pixel SP of each pixel P is connected to the circuit layer 12 through the second connection portion 32. For example, referring to Figures 4 and 7 (not shown in Figure 7), the first pixel P1 includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The cathode 231 of the second sub-pixel is connected to the second connection portion 32, and the second connection portion 32 is connected to the signal line through a via in the circuit layer 12. The cathode of the first sub-pixel and / or the third sub-pixel may also be connected to another second connection portion 32, respectively, or the cathode of the first sub-pixel and / or the third sub-pixel may also be connected to the first connection portion 31; and the cathode 231 of at least one (for example, one, or multiple) sub-pixel SP in the second pixel P2 (not shown in Figure 7) is also connected to the circuit layer 12 through the second connection portion 32.

[0096] The second connection portion 32 includes a second connection column group 321 and a first connection sub-portion 322 . The first connection sub-portion 322 is disposed on a side of the second connection column group 321 close to the substrate 10 .

[0097] The second connecting post group 321 includes at least one (e.g., one, or multiple) second connecting post 3211. The second connecting post 3211 is disposed on a side of the first connecting sub-portion 322 away from the substrate 10. The second connecting post 3211 includes a third end 81 away from the substrate 10 and a fourth end 82 closer to the substrate. The plurality of second connecting posts 3211 do not contact each other. For example, the orthographic projections of the plurality of second connecting posts 3211 on the substrate 10 do not overlap.

[0098] The cathode 231 is connected to at least one of the second connecting column group 321 and the first connecting sub-portion 322. The second connecting portion 322 is connected to the circuit layer 12. The second connecting column group 321 and the first connecting sub-portion 322 are made of conductive materials. The conductive materials are described above and are not further described here. The cathode voltage bus transmits the cathode voltage signal of each cathode to the signal line. The cathode voltage signal is transmitted to the second connecting column group 3211 via the first connecting sub-portion 322.

[0099] For example, referring again to FIG7 , cathode 231 is connected to second connecting column group 321, and cathode 231 is not connected to first connecting sub-portion 322. In this case, second connecting column group 321 is connected to first connecting sub-portion 322, which is connected to the signal line through a via in circuit layer 12. The cathode voltage signal is transmitted to cathode 231 via first connecting sub-portion 322 and second connecting column group 321. For example, second connecting column group 321 includes a second connecting column 3211, cathode 231b is connected to second connecting column 3211, second connecting column 3211 is connected to first connecting sub-portion 322b, first connecting sub-portion 322b is connected to circuit layer 12, and the cathode voltage signal is transmitted to cathode 231 via circuit layer 12, first connecting sub-portion 322b, and second connecting column 3211. For another example, the second connecting column group 321 includes a plurality of second connecting columns 3211. The cathode 231c is connected to at least one (e.g., one, or more) second connecting column 3211. The plurality of second connecting columns 3211 are all connected to the first connecting sub-portion 322c. The cathode voltage signal is transmitted to the cathode 231 via the circuit layer 12, the first connecting sub-portion 322c, and the plurality of second connecting columns 3211. Figure 8 is a structural diagram of another display panel provided in some embodiments of the present disclosure. Figure 9A is an enlarged view of point B in Figure 8. Figure 9B is an enlarged view of point C in Figure 8.

[0100] 8 and 9A and 9B, cathode 231 is connected to first connecting sub-portion 322, but not to second connecting column group 321. First connecting sub-portion 322 is connected to the signal line through a via in circuit layer 12, and the cathode voltage signal is transmitted to cathode 231 via first connecting sub-portion 322.

[0101] For example, referring to FIG9A , cathode 231d is connected to first connecting sub-portion 322d, and cathode 231d is not connected to second connecting post group 321. In other words, cathode 231d is not connected to any second connecting post 3211. First connecting sub-portion 322d is connected to a signal line through a via in circuit layer 12, and a cathode voltage signal is transmitted to cathode 231d via the circuit layer and first connecting sub-portion 322d.

[0102] 9B , cathode 231e is connected to first connecting sub-portion 322e, and cathode 231e is not connected to any second connecting post 3211 in second connecting post group 321. First connecting sub-portion 322e is connected to a signal line through a via in the circuit layer, and the cathode voltage signal is transmitted to cathode 231e via the circuit layer and first connecting sub-portion 322e.

[0103] FIG9C is an enlarged view of point D in FIG8 .

[0104] As another example, referring to Figures 8 and 9C , cathode 231 is simultaneously connected to second connecting column group 321 and first connecting sub-portion 322. In this case, first connecting sub-portion 322 is connected to the signal line through a via in circuit layer 12. The cathode voltage signal can be transmitted directly to cathode 231 via first connecting sub-portion 322, or transmitted to cathode 231 via first connecting sub-portion 322 and second connecting column group 321. For example, referring to Figure 9C , second connecting column group 321f and first connecting sub-portion 322f are simultaneously connected to cathode 231f. This can improve the connection strength between cathode 231f and second connecting portion 32, facilitating signal transmission.

[0105] In some embodiments, referring again to FIG. 7 , when the cathode 231 is connected only to the second connecting pillar group 321, the second connecting pillar 3211 connected to the cathode 231 has an overall structure that is narrow at the top and wide at the bottom. Specifically, the orthographic projection of the third end 81 of the second connecting pillar 3211 connected to the cathode 231 on the substrate 10 is located within the orthographic projection of the fourth end 82 on the substrate 10. In other words, along a direction parallel to the XY plane, the dimension of the third end 81 is smaller than the dimension of the fourth end 82. For example, the cross-section of the second connecting pillar 3211 along the XZ plane can have a trapezoidal structure, with the dimension of the second connecting pillar 3211 gradually increasing from the third end 81 to the fourth end 82 as it approaches the substrate 10. The boundary of the positive projection of the side of the second connecting column 3211 away from the third end 81 on the substrate 10 exceeds the boundary of the positive projection of the fourth end 82 on the substrate 10. When the cathode 231 is formed by a deposition process or an evaporation process, the conductive material is deposited from the side of the connecting part 30 away from the substrate 10 to between adjacent cathodes 231. The conductive material will first contact the side of the second connecting column 3211 away from the third end 81, which is conducive to the connection between the second connecting part 32 and the cathode 231.

[0106] In some embodiments, referring again to Figures 8 and 9B , when the cathode 231 is connected only to the first connecting sub-portion 322, the second connecting post 3211 connected to the cathode 231 has an overall structure that is wider at the top and narrower at the bottom. Specifically, the orthographic projection of the fourth end 82 of the second connecting post 3211 connected to the cathode 231 on the substrate 10 is located within the orthographic projection of the third end 81 on the substrate 10. That is, along a direction parallel to the XY plane, the dimension of the third end 81 is greater than the dimension of the fourth end 82. For example, the cross-section of the second connecting post 3211 in the XZ plane can have an inverted trapezoidal structure, with the dimension of the second connecting post 3211 gradually decreasing from the third end 81 to the fourth end 82 as it approaches the substrate 10. The third end 81 has the largest dimension. During the evaporation process to form the light-emitting sub-layer and cathode, the light-emitting sub-layer and cathode are disconnected at the edge of the second connecting post 3211, preventing interconnection between the light-emitting sub-layers of sub-pixels of different luminous colors and between the cathode 231, thereby reducing signal disturbances. In some implementations, when the cathode 231 is connected only to the first connecting sub-portion 322 , the second connecting column 3211 connected to the cathode 231 may also be a structure that is narrow at the top and wide at the bottom.

[0107] In some embodiments, cathode 231 is connected to second connecting portion 32. Second connecting column group 321 in second connecting portion 32 includes multiple second connecting columns 3211. Second connecting column 3211 closest to cathode 231 (the cathode connected to second connecting portion 32) among multiple second connecting columns 3211 is a selected second connecting column, and the orthographic projection of the selected second connecting column on substrate 10 is within the orthographic projection of the first connecting sub-portion 322 on substrate 10. "Closest" here may mean that, along the first direction X, the distance between the selected second connecting column and cathode 231 is the smallest compared to the distances between the other second connecting columns 3211 in second connecting column group 321 and cathode 231. Along the direction parallel to the XY plane, the size of the selected second connecting column is larger than the size of the first connecting sub-portion 322, and the boundary of the positive projection of the first connecting sub-portion 322 on the substrate 10 exceeds the boundary of the positive projection of the selected second connecting column on the substrate 10. When the cathode 231 is formed by a deposition process or an evaporation process, the conductive material is deposited from the side of the connecting portion 30 away from the substrate 10 to between adjacent cathodes 231. The conductive material will first contact the first connecting sub-portion 322, and the cathode 231 will be more easily connected to the first connecting sub-portion 322, which is conducive to the connection between the second connecting portion 32 and the cathode 231.

[0108] In some embodiments, the plurality of connection portions include a first connection portion 31 and / or a second connection portion 32. Exemplarily, the plurality of connection portions include a first connection portion 31. Each cathode is connected to the circuit layer 12 via the first connection portion 31, that is, the cathode of each sub-pixel is connected to the first connection portion 31. Another exemplary embodiment, the plurality of connection portions include a second connection portion 32. Each cathode is connected to the circuit layer 12 via the second connection portion 32, that is, the cathode of each sub-pixel is connected to the second connection portion 32. Another exemplary embodiment, the plurality of connection portions include a first connection portion 31 and a second connection portion 32. Among the plurality of cathodes, some cathodes are connected to the circuit layer 12 via the first connection portion 31, and some cathodes are connected to the circuit layer 12 via the second connection portion 32. Some cathodes may also be connected to both the first connection portion 31 and the second connection portion 32. The cathodes may be connected to the circuit layer 12 via different connection portions 30.

[0109] The connection portion to which the cathode of at least one sub-pixel is connected is the first connection portion 31 , and / or the connection portion to which the cathode of at least one sub-pixel is connected is the second connection portion 32 .

[0110] Exemplarily, the connection portion to which the cathode of at least one (e.g., one, or more) sub-pixels is connected is the first connection portion 31. The cathode connected to the first connection portion 31 may be the cathode of a different sub-pixel SP of the same pixel P, or the cathode of a different sub-pixel SP of different pixels P. Further exemplarily, the connection portion to which the cathode of at least one (e.g., one, or more) sub-pixels is connected is the second connection portion 32, and the cathode connected to the second connection portion 32 may be the cathode of a different sub-pixel SP of the same pixel P, or the cathode of a different sub-pixel SP of different pixels P. Further exemplarily, the connection portion to which the cathode of at least one (e.g., one, or more) sub-pixels is connected is the first connection portion 31, and the connection portion to which the cathode of at least one (e.g., one, or more) sub-pixels is connected is the second connection portion 32. Among the multiple cathodes of different sub-pixels SP in the same pixel P, some are connected to the first connection portion 31, and some are connected to the second connection portion 32. In different pixels P, the multiple cathodes of different sub-pixels SP in one pixel P are all connected to the first connection portion 31, while the multiple cathodes of different sub-pixels SP in another pixel P are all connected to the second connection portion 32. The cathode of a sub-pixel in the same pixel P is connected to both the first connection portion 31 and the second connection portion 32.

[0111] FIG10 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0112] In some embodiments, referring to FIG. 10 , the display panel 100 further includes a spacer 70. Along a direction parallel to the plane of the substrate 10, the spacer 70 and the connecting portion 30 are located on the same side of the cathode 231 to which the connecting portion 30 is connected. For example, among adjacent cathodes, the cathode connected to the connecting portion 30a is the first cathode 2311, and the other cathode is the second cathode 2312. The first cathode 2311 is located on one side of the second cathode 2312, and the spacer 70 and the connecting portion 30a are both located on the side of the first cathode 2311 closest to the second cathode 2312. For example, along the first direction X, the second cathode 2312, the spacer 70, the connecting portion 30, and the first cathode 2311 are arranged in sequence. In this way, the spacer 70 further prevents adjacent cathodes 231 from connecting to each other. The orthographic projection of the spacer 70 on the substrate 10 does not overlap with the orthographic projection of the connecting portion 30 on the substrate 10, preventing the spacer 70 from connecting to the connecting portion 30 and causing signal transmission disruption. The spacer 70 is not connected to the signal line. When forming the spacer 70, it is not necessary to provide a via hole in the circuit layer 12 to connect the spacer 70. The spacer 70 can be directly formed on the side of the circuit layer 12 away from the base substrate 11. The material of the spacer 70 can be a conductive material or an insulating material.

[0113] In some embodiments, with continued reference to FIG10 , the distance between the spacer 70 and the cathode 231 is greater than or equal to 2 μm. Specifically, the distance between the boundary of the orthographic projection of the spacer 70 on the substrate 10 and the boundary of the orthographic projection of the cathode 231 on the substrate 10 is greater than or equal to 2 μm, for example, 2 μm, 2.5 μm, 3 μm, etc. Exemplarily, the distance between the boundary of the orthographic projection of the spacer 70 on the substrate 10 and the boundary of the orthographic projection of the first cathode 2311 on the substrate 10 is a first distance d1, which is greater than or equal to 2 μm, for example, 2 μm, 2.5 μm, 3 μm, etc., and the distance between the boundary of the orthographic projection of the spacer 70 on the substrate 10 and the boundary of the orthographic projection of the second cathode 2312 on the substrate 10 is a second distance d2, which is greater than or equal to 2 μm, for example, 2 μm, 2.5 μm, 3 μm, etc. The first distance d1 and the second distance d2 may be the same or different. A distance is maintained between the spacer 70 and the cathode 231 so that the spacer 70 and the cathode 231 do not contact each other.

[0114] FIG11 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0115] In some embodiments, referring to FIG11 , the connecting portion 30 is connected to the first cathode 2311, and the spacer 70 is connected to the second cathode 2312. When the spacer 70 is made of a conductive material, the signal of the signal line connected to the second cathode 2312 can be transmitted to the spacer 70. Because there is no overlap between the spacer 70 and the connecting portion 30b, the cathode voltage signal of the second cathode 2312 is not transmitted to the connecting portion 30b connected to the first cathode 2311. This allows the voltage signals provided by the circuit layer 12 to the first cathode 2311 and the second cathode 2312 to be independent of each other. The spacer 70 and the anode are not in contact with each other, preventing the cathode and anode of the light-emitting device from being connected through the spacer 70, resulting in the cathode and anode having the same voltage and the light-emitting sublayer not emitting light. When the spacer 70 is made of an insulating material, the spacer 70 can contact the anode, and the cathode voltage signal of the second cathode 2312 cannot be transmitted to the anode through the spacer, thereby maintaining a voltage difference between the anode and cathode, allowing the light-emitting sublayer to emit light normally.

[0116] 5 , in some embodiments, the display panel 100 further includes a pixel defining layer 40 . The pixel defining layer 40 is disposed on one side of the substrate 10 .

[0117] The pixel-defining layer 40 includes a plurality of pixel openings 41, and the light-emitting devices L of the sub-pixels are disposed correspondingly to the pixel openings 41. Each pixel opening 41 exposes a portion of the anode 211, and the light-emitting sub-layers are disposed one by one within the pixel openings 41. The light-emitting sub-layers are formed on the anodes 211 exposed by the pixel openings 41, and the cathodes 231 can be located within the pixel openings 41.

[0118] The pixel defining layer 40 also includes a pixel defining body 42. The pixel defining body 42 is located between two adjacent cathodes 231. The material of the pixel defining body 42 includes, for example, an organic insulating material such as a negative photoresist, polyimide, or epoxy resin to prevent the cathodes 231 from being connected to each other. The connecting portion 30 passes through the pixel defining body 42 and is connected to the circuit layer 12. When forming the pixel defining layer 40, the connecting portion 30 can be first formed on one side of the substrate 10, and then the pixel defining layer 40 can be formed through a patterning process so that the connecting portion 30 corresponds to the via in the circuit layer 12 to ensure that the connecting portion 30 is connected to the signal line of the circuit layer 12.

[0119] The pixel defining layer 40 is formed by a patterning process, including: if the pixel defining film is made of an inorganic material, a pixel defining film having a certain thickness can be formed by deposition; if the pixel defining film is made of an organic material, a pixel defining film having a certain thickness can be formed by a coating process. The pixel defining film can be the same height as the connecting portion 30, and the pixel defining film covers the anode layer. The pixel defining film is patterned using a photolithography process to form a plurality of pixel openings 41, thereby obtaining the pixel defining layer 40.

[0120] FIG12 is a top view of the structure of the isolation layer and the pixel defining layer provided in some embodiments of the present disclosure.

[0121] 5 , the display panel 100 further includes an isolation layer 50. The isolation layer 50 is disposed on a side of the pixel defining layer 40 away from the substrate 10. The isolation layer 50 is made of an insulating material, which can be seen from the above description and will not be further described here.

[0122] 5 and 12 , the isolation layer 50 includes a plurality of isolation openings 51, and the plurality of isolation openings 51 correspond to the positions of the plurality of pixel openings 41. The size d3 of the corresponding isolation openings 51 is smaller than the size d4 of the pixel opening 41. The edge of the isolation layer 50 exceeds the boundary of the pixel defining body directly opposite to it. The isolation layer 50 covers a portion of the pixel opening 41. In the process of forming the light-emitting sublayer and the cathode in the pixel opening 41 by the evaporation process, the isolation layer 50 disconnects the light-emitting sublayer and the cathode of adjacent sub-pixels, and forms an independent light-emitting sublayer and an independent cathode in the pixel opening 41, thereby preventing the cathodes 231 from being connected to each other. In some embodiments, referring again to FIG. 5 , the via hole in the circuit layer 12 connected to the anode 211 is a first via hole 91. Along a direction parallel to the plane of the substrate 10, the distance between the first via hole 91 and the anode 211 is a third distance d5. That is, the distance between the boundary of the orthographic projection of the first via hole 91 on the substrate 10 and the boundary of the orthographic projection of the anode 211 connected to the first via hole 91 on the substrate 10 is the third distance d5. The third distance d5 is greater than or equal to 5 μm, for example, 5 μm, 6 μm, 7 μm, etc. If the third distance d5 is less than 5 μm, the distance between the boundary of the anode 211 and the first via hole 91 is small, which may cause the edge of the anode 211 to be recessed during the formation of the anode 211, affecting the flatness of the anode 211.

[0123] In some embodiments, referring again to FIG5 , the connection portion 30 is connected to the circuit layer 12 through a second via 92. Along a direction parallel to the plane of the substrate 10, the distance between the second via 92 and the light-emitting sublayer is a fourth distance d6. In other words, the distance between the boundary of the orthographic projection of the second via 92 on the substrate 10 and the boundary of the orthographic projection of the light-emitting sublayer 220 corresponding to the connection portion 30 connected to the second via 92 on the substrate 10 is the fourth distance d6.

[0124] The pixel P includes a red light-emitting sublayer, a green light-emitting sublayer, and a blue light-emitting sublayer. The fourth distance d6 corresponding to the green light-emitting sublayer is less than or equal to 2.8 μm, for example, 2.8 μm, 2.5 μm, 2 μm, 1.5 μm, etc. The fourth distance d6 corresponding to the red light-emitting sublayer or the blue light-emitting sublayer is less than or equal to 1.2 μm, for example, 1.2 μm, 1 μm, 0.5 μm, etc. The distance between the via and the light-emitting sublayer is limited so that the surfaces of the connecting portion 30 and the pixel defining layer 40 away from the isolation layer 50 are flat, which facilitates the overlapping of the connecting portion 30 and the second via 92.

[0125] 5 , the display panel 100 further includes an encapsulation layer 60 . The encapsulation layer 60 is located on a side of the light emitting device layer 20 away from the substrate 10 .

[0126] Exemplarily, the encapsulation layer 60 includes a first inorganic encapsulation layer 61, an organic encapsulation layer 62, and a second inorganic encapsulation layer 63. For example, the first inorganic encapsulation layer 61 and the second inorganic encapsulation layer 63 are formed by deposition or the like. The organic encapsulation layer 62 is formed by inkjet printing. The first inorganic encapsulation layer 61, the organic encapsulation layer 62, and the second inorganic encapsulation layer 63 form a composite encapsulation layer. The materials of the first inorganic encapsulation layer 61 and the second inorganic encapsulation layer 63 can be inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, and the material of the organic encapsulation layer 63 can be organic materials such as polyimide (PI) and epoxy resin. As a result, the encapsulation layer 60 can provide multiple protections for the functional structure of the display panel 100, thereby achieving a better encapsulation effect.

[0127] The present disclosure also provides a method for manufacturing a display panel. Figure 13 is a flow chart of a method for manufacturing a display panel according to one embodiment of the present disclosure. Figures 14A to 14N are structural diagrams of various steps of a method for manufacturing a display panel according to some embodiments of the present disclosure.

[0128] The following schematically illustrates the manufacturing method of the display panel provided by some embodiments of the present disclosure with reference to the accompanying drawings. Referring to FIG13 , the manufacturing method of the display panel includes: S1 to S9.

[0129] S1. Provide a substrate 10.

[0130] FIG14A is a structural diagram of a substrate provided in some embodiments of the present disclosure.

[0131] Referring to FIG. 14A , substrate 10 includes a base substrate 11 and a circuit layer 12 . The structure of substrate 10 can be found in the description above and will not be further elaborated here. Circuit layer 12 further includes a first via 91 and a second via 92 . First via 91 exposes a portion of the pixel circuitry and is used to connect the pixel circuitry in circuit layer 12 to a subsequently formed anode. Second via 92 exposes a signal line to be connected and is used to connect the signal line in circuit layer 12 to a subsequently formed connection portion 30 .

[0132] S2. Forming the anode layer 21.

[0133] FIG14B is a structural diagram of forming an anode layer according to some embodiments of the present disclosure.

[0134] An initial anode layer is formed on the side of the circuit layer 12 away from the base substrate 11, and then patterned by etching to form a plurality of anodes 211. Referring to FIG14B, the anodes 211 are connected to the first vias 91, and the anodes 211 are connected to the pixel circuit through the first vias 91.

[0135] S3. Forming the connection portion 30.

[0136] FIG14C is a structural diagram of forming a connection portion provided by some embodiments of the present disclosure.

[0137] A connection layer is formed on circuit layer 12 using a deposition process, and then patterned using an etching process to form connection portion 30. Referring to FIG14C , connection portion 30 is connected to second via 92 in circuit layer 12. Connection portion 30 is connected to the signal line of circuit layer 12 through second via 92. Connection portion 30 is higher than cathode layer 23. In some examples, a gap is left between connection portion 30 and anode 211.

[0138] The structure of the connecting portion 30 can be found in the above description and will not be repeated here.

[0139] S4. Forming a pixel definition film 401.

[0140] FIG14D is a structural diagram of a pixel-defining film formed according to some embodiments of the present disclosure.

[0141] Referring to FIG. 14D , a pixel defining film 401 is formed on the side of the circuit layer 12 away from the base substrate 11. The pixel defining film 401 can be at the same height as the connection portion 30, or it can cover the connection portion 30 and the cathode layer 23. The material for the pixel defining film 401 can be found in the materials for the pixel defining layer described above and will not be further described here.

[0142] S5. Forming an initial isolation layer 501.

[0143] FIG14E is a structural diagram of forming an initial isolation layer according to some embodiments of the present disclosure.

[0144] 14E , an initial isolation layer 501 is formed on the side of the pixel defining film 401 away from the substrate 10. The initial isolation layer 501 covers the connection portion 30 and the pixel defining film 401. The materials of the initial isolation layer 501 can be found in the above-mentioned isolation layer and are not described again here.

[0145] S6. Forming an isolation layer 50.

[0146] FIG14F is a structural diagram of forming an isolation layer provided in some embodiments of the present disclosure.

[0147] 14F , the initial isolation layer 501 is patterned using a photolithography process to form a plurality of isolation openings 51 , thereby obtaining an isolation layer 50 . The isolation openings 51 penetrate the initial isolation layer 501 , and each isolation opening 51 corresponds to at least one anode 211 . The isolation layer 50 covers the connection portion 30 .

[0148] S7 . Forming a pixel definition layer 40 .

[0149] FIG14G is a structural diagram of forming a pixel defining layer provided in some embodiments of the present disclosure.

[0150] Referring to FIG14G , the pixel defining film 401 is patterned using a photolithography process to form a plurality of pixel openings 41, thereby obtaining a pixel defining layer 40. A portion of the connecting portion 30 is exposed on the side of the pixel opening 41, and the exposed portion of the connecting portion 30 is used to connect the cathode formed subsequently to the connecting portion 30. The exposed portion of the connecting portion 30 may be the first connecting column of the first connecting portion, the second connecting column group of the second connecting portion, the first connecting sub-portion of the second connecting portion, or the second connecting column group and the first connecting sub-portion of the second connecting portion are exposed simultaneously. The bottom of the pixel opening 41 exposes a portion of the anode 211. The plurality of pixel openings 41 include a first pixel opening 411, a second pixel opening 412, and a third pixel opening 413. The first pixel opening 411 corresponds to the first light-emitting sub-layer, the second pixel opening 412 corresponds to the second light-emitting sub-layer, and the third pixel opening 413 corresponds to the third light-emitting sub-layer.

[0151] The pixel defining layer 40 further includes a pixel defining body 42. The isolation layer 50 covers the pixel defining body 42. The material and structure of the pixel defining layer 40 can be found in the above description and will not be repeated here.

[0152] S8. Form a plurality of light-emitting devices.

[0153] The plurality of light-emitting devices include a first light-emitting device, a second light-emitting device and a third light-emitting device, wherein the first light-emitting device includes a cathode, an anode and a first light-emitting sublayer located between the cathode and the anode, the second light-emitting device includes a cathode, an anode and a second light-emitting sublayer located between the cathode and the anode, the third light-emitting device includes a cathode, an anode and a third light-emitting sublayer located between the cathode and the anode, the first light-emitting device emits red light, the second light-emitting device emits green light, and the third light-emitting device emits blue light.

[0154] The embodiment of the present disclosure takes the formation of the first light-emitting device first, the formation of the second light-emitting device, and the formation of the third light-emitting device as an example. It can be understood that the order of forming the first light-emitting device, the second light-emitting device and the third light-emitting device can also be other orders, and the embodiment of the present disclosure does not limit this.

[0155] The process of forming a plurality of light emitting devices may include: S81 to S86.

[0156] 14H to 14M are structural diagrams of various steps of forming a plurality of light-emitting devices according to some embodiments of the present disclosure.

[0157] S81 , forming a first light-emitting layer 202 , an initial first cathode layer 203 and an initial first encapsulation layer 601 .

[0158] 14H , a stacked first light-emitting layer 202, an initial first cathode layer 203, and an initial first encapsulation layer 601 are sequentially formed. A portion of the first light-emitting layer 202 is located within the pixel opening 41, while another portion is located on the side of the isolation layer 50 away from the substrate 10. The initial first cathode layer 203 is located on the side of the first light-emitting layer 202 away from the substrate 10, with a portion of the initial first cathode layer 203 located within the pixel opening 41. The initial first encapsulation layer 601 is located on the side of the initial first cathode layer 203 away from the substrate 10.

[0159] Among them, the part of the first light-emitting layer 202 located in the first pixel opening 411 is the first light-emitting sublayer 221, the part of the initial first cathode layer 203 located in the first pixel opening 411 is the cathode 231 corresponding to the first light-emitting sublayer 221, and the part of the initial first encapsulation layer 601 located on the side of the first light-emitting sublayer 221 away from the substrate 10 is the first encapsulation sublayer 611, and the first encapsulation sublayer 611 covers the isolation opening 51.

[0160] S82 , forming a first light emitting device L1 .

[0161] 14I , the first light-emitting sublayer 221, the cathode 231 corresponding to the first light-emitting sublayer 221, and the first encapsulation sublayer 611 are retained, while the first light-emitting layer 202, the initial first cathode layer 203, and the remaining portions of the initial first encapsulation layer 601 are removed, exposing the second pixel opening 412, the third pixel opening 413, and the isolation openings 51 corresponding to the second pixel opening 412 and the third pixel opening 413. The anode 211, the first light-emitting sublayer 221, and the cathode 231 stacked in sequence constitute a first light-emitting device L1.

[0162] S83 , forming a second light emitting layer 204 , an initial second cathode layer 205 and an initial second encapsulation layer 602 .

[0163] Referring to FIG14J , the second light-emitting layer 204, the initial second cathode layer 205, and the initial second encapsulation layer 602 are sequentially stacked. A portion of the second light-emitting layer 204 is located on the side of the isolation layer 50 away from the substrate 10, a portion is located on the side of the first encapsulation sublayer 611 away from the substrate 10, and a portion is located within the pixel opening 41. The initial second cathode layer 205 is located on the side of the second light-emitting layer 204 away from the substrate 10, wherein a portion of the initial second cathode layer 205 is located within the pixel opening 41. The initial second encapsulation layer 602 is located on the side of the initial second cathode layer 205 away from the substrate 10.

[0164] Among them, the part of the second light-emitting layer 204 located in the second pixel opening 412 is the second light-emitting sublayer 222, the part of the initial second cathode layer 205 located in the second pixel opening 412 is the cathode 231 corresponding to the second light-emitting sublayer 222, and the part of the initial second encapsulation layer 602 located on the side of the second light-emitting sublayer 222 away from the substrate 10 is the second encapsulation sublayer 612, and the second encapsulation sublayer 612 covers the isolation opening 51 corresponding to the second pixel opening 412.

[0165] S84: forming a second light emitting device L2.

[0166] 14K , the second light-emitting sublayer 222, the cathode 231 corresponding to the second light-emitting sublayer 222, and the second encapsulation sublayer 612 are retained, while the second light-emitting layer 204, the initial second cathode layer 205, and the remaining portion of the initial second encapsulation layer 602 are removed, exposing the third pixel opening 413 and the isolation opening 51 corresponding to the third pixel opening 413. The anode 211, the second light-emitting sublayer 222, and the cathode 231 stacked in sequence constitute a second light-emitting device L2.

[0167] S85 , forming a third light-emitting layer 206 , an initial third cathode layer 207 and an initial third encapsulation layer 603 .

[0168] Referring to FIG. 14L , the third light-emitting layer 206, the initial third cathode layer 207, and the initial third encapsulation layer 603 are sequentially stacked. A portion of the third light-emitting layer 206 is located on the side of the isolation layer 50 away from the substrate 10, a portion is located on the side of the first encapsulation sublayer 611 away from the substrate 10, a portion is located on the side of the second encapsulation sublayer 612 away from the substrate 10, and another portion is located within the pixel opening 41. The initial third cathode layer 207 is located on the side of the third light-emitting layer 206 away from the substrate 10, wherein a portion of the initial third cathode layer 207 is located within the third pixel opening 413. The initial third encapsulation layer 603 is located on the side of the initial third cathode layer 207 away from the substrate 10.

[0169] Among them, the part of the third light-emitting layer 206 located in the third pixel opening 413 is the third light-emitting sublayer 223, the part of the initial third cathode layer 207 located in the third pixel opening 413 is the cathode 231 corresponding to the third light-emitting sublayer 223, and the part of the initial third encapsulation layer 603 located on the side of the third light-emitting sublayer 223 away from the substrate 10 is the third encapsulation sublayer 613, and the third encapsulation sublayer 613 covers the isolation opening 51 corresponding to the third pixel opening 413.

[0170] S86 , forming a third light emitting device L3 .

[0171] Referring to FIG. 14M , the third light-emitting sublayer 223, the cathode 231 corresponding to the third light-emitting sublayer 223, and the third encapsulation sublayer 613 are retained, while the third light-emitting layer 206, the initial third cathode layer 207, and the remaining portions of the initial third encapsulation layer 603 are removed. The anode 211, the third light-emitting sublayer 223, and the cathode 231 stacked in sequence form a third light-emitting device L3. At this point, the first encapsulation sublayer 611, the second encapsulation sublayer 612, and the third encapsulation sublayer 613 form the first inorganic encapsulation layer 61.

[0172] S9 , forming an encapsulation layer 60 .

[0173] Referring to FIG14N , an organic encapsulation layer 63 is formed by inkjet printing on the side of the isolation layer 50 and the first inorganic encapsulation layer 61 away from the substrate 10, and a second inorganic encapsulation layer 63 is formed by deposition. The materials for the first inorganic encapsulation layer 61, the organic encapsulation layer 62, and the second inorganic encapsulation layer 63 are described above and are not further described here. The multiple layers of encapsulation layer provide multiple protections for the light-emitting device, achieving a better encapsulation effect.

[0174] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel having a plurality of sub-pixels; The display panel includes: a substrate provided with a circuit layer; A light-emitting device layer is provided on one side of the substrate; the light-emitting device layer comprises: A cathode layer and an anode layer are arranged opposite to each other; the cathode layer is farther away from the substrate than the anode layer; the cathode layer includes a plurality of cathodes independent of each other; the cathode corresponds to at least one of the sub-pixels; a light-emitting layer disposed between the cathode layer and the anode layer; A plurality of connecting parts are provided on one side of the substrate; the connecting parts are located on at least one side of the cathode along a direction parallel to the plane where the substrate is located; the cathode is connected to the circuit layer through the connecting parts.

2. The display panel according to claim 1, wherein: At least one of the plurality of connection parts is a first connection part, and the first connection part includes: A first connecting post is provided on one side of the substrate; the cathode is connected to the first connecting post, and the first connecting post is connected to the circuit layer.

3. The display panel according to claim 2, wherein: The first connecting column includes a first end away from the substrate and a second end close to the substrate, and an orthographic projection of the first end on the substrate is located within an orthographic projection of the second end on the substrate.

4. The display panel according to any one of claims 1 to 3, wherein: At least one of the plurality of connection portions is a second connection portion, and the second connection portion includes: a second connecting post group, comprising at least one second connecting post, disposed on one side of the substrate; a first connecting sub-portion, disposed on a side of the second connecting column close to the substrate; The cathode is connected to at least one of the second connection column group and the first connection sub-portion, and the second connection portion is connected to the circuit layer.

5. The display panel according to claim 4, wherein: The second connecting column includes a third end away from the substrate and a fourth end close to the substrate; When the cathode is connected to the second connecting column group, the orthographic projection of the third end of the second connecting column connected to the cathode on the substrate is located within the orthographic projection of the fourth end on the substrate; When the cathode is connected to the first connecting sub-part, the orthographic projection of the fourth end of the second connecting column connected to the cathode on the substrate is located within the orthographic projection of the third end on the substrate.

6. The display panel according to claim 4 or 5, wherein: The orthographic projection of the second connecting column closest to the cathode on the substrate is located within the orthographic projection of the first connecting sub-portion on the substrate.

7. The display panel according to any one of claims 1 to 6, wherein: The display panel includes a plurality of pixels, each pixel includes at least three sub-pixels, and the cathode of each sub-pixel is independent of each other; The plurality of connection parts include a first connection part and / or a second connection part; a connection part to which the cathode of at least one sub-pixel is connected; The connection portion is the first connection portion, and / or the connection portion to which the cathode of at least one sub-pixel is connected is the second connection portion.

8. The display panel according to claim 7, wherein: The circuit layer includes a first signal line, a second signal line and a third signal line; the pixel includes at least a first sub-pixel, a second sub-pixel and a third sub-pixel; The connection portion connected to the cathode of the first sub-pixel is connected to the first signal line; the connection portion connected to the cathode of the second sub-pixel is connected to the second signal line; and the connection portion connected to the cathode of the third sub-pixel is connected to the third signal line.

9. The display panel according to claim 8, wherein: The anode layer includes a plurality of anodes; the circuit layer also includes a plurality of pixel circuits, and the anodes are connected to the pixel circuits; The pixel circuit does not contact the first signal line, the second signal line, and the third signal line.

10. The display panel according to any one of claims 1 to 9, wherein: The display panel further includes: along a direction parallel to the plane of the substrate, the spacer and the connecting portion are located on the same side of the cathode connected to the connecting portion; the orthographic projection of the spacer on the substrate does not overlap with the orthographic projection of the connecting portion on the substrate.

11. The display panel according to claim 10, wherein: A distance between the spacer and the cathode is greater than or equal to 2 μm.

12. The display panel according to claim 10 or 11, wherein: Among the plurality of cathodes, two adjacent cathodes are respectively a first cathode and a second cathode, and along a direction parallel to the plane where the substrate is located, the first cathode is located on one side of the second cathode; The connecting portion is connected to the first cathode, and the partition portion is connected to the second cathode.

13. The display panel according to any one of claims 1 to 12, wherein: Also includes: A pixel defining layer is disposed on one side of the substrate; The pixel definition layer includes: a plurality of pixel openings, wherein the light-emitting devices of the sub-pixels are arranged corresponding to the pixel openings; The pixel defining body, the connecting portion passes through the pixel defining body and is connected to the circuit layer.

14. The display panel according to claim 13, wherein: Also includes: The isolation layer is arranged on a side of the pixel defining layer away from the substrate; the isolation layer includes a plurality of isolation openings, the plurality of isolation openings correspond to the positions of the plurality of pixel openings, and the corresponding size of the isolation openings is smaller than the size of the pixel openings.

15. A display device comprising: The display panel according to any one of claims 1 to 14.

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