Display panel and display device

Abstract

A display panel and a display device. The display panel has a display area. The display area has a hole area, an isolation area, and a pixel area. The isolation area is arranged between the hole area and the pixel area. A hydrophilic layer is provided in the pixel area and extends to the isolation area. A first sub-part is provided on the side of a first isolation structure distant from a substrate. A second sub-part is provided on the side of the first isolation structure distant from or close to the hole area. A packaging layer covers the side wall of the first isolation structure, the first sub-part, and the second sub-part. The minimum distance between the surface of the packaging layer distant from the first sub-part and the first sub-part is greater than the minimum distance between the surface of the packaging layer distant from the side surface of the first sub-part and the first sub-part. At least one blocking structure is provided on the side of the packaging layer distant from the substrate. The blocking structure at least covers the part of the packaging layer that covers the side surface of the first sub-part.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410362952.1, filed on March 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the development of display technology, display devices (such as mobile phones, laptops, and tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) displays have attracted widespread attention due to their advantages such as active illumination, wide viewing angle, high contrast, fast response, low power consumption, and ultra-thinness. Summary of the Invention

[0004] On the one hand, a display panel is provided. The display panel has a display area; the display area includes an aperture area, an isolation area and a pixel area; the isolation area is arranged between the aperture area and the pixel area. The display panel includes a substrate, a first isolation structure, a hydrophilic layer, an encapsulation layer and at least one barrier structure. The first isolation structure is arranged on the substrate; the first isolation structure is arranged in the isolation area; the first isolation structure at least partially surrounds the aperture area. The hydrophilic layer is arranged on the side of the first isolation structure away from the substrate, the hydrophilic layer is arranged in the pixel area and extends to the isolation area, the hydrophilic layer arranged in the isolation area includes a first sub-portion and a second sub-portion separated from each other, the first sub-portion is arranged on the side of the first isolation structure away from the substrate, and the second sub-portion is arranged on the side of the isolation structure away from or close to the aperture area; the hydrophilic layer includes at least one of a light-emitting functional layer and a cathode layer. The encapsulation layer is disposed on a side of the hydrophilic layer away from the substrate; the encapsulation layer is disposed in the pixel region and extends to the isolation region; the encapsulation layer covers the sidewalls of the first isolation structure, the first sub-section, and the second sub-section; the minimum distance between the surface of the encapsulation layer away from the first sub-section and the first sub-section is greater than the minimum distance between the surface of the encapsulation layer away from the side of the first sub-section and the first sub-section. The at least one barrier structure is disposed in the isolation region; the at least one barrier structure is disposed on a side of the encapsulation layer away from the substrate, the barrier structure at least covering the portion of the encapsulation layer covering the side of the first sub-section, and the barrier structure is configured to block water and oxygen.

[0005] In some embodiments, the first isolation structure includes a first isolation portion and a second isolation portion, the second isolation portion is arranged on a side of the first isolation portion away from the substrate, and both ends of the second isolation portion extend beyond the first isolation portion along the direction of the isolation region pointing to the opening region; the first sub-portion is arranged on a side of the second isolation portion away from the substrate, and the second sub-portion is arranged on a side of the first isolation portion away from or close to the opening region, and is arranged on a side of the second isolation portion close to the substrate.

[0006] In some embodiments, the display panel also includes a first insulating layer stack, which is arranged between the substrate and the hydrophilic layer; the first insulating layer stack is arranged in the pixel area and extends to the isolation area; the surface of the first insulating layer stack away from the substrate has a plurality of isolation grooves, and the plurality of isolation grooves are arranged in the isolation area, and along the direction from the isolation area to the opening area, the plurality of isolation grooves are arranged at intervals, and the isolation grooves at least partially surround the opening area, and the second sub-portion is arranged in the isolation groove; the encapsulation layer is partially arranged in the isolation groove; the boundary of the orthographic projection of the second isolation portion on the substrate is arranged within the range of the orthographic projection of the isolation groove on the substrate.

[0007] In some embodiments, the barrier structure includes at least one barrier block, which partially covers the packaging layer disposed in the isolation trench and partially covers the packaging layer disposed on a side of the first sub-portion away from the substrate.

[0008] In some embodiments, the blocking structure includes a plurality of blocking blocks. The plurality of first isolation structures are arranged at intervals along a direction from the pixel area to the opening area, and one blocking block corresponds to one isolation groove.

[0009] In some embodiments, the barrier structure includes a barrier layer, and an orthographic projection of the barrier layer on the substrate covers the isolation region.

[0010] In some embodiments, the material of the barrier layer includes metal. The display panel further includes a first barrier layer, a second barrier layer, and a fourth insulating layer. The orthographic projection of the first barrier layer on the substrate covers the isolation region. The second barrier layer is disposed on a side of the first barrier layer away from the substrate and covers the first barrier layer. The fourth insulating layer is disposed between the first barrier layer and the second barrier layer; the fourth insulating layer has a first through hole extending through the fourth insulating layer, and the second barrier layer extends into the first through hole to connect to the fourth barrier layer.

[0011] In some embodiments, the display panel further includes a multi-layer touch layer, which is arranged on a side of the packaging layer away from the substrate; the multi-layer touch layer includes a plurality of first touch electrodes and a plurality of second touch electrodes; the plurality of first touch electrodes and the plurality of second touch electrodes are arranged in the pixel area; and a layer of the barrier structure is arranged on a layer of the touch layer.

[0012] In some embodiments, one of the first touch electrode and the second touch electrode is an integral structure, and the other includes a plurality of touch sub-electrodes and a plurality of bridging portions arranged at intervals, and any two adjacent touch sub-electrodes are coupled by at least one bridging portion; the plurality of touch sub-electrodes and the touch electrode with an integral structure are arranged on one touch layer, and the bridging portion is arranged on another touch layer.

[0013] In some embodiments, each of the first touch electrodes and each of the second touch electrodes are an integrated structure; the first touch electrodes are disposed on one touch layer, and the second touch electrodes are disposed on another touch layer.

[0014] In some embodiments, the display panel further comprises a driving circuit stack. The driving circuit stack is disposed between the substrate and the hydrophilic layer; the driving circuit stack comprises a first stack and a second stack; the first stack is disposed on a side of the second stack away from the substrate; the first stack comprises at least one source-drain conductive layer; the second isolation portion is disposed on one of the source-drain conductive layers; and the second stack comprises at least one semiconductor layer and multiple gate conductive layers.

[0015] In some embodiments, the first stack includes multiple source / drain conductive layers, with a second insulating layer disposed between adjacent source / drain conductive layers; the second stack includes multiple third insulating layers. The first isolation portion includes a first sub-isolation portion and two second sub-isolation portions, one second sub-isolation portion being at least partially disposed on a side of the first sub-isolation portion away from the opening region, and the other second sub-isolation portion being at least partially disposed on a side of the first sub-isolation portion closer to the opening region. The first sub-isolation portion is disposed within the multiple third insulating layers, and the second sub-isolation portion is disposed within a single second insulating layer.

[0016] In some embodiments, the second stacked structure further includes a plurality of third insulating layers, and the first isolation portion is disposed in the plurality of second insulating layers.

[0017] In some embodiments, the first insulating layer stack includes at least one first-type insulating layer and at least one second-type insulating layer, the first-type insulating layer being disposed on a side of the second-type insulating layer away from the substrate; the isolation trench penetrates the first-type insulating layer. The display panel further includes a plurality of blocking blocks disposed between the first-type insulating layer and the second-type insulating layer, with the orthographic projection of one blocking block on the substrate overlapping the orthographic projection of one isolation trench on the substrate; the blocking blocks are made of a different material than the first insulating layer stack.

[0018] In some embodiments, the display panel further includes a semiconductor layer, and the semiconductor layer is disposed between the substrate and the hydrophilic layer; wherein the first blocking block is disposed in the semiconductor layer.

[0019] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0021] FIG1 is a structural diagram of a display device according to some embodiments;

[0022] FIG2 is a structural diagram of a display panel according to some embodiments;

[0023] 3 is a structural diagram of a display panel including a low-temperature polysilicon semiconductor layer according to some embodiments;

[0024] 4 is a structural diagram of a display panel including a low-temperature polysilicon semiconductor layer and an oxide semiconductor layer according to some embodiments;

[0025] FIG5 is a cross-sectional view along section line DD in FIG2 ;

[0026] FIG6 is a partial enlarged view of E in FIG5 ;

[0027] FIG7 is another partial enlarged view of E in FIG5 ;

[0028] FIG8 is another partial enlarged view of E in FIG5 ;

[0029] FIG9 is another partial enlarged view of E in FIG5 ;

[0030] FIG10 is another cross-sectional view along section line DD in FIG2 ;

[0031] FIG11 is a partial enlarged view of F in FIG10 ;

[0032] FIG12 is another partial enlarged view of F in FIG10 ;

[0033] FIG13 is another partial enlarged view of F in FIG10 ;

[0034] FIG14 is another cross-sectional view along section line DD in FIG2 ;

[0035] FIG15 is another cross-sectional view along section line DD in FIG2 ;

[0036] FIG16 is a partial enlarged view of G in FIG15 ;

[0037] FIG17 is another partial enlarged view of G in FIG15 ;

[0038] FIG18 is another partial enlarged view of G in FIG15 ;

[0039] FIG19 is a structural diagram of a touch structure according to some embodiments;

[0040] FIG20 is a cross-sectional view taken along section line HH in FIG19;

[0041] FIG21 is another structural diagram of a touch structure according to some embodiments;

[0042] FIG22 is a cross-sectional view taken along section line II in FIG21;

[0043] FIG23 is another structural diagram of a touch structure according to some embodiments;

[0044] FIG24 is a cross-sectional view taken along section line JJ in FIG23 . DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0052] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0056] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] Some embodiments of the present disclosure provide a display device 1000. As shown in FIG1 , the display device 1000 may be any product or component with a display function, such as a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or a car central control screen.

[0059] The display device 1000 may be a liquid crystal display (LCD), an organic light-emitting display (OLED), a quantum dot light-emitting display (QLED), a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or an active-matrix organic light-emitting diode (AMOLED) display.

[0060] It should be noted that Micro LED refers to an LED with a size (such as length) less than 50 μm, and Mini LED refers to an LED with a size (such as length) of 50 μm to 200 μm.

[0061] The following uses an OLED display device as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited thereto, and other display devices may also be considered as long as the same technical concept is applied.

[0062] In some embodiments, as shown in FIG1 , a display device 1000 includes a display panel 100 .

[0063] For example, the display device 1000 may further include a housing 200 , a functional device 300 , a circuit board, and other electronic components. The display panel 100 , the functional device 300 , and the circuit board may be disposed within the housing 200 .

[0064] It should be noted that the functional device 300 may be a camera, an infrared sensor, a proximity sensor, an eye tracking module, a face recognition module, etc. For example, as shown in FIG1 , the functional device 300 is a camera.

[0065] As shown in FIG. 2 , the display panel 100 may be provided with a mounting hole H, and the functional device 300 may be mounted at the mounting hole H to prevent the display panel 100 from blocking the lighting of the functional device 300 .

[0066] In some embodiments, as shown in FIG2 , the display panel 100 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA. FIG2 illustrates an example in which the peripheral area BB surrounds the display area AA. The peripheral area BB is an area where no image is displayed and is configured to house display driver circuits, such as scan driver circuits and source driver circuits.

[0067] As shown in Figure 2, the display area AA includes an aperture area AA1, an isolation area AA2, and a pixel area AA3. The isolation area AA2 is located between the aperture area AA1 and the pixel area AA3. The pixel area AA3 is used for displaying images, the aperture area AA1 is used to provide the mounting hole H, and the isolation area AA2 is used to prevent water and oxygen from intruding into the pixel area AA3 from the aperture area AA1.

[0068] In some embodiments, as shown in FIG. 2 , a display panel 100 includes a substrate 10 and a plurality of sub-pixels 20 .

[0069] As shown in Figure 2, the substrate 10 extends from the pixel area AA3 to the isolation area AA2. The substrate 10 can be a flexible substrate 10 or a rigid substrate 10. The material used for the substrate 10 can include polymer resin or glass. For example, the substrate 10 may be flexible, and the material used for the substrate 10 includes a polymer resin, such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formal acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenylene sulfide granula (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). For example, the substrate 10 may be rigid, and the material used for the substrate 10 includes glass containing SiO2 as a main component.

[0070] In some embodiments, as shown in FIG3 , the display panel 100 further includes a buffer layer 30 disposed between the substrate 10 and the plurality of sub-pixels 20. The buffer layer 30 may be made of inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON), and silicon oxide (SiOx, x>0). The buffer layer 30 provides a good foundation for thin film formation when thin films are fabricated on the substrate 10.

[0071] As shown in FIG. 2 , a plurality of sub-pixels 20 are disposed on the substrate 10 , and the plurality of sub-pixels 20 are disposed in the pixel area AA3 .

[0072] The plurality of sub-pixels 20 may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color. The first, second, and third colors are three primary colors. For example, the first color is red, the second color is blue, and the third color is green. This is not specifically limited in the present embodiment.

[0073] For example, as shown in FIG2 , the plurality of sub-pixels 20 may be arranged in multiple rows and columns, where each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0074] 3 and 4 , each sub-pixel 20 includes a pixel circuit 21 and a light-emitting device 22 disposed on a substrate 10. The pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (Capacitor, C for short).

[0075] The transistor 211 used in the circuit provided in the embodiment of the present disclosure may be a thin film transistor, a field effect transistor or other switching devices with the same characteristics. The embodiments of the present disclosure are described using a thin film transistor as an example.

[0076] Exemplarily, the transistor 211 is, for example, an oxide thin film transistor. The oxide thin film transistor has a high carrier mobility, which can improve the response speed of the transistor 211 .

[0077] 3 and 4 , the transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114. The source 2112 and the drain 2113 are respectively in contact with the active portion 2111. The storage capacitor 212 includes two plates disposed opposite to each other.

[0078] It should be noted that the source 2112 and the drain 2113 can be interchanged, that is, 2112 in FIG. 3 represents the drain, and 2113 represents the source.

[0079] The pixel circuit 21 may have various structures, which can be selected based on actual needs. For example, the pixel circuit 21 may have a structure such as "2T1C," "3T1C," "6T1C," "7T1C," "6T2C," or "7T2C." "T" represents the transistor 211, and the number preceding "T" represents the number of transistors 211. "C" represents the storage capacitor 212, and the number preceding "C" represents the number of storage capacitors 212.

[0080] As shown in Figures 3 and 4, the light-emitting device 22 includes an anode 221, a light-emitting functional layer 222, and a cathode 223. The anode 221 can be electrically connected to the source 2112 or drain 2113 of the multiple transistors 211 serving as the driving transistor. Figures 3 and 4 illustrate the electrical connection between the anode 221 and the drain 2113 of the transistor 211. The material of the anode 221 includes indium tin oxide (ITO). The material of the cathode 223 includes a hydrophilic material, for example, indium tin oxide.

[0081] In some examples, multiple cathodes 223 are connected to form a continuous layer structure, that is, multiple cathodes 223 are connected to form a whole cathode layer. In this case, the cathode layer can extend to the isolation area AA2.

[0082] The light-emitting functional layer 222 may include only a light-emitting layer, or may include a common layer in addition to the light-emitting layer, and the material of the common layer includes a hydrophilic material.

[0083] It should be understood that the common layer includes at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), a hole transport layer (HTL), a hole injection layer (HIL), and an electron blocking layer (EBL).

[0084] In some examples, the light-emitting functional layer 222 further includes a common layer, and the common layer may extend to the isolation area AA2 , that is, the light-emitting functional layer 222 also extends to the isolation area AA2 .

[0085] In some embodiments, as shown in Figures 3 and 4 , the display panel 100 further includes an encapsulation layer 40, which is disposed in the pixel area AA3 and extends to the isolation area AA2. The encapsulation layer 40 is disposed on a side of the plurality of light-emitting devices 22 away from the substrate 10. The encapsulation layer 40 is used to encapsulate the light-emitting devices 22 and improve the service life of the light-emitting devices 22. The encapsulation layer 40 may be an encapsulation film or an encapsulation substrate, which is not specifically limited in the present embodiment.

[0086] Exemplarily, the encapsulation layer 40 may include a single encapsulation film, or may include two or more superimposed encapsulation films. For example, as shown in Figures 3 and 4, the encapsulation layer 40 includes a first inorganic encapsulation layer 41, a first organic encapsulation layer 42, and a second inorganic encapsulation layer 43 superimposed in a direction perpendicular to and away from the substrate 10. The materials of the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 42 includes a polymer resin, such as polyimide.

[0087] The following takes the encapsulation layer including the first inorganic encapsulation layer 41, the first organic encapsulation layer 42 and the second inorganic encapsulation layer 43 as an example to schematically illustrate some embodiments of the present disclosure, but the implementation of the present disclosure is not limited to this, and other encapsulation layers can also be considered as long as the same technical concept is applied.

[0088] In some embodiments, as shown in Figures 2 and 5, the display panel 100 further includes at least one retaining wall structure 50, which is disposed in the isolation area AA2 and surrounds the aperture area AA1. The retaining wall structure 50 is used to block water and oxygen, thereby improving the water and oxygen barrier properties of the encapsulation layer 40. During the preparation of the first organic encapsulation layer 42, the retaining wall structure 50 is also used to block the first organic encapsulation layer 42, so that the first organic encapsulation layer 42 is located on the side of the retaining wall structure 50 away from the aperture area AA1, thereby allowing the second inorganic encapsulation layer 43 to completely cover the first organic encapsulation layer 42, thereby improving the problem of water and oxygen corroding the first organic encapsulation layer 42 and causing the first organic encapsulation layer 42 to fail. That is to say, the portion of the encapsulation layer 40 located on the side of the retaining wall structure 50 away from the opening area AA1 includes a first inorganic encapsulation layer 41, a first organic encapsulation layer 42 and a second inorganic encapsulation layer 43 that are stacked together, and the portion of the encapsulation layer 40 located on the side of the retaining wall structure 50 close to the opening area AA1 includes a first inorganic encapsulation layer 41 and a second inorganic encapsulation layer 43 that are stacked together, and the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43 are in contact.

[0089] In some embodiments, as shown in Figures 2 and 5 to 18, the display panel 100 further includes a first isolation structure 60. As shown in Figure 2, the first isolation structure 60 is disposed in the isolation area AA2. The first isolation structure 60 is disposed on a side of the retaining wall structure 50 near the opening area AA1. As shown in Figures 5 to 18, the first isolation structure 60 is disposed between the substrate 10 and the hydrophilic layer 1. In the case where only the cathode layer extends to the isolation area AA2, the hydrophilic layer 1 includes only the cathode layer. In the case where only the light-emitting functional layer 222 extends to the isolation area AA2, the hydrophilic layer 1 includes only the light-emitting functional layer 222. In the case where both the cathode layer and the light-emitting functional layer 222 extend to the isolation area AA2, the hydrophilic layer 1 includes the cathode layer and the light-emitting functional layer 222.

[0090] As shown in Figures 6, 7, 8, 9, 11, 12, 13, 16, 17 and 18, the hydrophilic layer 1 includes a first sub-portion 11 and a second sub-portion 12 that are isolated from each other. The first sub-portion 11 is arranged on the side of the first isolation structure 60 away from the substrate 10, and the second sub-portion 12 is arranged on the side of the first isolation structure 60 away from or close to the opening area AA1, that is, the hydrophilic layer 1 is disconnected at the first isolation structure 60, which can reduce the risk of water and oxygen invading the pixel area AA3 from the opening area AA1 through the hydrophilic layer 1, thereby improving the problem of black spots at the edge of the hole (English: Growing Dark Spot In Hole, abbreviated as: GDSH) generated by the display panel 100.

[0091] It can be understood that the display panel 100 also includes a second isolation structure 150, which is arranged in the isolation area AA2. The second isolation structure 150 is arranged on the side of the retaining wall structure 50 away from the hole area AA1. The second isolation structure 150 can have the same structure as the first isolation structure 60.

[0092] In some examples, as shown in Figures 6, 7, 8, 9, 11, 12, 13, 16, 17, and 18, the first isolation structure 60 includes a first isolation portion 61 and a second isolation portion 62. The second isolation portion 62 is disposed on a side of the first isolation portion 61 away from the substrate 10, and points along the isolation area AA2 toward the opening area AA1. Both ends of the second isolation portion 62 extend beyond the first isolation portion 61. The first sub-portion 11 is disposed on a side of the second isolation portion 62 away from the substrate 10, that is, the second sub-portion 12 is disposed on a side of the first isolation portion 61 away from or close to the opening area AA1, and is disposed on a side of the second isolation portion 62 close to the substrate 10.

[0093] 6, 7, 8, 9, 11, 12, 13, 16, 17, and 18, the encapsulation layer 40 covers the sidewalls of the first isolation structure 60, the first sub-section 11, and the second sub-section 12. Thus, the encapsulation layer 40 can reduce the risk of water and oxygen intruding into the first sub-section 11 and the second sub-section 12, thereby reducing the risk of water and oxygen intruding into the first sub-section 11 and the second sub-section 12.

[0094] 6 , 7 , 8 and 9 , when the first isolation structure 60 includes the first sub-portion 11 and the second sub-portion 12 , the encapsulation layer 40 covers the sidewalls of the first sub-portion 11 and the second sub-portion 12 .

[0095] In the related art, the minimum distance between the surface of the encapsulation layer away from the first sub-section and the first sub-section is greater than the minimum distance between the surface of the encapsulation layer away from the side of the first sub-section and the first sub-section, that is, the encapsulation layer at the side of the first sub-section is thinner, and water oxygen will enter the first sub-section through the encapsulation layer, causing oxidation of the first sub-section and the display panel to produce the GDSH problem.

[0096] To address the above technical issues, as shown in Figures 6, 7, 8, 9, 11, 12, 13, 16, 17, and 18, some embodiments of the present disclosure provide a display panel 100, which further includes at least one barrier structure 70. For example, as shown in Figures 6, 7, 9, 11, 12, 16, 17, and 18, the display panel 100 includes a single barrier structure 70; for another example, as shown in Figures 8 and 13, the display panel 100 includes two barrier structures 70.

[0097] As shown in Figures 6, 7, 8, and 9, at least one barrier structure 70 (all barrier structures 70) is disposed in isolation area AA2. At least one barrier structure 70 is disposed on a side of the encapsulation layer 40 away from the substrate 10. The barrier structure 70 covers at least the portion of the encapsulation layer 40 that covers the side surface of the first sub-section 11. The barrier structure 70 is configured to block water and oxygen.

[0098] Placed in this manner, the barrier structure 70 can block water and oxygen from invading the first sub-portion 11 from the portion of the encapsulation layer 40 covering the side of the first sub-portion 11, thereby reducing the risk of oxidation of the first sub-portion 11 and improving the problem of GDSH generated in the display panel 100 due to oxidation of the first sub-portion 11.

[0099] In some embodiments, as shown in Figures 11, 12, and 13, the display panel 100 further includes a first insulating layer stack 80. The first insulating layer stack 80 is disposed between the substrate 10 and the hydrophilic layer 1. The surface of the first insulating layer stack 80 away from the substrate 10 has a plurality of isolation trenches 81. The plurality of isolation trenches 81 are disposed in the isolation area AA2 and are spaced apart from each other in the direction from the isolation area AA2 to the opening area AA1. The isolation trenches 81 at least partially surround the opening area AA1, that is, the first insulating layer stack 80 between two adjacent isolation trenches 81 forms a first isolation portion 61. The boundary of the orthographic projection of the second isolation portion 62 on the substrate 10 is disposed within the range of the orthographic projection of the isolation trench 81 on the substrate 10. The second sub-portion 12 is disposed within the isolation trench 81. The encapsulation layer 40 is partially disposed within the isolation trench 81.

[0100] In some embodiments, as shown in Figures 3 and 4, the display panel 100 further includes a driving circuit stack 90, which includes a first stack 91 and a second stack 92. The first stack 91 includes at least one source-drain conductive layer SD, and the source electrode 2112 and the drain electrode 2113 described above are disposed in the at least one source-drain conductive layer SD. For example, the first stack 91 includes one, two, three, or four source-drain conductive layers SD. The second stack 92 includes at least one semiconductor layer ACT and multiple gate conductive layers GT. For example, the second stack 92 includes one or two semiconductor layers ACT, and the second stack 92 includes two or three gate conductive layers GT. The active portion 2111 described above is disposed in the at least one semiconductor layer ACT, and the gate electrode 2114 is disposed in the multiple gate conductive layers GT.

[0101] In addition, the second isolation portion 62 is disposed in a source-drain conductive layer SD, so that the second isolation portion 62 can be formed at the same time as the source-drain conductive layer SD is formed.

[0102] Exemplarily, the source electrode 2112 is disposed in the conductive layer where the second isolation portion 62 is located. In this case, the source electrode and the second isolation portion 62 can be formed through a single patterning process, thereby reducing the manufacturing cost of the display panel 100. Alternatively, exemplarily, the drain electrode 2113 is disposed in the source-drain conductive layer SD where the second isolation portion 62 is located. In this case, the drain electrode and the second isolation portion 62 can be formed through a single patterning process.

[0103] In some embodiments, as shown in FIG3 and FIG4 , the first stack 91 includes multiple source / drain conductive layers SD, with a second insulating layer 93 (e.g., a planarization layer) disposed between two adjacent source / drain conductive layers SD. The second stack 92 structure includes multiple third insulating layers 94 (e.g., a gate insulating layer GI and an interlayer insulating layer ILD), and a third insulating layer 94 is disposed between each adjacent two layers of at least one semiconductor layer ACT and multiple gate conductive layers GT.

[0104] On this basis, as shown in Figures 11, 12, and 13, the first isolation portion 61 includes a first sub-isolation portion 611 and two second sub-isolation portions 612. One second sub-isolation portion 612 is at least partially disposed on a side of the first sub-isolation portion 611 away from the aperture area AA1, and the other second sub-isolation portion 612 is at least partially disposed on a side of the first sub-isolation portion 611 closer to the aperture area AA1. The first sub-isolation portion 611 is disposed within multiple layers of the third insulating layer 94, while the second sub-isolation portion 612 is disposed within a single layer of the second insulating layer 93. In this case, the second insulating layer 93 where the second isolation portion 62 is located and the multiple layers of the third insulating layer 94 form a first insulating layer stack 80.

[0105] 3 and 4 , the second stack 92 includes multiple third insulating layers 94. As shown in FIG9 , the first isolation portion 61 is disposed in the multiple third insulating layers 94. In this case, the multiple third insulating layers 94 form the first insulating layer stack 80.

[0106] The first stacked layer 91 , the second stacked layer 92 , the second insulating layer 93 and the third insulating layer 94 are described below by way of example in conjunction with the film layers included in the driving circuit stacked layer 90 .

[0107] In some embodiments, as shown in FIG3 , the pixel circuit 21 includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor. Here, along a direction perpendicular to and away from the substrate 10, the driving circuit stack 90 includes, in sequence, a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first interlayer insulating layer ILD1, an oxide semiconductor layer ACT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a second interlayer insulating layer ILD2, a first source-drain conductive layer SD1, a first planar layer PLN1, a second source-drain conductive layer SD2, and a second planar layer PLN2.

[0108] In this case, the first stack 91 includes a first source-drain conductive layer SD1 , a first planarization layer PLN1 , a second source-drain conductive layer SD2 , and a second planarization layer PLN2 , and the first planarization layer PLN1 is the second insulating layer 93 .

[0109] The second stack 92 includes a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first interlayer insulating layer ILD1, an oxide semiconductor layer ACT2, a third gate insulating layer GI3, a third gate conductive layer GT3, and a second interlayer insulating layer ILD2.

[0110] The first gate insulating layer GI1 , the second gate insulating layer GI2 , the first interlayer insulating layer ILD1 , the third gate insulating layer GI3 , and the second interlayer insulating layer ILD2 form a multi-layer third insulating layer 94 .

[0111] When the second sub-isolating portion 612 is provided in a single layer of the second insulating layer 93, the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, the second interlayer insulating layer ILD2, and the first planarization layer PLN1 form a first insulating layer stack 80. When the second isolating portion 62 is provided in a plurality of layers of the third insulating layer 94, the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 form a first insulating layer stack 80.

[0112] In other embodiments, as shown in FIG4 , the pixel circuit 21 includes only a low-temperature polysilicon thin film transistor. In this case, the driving circuit stack 90 is sequentially stacked along a direction perpendicular to and away from the substrate 10, including a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first interlayer insulating layer ILD1, a first source-drain conductive layer SD1, a first planarization layer PLN1, a second source-drain conductive layer SD2, and a second planarization layer PLN2.

[0113] In this case, the first stack 91 includes a first source-drain conductive layer SD1 , a first planarization layer PLN1 , a second source-drain conductive layer SD2 , and a second planarization layer PLN2 , and the first planarization layer PLN1 is the second insulating layer 93 .

[0114] The second stack 92 includes a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2 and a first interlayer insulating layer ILD1, and the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD form a multi-layer third insulating layer 94.

[0115] In the case where the second sub-isolating portion 612 is provided in a single layer of the second insulating layer 93, the first planarization layer PLN1, the first gate insulating layer GI1, the second gate insulating layer GI2, and the first interlayer insulating layer ILD1 form a first insulating layer stack 80. In the case where the second isolating portion 62 is provided in a plurality of layers of the third insulating layer 94, the first gate insulating layer GI1, the second gate insulating layer GI2, and the first interlayer insulating layer ILD1 form a first insulating layer stack 80.

[0116] In some embodiments, as shown in Figures 6, 7 and 8, the blocking structure 70 includes at least one blocking block 71, which partially covers the packaging layer 40 arranged in the isolation groove 81 and partially covers the packaging layer 40 arranged on the side of the first isolation structure 60 away from the substrate 10.

[0117] Illustratively, from pixel area AA3 toward aperture area AA1, the barrier block 71 includes a first barrier portion 711, a second barrier portion 712, a third barrier portion 713, a fourth barrier portion 714, and a fifth barrier portion 715, which are sequentially connected. The first barrier portion 711 covers the portion of the encapsulation layer 40 disposed on the side of the first sub-portion 11, which is located away from the aperture area AA1, of the two adjacent first sub-portions 11, away from the substrate 10. The second barrier portion 712 is perpendicular to the substrate 10 and covers the encapsulation layer 40 disposed within the isolation trench 81 and located near the side of the first sub-portion 11 near the aperture area AA1 and the side of the first isolation structure 60 near the aperture area AA1. The third barrier portion 713 covers the encapsulation layer 40, which is parallel to the substrate 10 and disposed within the isolation trench 81 and located on the side of the second sub-portion 12 away from the substrate 10. The fourth barrier portion 714 is perpendicular to the substrate 10 and covers the encapsulation layer 40 disposed within the isolation trench 81 and located near the side of the first sub-section 11 away from the aperture area AA1 and the side of the first isolation structure 60 away from the aperture area AA1. The fifth barrier portion 715 partially covers the encapsulation layer 40 disposed on the side of the first sub-section 11 of the two adjacent first sub-sections 11 near the aperture area AA1 away from the substrate 10.

[0118] On this basis, as shown in FIG5 , the barrier structure 70 includes a plurality of barrier blocks 71, which are arranged in a direction from the pixel area AA3 toward the aperture area AA1. The plurality of first isolation structures 60 are arranged at intervals, with one barrier block 71 corresponding to one isolation trench 81. For example, a barrier block 71 partially covers the encapsulation layer 40 disposed within an isolation trench 81 and partially covers the encapsulation layer 40 disposed on the side of the first isolation structure 60 away from the substrate 10.

[0119] 8 , the display panel 100 includes a first barrier structure 701, a second barrier structure 702, and a fourth insulating layer 110. The second barrier structure 702 is disposed on a side of the first barrier structure 701 away from the substrate 10. The fourth insulating layer 110 is disposed between the first barrier structure 701 and the second barrier structure 702.

[0120] The first barrier structure 701 includes a first barrier block 7001, and the second barrier structure includes a second barrier block 7002. The first barrier block 7001 partially covers the encapsulation layer 40 disposed within the isolation trench 81 and partially covers the encapsulation layer 40 disposed on the side of the first isolation structure 60 away from the substrate 10. The second barrier block 7002 covers the portion of the fourth insulating layer 110 that covers the first barrier block 7001.

[0121] In other embodiments, as shown in Figures 10, 11, 12 and 13, the barrier structure 70 includes a barrier layer 72, and the orthographic projection of the barrier layer 72 on the substrate 10 covers the isolation area AA2. That is, the barrier layer 72 is a continuous whole layer structure.

[0122] In some examples, the material of the barrier layer 72 includes metal, for example, the material of the barrier layer 72 includes copper or silver.

[0123] Based on the above embodiment, as shown in FIG13 , the display panel 100 includes a first barrier layer 721, a second barrier layer 722, and a fourth insulating layer 110. The first barrier layer 721 is disposed on a side of the second barrier layer 722 close to the substrate 10. The fourth insulating layer 110 is disposed between the first barrier layer 721 and the second barrier layer 722.

[0124] The orthographic projection of the first barrier layer 721 on the substrate 10 covers the isolation area AA2. The second barrier layer 722 is disposed on a side of the first barrier layer 721 facing away from the substrate 10 and covers the first barrier layer 721. The fourth insulating layer 110 is disposed between the first and second barrier layers 721, 722. As shown in FIG14 , the fourth insulating layer 110 has a first through hole 111 extending through the fourth insulating layer 110. The second barrier layer 722 extends into the first through hole 111 and connects to the fourth barrier layer 72. This ensures electrical connection between the first and second barrier layers 721, 722, reducing the risk of static electricity generation between the first and second barrier layers 721, 722.

[0125] In some embodiments, as shown in Figures 11, 12 and 13, the first insulating layer stack 80 includes at least one first-type insulating layer 82 and at least one second-type insulating layer 83, the first-type insulating layer 82 is arranged on the side of the second-type insulating layer 83 away from the substrate 10, and the isolation groove 81 passes through the first-type insulating layer 82.

[0126] In addition, the display panel 100 further includes a plurality of blocking blocks 120 . The blocking blocks 120 are disposed between the first type insulating layer 82 and the second type insulating layer 83 , and the orthographic projection of one blocking block 120 on the substrate 10 covers the orthographic projection of one isolation trench 81 on the substrate 10 .

[0127] In this way, in the process of forming the isolation groove 81 by the etching process, the material of the blocking block 120 is different from the material of the first insulating layer stack 80, so that the etching gas or etching liquid can stop when it etches to the blocking block 120, thereby reducing the difference in the equal depth of multiple isolation grooves 81, which is beneficial to improving the force uniformity at the isolation groove 81.

[0128] In some embodiments, the display panel 100 further includes a semiconductor layer ACT disposed between the substrate 10 and the hydrophilic layer 1. The first blocking blocks 120 are disposed in the semiconductor layer ACT. Forming the blocking blocks 120 simultaneously with the semiconductor layer ACT can reduce the number of steps required to manufacture the display panel 100 and lower the manufacturing cost of the display panel 100.

[0129] In some examples, as shown in FIG. 3 , pixel circuit 21 includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor.

[0130] Exemplarily, the blocking block 120 is disposed in the low-temperature polysilicon semiconductor layer ACT1. In this case, the display panel 100 further includes a buffer layer 30. When the second sub-isolating portion 612 is disposed in a second insulating layer 93, the buffer layer 30 is the first type insulating layer 82, and the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, the second interlayer insulating layer ILD2, and the first planarizing layer PLN1 are the second type insulating layer 83.

[0131] When the first isolation portion 61 is arranged in the multi-layer third insulating layer 94, the buffer layer 30 is the first type insulating layer 82, and the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 are the second type insulating layer 83.

[0132] Alternatively, for example, the blocking block 120 is provided in the oxide semiconductor layer ACT2. In this case, the display panel 100 may not include the buffer layer 30. When the second sub-isolating portion 612 is provided in a second insulating layer 93, the first gate insulating layer GI1, the second gate insulating layer GI2, and the first interlayer insulating layer ILD1 are the first type insulating layer 82. The third gate insulating layer GI3, the second interlayer insulating layer ILD2, and the first planarizing layer PLN1 are the second type insulating layer 83.

[0133] When the first isolation portion 61 is disposed in the multilayer third insulating layer 94, the first gate insulating layer GI1, the second gate insulating layer GI2 and the first interlayer insulating layer ILD1 are the first type insulating layer 82. The third gate insulating layer GI3 and the second interlayer insulating layer ILD2 are the second type insulating layer 83.

[0134] As shown in FIG. 4 , in other examples, the pixel circuit 21 only includes a low-temperature polysilicon thin film transistor, and the blocking block 120 is disposed in the low-temperature polysilicon semiconductor layer ACT1 . In this case, the display panel 100 further includes a buffer layer 30 .

[0135] When the second sub-isolating portion 612 is provided in a single layer of the second insulating layer 93, the buffer layer 30 is the first type insulating layer 82, and the first gate insulating layer GI1, the second gate insulating layer GI2, the first planarization layer PLN1, and the interlayer insulating layer ILD are the first type insulating layer 82. When the second isolating portion 62 is provided in multiple layers of the third insulating layer 94, the buffer layer 30 is the first type insulating layer 82, and the first gate insulating layer GI1, the second gate insulating layer GI2, and the first planarization layer PLN1 are the second type insulating layer 83.

[0136] It is understandable that the blocking block 120 may also be provided in the first gate conductive layer GT1 , the second gate conductive layer GT2 , or the third gate conductive layer GT3 .

[0137] 15 , 16 , 17 and 18 , the first isolation structure 60 is disposed on a side of the third insulating layer 94 of the driving circuit stack 90 away from the substrate 10 . That is, the third insulating layer 94 is not part of the first isolation structure 60 .

[0138] In some examples, as shown in FIG. 16 , the first isolation portion 61 is disposed in the first planarization layer PLN1 , and the second isolation portion 62 is disposed in the second source-drain conductive layer SD2 .

[0139] In other examples, as shown in FIG. 17 , the first isolation portion 61 and the second isolation portion 62 are both disposed in the first planarization layer PLN1 or the second planarization layer PLN2 .

[0140] In some other examples, as shown in FIG. 18 , the first isolation portion 61 is disposed in the first source-drain conductive layer SD1 , and the second isolation portion 62 is disposed in the second source-drain conductive layer SD2 .

[0141] In some embodiments, the display device further includes a touch structure 130 . The touch structure 130 may be disposed on the display side of the display panel 100 , or the touch structure 130 may be disposed within the display panel 100 .

[0142] The following uses the touch structure 130 disposed in the display panel 100 as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and other touch structures 130 can also be considered to be disposed on the display side of the display panel 100, as long as the same technical concept is applied.

[0143] At this time, as shown in FIG3 , the touch structure 130 is disposed on a side of the encapsulation layer 40 away from the substrate 10. As shown in FIG19 , FIG20 , FIG21 , FIG22 , FIG23 , and FIG24 , the touch structure 130 includes a multi-layer touch layer 131. That is, the display panel 100 also includes a multi-layer touch layer 131. The multi-layer touch layer 131 includes a plurality of first touch electrodes 1311 and a plurality of second touch electrodes 1312. The plurality of first touch electrodes 1311 and the plurality of second touch electrodes 1312 are disposed in the pixel area AA3. Each first touch electrode 1311 is intersected with a plurality of second touch electrodes 1312, and each second touch electrode 1312 is intersected with a plurality of first touch electrodes 1311. The plurality of first touch electrodes 1311 and the plurality of second touch electrodes 1312 are insulated from each other.

[0144] The first touch electrode 1311 may be a touch transmitting electrode (Transmit Tx, Tx for short), and the second touch electrode 1312 may be a touch receiving electrode (Receive, Rx for short). Alternatively, the first touch electrode 1311 may be a receiving electrode Rx, and the second touch electrode 1312 may be a transmitting electrode Tx, which is not limited in some embodiments of the present disclosure.

[0145] On this basis, as shown in the figure, a barrier structure 70 is disposed in a touch layer 131. In this way, the barrier structure 70 is formed at the same time as the touch layer 131, thereby reducing the number of steps in manufacturing the display panel 100.

[0146] In some embodiments, as shown in Figures 19 to 24 , the display panel 100 includes a first touch layer 1301, a second touch layer 1302, and a touch insulation layer 140. The first touch layer 1301 is disposed on a side of the second touch layer 1302 close to the encapsulation layer 40, and the touch insulation layer 140 is disposed between the first touch layer 1301 and the second touch layer 1302.

[0147] When the display panel 100 includes a barrier structure 70, as shown in Figures 6 and 11 , the barrier structure 70 is disposed in the first touch layer 1301. As shown in Figures 7 and 12 , the barrier structure 70 is disposed in the second touch layer 1302. In this case, the aforementioned touch insulation layer 140 is disposed between the barrier structure 70 and the encapsulation layer 40.

[0148] 8 , when the display panel 100 includes two barrier structures 70 , the first barrier structure 701 is disposed in the first touch layer 1301 , and the second barrier structure 702 is disposed in the second touch layer 1302 .

[0149] In some embodiments, as shown in Figures 19, 21, and 23, each first touch electrode 1311 and each second touch electrode 1312 includes multiple sequentially connected block-shaped portions. The planar shape of each block-shaped portion (i.e., the outline of its orthographic projection on the substrate 10) can be, for example, a diamond. In this case, four adjacent block-shaped electrodes are located around the intersection of the two blocks.

[0150] In some embodiments, as shown in FIG19 , FIG21 , and FIG23 , each first touch electrode 1311 extends along a first direction X, and the plurality of first touch electrodes 1311 are sequentially arranged in a direction perpendicular to the second direction Y. Each second touch electrode 1312 extends along the second direction Y, and the plurality of second touch electrodes 1312 are sequentially arranged in the first direction X, and an angle θ between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°.

[0151] For example, the angle θ between the first direction X and the second direction Y can be one of 10°, 15°, 30°, 45°, 60°, 75°, and 90°. Figures 19, 21, and 23 illustrate an example where the angle θ between the first direction X and the second direction Y is 90° (i.e., the first direction X and the second direction Y are perpendicular to each other). In this case, each first touch electrode 1311 extends horizontally, and multiple first touch electrodes 1311 are arranged in sequence vertically. Each second touch electrode 1312 extends vertically, and multiple second touch electrodes 1312 are arranged in sequence horizontally.

[0152] In some embodiments, one of the first touch electrode 1311 and the second touch electrode 1312 is an integral structure, and the other includes a plurality of touch sub-electrodes and a plurality of bridging portions arranged at intervals, and any two adjacent touch sub-electrodes are coupled by at least one bridging portion; the plurality of touch sub-electrodes and the touch electrode with an integral structure are arranged on one touch layer 131, and the bridging portion is arranged on another touch layer 131.

[0153] It should be noted that “one of the first touch electrode 1311 and the second touch electrode 1312 is an integrated structure” means that all parts of one of the first touch electrode 1311 and the second touch electrode 1312 are located in the same layer and are directly connected together.

[0154] In some examples, as shown in FIG21 , each first touch electrode 1311 is a one-piece structure. Each second touch electrode 1312 includes a plurality of second touch sub-electrodes 1031 and a plurality of second bridge portions 1032 spaced apart from each other, with each adjacent second touch sub-electrodes 1031 coupled via at least one second bridge portion 1032. All second touch sub-electrodes 1031 and all first touch electrodes 1311 are disposed in the same layer, and all second bridge portions 1032 are disposed in the same layer. In this case, each second bridge portion 1032 is disposed across a first touch electrode 1311.

[0155] At this time, when the display panel 100 includes a barrier structure 70 , the barrier structure 70 may be provided on the touch layer 131 where the first touch electrodes 1311 are located or on the conductive layer where the second bridge portions 1032 are located.

[0156] When the display panel 100 includes a first touch layer 1301 and a second touch layer 1302 , the second touch sub-electrode 1031 and the first touch electrode 1311 are disposed on the first touch layer 1301 , and the second bridge portion 1032 is disposed on the second touch layer 1302 .

[0157] In other examples, as shown in FIG23 , each second touch electrode 1312 is an integral structure. Each first touch electrode 1311 includes a plurality of first touch sub-electrodes 1033 and a plurality of first bridge portions 1034 spaced apart from each other, and each adjacent two first touch sub-electrodes 1033 are coupled via at least one first bridge portion 1034. All first touch sub-electrodes 1033 and all second touch electrodes 1312 are arranged in the same layer, and all first bridge portions 1034 are arranged in the same layer. In this case, each first bridge portion 1034 is arranged across a second touch electrode 1312.

[0158] At this time, when the display panel 100 includes a barrier structure 70 , the barrier structure 70 may be provided on the touch layer 131 where the second touch electrode 1312 is located or on the conductive layer where the first bridge portion 1034 is located.

[0159] When the display panel 100 includes a first touch layer 1301 and a second touch layer 1302 , the first touch sub-electrodes 1033 and the second touch electrodes 1312 are disposed on the first touch layer 1301 , and the first bridge portions 1034 are disposed on the second touch layer 1302 .

[0160] In other embodiments, as shown in FIG. 19 , each first touch electrode 1311 and each second touch electrode 1312 are an integral structure; the first touch electrodes 1311 are disposed on one touch layer 131 , and the second touch electrodes 1312 are disposed on another touch layer 131 .

[0161] In this case, when the display panel 100 includes a barrier structure 70, the barrier structure 70 can be disposed in the touch layer 131 where the first touch electrode 1311 is located, or in the touch layer 131 where the second touch electrode 1312 is located. When the display panel 100 includes a first touch layer 1301 and a second touch layer 1302, the first touch electrode 1311 is disposed in the first touch layer 1301, and the first touch electrode 1312 is disposed in the second touch layer 1302.

[0162] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0163] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel comprising a display area; the display area includes an aperture area, an isolation area, and a pixel area; the isolation area is disposed between the aperture area and the pixel area; The display panel includes: substrate; A first isolation structure is provided on the substrate; The first isolation structure is disposed in the isolation region; The first isolation structure at least partially surrounds the opening area; a hydrophilic layer disposed on a side of the first isolation structure away from the substrate, the hydrophilic layer disposed in the pixel region and extending to the isolation region, the hydrophilic layer disposed in the isolation region comprising a first sub-portion and a second sub-portion, the first sub-portion being disposed on a side of the first isolation structure away from the substrate, and the second sub-portion being disposed on a side of the first isolation structure away from or close to the opening region; the hydrophilic layer comprising at least one of a light-emitting functional layer and a cathode layer; an encapsulation layer disposed on a side of the hydrophilic layer away from the substrate; the encapsulation layer is disposed in the pixel region and extends to the isolation region; the encapsulation layer covers the sidewalls of the first isolation structure, the first sub-portion, and the second sub-portion; a minimum distance between a surface of the encapsulation layer away from the first sub-portion and the first sub-portion is greater than a minimum distance between a surface of the encapsulation layer away from a side surface of the first sub-portion and the first sub-portion; At least one barrier structure is arranged in the isolation area; the at least one barrier structure is arranged on a side of the encapsulation layer away from the substrate, the barrier structure at least covers the part of the side surface of the first sub-section covered by the encapsulation layer, and the barrier structure is configured to block water and oxygen.

2. The display panel according to claim 1, wherein The first isolation structure includes a first isolation portion and a second isolation portion, wherein the second isolation portion is provided on a side of the first isolation portion away from the substrate and points from the isolation region to the opening region, with both ends of the second isolation portion extending beyond the first isolation portion; The first sub-portion is arranged on a side of the second isolation portion away from the substrate, and the second sub-portion is arranged on a side of the first isolation portion away from or close to the opening area, and on a side of the second isolation portion close to the substrate.

3. The display panel according to claim 2, further comprising: A first insulating layer stack is disposed between the substrate and the hydrophilic layer; the first insulating layer stack is disposed in the pixel region and extends to the isolation region; The surface of the first insulating layer stack away from the substrate has a plurality of isolation trenches, the plurality of isolation trenches are arranged in the isolation region, and are arranged at intervals along the direction from the isolation region to the opening region. The isolation trenches at least partially surround the opening region, and the second sub-portion is arranged in the isolation trenches; the encapsulation layer is partially arranged in the isolation trenches; A boundary of an orthographic projection of the second isolation portion on the substrate is set within a range of an orthographic projection of the isolation trench on the substrate.

4. The display panel according to claim 3, wherein: The barrier structure includes at least one barrier block, which partially covers the packaging layer disposed in the isolation trench and partially covers the packaging layer disposed on a side of the first sub-portion away from the substrate.

5. The display panel according to claim 4, wherein: The blocking structure includes a plurality of blocking blocks, which are arranged along a direction from the pixel area to the opening area. The plurality of first isolation structures are arranged at intervals, and one blocking block corresponds to one isolation groove. The display panel according to claim 3 , wherein: The barrier structure includes a barrier layer, and an orthographic projection of the barrier layer on the substrate covers the isolation region.

7. The display panel according to claim 6, wherein: The material of the barrier layer includes metal; The display panel further includes a first barrier layer, whose orthographic projection on the substrate covers the isolation region; a second barrier layer, disposed on a side of the first barrier layer away from the substrate and covering the first barrier layer; The fourth insulating layer is arranged between the first barrier layer and the second barrier layer; the fourth insulating layer has a first through hole penetrating the fourth insulating layer, and the second barrier layer extends into the first through hole and is connected to the fourth barrier layer.

8. The display panel according to claim 6, further comprising: a multi-layer touch layer, disposed on a side of the packaging layer away from the substrate; the multi-layer touch layer comprises a plurality of first touch electrodes and a plurality of second touch electrodes; The plurality of first touch electrodes and the plurality of second touch electrodes are disposed in the pixel area; A layer of the barrier structure is disposed on a layer of the touch layer.

9. The display panel according to claim 8, wherein: One of the first touch electrode and the second touch electrode is an integral structure, and the other includes a plurality of touch sub-electrodes and a plurality of bridging portions arranged at intervals, and any two adjacent touch sub-electrodes are coupled by at least one bridging portion; the plurality of touch sub-electrodes and the touch electrode with an integral structure are arranged on one touch layer, and the bridging portion is arranged on another touch layer.

10. The display panel according to claim 8, wherein: Each of the first touch electrodes and each of the second touch electrodes are an integrated structure; the first touch electrodes are arranged on one touch layer, and the second touch electrodes are arranged on another touch layer.

11. The display panel according to any one of claims 3 to 10, further comprising: A driving circuit stack is provided between the substrate and the hydrophilic layer; the driving circuit stack includes a first stack and a second stack; The first stack is arranged on a side of the second stack away from the substrate, the first stack includes at least one source-drain conductive layer, and the second isolation portion is arranged on one of the source-drain conductive layers; the second stack includes at least one semiconductor layer and multiple gate conductive layers.

12. The display panel according to claim 11, wherein: The first stack structure includes multiple source-drain conductive layers, and a second insulating layer is provided between two adjacent source-drain conductive layers; the second stack structure includes multiple third insulating layers; The first isolation portion includes a first sub-isolation portion and two second sub-isolation portions, one second sub-isolation portion is at least partially disposed on a side of the first sub-isolation portion away from the opening region, and the other second sub-isolation portion is at least partially disposed on a side of the first sub-isolation portion close to the opening region; The first sub-isolating portion is provided in the plurality of third insulating layers, and the second sub-isolating portion is provided in one layer of the second insulating layer.

13. The display panel according to claim 11, wherein: The second stacked structure further includes a plurality of third insulating layers, and the first isolation portion is disposed in the plurality of second insulating layers.

14. The display panel according to any one of claims 3 to 13, wherein: The first insulating layer stack comprises at least one first-type insulating layer and at least one second-type insulating layer, wherein the first-type insulating layer is arranged on a side of the second-type insulating layer away from the substrate; the isolation trench penetrates the first-type insulating layer; The display panel also includes a plurality of blocking blocks, which are arranged between the first type of insulating layer and the second type of insulating layer, and the orthographic projection of one of the blocking blocks on the substrate covers the orthographic projection of one of the isolation grooves on the substrate; wherein the material of the blocking blocks is different from the material of the first insulating layer stack.

15. The display panel according to claim 14, further comprising: a semiconductor layer disposed between the substrate and the hydrophilic layer; The first blocking block is disposed on the semiconductor layer.

16. A display device comprising the display panel according to any one of claims 1 to 15.

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