Display substrate and display device

Abstract

Provided is a display substrate. The display substrate comprises: a base substrate; and a plurality of sub-pixels, wherein each sub-pixel comprises a light-emitting element and a driving circuit, the driving circuit comprising a first transistor, a second transistor, a third transistor and a first storage capacitor; the second transistor comprises an active portion; the active portion comprises a channel portion, and a first electrode and a second electrode that are connected to two sides of the channel portion, respectively; and the channel portion comprises a first sub-channel portion, a second sub-channel portion and a channel connecting portion, the channel connecting portion being connected between the first sub-channel portion and the second sub-channel portion. The display substrate further comprises a shielding portion, wherein the layer where the shielding portion is located is located on the side of the layer where the active portion of the second transistor is located that is away from the base substrate, and the orthographic projection of the shielding portion on the base substrate at least partially overlaps the orthographic projection of the channel connecting portion on the base substrate.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, Organic Light-Emitting Diode (OLED) display devices have become a research hotspot and technology development direction for major manufacturers due to their advantages such as wide color gamut, high contrast, thin and light design, self-luminescence, and wide viewing angle.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, the display substrate including a display area and a peripheral area located around the display area, the display substrate including:

[0006] a substrate; and

[0007] a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged in the display area along a first direction and / or a second direction, the first direction intersecting the second direction, the sub-pixels comprising a light-emitting element and a driving circuit electrically connected to the light-emitting element, the driving circuit comprising a plurality of transistors and at least one storage capacitor, the plurality of transistors comprising a first transistor, a second transistor, and a third transistor, and the at least one storage capacitor comprising a first storage capacitor;

[0008] The first electrode of the first transistor is configured to receive a data signal, and the second electrode of the first transistor is electrically connected to the second plate of the first storage capacitor;

[0009] The first electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the gate of the third transistor; and

[0010] The first electrode of the third transistor is configured to receive a first power supply signal, and the gate of the third transistor is electrically connected to the first plate of the first storage capacitor;

[0011] The second transistor includes an active portion, the active portion includes a channel portion and a first electrode and a second electrode respectively connected to both sides of the channel portion, the channel portion includes a first sub-channel portion, a second sub-channel portion and a channel connecting portion, and the channel connecting portion is connected between the first sub-channel portion and the second sub-channel portion; and

[0012] The display substrate also includes a blocking portion located on the base substrate, the layer where the blocking portion is located is located on the side of the layer where the active portion of the second transistor is located away from the base substrate, and the orthographic projection of the blocking portion on the base substrate at least partially overlaps with the orthographic projection of the channel connection portion on the base substrate.

[0013] According to some exemplary embodiments, the shielding portion is configured to receive a constant voltage signal.

[0014] According to some exemplary embodiments, the plurality of transistors further include a fourth transistor, a first electrode of the fourth transistor being configured to receive a first initialization signal, a second electrode of the fourth transistor being electrically connected to a gate of the third transistor, and the shielding portion being configured to receive the first initialization signal.

[0015] According to some exemplary embodiments, the display substrate includes a first initialization signal line, the first initialization signal line transmits the first initialization signal, and the shielding portion is electrically connected to the first initialization signal line.

[0016] According to some exemplary embodiments, the display substrate includes a third conductive layer located on the base substrate and a second conductive layer located on a side of the third conductive layer away from the base substrate, and the first initialization signal line is located in the second conductive layer; and

[0017] The second conductive layer further includes a first initialization connection portion spaced apart from the first initialization signal line, the third conductive layer includes a second initialization connection portion, the second initialization connection portion being electrically connected to the first initialization signal line and the first initialization connection portion, respectively, and the first initialization connection portion being electrically connected to the first electrode of the fourth transistor;

[0018] The shielding portion is located in the third conductive layer, and the shielding portion and the second initialization connection portion are connected to form an integrated structure.

[0019] According to some exemplary embodiments, the second electrode of the light-emitting element is configured to be connected to a second power signal, and the shielding portion is configured to be connected to the second power signal.

[0020] According to some exemplary embodiments, the display substrate includes a second power signal transmission structure, the second power signal transmission structure transmits the second power signal, and the shielding portion is electrically connected to the second power signal transmission structure.

[0021] According to some exemplary embodiments, the display substrate includes a second conductive layer located on the base substrate and a first conductive layer located on a side of the second conductive layer away from the base substrate;

[0022] The second power signal transmission structure includes a second power signal line located in the first conductive layer and a second power grid line located in the second conductive layer, the second power grid line extending along the first direction, the second power signal line extending along the second direction, and the second power grid line being electrically connected to the second power signal line;

[0023] The shielding portion is located in the first conductive layer, and the shielding portion is connected to the second power signal line to form an integrated structure.

[0024] According to some exemplary embodiments, the shielding portion is configured to receive the first power signal; or

[0025] The plurality of transistors further include a fifth transistor, a first electrode of the fifth transistor being configured to receive a reference voltage signal, a second electrode of the fifth transistor being electrically connected to the second electrode of the first transistor, and the shielding portion being configured to receive the reference voltage signal; or

[0026] The plurality of transistors further include an eighth transistor, a first electrode of the eighth transistor being configured to receive a second initialization signal, a second electrode of the eighth transistor being electrically connected to the first electrode of the light-emitting element, and the shielding portion being configured to receive the second initialization signal.

[0027] According to some exemplary embodiments, the display substrate further includes a scan signal line, wherein the scan signal line is configured to connect a scan signal to the gate of the second transistor;

[0028] The orthographic projection of the shielding portion on the base substrate is spaced apart from the orthographic projection of the scanning signal line on the base substrate, and / or the orthographic projection of the shielding portion on the base substrate is spaced apart from the orthographic projection of the gate of the second transistor on the base substrate.

[0029] According to some exemplary embodiments, the display substrate includes an active layer located on the base substrate and a light-shielding layer located between the active layer and the base substrate, multiple active portions of the multiple transistors are located in the active layer, and the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projection of the multiple active portions on the base substrate.

[0030] According to some exemplary embodiments, the plurality of transistors further include a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0031] A first electrode of the fourth transistor is configured to receive a first initialization signal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor;

[0032] The first electrode of the fifth transistor is configured to receive a reference voltage signal, and the second electrode of the fifth transistor is electrically connected to the second electrode of the first transistor;

[0033] The first electrode of the sixth transistor is configured to receive a reference voltage signal, and the second electrode of the sixth transistor is electrically connected to the second electrode of the first transistor;

[0034] The first electrode of the seventh transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element;

[0035] The first electrode of the eighth transistor is configured to receive the second initialization signal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element; and

[0036] The gate of the first transistor and the gate of the second transistor are respectively configured to receive a scan signal, the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the eighth transistor are respectively configured to receive a reset signal, and the gate of the sixth transistor and the gate of the seventh transistor are respectively configured to receive a light emitting control signal;

[0037] In which, the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projections of the active portion of the first transistor, the active portion of the second transistor, the active portion of the third transistor, the active portion of the fourth transistor, the active portion of the fifth transistor, and the active portion of the eighth transistor on the base substrate, respectively.

[0038] According to some exemplary embodiments, the light shielding layer is configured to receive the first power signal.

[0039] According to some exemplary embodiments, the display substrate includes a first power signal transmission structure configured to transmit a first power signal;

[0040] The first power signal transmission structure includes a plurality of first power signal lines and a plurality of first power signal connection portions, the plurality of first power signal lines are arranged along a first direction and extend along a second direction, the first power signal connection portion is electrically connected to the first power signal lines, and the first power signal connection portion is electrically connected to the first electrode of the third transistor; and

[0041] The display substrate includes a second conductive layer located on a side of the active layer away from the base substrate and a first conductive layer located on a side of the second conductive layer away from the base substrate, the first power signal line is located on the first conductive layer, and the first power signal connection portion is located on the second conductive layer;

[0042] Wherein, the light shielding layer is electrically connected to at least one of the first power signal connection parts.

[0043] According to some exemplary embodiments, the multiple transistors further include a fifth transistor, a first electrode of the fifth transistor being connected to a reference voltage signal, a second electrode of the fifth transistor being electrically connected to the second electrode of the first transistor, and the light shielding layer being configured to be connected to the reference voltage signal.

[0044] According to some exemplary embodiments, the display substrate includes a reference voltage signal line, the reference voltage signal line is configured to transmit the reference voltage signal, the display substrate further includes a second conductive layer located on a side of the active layer away from the base substrate, the reference voltage signal line is located in the second conductive layer; and

[0045] The display substrate further includes a first insulating layer located between the light-shielding layer and the active layer, and a second insulating layer located between the active layer and the second conductive layer, the second insulating layer having a first via hole, and the first insulating layer and the second insulating layer having a second via hole, the first via hole exposing at least a portion of the first electrode of the fifth transistor, and the second via hole exposing at least a portion of the light-shielding layer, the reference voltage signal line being electrically connected to the first electrode of the fifth transistor through the first via hole, and the reference voltage signal line being electrically connected to the light-shielding layer through the second via hole;

[0046] The orthographic projection of the second via hole on the base substrate is adjacent to the orthographic projection of the first via hole on the base substrate.

[0047] According to some exemplary embodiments, the display substrate includes a driving circuit layer located on the base substrate and a light-emitting element layer located on a side of the driving circuit layer away from the base substrate, wherein each driving circuit is located in the driving circuit layer, and each light-emitting element is located in the light-emitting element layer;

[0048] The display substrate includes a second power signal transmission structure, the second power signal transmission structure is located in the driving circuit layer, the second power signal transmission structure is configured to transmit a second power signal, and the second power signal transmission structure includes at least one auxiliary electrode located in the display area; and

[0049] The light-emitting element layer includes a first electrode layer located on the side of the driving circuit layer away from the base substrate, a light-emitting functional layer located on the side of the first electrode layer away from the base substrate, and a second electrode layer located on the side of the light-emitting functional layer away from the base substrate, wherein the second electrode layer is electrically connected to the auxiliary electrode.

[0050] According to some exemplary embodiments, the driving circuit layer includes a second conductive layer located on the base substrate and a first conductive layer located on a side of the second conductive layer away from the base substrate; and

[0051] The second power signal transmission structure includes a second power signal line and a second power grid line, the second power signal line extends along the second direction, the second power signal line is located in the first conductive layer, the second power grid line extends along the first direction, the second power grid line is located in the second conductive layer, and the second power grid line is electrically connected to the second power signal line;

[0052] The auxiliary electrode is located in the first conductive layer, and the auxiliary electrode is connected to the second power signal line to form an integrated structure.

[0053] According to some exemplary embodiments, the first electrode layer includes a plurality of first electrodes arranged at intervals, and an orthographic projection of the auxiliary electrode on the base substrate is located between orthographic projections of at least two of the first electrodes on the base substrate.

[0054] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0056] FIG1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0057] FIG2 schematically shows a circuit principle diagram of a driving circuit in a display substrate according to some embodiments of the present disclosure.

[0058] FIG3 schematically illustrates a plan view of an active layer in a display substrate according to some embodiments of the present disclosure.

[0059] 4A schematically shows a plan view of an overlay of an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0060] FIG4B schematically illustrates a plan view of a second conductive layer in a display substrate according to some embodiments of the present disclosure.

[0061] 5A schematically illustrates a plan view of an overlay of an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0062] FIG5B schematically illustrates a plan view of a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0063] FIG6A schematically shows a cross-sectional view of a display substrate in which a shielding portion is electrically connected to a first power signal line according to some embodiments of the present disclosure.

[0064] FIG6B schematically illustrates a cross-sectional view of a display substrate in which a shielding portion is electrically connected to a reference voltage signal line according to some embodiments of the present disclosure.

[0065] FIG6C schematically illustrates a cross-sectional view of a display substrate in which a shielding portion is electrically connected to a second initialization signal line according to some embodiments of the present disclosure.

[0066] FIG7 schematically shows a plan view of a light shielding layer in a display substrate according to some embodiments of the present disclosure.

[0067] 8 schematically illustrates a plan view of an overlay of a light shielding layer, an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0068] FIG9 schematically shows a plan view of an overlay of a light shielding layer and a second conductive layer in a display substrate according to some embodiments of the present disclosure.

[0069] 10 schematically shows a superimposed plan view of a light shielding layer, an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0070] FIG11 schematically shows a plan view of an overlay of a light shielding layer and a second conductive layer in a display substrate according to some embodiments of the present disclosure.

[0071] 12 schematically illustrates a superimposed plan view of a light shielding layer, an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0072] FIG13 schematically shows a plan view of an overlay of a light shielding layer and a first conductive layer, a first electrode layer and a pixel defining layer in a display substrate according to some embodiments of the present disclosure.

[0073] 14 schematically illustrates a superimposed plan view of a light shielding layer, an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, a first conductive layer, and a first electrode layer in a display substrate according to some embodiments of the present disclosure.

[0074] FIG. 15 schematically shows a cross-sectional view taken along line AA′ in FIG. 13 .

[0075] Figures 16A to 16H are plan views of some film layers located in the display area of ​​a display substrate according to some exemplary embodiments of the present disclosure; wherein, Figure 16A illustrates an active layer; Figure 16B illustrates a first gate metal layer; Figure 16C illustrates a second gate metal layer; Figure 16D illustrates an interlayer insulating layer; Figure 16E illustrates a first source-drain metal layer; Figure 16F illustrates a passivation layer; Figure 16G illustrates a first planarization layer; and Figure 16H illustrates a second source-drain metal layer. DETAILED DESCRIPTION

[0076] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0077] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0078] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0079] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0080] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0081] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0082] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0083] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0084] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0085] FIG1 schematically illustrates a plan view of a display substrate according to some embodiments of the present disclosure. FIG2 schematically illustrates a circuit schematic of a driving circuit in a display substrate according to some embodiments of the present disclosure. FIG3 schematically illustrates a plan view of an active layer in a display substrate according to some embodiments of the present disclosure. FIG4A schematically illustrates a plan view of an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer superimposed on each other in a display substrate according to some embodiments of the present disclosure. FIG4B schematically illustrates a plan view of a second conductive layer in a display substrate according to some embodiments of the present disclosure.

[0086] It should be noted that in the plan views of some film layers of the display substrate provided in the embodiments of the present disclosure, the rectangular frame lines and the cross lines within the rectangular frame lines are only for illustrating the setting range of a driving circuit, and are not part of the film layer structure in the display substrate.

[0087] 1 , a display substrate includes a display area AA and a peripheral area NA located around the display area AA. The display substrate includes a base substrate 10 and a plurality of sub-pixels SP located on the base substrate 10. The plurality of sub-pixels SP are arranged within the display area AA along a first direction X and a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y. Each sub-pixel SP includes a light-emitting element and a driving circuit electrically connected to the light-emitting element. The driving circuit is configured to independently drive the light-emitting element to emit light, thereby causing the display substrate to display an image.

[0088] The light-emitting element used in the embodiments of the present disclosure may specifically be an organic light-emitting diode (OLED). For example, the light-emitting element may be an OLED with a top-emitting structure, which may emit red light, green light, blue light, or white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode of the light-emitting element is the anode of the OLED, and the second electrode is the cathode of the OLED, that is, the pixel circuit is a common cathode structure. However, the embodiments of the present disclosure are not limited to this, and according to changes in the circuit structure, the pixel circuit may also be a common anode structure.

[0089] The display substrate used in the embodiments of the present disclosure can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.

[0090] According to some exemplary embodiments, the display substrate includes a driving circuit layer located on a base substrate and a light emitting element layer located on a side of the driving circuit layer away from the base substrate. Each driving circuit is located in the driving circuit layer, and each light emitting element is located in the light emitting element layer.

[0091] For example, the driving circuit layer includes a first conductive layer located on the base substrate, a second conductive layer located between the first conductive layer and the base substrate, a third conductive layer located between the second conductive layer and the base substrate, a fourth conductive layer located between the third conductive layer and the base substrate, and an active layer located between the fourth conductive layer and the base substrate.

[0092] 2 , the driving circuit includes a plurality of transistors and at least one storage capacitor. The plurality of transistors include a first transistor T1 , a second transistor T2 , and a third transistor T3 . The at least one storage capacitor includes a first storage capacitor C1 .

[0093] The first electrode of the first transistor T1 is configured to receive the data signal Vdata, and the second electrode of the first transistor T1 is electrically connected to the second plate of the first storage capacitor C1. The first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3. The first electrode of the third transistor T3 is configured to receive the first power supply signal VDD, and the gate of the third transistor T3 is electrically connected to the first plate of the first storage capacitor C1.

[0094] 3 , the display substrate includes an active layer located on a base substrate, wherein active portions of at least a portion of the transistors are located in the active layer, including the active portions of the first transistor T1 , the second transistor T2 , and the third transistor T3 .

[0095] For example, the active portion of the first transistor T1 includes a channel portion CH1, and a first electrode S1 and a second electrode D1 connected to both sides of the channel portion CH1. The active portion of the second transistor T2 includes a channel portion CH2, and a first electrode S2 and a second electrode D2 connected to both sides of the channel portion CH2. The active portion of the third transistor T3 includes a channel portion CH3, and a first electrode S3 and a second electrode D3 connected to both sides of the channel portion CH3. The first electrode S2 of the second transistor T2 is directly connected to the second electrode D3 of the third transistor T3, and the active portion of the second transistor T2 is connected to the active portion of the third transistor T3 to form an integrated structure. The active portion of the first transistor T1 is arranged alternately with the active portion of the second transistor T2 and the active portion of the third transistor T3.

[0096] The "integrated structure" in the embodiments of the present disclosure refers to a structure in which two (or more) parts or components are formed by the same film forming process and patterned by the same composition process to be connected to each other, and their materials may be the same or different.

[0097] 4A , a first conductive portion 11 is provided in the display substrate. The first conductive portion 11 is located in the fourth conductive layer. Referring to FIG3 , an orthographic projection of the first conductive portion 11 on the base substrate partially overlaps with an orthographic projection of the active portion of the first transistor T1 on the base substrate. The overlapping portion of the first conductive portion 11 and the active portion of the first transistor T1 serves as the gate of the first transistor T1. The overlapping portion of the active portion of the first transistor T1 and the first conductive portion 11 serves as the channel CH1 of the first transistor T1. There are two overlapping areas between the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the active portion of the second transistor T2 on the substrate. The two overlapping portions of the first conductive portion 11 and the active portion of the second transistor T2 serve as the first gate and the second gate of the second transistor T2, respectively. The two overlapping portions of the active portion of the second transistor T2 and the first conductive portion 11 serve as the first sub-channel portion CH21 and the second sub-channel portion CH22 of the second transistor T2, respectively. The portion connected between the first sub-channel portion CH21 and the second sub-channel portion CH22 is the channel connection portion CH23. The first sub-channel portion CH21, the second sub-channel portion CH22 and the channel connection portion CH23 collectively serve as the channel portion CH2 of the second transistor T2.

[0098] 4A , the display substrate further includes a shielding portion 24 , which is located on a side of the active layer away from the base substrate. The orthographic projection of the shielding portion 24 on the base substrate at least partially overlaps with the orthographic projection of the channel connection portion CH23 on the base substrate.

[0099] In the display substrate provided in the embodiment of the present disclosure, the second transistor T2 serves as a threshold compensation transistor. The second transistor T2 is configured as a dual-gate dual-channel transistor. At the same time, a shielding portion is provided on the upper side of the channel connection portion of the second transistor T2 away from the base substrate. The shielding portion is used to block light directed toward the channel connection portion, thereby effectively reducing the leakage current of the second transistor T2, so that the voltage of the connection node between the gate of the third transistor and the first substrate of the first storage capacitor remains stable, thereby improving the driving effect of the driving circuit.

[0100] According to some exemplary embodiments, the shielding portion is configured to receive a constant voltage signal.

[0101] According to some exemplary embodiments, referring to FIG. 2 , the plurality of transistors further include a fourth transistor T4 , a first electrode of the fourth transistor T4 being configured to receive the first initialization signal Vinit1 , a second electrode of the fourth transistor T4 being electrically connected to the gate of the third transistor T3 , and the shielding portion 24 being configured to receive the first initialization signal Vinit1 .

[0102] According to some exemplary embodiments, referring to FIG. 4A , the display substrate includes a first initialization signal line 31 configured to transmit a first initialization signal Vinit1 , and the shielding portion 24 is electrically connected to the first initialization signal line 31 , so that the shielding portion 24 receives the first initialization signal.

[0103] According to some exemplary embodiments, with reference to FIG4A , the first initialization signal line 31 is located in the second conductive layer. The second conductive layer also includes a first initialization connection portion 371 spaced apart from the first initialization signal line, and the third conductive layer includes a second initialization connection portion 23. The second initialization connection portion 23 extends along the second direction Y, and the second initialization connection portion 23 is electrically connected to the first initialization signal line 31 and the first initialization connection portion 371, respectively. The first initialization connection portion 371 is also electrically connected to the first pole S4 of the fourth transistor T4. That is, the first initialization signal transmitted in the first initialization signal line 31 is connected to the first pole S4 of the fourth transistor T4 in sequence through the second initialization connection portion 23 and the first initialization connection portion 371. Further, with reference to FIG4B , the shielding portion 24 is provided in the third conductive layer, and in two adjacent drive circuits along the second direction Y, the shielding portion 24 located in one drive circuit is connected to the second initialization connection portion 23 located in the other drive circuit as an integrated structure.

[0104] According to some exemplary embodiments, referring to FIG. 2 , the second electrode of the light emitting element is configured to be connected to the second power signal VSS, and the shielding portion is configured to be connected to the second power signal VSS.

[0105] According to some exemplary embodiments, the display substrate includes a second power signal transmission structure configured to transmit a second power signal, and the shielding portion is electrically connected to the second power signal transmission structure so that the shielding portion receives the second power signal.

[0106] Figure 5A schematically shows a plan view of the active layer, fourth conductive layer, third conductive layer, second conductive layer and first conductive layer in a display substrate according to some embodiments of the present disclosure. Figure 5B schematically shows a plan view of the first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0107] According to some exemplary embodiments, with reference to FIG5A and FIG5B , the second power signal transmission structure includes a second power signal line 41 located in the first conductive layer and a second power grid line 36 located in the second conductive layer. The second power grid line 36 extends along a first direction X, and the second power signal line 41 extends along a second direction Y. The second power grid line 36 is electrically connected to the second power signal line 41. Furthermore, the shielding portion 24 is located in the first conductive layer, and the shielding portion 24 and the second power signal line 41 are connected to form an integral structure.

[0108] According to some exemplary embodiments, the shielding portion is configured to receive a first power signal.

[0109] FIG6A schematically shows a cross-sectional view of a display substrate in which a shielding portion is electrically connected to a first power signal line according to some embodiments of the present disclosure.

[0110] According to some exemplary embodiments, the display substrate includes a first power signal line configured to transmit a first power signal, and the shielding portion is electrically connected to the first power signal line, thereby allowing the shielding portion to receive the first power signal. For example, referring to FIG6A , the first power signal line 43 is located in the first conductive layer M1, the shielding portion 24 is located in the second conductive layer M2, and a third insulating layer L3 is disposed between the first conductive layer M1 and the second conductive layer M2. The third insulating layer L3 includes a third via V03, and the third via V03 exposes at least a portion of the shielding portion 24. The shielding portion 24 is electrically connected to the first power signal line 43 through the third via V03.

[0111] According to some exemplary embodiments, referring to FIG. 2 , the plurality of transistors further include a fifth transistor T5 , a first electrode of the fifth transistor T5 being configured to access a reference voltage signal Vref, a second electrode of the fifth transistor T5 being electrically connected to the second electrode of the first transistor T1 , and a shielding portion being configured to access the reference voltage signal Vref.

[0112] FIG6B schematically illustrates a cross-sectional view of a display substrate in which a shielding portion is electrically connected to a reference voltage signal line according to some embodiments of the present disclosure.

[0113] According to some exemplary embodiments, the display substrate includes a reference voltage signal line configured to transmit a reference voltage signal, and the shielding portion is electrically connected to the reference voltage signal line, thereby allowing the shielding portion to receive the reference voltage signal. For example, referring to FIG6B , the reference voltage signal line 34 is located in the second conductive layer M2, the shielding portion 24 is located in the third conductive layer M3, a fourth insulating layer L4 is located between the third conductive layer M3 and the second conductive layer M2, and the fourth insulating layer L4 has a fourth via V04 therein, the fourth via V04 exposing at least a portion of the shielding portion 24, and the shielding portion 24 is electrically connected to the reference voltage signal line 34 through the fourth via V04.

[0114] According to some exemplary embodiments, referring to FIG2 , the plurality of transistors further include an eighth transistor T8 , a first electrode of the eighth transistor T8 is configured to receive a second initialization signal Vinit2 , a second electrode of the eighth transistor T8 is electrically connected to a first electrode of the light emitting element, and the shielding portion is configured to receive the second initialization signal Vinit2 .

[0115] FIG6C schematically illustrates a cross-sectional view of a display substrate in which a shielding portion is electrically connected to a second initialization signal line according to some embodiments of the present disclosure.

[0116] According to some exemplary embodiments, the display substrate includes a reference second initialization signal line, the second initialization signal line configured to transmit a second initialization signal, and the shielding portion is electrically connected to the second initialization signal line, thereby allowing the shielding portion to receive the second initialization signal. For example, referring to FIG6C , the second initialization signal line 32 is located in the second conductive layer M2, the shielding portion 24 is located in the third conductive layer M3, a fourth insulating layer L4 is located between the third conductive layer M3 and the second conductive layer M2, and the fourth insulating layer L4 has a fifth via V05, the fifth via V05 exposing at least a portion of the shielding portion 24, and the shielding portion 24 is electrically connected to the second initialization signal line 32 through the fifth via V05.

[0117] According to some exemplary embodiments, referring to Figures 4A and 5A, the display substrate further includes a scan signal line 35 located in the second conductive layer. The scan signal line 35 is electrically connected to the first conductive portion 11 located in the fourth conductive layer. That is, the scan signal line 35 is electrically connected to the gate of the first transistor and the gate of the second transistor. The scan signal line 35 is configured to input a scan signal to the gate of the first transistor and the gate of the second transistor. The orthographic projection of the shielding portion 24 on the base substrate is spaced apart from the orthographic projection of the scan signal line 35 on the base substrate. The orthographic projection of the shielding portion 24 on the base substrate is spaced apart from the orthographic projection of the gate of the second transistor on the base substrate, that is, the orthographic projection of the shielding portion 24 on the base substrate is spaced apart from the orthographic projection of the first conductive portion 11 on the base substrate. The shielding portion 24 is spaced apart from the first conductive portion 11 and the scan signal line 35 to prevent the signal in the shielding portion 24 from interfering with the scan signal transmitted in the first conductive portion 11 and the scan signal line 35.

[0118] According to some exemplary embodiments, the display substrate includes a light-shielding layer located between the active layer and the base substrate, multiple active portions of the multiple transistors are located in the active layer, and the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projection of the multiple active portions on the base substrate.

[0119] According to some exemplary embodiments, referring to FIG2 and FIG3 , the plurality of transistors further include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. A first electrode S4 of the fourth transistor T4 is configured to receive a first initialization signal Vinit1, and a second electrode D4 of the fourth transistor T4 is electrically connected to the gate of the third transistor T3. A first electrode S5 of the fifth transistor T5 is configured to receive a reference voltage signal Vref, and a second electrode D5 of the fifth transistor T5 is electrically connected to the second electrode D1 of the first transistor T1. A first electrode S6 of the sixth transistor T6 is configured to receive a reference voltage signal Vref, and a second electrode D6 of the sixth transistor T6 is electrically connected to the second electrode D1 of the first transistor T1. A first electrode S7 of the seventh transistor T7 is electrically connected to the second electrode D3 of the third transistor T3, and a second electrode D7 of the seventh transistor T7 is electrically connected to the first electrode of the light-emitting element. A first electrode S8 of the eighth transistor T8 is configured to receive a second initialization signal Vinit2, and a second electrode D8 of the eighth transistor T8 is electrically connected to the first electrode of the light-emitting element. The gates of the first transistor T1 and the second transistor T2 are respectively configured to receive the scan signal Gate, the gates of the fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 are respectively configured to receive the reset signal Reset, and the gates of the sixth transistor T6 and the seventh transistor T7 are respectively configured to receive the light-emitting control signal EM.

[0120] Referring to Figure 3 , the active portion of the fourth transistor T4 includes a channel portion CH4 and a first electrode S4 and a second electrode D4 connected to either side of the channel portion CH4. The fourth transistor T4 is a dual-gate, dual-channel transistor. The channel portion CH4 of the fourth transistor T4 includes a first sub-channel portion CH41 and a second sub-channel portion CH42 spaced apart from each other. The first sub-channel portion CH41 and the second sub-channel portion CH42 are connected via a channel connector CH43. The active portion of the fifth transistor T5 includes a channel portion CH5 and a first electrode S5 and a second electrode D5 connected to either side of the channel portion CH5. The active portion of the sixth transistor T6 includes a channel portion CH6 and a first electrode S6 and a second electrode D6 connected to either side of the channel portion CH6. The active portion of the seventh transistor T7 includes a channel portion CH7 and a first electrode S7 and a second electrode D7 connected to either side of the channel portion CH7. The active portion of the eighth transistor T8 includes a channel portion CH8 and a first electrode S8 and a second electrode D8 connected to two sides of the channel portion CH8.

[0121] Figure 7 schematically illustrates a plan view of a light shielding layer in a display substrate according to some embodiments of the present disclosure. Figure 8 schematically illustrates a plan view of the light shielding layer, active layer, fourth conductive layer, third conductive layer, second conductive layer, and first conductive layer in a display substrate according to some embodiments of the present disclosure. Specifically, to clearly illustrate the connection between light shielding layer patterns in adjacent sub-pixels, Figure 8 schematically illustrates a plan view of the regions where three adjacent drive circuits are located along a first direction.

[0122] 3 and 8 , the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projections of the active portion of the first transistor T1, the active portion of the second transistor T2, the active portion of the third transistor T3, the active portion of the fourth transistor T4, the active portion of the fifth transistor T5, and the active portion of the eighth transistor T8 on the base substrate, respectively.

[0123] 7 , the light shielding layer includes a first light shielding portion 51, a second light shielding portion 52, a third light shielding portion 53, a first connecting segment 54, a second connecting segment 55, and a third connecting segment 56. The first connecting segment 54 is a straight connecting segment extending along the second direction Y, the second connecting segment 55 is a straight connecting segment extending along the second direction Y, and the third connecting segment 56 is a zigzag connecting segment extending along the second direction Y. The first light shielding portion 51 is connected between the first connecting segment 54 and the second connecting segment 55. The second light shielding portion 52 is located on one side of the second connecting segment 55 along the first direction X and is connected to the second connecting segment 55. The third light shielding portion 53 is connected between the second connecting segment 55 and the third connecting segment 56.

[0124] 7 and 8 , the orthographic projection of the first light shielding portion 51 on the substrate covers the orthographic projection of the channel portion CH5 of the fifth transistor T5 on the substrate. The orthographic projection of the first light shielding portion 51 on the substrate covers the orthographic projection of the first sub-channel portion CH41 and the second sub-channel portion CH42 of the fourth transistor T4 on the substrate. The orthographic projection of the first light shielding portion 51 on the substrate covers the orthographic projection of the channel portion CH8 of the eighth transistor T8 on the substrate. The orthographic projection of the second light shielding portion 52 on the substrate covers the orthographic projection of the channel portion CH3 of the third transistor T3 on the substrate. The orthographic projection of the third light shielding portion 53 on the substrate covers the orthographic projection of the channel portion CH1 of the first transistor T1 on the substrate. The orthographic projection of the third light shielding portion 53 on the substrate covers the orthographic projection of the channel portion CH2 of the second transistor T2 on the substrate.

[0125] By blocking the bottom of the channel portion of the first transistor T1, the channel portion of the second transistor T2, the channel portion of the third transistor T3, the channel portion of the fourth transistor T4, the channel portion of the fifth transistor T5 and the channel portion of the eighth transistor T8 through the light-shielding layer, the hysteresis effect of the third transistor serving as the driving transistor can be improved, and the driving performance of the driving circuit can be made more stable.

[0126] According to some exemplary embodiments, referring to FIG8 , the light-shielding layer patterns in different sub-pixels are interconnected to form an integrated structure, i.e., the light-shielding layer has a grid-like structure. For example, referring to FIG7 and FIG8 , in two light-shielding layer patterns of two adjacent sub-pixels along a first direction X, the first light-shielding portion 51 in one light-shielding layer pattern is directly connected to the second connecting segment 55 in the other light-shielding layer pattern, and the third light-shielding portion 53 in one light-shielding layer pattern is directly connected to the second connecting segment 55 in the other light-shielding layer pattern. In two light-shielding layer patterns of two adjacent sub-pixels along a second direction Y, the third connecting segment 56 in one light-shielding layer pattern is directly connected to the first connecting segment 54 in the other light-shielding layer pattern.

[0127] According to some exemplary embodiments, the light shielding layer is configured to receive a constant voltage signal. For example, the light shielding layer may be configured to receive a first power supply signal.

[0128] According to some exemplary embodiments, the display substrate includes a first power signal transmission structure configured to transmit a first power signal, and the light shielding layer is electrically connected to the first power signal transmission structure within the display area. Electrically connecting the light shielding layer having a grid structure to the first power signal transmission structure can effectively improve the uniformity of the distribution of the first power signal within the display area, thereby improving display uniformity.

[0129] Figure 9 schematically illustrates a plan view of a light shielding layer and a second conductive layer in a display substrate according to some embodiments of the present disclosure. Figure 10 schematically illustrates a plan view of a light shielding layer, an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0130] According to some exemplary embodiments, referring to FIG. 10 , the first power signal transmission structure includes a plurality of first power signal lines 43 located in the first conductive layer and a plurality of first power signal connection portions 372 located in the second conductive layer. The plurality of first power signal lines 43 are arranged along a first direction X and extend along a second direction Y. The first power signal connection portions 372 are electrically connected to the first power signal lines 43, and the first power signal connection portions 372 are electrically connected to the first electrode S3 of the third transistor T3.

[0131] Referring to Figure 9, a first connecting portion 57 is also provided in the light-shielding layer. The first connecting portion 57 is connected to the second connecting segment 55 as an integral structure. The orthographic projection of the first connecting portion 57 on the base substrate partially overlaps with the orthographic projection of the first power signal connecting portion 372 on the base substrate. In this overlapping area, the first connecting portion 57 is electrically connected to the first power signal connecting portion 372.

[0132] For example, the light shielding layer is provided with a first connection portion 57 in each of the multiple sub-pixels, and the multiple first connection portions 57 are electrically connected to the multiple first power signal connection portions 372. In other words, the light shielding layer is electrically connected to the first power signal transmission structure in each of the multiple sub-pixels. This allows for more uniform wiring across the different sub-pixels in the display substrate, thereby improving display uniformity across the display substrate.

[0133] According to some exemplary embodiments, referring to FIG. 2 , a first electrode of the fifth transistor T5 is connected to a reference voltage signal Vref, and the light shielding layer may be configured to be connected to the reference voltage signal Vref.

[0134] Figure 11 schematically illustrates a plan view of a light shielding layer and a second conductive layer in a display substrate according to some embodiments of the present disclosure. Figure 12 schematically illustrates a plan view of a light shielding layer, an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0135] According to some exemplary embodiments, referring to FIG11 and FIG12 , the display substrate includes a reference voltage signal line 34 configured to transmit a reference voltage signal. For example, the reference voltage signal line 34 may be located in the second conductive layer. The display substrate further includes a first insulating layer located between the light shielding layer and the active layer, and a second insulating layer located between the active layer and the second conductive layer. The second insulating layer has a first via hole V01, and the first and second insulating layers have second via holes V02. The first via hole V01 exposes at least a portion of the first electrode S5 of the fifth transistor T5, and the second via hole V02 exposes at least a portion of the light shielding layer. The reference voltage signal line 34 is electrically connected to the first electrode S5 of the fifth transistor T5 via the first via hole V01. The reference voltage signal line 34 is electrically connected to the light shielding layer via the second via hole V02. The orthographic projection of the second via hole V02 on the base substrate is adjacent to and spaced apart from the orthographic projection of the first via hole V01 on the base substrate.

[0136] It should be noted that the phrase "the orthographic projection of the second via V02 on the base substrate is adjacent to and spaced from the orthographic projection of the first via V01 on the base substrate" should be understood to mean that the orthographic projection of the second via V02 on the base substrate does not overlap with the orthographic projection of the first via V01 on the base substrate, and the distance between the orthographic projection of the second via V02 on the base substrate and the orthographic projection of the first via V01 on the base substrate is less than a predetermined distance. For example, the distance between the orthographic projection of the second via V02 on the base substrate and the orthographic projection of the first via V01 on the base substrate is less than the dimension of the orthographic projection of the second via V02 on the base substrate along the first direction X, or the distance between the orthographic projection of the second via V02 on the base substrate and the orthographic projection of the first via V01 on the base substrate is less than the dimension of the orthographic projection of the first via V01 on the base substrate along the first direction X.

[0137] According to some exemplary embodiments, the light-shielding layer includes a second connecting portion 58, which is connected to the second connecting section 55 as an integral structure. The orthographic projection of the second connecting portion 58 on the substrate overlaps with the orthographic projection of the reference voltage signal line 34 on the substrate. In this overlapping area, the second connecting portion 58 is electrically connected to the reference voltage signal line 34 through the second via V02.

[0138] For example, the light shielding layer is provided with a second connection portion 58 in each of the multiple sub-pixels, and the multiple second connection portions 58 are electrically connected to the multiple reference voltage signal lines 34 through the multiple second vias V02. That is, the light shielding layer is electrically connected to the reference voltage signal lines 34 in each of the multiple sub-pixels. Electrically connecting the light shielding layer having a grid structure to the multiple reference voltage signal lines can effectively improve the uniformity of the distribution of the reference voltage signal within the display area, thereby improving display uniformity.

[0139] According to some exemplary embodiments, the light-emitting element layer includes a first electrode layer located on a side of the driving circuit layer away from the base substrate, a pixel defining layer located on a side of the first electrode layer away from the base substrate, a light-emitting functional layer located on a side of the pixel defining layer away from the base substrate, and a second electrode layer located on a side of the light-emitting functional layer away from the base substrate. The display substrate includes a second power signal transmission structure, the second power signal transmission structure being located in the driving circuit layer, the second power signal transmission structure being configured to transmit a second power signal, the second power signal transmission structure including at least one auxiliary electrode located in the display area, the auxiliary electrode being electrically connected to the second electrode layer. By electrically connecting the second power signal transmission structure to the second electrode layer in the display area, the voltage drop (IR drop) when the second electrode layer transmits the second power signal can be effectively reduced, the distribution uniformity of the second power signal in the second electrode layer can be improved, and thus the display uniformity can be improved.

[0140] Figure 13 schematically illustrates a plan view of the superposition of a light shielding layer, a first conductive layer, a first electrode layer, and a pixel defining layer in a display substrate according to some embodiments of the present disclosure. Figure 14 schematically illustrates a plan view of the superposition of a light shielding layer, an active layer, a fourth conductive layer, a third conductive layer, a second conductive layer, a first conductive layer, and a first electrode layer in a display substrate according to some embodiments of the present disclosure. Figure 15 schematically illustrates a cross-sectional view taken along line AA' in Figure 13 .

[0141] According to some exemplary embodiments, referring to FIG. 13 and FIG. 14 , the second power signal transmission structure includes a second power signal line 41 and a second power grid line 36. The second power signal line 41 extends along a second direction Y and is located in the first conductive layer. The second power grid line 36 extends along a first direction X and is located in the second conductive layer. The second power grid line 36 is electrically connected to the second power signal line 41. An auxiliary electrode 411 is located in the first conductive layer, and the auxiliary electrode 41 and the second power signal line 41 are connected as an integral structure.

[0142] According to some exemplary embodiments, referring to FIG. 15 , an auxiliary electrode 411 is located on a first conductive layer M1. A first planarization layer PLN1 is provided on a side of the first conductive layer M1 that is close to the substrate, a second planarization layer PLN2 is provided on a side of the first conductive layer M1 that is away from the substrate, a first electrode layer ANE is provided on a side of the second planarization layer PLN2 that is away from the substrate, a pixel definition layer PDL is provided on a side of the first electrode layer ANE that is away from the substrate, a light-emitting functional layer EML is provided on a side of the pixel definition layer PDL that is away from the substrate, and a second electrode layer Cath is provided on a side of the light-emitting functional layer EML that is away from the substrate. An orthographic projection of the auxiliary electrode 411 on the substrate is spaced apart from an orthographic projection of the first electrode layer ANE on the substrate. An opening K is provided in the second planarization layer PLN2, the pixel definition layer PDL, and the light-emitting functional layer EML. The opening K exposes at least a portion of the auxiliary electrode 411, and the second electrode layer Cath is electrically connected to the auxiliary electrode 411 through the opening K.

[0143] According to some exemplary embodiments, referring to FIG. 15 , before forming the second electrode layer Cath by evaporation, an opening K may be formed in the second planarization layer PLN2, the pixel definition layer PDL, and the light-emitting function layer EML by a laser etching process, so that the subsequently formed second electrode layer Cath overlaps the auxiliary electrode 411 through the opening K. Referring to FIG. 13 , the orthographic projection of the auxiliary electrode 411 on the base substrate may be rectangular, and the dimension of the auxiliary electrode 411 along the first direction X may be greater than or equal to 15 microns, and the dimension of the auxiliary electrode 411 along the second direction Y may be greater than or equal to 15 microns.

[0144] According to some exemplary embodiments, referring to FIG13 , the first electrode layer includes a plurality of first electrodes 61 spaced apart. The pixel defining layer includes a plurality of first openings K1 and a plurality of second openings K2. The orthographic projection of the first opening K1 on the base substrate is located within the orthographic projection of the first electrode 61 on the base substrate, and the orthographic projection of the second opening K2 on the base substrate is spaced apart from the orthographic projection of the first electrode 61 on the base substrate. At least one first opening K1 exposes a portion of the first electrode 61, for example, three first openings K1 expose a portion of the first electrode 61, and the portion of the first electrode 61 exposed by the first opening K1 is used to contact the light-emitting functional layer. The second opening K2 is located in the spaced region between at least two first electrodes 61, for example, the cross-section of the first opening K2 has an undercut structure, and the sidewall of the first opening K2 is used to isolate the common functional layer in the light-emitting functional layer.

[0145] According to some exemplary embodiments, referring to FIG14 , the plurality of first electrodes 61 include a first sub-electrode 611, a second sub-electrode 612, and a third sub-electrode 613. For example, the first sub-electrode 611 and the third sub-electrode 613 are arranged along the second direction Y; and the first sub-electrode 611, the third sub-electrode 613, and the second sub-electrode 612 are arranged along the first direction X.

[0146] According to some exemplary embodiments, referring to FIG14 , the orthographic projection of the auxiliary electrode 411 on the base substrate is located between the orthographic projections of at least two first electrodes 61 on the base substrate. For example, the orthographic projection of the auxiliary electrode 411 on the base substrate is located between the orthographic projections of two second sub-electrodes 612 adjacent to each other along the second direction Y.

[0147] According to some exemplary embodiments, the distribution density of the auxiliary electrodes in the display area can be set according to actual needs. For example, one auxiliary electrode is provided in each sub-pixel, or one auxiliary electrode is provided in multiple sub-pixels.

[0148] According to some exemplary embodiments, referring to FIG. 2 , the pixel circuit has a 9T1C pixel circuit structure, and the pixel circuit includes a storage capacitor C1 and nine transistors T1 to T9 . For example, all transistors are N-type transistors, wherein the third transistor T3 is a driving transistor, and the other transistors are switching transistors.

[0149] 2 , a first electrode of the first transistor T1 is configured to receive a data signal Vdata, and a second electrode of the first transistor T1 is electrically connected to the second plate of the first storage capacitor C1. A first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3. A first electrode of the third transistor T3 is configured to receive a first power supply signal VDD, and the gate of the third transistor T3 is electrically connected to the first plate of the storage capacitor C1. A first electrode of the fourth transistor T4 is configured to receive a first initialization signal Vinit1, and the second electrode of the fourth transistor T4 is electrically connected to the gate of the third transistor T3. A first electrode of the fifth transistor T5 is configured to receive a reference voltage signal Vref, and the second electrode of the fifth transistor T5 is electrically connected to the second electrode D1 of the first transistor T1. A first electrode of the sixth transistor T6 is configured to receive the reference voltage signal Vref, and the second electrode of the sixth transistor T6 is electrically connected to the second electrode of the first transistor T1. A first electrode of the seventh transistor T7 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the light-emitting element. The first electrode of the eighth transistor T8 is configured to receive the second initialization signal Vinit2, the second electrode of the eighth transistor T8 is electrically connected to the first electrode of the light emitting element, the first electrode of the ninth transistor T9 is electrically connected to the gate of the third transistor T3, and the second electrode of the ninth transistor T9 is floating.

[0150] The gates of the first transistor T1 and the second transistor T2 are respectively configured to receive a scan signal Gate. The gates of the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are respectively configured to receive a reset signal Reset. The gates of the sixth transistor T6 and the seventh transistor T7 are respectively configured to receive a light-emission control signal EM.

[0151] The gate of the third transistor T3, the first plate of the storage capacitor, the second electrode of the second transistor T2, and the first electrode of the ninth transistor T9 are connected to a first node N1. The second plate of the storage capacitor, the second electrode of the first transistor T1, the second electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 are connected to a second node N2. The second electrode of the seventh transistor T7, the second electrode D8 of the eighth transistor T8, and the first electrode of the light-emitting element are connected to a third node N3.

[0152] According to some exemplary embodiments, the driving process of the driving circuit includes three stages: stage 1, stage 2, and stage 3, which are described below in conjunction with FIG. 2 .

[0153] In the first phase, under the control of the reset signal Reset, the fourth transistor T4 turns on, and the first initialization signal Vinit1 initializes the first node N1. At this time, the potential of the first node N1 is the first initialization signal Vinit1. The fifth transistor T5 turns on, and the reference voltage signal Vref is written to the second node N2. The eighth transistor T8 turns on to release the residual charge displayed in the previous frame, and the second initialization signal Vinit2 is written to the third node N3, which is the first electrode of the light-emitting element.

[0154] In the second phase, under the control of the scan signal Gate, the first transistor T1 turns on, and the data signal Vdata is written to the second node N2. The second transistor T2 turns on, sampling the diode connection of the third transistor T3. The potential of the first node N1 rises to VDD + Vth, and the third transistor T3 gradually changes from the on state to the off state, compensating for the threshold voltage Vth of the driving transistor T3.

[0155] In the third phase, under the control of the light-emission control signal EM, the sixth transistor T6 turns on, and the reference voltage signal Vref is written to the second node N2. The ninth transistor T9 turns on, reducing leakage at the first node N1 during the light-emission phase. As the potential of the second node N2 jumps, the potential at N2 becomes VDD + Vth + Vref - Vdata. Simultaneously, the seventh transistor T7 turns on, driving current output, causing the light-emitting element to emit light.

[0156] In the embodiment of the present disclosure, under the driving of the driving circuit, the current formula of the light emitting element is: I = k (Vref - Vdata) 2, where I is the current value used to drive the light-emitting element, k is a coefficient, Vref is the value of the reference voltage signal, and Vdata is the value of the data signal. According to the current formula, the current value is not affected by the threshold voltage Vth of the transistor and the voltage VDD of the first power supply signal, that is, compensation of Vth and VDD is achieved. Referring back to Figures 11 and 12, in this embodiment, the light-shielding layer having a grid structure is electrically connected to a plurality of reference voltage signal lines, which can improve the uniformity of the Vref signal, thereby ensuring that the current I is less affected by the Vref difference. According to some exemplary embodiments, the display substrate includes a base substrate, and an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source and drain metal layer, a passivation layer, a first planarization layer, a second source and drain metal layer, a second planarization layer, a first electrode layer, a pixel defining layer, a light-emitting functional layer, and a second electrode layer, which are sequentially arranged on the base substrate in a direction away from the base substrate. The active layer, first gate insulating layer, first gate metal layer, second gate insulating layer, second gate metal layer, interlayer insulating layer, first source-drain metal layer, passivation layer, first planarization layer, and second source-drain metal layer constitute the driving circuit layer; the first electrode layer, pixel defining layer, light-emitting functional layer, and second electrode layer constitute the light-emitting element layer. The first gate metal layer serves as the fourth conductive layer in the aforementioned embodiment, the second gate metal layer serves as the third conductive layer in the aforementioned embodiment, the first source-drain metal layer serves as the second conductive layer in the aforementioned embodiment, and the second source-drain metal layer serves as the first conductive layer in the aforementioned embodiment.

[0157] 16A to 16H are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0158] 16A illustrates an active layer; FIG16B illustrates a first gate metal layer; FIG16C illustrates a second gate metal layer; FIG16D illustrates an interlayer insulating layer; FIG16E illustrates a first source-drain metal layer; FIG16F illustrates a passivation layer; FIG16G illustrates a first planarization layer; and FIG16H illustrates a second source-drain metal layer.

[0159] According to some exemplary embodiments, referring to FIG16A , the active layer includes at least some of the active portions of the aforementioned transistors. Exemplarily, the active layer includes the active portions of a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The active portion of each transistor includes a channel portion and a first electrode and a second electrode connected to either side of the channel portion. The channel portions of the aforementioned transistors in the same pixel circuit are integrally formed with the first electrode and the second electrode. Specifically, the active portion of the first transistor T1 includes a channel portion CH1 and a first electrode S1 and a second electrode D1 connected to either side of the channel portion CH1. The active portion of the second transistor T2 includes a channel portion CH2 and a first electrode S2 and a second electrode D2 connected to either side of the channel portion CH2. The active portion of the third transistor T3 includes a channel portion CH3 and a first electrode S3 and a second electrode D3 connected to either side of the channel portion CH3. The active portion of the fourth transistor T4 includes a channel portion CH4, and a first electrode S4 and a second electrode D4 connected to both sides of the channel portion CH4. The active portion of the fifth transistor T5 includes a channel portion CH5, and a first electrode S5 and a second electrode D5 connected to both sides of the channel portion CH5. The active portion of the sixth transistor T6 includes a channel portion CH6, and a first electrode S6 and a second electrode D6 connected to both sides of the channel portion CH6. The active portion of the seventh transistor T7 includes a channel portion CH7, and a first electrode S7 and a second electrode D7 connected to both sides of the channel portion CH7. The active portion of the eighth transistor T8 includes a channel portion CH8, and a first electrode S8 and a second electrode D8 connected to both sides of the channel portion CH8. The active portion of the ninth transistor T9 includes a channel portion CH9, and a first electrode S9 and a second electrode D9 connected to both sides of the channel portion CH9.

[0160] For example, the second transistor T2 is a dual-gate dual-channel transistor, and the channel portion CH2 of the second transistor T2 includes a first sub-channel portion CH21 and a second sub-channel portion CH22 that are spaced apart. The first sub-channel portion CH21 and the second sub-channel portion CH22 are connected via a channel connecting portion CH23.

[0161] For example, the fourth transistor T4 is a dual-gate dual-channel transistor, and the channel portion CH4 of the fourth transistor T4 includes a first sub-channel portion CH41 and a second sub-channel portion CH42 that are spaced apart. The first sub-channel portion CH41 and the second sub-channel portion CH42 are connected via a channel connecting portion CH43.

[0162] For example, the active portion of the second transistor T2 , the active portion of the third transistor T3 , the active portion of the seventh transistor T7 , and the active portion of the eighth transistor T8 are connected to each other as an integrated structure.

[0163] For example, the active portion of the fourth transistor T4 and the active portion of the ninth transistor T9 are connected as an integrated structure.

[0164] For example, the active portion of the fifth transistor T5 and the active portion of the sixth transistor T6 are connected to form an integral structure.

[0165] For example, the active portions of the first transistor T1 and the third transistor T3 are arranged in a Z-shape, the active portions of the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are arranged in a U-shape, and the active portions of the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are arranged in a straight line.

[0166] According to some exemplary embodiments, referring to FIG. 16B , the first gate metal layer may include a first conductive portion 11 , a second conductive portion 12 , a third conductive portion 13 , and a light emitting control signal line 14 .

[0167] For example, referring to Figures 16A and 16B, the orthographic projection of the first conductive portion 11 on the substrate partially overlaps with the orthographic projection of the active portion of the first transistor T1 on the substrate, and the portion where the first conductive portion 11 overlaps with the active portion of the first transistor T1 serves as the gate G1 of the first transistor T1, and the portion where the active portion of the first transistor T1 overlaps with the first conductive portion 11 is the channel portion CH1 of the first transistor T1. There are two overlapping areas between the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the active portion of the second transistor T2 on the substrate. The two overlapping portions of the first conductive portion 11 and the active portion of the second transistor T2 serve as the first gate G21 and the second gate G22 of the second transistor T2, respectively. The two overlapping portions of the active portion of the second transistor T2 and the first conductive portion 11 serve as the first sub-channel portion CH21 and the second sub-channel portion CH22 of the second transistor T2, respectively. The portion connected between the first sub-channel portion CH21 and the second sub-channel portion CH22 is the channel connection portion CH23. The first sub-channel portion CH21, the second sub-channel portion CH22 and the channel connection portion CH23 collectively serve as the channel portion CH2 of the second transistor T2.

[0168] For example, referring to Figures 16A and 16B, the orthographic projection of the second conductive portion 12 on the substrate partially overlaps with the orthographic projection of the active portion of the fifth transistor T5 on the substrate, and the overlapping portion of the second conductive portion 12 and the active portion of the fifth transistor T5 serves as the gate G5 of the fifth transistor T5, and the overlapping portion of the active portion of the fifth transistor T5 and the second conductive portion 12 is the channel portion CH5 of the fifth transistor T5. There are two overlapping areas between the orthographic projection of the second conductive portion 12 on the substrate and the orthographic projection of the active portion of the fourth transistor T4 on the substrate. The two overlapping portions of the second conductive portion 12 and the active portion of the second transistor T2 serve as the first gate G41 and the second gate G42 of the fourth transistor T4, respectively. The two overlapping portions of the active portion of the fourth transistor T4 and the second conductive portion 12 serve as the first sub-channel portion CH41 and the second sub-channel portion CH42 of the fourth transistor T4, respectively. The portion connected between the first sub-channel portion CH41 and the second sub-channel portion CH42 is the channel connecting portion CH43. The first sub-channel portion CH41, the second sub-channel portion CH42 and the channel connecting portion CH43 together serve as the channel portion CH4 of the fourth transistor T4. The orthographic projection of the second conductive portion 12 on the substrate partially overlaps with the orthographic projection of the active portion of the eighth transistor T8 on the substrate. The overlapping portion of the second conductive portion 12 and the active portion of the eighth transistor T8 serves as the gate G8 of the eighth transistor T8, and the overlapping portion of the active portion of the eighth transistor T8 and the second conductive portion 12 serves as the channel CH8 of the eighth transistor T8.

[0169] For example, referring to FIG16A and FIG16B , the orthographic projection of the third conductive portion 13 on the substrate partially overlaps the orthographic projection of the active portion of the third transistor T3 on the substrate. The overlapping portion of the second conductive portion 12 and the active portion of the third transistor T3 serves as the gate G3 of the third transistor T3, and the overlapping portion of the active portion of the third transistor T3 and the second conductive portion 12 serves as the channel CH3 of the third transistor T3. The third conductive portion 13 can also serve as the first substrate of a storage capacitor.

[0170] For example, referring to Figures 16A and 16B , the main portion of the light-emission control signal line 14 extends along a first direction. The light-emission control signal line 14 overlaps with the orthographic projection of the active portion of the sixth transistor T6 on the substrate. The overlapping portion of the light-emission control signal line 14 and the active portion of the sixth transistor T6 serves as the gate G6 of the sixth transistor T6. The overlapping portion of the active portion of the sixth transistor T6 and the light-emission control signal line 14 serves as the channel CH6 of the sixth transistor T6. The light-emission control signal line 14 overlaps with the orthographic projection of the active portion of the seventh transistor T7 on the substrate. The overlapping portion of the light-emission control signal line 14 and the active portion of the seventh transistor T7 serves as the gate G7 of the seventh transistor T7. The overlapping portion of the active portion of the seventh transistor T7 and the light-emission control signal line 14 serves as the channel CH7 of the seventh transistor T7. The light-emitting control signal line 14 overlaps with the positive projection of the active part of the ninth transistor T9 on the base substrate. The overlapping part of the light-emitting control signal line 14 and the active part of the ninth transistor T9 serves as the gate G9 of the ninth transistor T9. The overlapping part of the active part of the ninth transistor T9 and the light-emitting control signal line 14 is the channel CH9 of the ninth transistor T9.

[0171] According to some exemplary embodiments, referring to FIG. 16C , the second gate metal layer may include a first power grid line 21 , a fourth conductive portion 22 , a second initialization connection portion 23 , and a shielding portion 24 .

[0172] For example, referring to FIG. 16C , the first power grid lines 21 extend along the first direction X, and the first power grid lines 21 are configured to transmit a first power signal.

[0173] For example, referring to FIG16B and FIG16C , the orthographic projection of the fourth conductive portion 22 on the substrate at least partially overlaps with the orthographic projection of the third conductive portion 13 on the substrate, and the fourth conductive portion 22 serves as the second plate of the storage capacitor. The fourth conductive portion 22 has a hollow structure 221, and the orthographic projection of the hollow structure 221 on the substrate is located within the orthographic projection of the third conductive portion 13 on the substrate.

[0174] 16A and 16C , the second initialization connection portion 23 and the shielding portion 24 are connected as an integral structure, and the orthographic projection of the shielding portion 24 on the base substrate at least partially overlaps with the orthographic projection of the channel connection portion CH23 on the base substrate.

[0175] According to some exemplary embodiments, referring to Figure 16D, the interlayer insulating layer has multiple vias, for example, the interlayer insulating layer has a first via V11, a second via V12, a third via V13, a fourth via V14, a fifth via V15, a sixth via V16, a seventh via V17, an eighth via V18, a ninth via V19, a tenth via V20, an eleventh via V21, a twelfth via V22, a thirteenth via V23, a fourteenth via V24, a fifteenth via V25, a sixteenth via V26, a seventeenth via V27 and an eighteenth via V28.

[0176] According to some exemplary embodiments, referring to Figure 16E, the first source-drain metal layer may include a first initialization signal line 31, a second initialization signal line 32, a reset signal line 33, a reference voltage signal line 34, a scan signal line 35, a second power grid line 36, a first initialization connection portion 371, a first power signal connection portion 372, a third connection structure 373, a fourth connection structure 374, a fifth connection structure 375 and a sixth connection structure 376.

[0177] For example, referring to Figures 16A, 16C, 16D, and 16E, the first initialization signal line 31 extends along the first direction X and is configured to transmit a first initialization signal. The first initialization signal line 31 is electrically connected to the second initialization connection portion 23 via a first via V11. The first initialization connection portion 371 is electrically connected to the second initialization connection portion 23 via a third via V13. The first initialization connection portion 371 is electrically connected to the first electrode S4 of the fourth transistor T4 via a fourth via V14. In other words, the first initialization signal line 31 is electrically connected to the first electrode S4 of the fourth transistor T4 via the second initialization connection portion 23 and the first initialization connection portion 371.

[0178] 16A , 16D and 16E , the second initialization signal line 32 extends along the first direction X and is configured to transmit a second initialization signal. The second initialization signal line 32 is electrically connected to the first electrode S8 of the eighth transistor T8 through the second via V12 .

[0179] 16B , 16D and 16E , the reset signal line 33 extends along the first direction X. The reset signal line 33 is configured to transmit a reset signal. The reset signal line 33 is electrically connected to the second conductive portion 12 through the fifth via V15 .

[0180] 16A , 16D , and 16E , the reference voltage signal line 34 extends along the first direction X. The reference voltage signal line 34 is configured to transmit a reference voltage signal. The reference voltage signal line 34 is electrically connected to the first electrode S5 of the fifth transistor T5 and the first electrode S6 of the sixth transistor T6 through a sixth via V16.

[0181] 16B , 16D and 16E , the scan signal line 35 extends along the first direction X. The scan signal line 35 is configured to transmit a scan signal. The scan signal line 35 is electrically connected to the first conductive portion 11 through the seventeenth via hole V27 .

[0182] For example, referring to FIG. 16E , the second power grid line 36 extends along the first direction X, and the second power grid line 36 is configured as a second power signal.

[0183] For example, referring to FIG16A , FIG16C , FIG16D , and FIG16E , the first power signal connection portion 372 extends along the second direction Y. The first power signal connection portion 372 is electrically connected to the first power grid line 21 through the seventh via V17 and the eighth via V18. The first power signal connection portion 372 is electrically connected to the first electrode S3 of the third transistor T3 through the thirteenth via V23. In other words, the first power grid line 21 is electrically connected to the first electrode S3 of the third transistor T3 through the first power signal connection portion 372.

[0184] For example, referring to FIG. 16A , FIG. 16D , and FIG. 16E , the third connection structure 373 is electrically connected to the second electrode D2 of the seventh transistor T7 through the eleventh via hole V21 .

[0185] For example, with reference to Figures 16A-16E , the fourth connection structure 374 is electrically connected to the first electrode S9 of the ninth transistor T9 through the tenth via V20, the fourth connection structure 374 is electrically connected to the gate G3 of the third transistor T3 through the fourth via V14 and the hollow structure 221 of the fourth conductive portion 22, and the fourth connection structure 374 is electrically connected to the second electrode D2 of the second transistor T2 through the fifteenth via V25. That is, through the connection of the fourth connection structure 374, the first electrode S9 of the ninth transistor T9, the gate G3 of the third transistor T3, and the second electrode D2 of the second transistor T2 are electrically connected to the same node.

[0186] For example, referring to FIG16A , FIG16C , FIG16D , and FIG16E , the fifth connection structure 375 is electrically connected to the second electrode D5 of the fifth transistor T5 and the second electrode D6 of the sixth transistor T6 through the ninth via V19. The fifth connection structure 375 is electrically connected to the fourth conductive portion 22 through the twelfth via V22. The fifth connection structure 375 is electrically connected to the second electrode D1 of the first transistor T1 through the fifteenth via V25. In other words, the second electrode D5 of the fifth transistor T5, the second electrode D6 of the sixth transistor T6, the second plate of the storage capacitor, and the second electrode D1 of the first transistor T1 are electrically connected to the same node through the fifth connection structure 375.

[0187] For example, referring to FIG. 16A , FIG. 16D , and FIG. 16E , the sixth connection structure 376 is electrically connected to the first electrode S1 of the first transistor T1 through the eighteenth via hole V28 .

[0188] According to some exemplary embodiments, referring to FIG. 16F , the passivation layer has a first via hole V31 , a second via hole V32 , a third via hole V33 , a fourth via hole V34 , and a fifth via hole V35 .

[0189] According to some exemplary embodiments, referring to FIG16G , the first planarization layer has a first via V41, a second via V42, a third via V43, a fourth via V44, and a fifth via V45. Referring to FIG16F in conjunction with FIG16G , the first via V41 is nested with the first via V31, i.e., the orthographic projection of the first via V41 on the substrate overlaps the orthographic projection of the first via V31 on the substrate. The second via V42 is nested with the second via V32, i.e., the orthographic projection of the second via V42 on the substrate overlaps the orthographic projection of the second via V32 on the substrate. The third via V43 is nested with the third via V33, i.e., the orthographic projection of the third via V43 on the substrate overlaps the orthographic projection of the third via V33 on the substrate. The fourth via V44 is nested with the fourth via V34, i.e., the orthographic projection of the fourth via V44 on the substrate overlaps the orthographic projection of the fourth via V34 on the substrate. The fifth via hole V45 is nested with the fifth via hole V35 , that is, the orthographic projection of the fifth via hole V45 on the base substrate covers the orthographic projection of the fifth via hole V35 on the base substrate.

[0190] According to some exemplary embodiments, referring to FIG. 16H , the second source / drain metal layer may include a second power signal line 41 , a mesh line 42 , a first power signal line 43 , a data line 44 , and a first electrode connection portion 45 .

[0191] According to some exemplary embodiments, with reference to FIG16E , FIG16F , FIG16G , and FIG16H , a second power signal line 41 extends along a second direction Y. The second power signal line 41 is configured to transmit a second power signal. The second power signal line 41 passes through the fifth via V45 , the fifth via V35 , and the second power grid line 36 .

[0192] 16E and 16H , the grid lines 42 extend along the second direction Y. A portion of the grid lines 42 may be electrically connected to the first initialization signal line 31 , a portion of the grid lines 42 may be electrically connected to the second initialization signal line 32 , and a portion of the grid lines 42 may be electrically connected to the reference voltage signal line 34 .

[0193] According to some exemplary embodiments, with reference to FIG16E , FIG16F , FIG16G , and FIG16H , the first power signal line 43 extends along the second direction Y. The first power signal line 43 is configured to transmit a first power signal. The first power signal line 43 is electrically connected to the third via V33 via the third via V43, and to the second via V32 via the second via V42 and the first power signal connection portion 372 via the third via V43. That is, the first power signal line 43 is electrically connected to the first power grid line 21 via the first power signal connection portion 372.

[0194] According to some exemplary embodiments, referring to FIG. 16E , FIG. 16F , FIG. 16G , and FIG. 16H , the data line 44 extends along the second direction Y and is configured to transmit a data signal. The data line 44 is electrically connected to the sixth connection structure 376 through the fourth via V44 and the fourth via V34 . That is, the data line 44 is electrically connected to the first electrode S1 of the first transistor T1 through the sixth connection structure 376 .

[0195] According to some exemplary embodiments, with reference to Figures 16E, 16F, 16G and 16H, the first electrode connecting portion 45 is electrically connected to the third connecting structure 373 through the first via V41, the first via V31, and the third connecting structure 373, that is, the first electrode connecting portion 45 is electrically connected to the second electrode D2 of the seventh transistor T7 through the third connecting structure 373, and the first electrode connecting portion 45 is also used to be electrically connected to the first electrode located on the upper side.

[0196] According to some exemplary embodiments, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the passivation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer structure, or a composite layer. The first planarization layer and the second planarization layer may be made of organic materials, such as resin.

[0197] At least some embodiments of the present disclosure further provide a display device comprising the display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0198] It should be understood that the display device according to the embodiment of the present disclosure has all the features and advantages of the above-mentioned display substrate. For details, please refer to the above description and will not be repeated here. Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate includes a display area and a peripheral area located around the display area, and the display substrate includes: a substrate; and A plurality of sub-pixels are located on the substrate, the plurality of sub-pixels are arranged in the display area along a first direction and / or a second direction, the first direction intersecting the second direction, the sub-pixels include a light-emitting element and a driving circuit electrically connected to the light-emitting element, the driving circuit includes a plurality of transistors and at least one storage capacitor, the plurality of transistors include a first transistor, a second transistor, and a third transistor, and the at least one storage capacitor includes a first storage capacitor; a first electrode of the first transistor is configured to receive a data signal, and a second electrode of the first transistor is electrically connected to a second plate of the first storage capacitor; a first electrode of the second transistor is electrically connected to a second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to a gate of the third transistor; and a first electrode of the third transistor is configured to receive a first power supply signal, and the gate of the third transistor is electrically connected to the first plate of the first storage capacitor; The second transistor includes an active portion, the active portion includes a channel portion and a first electrode and a second electrode respectively connected to both sides of the channel portion, the channel portion includes a first sub-channel portion, a second sub-channel portion and a channel connecting portion, and the channel connecting portion is connected between the first sub-channel portion and the second sub-channel portion; and The display substrate also includes a blocking portion located on the base substrate, the layer where the blocking portion is located is located on the side of the layer where the active portion of the second transistor is located away from the base substrate, and the orthographic projection of the blocking portion on the base substrate at least partially overlaps with the orthographic projection of the channel connection portion on the base substrate.

2. The display substrate according to claim 1, wherein The shielding portion is configured to receive a constant voltage signal.

3. The display substrate according to claim 2, wherein: The plurality of transistors further include a fourth transistor, a first electrode of the fourth transistor being configured to receive a first initialization signal, a second electrode of the fourth transistor being electrically connected to a gate of the third transistor, and the shielding portion being configured to receive the first initialization signal.

4. The display substrate according to claim 3, wherein: The display substrate includes a first initialization signal line, the first initialization signal line transmits the first initialization signal, and the shielding portion is electrically connected to the first initialization signal line.

5. The display substrate according to claim 4, wherein: The display substrate comprises a third conductive layer located on the base substrate and a second conductive layer located on a side of the third conductive layer away from the base substrate, and the first initialization signal line is located in the second conductive layer; and The second conductive layer further includes a first initialization connection portion spaced apart from the first initialization signal line, the third conductive layer includes a second initialization connection portion, the second initialization connection portion being electrically connected to the first initialization signal line and the first initialization connection portion, respectively, and the first initialization connection portion being electrically connected to the first electrode of the fourth transistor; The shielding portion is located in the third conductive layer, and the shielding portion and the second initialization connection portion are connected to form an integrated structure.

6. The display substrate according to claim 2, wherein: The second electrode of the light-emitting element is configured to receive a second power signal, and the shielding portion is configured to receive the second power signal.

7. The display substrate according to claim 6, wherein: The display substrate includes a second power signal transmission structure, which transmits the second power signal. The shielding portion is electrically connected to the second power signal transmission structure.

8. The display substrate according to claim 7, wherein: The display substrate comprises a second conductive layer located on the base substrate and a first conductive layer located on a side of the second conductive layer away from the base substrate; The second power signal transmission structure includes a second power signal line located in the first conductive layer and a second power grid line located in the second conductive layer, the second power grid line extending along the first direction, the second power signal line extending along the second direction, and the second power grid line being electrically connected to the second power signal line; The shielding portion is located in the first conductive layer, and the shielding portion is connected to the second power signal line to form an integrated structure.

9. The display substrate according to claim 2, wherein: The shielding portion is configured to receive the first power signal; or The plurality of transistors further include a fifth transistor, a first electrode of the fifth transistor being configured to receive a reference voltage signal, a second electrode of the fifth transistor being electrically connected to the second electrode of the first transistor, and the shielding portion being configured to receive the reference voltage signal; or The plurality of transistors further include an eighth transistor, a first electrode of the eighth transistor being configured to receive a second initialization signal, a second electrode of the eighth transistor being electrically connected to the first electrode of the light-emitting element, and the shielding portion being configured to receive the second initialization signal.

10. The display substrate according to any one of claims 1 to 9, wherein: The display substrate further includes a scanning signal line, wherein the scanning signal line is configured to connect a scanning signal to the gate of the second transistor; The orthographic projection of the shielding portion on the base substrate is spaced apart from the orthographic projection of the scanning signal line on the base substrate, and / or the orthographic projection of the shielding portion on the base substrate is spaced apart from the orthographic projection of the gate of the second transistor on the base substrate.

11. The display substrate according to any one of claims 1 to 10, wherein: The display substrate includes an active layer located on the base substrate and a light-shielding layer located between the active layer and the base substrate. Multiple active portions of the multiple transistors are located in the active layer, and the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projection of the multiple active portions on the base substrate.

12. The display substrate according to claim 11, wherein: The plurality of transistors further include a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; A first electrode of the fourth transistor is configured to receive a first initialization signal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor; The first electrode of the fifth transistor is configured to receive a reference voltage signal, and the second electrode of the fifth transistor is electrically connected to the second electrode of the first transistor; The first electrode of the sixth transistor is configured to receive a reference voltage signal, and the second electrode of the sixth transistor is electrically connected to the second electrode of the first transistor; The first electrode of the seventh transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element; The first electrode of the eighth transistor is configured to receive the second initialization signal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element; and The gate of the first transistor and the gate of the second transistor are respectively configured to receive a scan signal, the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the eighth transistor are respectively configured to receive a reset signal, and the gate of the sixth transistor and the gate of the seventh transistor are respectively configured to receive a light emitting control signal; In which, the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projections of the active portion of the first transistor, the active portion of the second transistor, the active portion of the third transistor, the active portion of the fourth transistor, the active portion of the fifth transistor, and the active portion of the eighth transistor on the base substrate, respectively.

13. The display substrate according to claim 11 or 12, wherein: The light shielding layer is configured to receive the first power signal.

14. The display substrate according to claim 13, wherein: The display substrate includes a first power signal transmission structure configured to transmit a first power signal; The first power signal transmission structure includes a plurality of first power signal lines and a plurality of first power signal connection portions, the plurality of first power signal lines are arranged along a first direction and extend along a second direction, the first power signal connection portion is electrically connected to the first power signal lines, and the first power signal connection portion is electrically connected to the first electrode of the third transistor; and The display substrate includes a second conductive layer located on a side of the active layer away from the base substrate and a first conductive layer located on a side of the second conductive layer away from the base substrate, the first power signal line is located on the first conductive layer, and the first power signal connection portion is located on the second conductive layer; Wherein, the light shielding layer is electrically connected to at least one of the first power signal connection parts.

15. The display substrate according to claim 11, wherein The plurality of transistors further include a fifth transistor, a first electrode of the fifth transistor being connected to a reference voltage signal, a second electrode of the fifth transistor being electrically connected to the second electrode of the first transistor, and the light shielding layer being configured to be connected to the reference voltage signal.

16. The display substrate according to claim 15, wherein: The display substrate includes a reference voltage signal line, the reference voltage signal line is configured to transmit the reference voltage signal, the display substrate further includes a second conductive layer located on a side of the active layer away from the base substrate, the reference voltage signal line is located in the second conductive layer; and The display substrate further includes a first insulating layer located between the light-shielding layer and the active layer, and a second insulating layer located between the active layer and the second conductive layer, the second insulating layer having a first via hole, and the first insulating layer and the second insulating layer having a second via hole, the first via hole exposing at least a portion of the first electrode of the fifth transistor, and the second via hole exposing at least a portion of the light-shielding layer, the reference voltage signal line being electrically connected to the first electrode of the fifth transistor through the first via hole, and the reference voltage signal line being electrically connected to the light-shielding layer through the second via hole; The orthographic projection of the second via hole on the base substrate is adjacent to the orthographic projection of the first via hole on the base substrate.

17. The display substrate according to any one of claims 1 to 16, wherein: The display substrate comprises a driving circuit layer located on the base substrate and a light emitting element layer located on a side of the driving circuit layer away from the base substrate, wherein each driving circuit is located on the driving circuit layer, and each light emitting element is located on the light emitting element layer; The display substrate includes a second power signal transmission structure, the second power signal transmission structure is located in the driving circuit layer, the second power signal transmission structure is configured to transmit a second power signal, and the second power signal transmission structure includes at least one auxiliary electrode located in the display area; as well as The light-emitting element layer includes: a first electrode layer located on the side of the driving circuit layer away from the base substrate, a light-emitting functional layer located on the side of the first electrode layer away from the base substrate, and a second electrode layer located on the side of the light-emitting functional layer away from the base substrate, wherein the second electrode layer is electrically connected to the auxiliary electrode.

18. The display substrate according to claim 17, wherein: The driving circuit layer includes a second conductive layer located on the base substrate and a first conductive layer located on a side of the second conductive layer away from the base substrate; and The second power signal transmission structure includes a second power signal line and a second power grid line, the second power signal line extends along the second direction, the second power signal line is located in the first conductive layer, the second power grid line extends along the first direction, the second power grid line is located in the second conductive layer, and the second power grid line is electrically connected to the second power signal line; The auxiliary electrode is located in the first conductive layer, and the auxiliary electrode is connected to the second power signal line to form an integrated structure.

19. The display substrate according to claim 18, wherein: The first electrode layer includes a plurality of first electrodes arranged at intervals, and the orthographic projection of the auxiliary electrode on the base substrate is located between orthographic projections of at least two of the first electrodes on the base substrate.

20. A display device, wherein: The display device includes the display substrate according to any one of claims 1 to 19.

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