Display substrate and display device

Abstract

Provided is a display substrate, comprising: a base substrate; a plurality of sub-pixels located on the base substrate, each sub-pixel comprising a light-emitting element and a driving circuit; a first initialization signal transmission structure electrically connected to the driving circuit; a second initialization signal transmission structure electrically connected to the driving circuit; a reference voltage signal transmission structure electrically connected to the driving circuit; and a second power supply signal transmission structure electrically connected to a second electrode of the light-emitting element, wherein the orthographic projection of at least one of the first initialization signal transmission structure, the second initialization signal transmission structure, the reference voltage signal transmission structure, and the second power supply signal transmission structure on the base substrate is in a grid shape.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, Organic Light-Emitting Diode (OLED) display devices have become a research hotspot and technology development direction for major manufacturers due to their advantages such as wide color gamut, high contrast, thin and light design, self-luminescence, and wide viewing angle.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising:

[0006] substrate;

[0007] a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged along a first direction and / or a second direction, the first direction intersecting the second direction, the sub-pixels comprising a light-emitting element and a driving circuit electrically connected to the light-emitting element;

[0008] a first initialization signal transmission structure, located on the base substrate, the first initialization signal transmission structure being electrically connected to the driving circuit and configured to input a first initialization signal to the driving circuit;

[0009] a second initialization signal transmission structure, located on the base substrate, the second initialization signal transmission structure being electrically connected to the driving circuit and configured to input a second initialization signal to the driving circuit;

[0010] a reference voltage signal transmission structure, located on the base substrate, the reference voltage signal transmission structure being electrically connected to the driving circuit and configured to provide the driving circuit with a reference voltage signal; and

[0011] a second power signal transmission structure, located on the base substrate, the second power signal transmission structure being electrically connected to the second electrode of the light-emitting element and being used to connect a second power signal to the second electrode;

[0012] The orthographic projection of at least one of the first initialization signal transmission structure, the second initialization signal transmission structure, the reference voltage signal transmission structure and the second power signal transmission structure on the base substrate is in a grid shape.

[0013] According to some exemplary embodiments, the display substrate includes a first conductive layer located on the base substrate and a second conductive layer located between the first conductive layer and the base substrate;

[0014] The first initialization signal transmission structure includes a plurality of first initialization signal lines located in the second conductive layer and a plurality of first initialization grid lines located in the first conductive layer, the plurality of first initialization signal lines extending along the first direction and arranged along the second direction, the plurality of first initialization grid lines extending along the second direction and arranged along the first direction, the first initialization grid line being electrically connected to at least one of the first initialization signal lines; and / or

[0015] The second initialization signal transmission structure includes a plurality of second initialization signal lines located in the second conductive layer and a plurality of second initialization grid lines located in the first conductive layer, the plurality of second initialization signal lines extending along the first direction and arranged along the second direction, the plurality of second initialization grid lines extending along the second direction and arranged along the first direction, and the second initialization grid lines being electrically connected to at least one of the second initialization signal lines; and / or

[0016] The reference voltage signal transmission structure includes a plurality of reference voltage signal lines located in the second conductive layer and a plurality of reference voltage grid lines located in the first conductive layer, the plurality of reference voltage signal lines extending along the first direction and arranged along the second direction, the plurality of reference voltage grid lines extending along the second direction and arranged along the first direction, the reference voltage grid line being electrically connected to at least one of the reference voltage signal lines; and / or

[0017] The second power signal transmission structure includes a plurality of second power signal lines located in the first conductive layer and a plurality of second power grid lines located in the second conductive layer, the plurality of second power signal lines extending along the second direction and arranged along the first direction, the plurality of second power grid lines extending along the first direction and arranged along the second direction, and the second power grid line is electrically connected to at least one second power signal line.

[0018] According to some exemplary embodiments, the first conductive layer includes a plurality of first routing groups arranged along the first direction, the first routing groups include three second power signal lines and three grid lines, the three second power signal lines and the three grid lines are alternately arranged along the first direction, and the three grid lines include one first initialization grid line, one second initialization grid line, and one reference voltage grid line.

[0019] According to some exemplary embodiments, the first routing group includes three first routing subgroups arranged along the first direction, and the first routing subgroup includes one second power signal line and one grid line;

[0020] The first wiring subgroup further includes a first power signal line and a data line, and the first power signal line and the data line are located on one side of the grid line and the second power signal line along the first direction.

[0021] According to some exemplary embodiments, the first conductive layer includes a plurality of first routing groups arranged along the first direction, the first routing group includes one second power signal line and three grid lines, the three grid lines include one first initialization grid line, one second initialization grid line, and one reference voltage grid line;

[0022] The second power signal line is located on one side of the three grid lines along the first direction, or the second power signal line is located between two of the three grid lines.

[0023] According to some exemplary embodiments, the first routing group includes three first routing sub-groups arranged in the first direction, two of the first routing sub-groups each include one of the grid lines, and the remaining first routing sub-group includes one of the grid lines and one of the second power signal lines;

[0024] In which, the first routing subgroup also includes a first power signal line and a data line, the first power signal line and the data line are located on one side of the grid line along the first direction, or the first power signal line and the data line are located on one side of the grid line and the second power signal line along the first direction.

[0025] According to some exemplary embodiments, the second conductive layer includes a plurality of second routing groups arranged along the second direction, and the second routing groups include a first initialization signal line, a second initialization signal line, a reference voltage signal line, and a second power grid line arranged along the second direction.

[0026] According to some exemplary embodiments, the display substrate further includes a first power signal transmission structure located on the base substrate, the first power signal transmission structure being electrically connected to the driving circuit and used to connect a first power signal to the driving circuit, and the orthographic projection of the first power signal transmission structure on the base substrate being in a grid shape.

[0027] According to some exemplary embodiments, the display substrate includes a first conductive layer located on the base substrate, a second conductive layer located between the first conductive layer and the base substrate, and a third conductive layer located between the second conductive layer and the base substrate;

[0028] The first power signal transmission structure includes a plurality of first power signal lines located in the first conductive layer, a plurality of first power signal connection portions located in the second conductive layer, and a plurality of first power grid lines located in the third conductive layer, the plurality of first power signal lines being arranged along the first direction and extending along the second direction, and the plurality of first power grid lines being arranged along the second direction and extending along the first direction;

[0029] The first power grid line is electrically connected to at least one first power signal line through at least one first power signal connection portion. The first power signal connection portion is electrically connected to the driving circuit and is used to connect the first power signal to the driving circuit.

[0030] According to some exemplary embodiments, an orthographic projection of the first power signal connection portion on the base substrate is located within an orthographic projection of the first power signal line on the base substrate.

[0031] According to some exemplary embodiments, the driving circuit includes a first transistor, a second transistor, a third transistor and a first storage capacitor;

[0032] The first electrode of the first transistor is configured to receive a data signal, and the second electrode of the first transistor is electrically connected to the second plate of the first storage capacitor;

[0033] The first electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the gate of the third transistor; and

[0034] The first electrode of the third transistor is configured to receive a first power supply signal, and the gate of the third transistor is electrically connected to the first plate of the first storage capacitor;

[0035] The gate of the first transistor and the gate of the second transistor are respectively configured to receive a scan signal.

[0036] According to some exemplary embodiments, the display substrate includes a second conductive layer located on the base substrate and a fourth conductive layer located between the second conductive layer and the base substrate, and the gate of the first transistor and the gate of the second transistor are located in the fourth conductive layer; and

[0037] The display substrate further includes a scanning signal line located in the second conductive layer, the scanning signal line being electrically connected to the gate of the first transistor and the gate of the second transistor respectively, and the scanning signal line being used to connect a scanning signal to the gate of the first transistor and the gate of the second transistor.

[0038] According to some exemplary embodiments, the driving circuit further includes a fourth transistor, a fifth transistor, and an eighth transistor;

[0039] A first electrode of the fourth transistor is configured to receive a first initialization signal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor;

[0040] A first electrode of the fifth transistor is configured to receive a reference voltage signal, and a second electrode of the fifth transistor is electrically connected to the second electrode of the first transistor; and

[0041] The first electrode of the eighth transistor is configured to receive the second initialization signal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element;

[0042] The gate of the fourth transistor, the gate of the fifth transistor and the gate of the eighth transistor are respectively configured to receive a reset signal.

[0043] According to some exemplary embodiments, the display substrate includes a second conductive layer located on the base substrate and a fourth conductive layer located between the second conductive layer and the base substrate, and the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the eighth transistor are located in the fourth conductive layer; and

[0044] The display substrate also includes a reset signal line located in the second conductive layer, the reset signal line is electrically connected to the gate of the fourth transistor, the gate of the fifth transistor and the gate of the eighth transistor, respectively, and the reset signal line is used to connect the scanning signal to the gate of the fourth transistor, the gate of the fifth transistor and the gate of the eighth transistor.

[0045] According to some exemplary embodiments, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel including a first driving circuit and a first light-emitting element electrically connected to the first driving circuit, the second sub-pixel including a second driving circuit and a second light-emitting element electrically connected to the second driving circuit, and the third sub-pixel including a third driving circuit and a third light-emitting element electrically connected to the third driving circuit;

[0046] The active portion of the third transistor has a channel portion, a first electrode, and a second electrode, wherein the first electrode and the second electrode are respectively connected to two sides of the channel portion along the first direction; and

[0047] The third transistor in the first driving circuit has a first channel portion, the third transistor in the second driving circuit has a second channel portion, and the third transistor in the third driving circuit has a third channel portion;

[0048] wherein a ratio of a size of the first channel portion along the first direction to a size of the second channel portion along the second direction is different from a ratio of a size of the second channel portion along the first direction to a size of the second direction; and / or

[0049] A ratio of a size of the first channel portion along the first direction to a size of the second direction is different from a ratio of a size of the third channel portion along the first direction to a size of the second direction; and / or

[0050] A ratio of a size of the second channel portion along the first direction to a size of the second direction is different from a ratio of a size of the third channel portion along the first direction to a size of the second direction.

[0051] According to some exemplary embodiments, the first light emitting element emits red light, the second light emitting element emits green light, and the third light emitting element emits blue light;

[0052] wherein a ratio of a size of the third channel portion along the first direction to a size of the third channel portion along the second direction is greater than a ratio of a size of the first channel portion along the first direction to a size of the first channel portion along the second direction; and / or

[0053] A ratio of a dimension of the third channel portion along the first direction to a dimension of the third channel portion along the second direction is greater than a ratio of a dimension of the second channel portion along the first direction to a dimension of the second channel portion along the second direction.

[0054] According to some exemplary embodiments, a size of the third channel portion along the first direction is equal to a size of the first channel portion along the first direction, and a size of the third channel portion along the second direction is smaller than a size of the first channel portion along the second direction; and / or

[0055] A size of the third channel portion along the first direction is equal to a size of the second channel portion along the first direction, and a size of the third channel portion along the second direction is smaller than a size of the second channel portion along the second direction.

[0056] According to some exemplary embodiments, the display substrate includes a second conductive layer located on the base substrate, an insulating layer located on a side of the second conductive layer away from the base substrate, a first conductive layer located on a side of the insulating layer away from the base substrate, and a first electrode layer located on a side of the first conductive layer away from the base substrate;

[0057] The first electrode layer includes a plurality of first electrodes, each of the first electrodes including a first electrode main body and a first electrode connecting portion connected to the first electrode main body;

[0058] The first conductive layer includes a plurality of first transition portions, the second conductive layer includes a plurality of second transition portions, the insulating layer has a plurality of via holes, and the plurality of via holes respectively expose at least a portion of the plurality of second transition portions; and

[0059] The first electrode connecting portion is electrically connected to the first transition portion, the first transition portion is electrically connected to the second transition portion through the via hole, and the second transition portion is electrically connected to the driving circuit;

[0060] wherein the orthographic projections of the plurality of first electrode main bodies on the base substrate cover at least a portion of the orthographic projections of the plurality of via holes on the base substrate; and / or

[0061] The orthographic projections of the plurality of first electrode main bodies on the base substrate cover at least a portion of the orthographic projections of the plurality of first transition portions on the base substrate; and / or

[0062] The orthographic projections of the plurality of first electrode main bodies on the base substrate cover at least a portion of the orthographic projections of the plurality of second transition portions on the base substrate.

[0063] According to some exemplary embodiments, the plurality of first electrodes include a plurality of first sub-electrodes, a plurality of second sub-electrodes, and a plurality of third sub-electrodes, and the plurality of first transition portions include a plurality of first transition sub-portions, a plurality of second transition sub-portions, and a plurality of third transition sub-portions;

[0064] The first sub-electrode and the third sub-electrode are arranged at intervals along the second direction, and the second sub-electrode is located on one side of the first sub-electrode and the third sub-electrode along the first direction;

[0065] The first sub-electrode includes a first sub-electrode main portion and a first sub-electrode connecting portion connected to a side of the first sub-electrode main portion close to the third sub-electrode, one end of the first adapter sub-portion is electrically connected to the first sub-electrode connecting portion, and the other end of the first adapter sub-portion extends along the second direction and is electrically connected to the second adapter portion;

[0066] The second sub-electrode includes a second sub-electrode main portion and a second sub-electrode connecting portion connected to a side of the second sub-electrode main portion close to the first sub-electrode and the third sub-electrode, one end of the second transition sub-portion is electrically connected to the second sub-electrode connecting portion, and the other end of the second transition sub-portion extends along the second direction and is electrically connected to the second transition portion; and

[0067] The third sub-electrode includes a third sub-electrode main portion and a third sub-electrode connecting portion connected to a corner of the second sub-electrode main portion away from the first sub-electrode and close to the second sub-electrode, the third sub-electrode connecting portion extending along the first direction and electrically connected to one end of the third adapter sub-portion, and the other end of the third adapter sub-portion extending along the second direction and electrically connected to the second adapter portion;

[0068] Among them, the orthographic projection of the second adapter part electrically connected to the first adapter sub-part on the base substrate is located within the orthographic projection of the third sub-electrode main part on the base substrate; the orthographic projection of the second adapter part electrically connected to the third adapter sub-part on the base substrate is located within the orthographic projection of the second sub-electrode main part on the base substrate.

[0069] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items or the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0071] FIG. 1 is a schematic plan view of a display substrate according to some embodiments of the present disclosure.

[0072] FIG2 schematically shows a circuit principle diagram of a driving circuit in a display substrate according to some embodiments of the present disclosure.

[0073] FIG3 schematically shows a plan view of the superposition of a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0074] FIG4 schematically shows a plan view of the superposition of a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0075] 5A-5D are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0076] 5A illustrates a superimposed plan view of the active layer, the fourth conductive layer, the third conductive layer, the second conductive layer and the first conductive layer; FIG. 5B illustrates the fourth conductive layer; FIG. 5C illustrates the second insulating layer; and FIG. 5D illustrates the second conductive layer.

[0077] FIG6 schematically shows a plan view of an overlay of an active layer and a fourth conductive layer in a display substrate according to some embodiments of the present disclosure.

[0078] 7A-7G are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0079] Among them, Figure 7A illustrates a superimposed plan view of the second conductive layer, the first conductive layer and the first electrode layer; Figure 7B illustrates the first electrode layer; Figure 7C illustrates the second planarization layer; Figure 7D illustrates the first conductive layer; Figure 7E illustrates the first planarization layer; Figure 7F illustrates the passivation layer; Figure 7G illustrates the second conductive layer; Figure 7H illustrates a superimposed plan view of the active layer, the fourth conductive layer, the third conductive layer, the second conductive layer, the first conductive layer and the first electrode layer.

[0080] 8A-8H are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0081] 8A illustrates an active layer; FIG. 8B illustrates a first gate metal layer; FIG. 8C illustrates a second gate metal layer; FIG. 8D illustrates an interlayer insulating layer; FIG. 8E illustrates a first source / drain metal layer; FIG. 8F illustrates a passivation layer; FIG. 8G illustrates a first planarization layer; and FIG. 8H illustrates a second source / drain metal layer. DETAILED DESCRIPTION

[0082] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0083] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0084] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0085] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0086] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0087] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0088] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0089] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0090] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0091] FIG1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0092] According to some exemplary embodiments, referring to FIG. 1 , a display substrate includes a display area AA and a peripheral area NA located around the display area AA. The display substrate includes a base substrate 10 and a plurality of sub-pixels SP located on the base substrate 10. The plurality of sub-pixels SP are arranged in the display area AA along a first direction X and a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y. Each sub-pixel SP includes a light-emitting element and a driving circuit electrically connected to the light-emitting element. The driving circuit is configured to independently drive the light-emitting element to emit light, thereby causing the display substrate to display an image.

[0093] The light-emitting element used in the embodiments of the present disclosure may specifically be an organic light-emitting diode (OLED). For example, the light-emitting element may be an OLED with a top-emitting structure, which may emit red light, green light, blue light, or white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode of the light-emitting element is the anode of the OLED, and the second electrode is the cathode of the OLED, that is, the pixel circuit is a common cathode structure. However, the embodiments of the present disclosure are not limited to this, and according to changes in the circuit structure, the pixel circuit may also be a common anode structure.

[0094] The display substrate used in the embodiments of the present disclosure can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (P1), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.

[0095] According to some exemplary embodiments, the display substrate includes a driving circuit layer located on a base substrate and a light emitting element layer located on a side of the driving circuit layer away from the base substrate, wherein each driving circuit is located in the driving circuit layer and each light emitting element is located in the light emitting element layer.

[0096] For example, the driving circuit layer includes a first conductive layer located on the base substrate, a second conductive layer located between the first conductive layer and the base substrate, a third conductive layer located between the second conductive layer and the base substrate, a fourth conductive layer located between the third conductive layer and the base substrate, and an active layer located between the fourth conductive layer and the base substrate.

[0097] For example, the light-emitting element layer includes a first electrode layer located on the side of the driving circuit layer away from the base substrate, a pixel defining layer located on the side of the first electrode layer away from the base substrate, a light-emitting functional layer located on the side of the pixel defining layer away from the base substrate, and a second electrode layer located on the side of the light-emitting functional layer away from the base substrate.

[0098] Figure 2 schematically illustrates a circuit principle diagram of a driving circuit in a display substrate according to some embodiments of the present disclosure. Figure 3 schematically illustrates a plan view of a superimposed third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0099] It should be noted that in the plan views of some film layers of the display substrate provided in the embodiments of the present disclosure, the rectangular frame lines and the cross lines within the rectangular frame lines are only for illustrating the setting range of a driving circuit, and are not part of the film layer structure in the display substrate.

[0100] 3 , the display substrate includes a first initialization signal transmission structure A10, a second initialization signal transmission structure A20, a reference voltage signal transmission structure A30, and a second power signal transmission structure A40 located on the base substrate. For example, the first initialization signal transmission structure A10, the second initialization signal transmission structure A20, the reference voltage signal transmission structure A30, and the second power signal transmission structure A40 are located on the driver circuit layer.

[0101] 2 and 3 , a first initialization signal transmission structure A10 is electrically connected to the driver circuit and is used to supply a first initialization signal Vinit1 to the driver circuit. A second initialization signal transmission structure A20 is electrically connected to the driver circuit and is used to supply a second initialization signal Vinit2 to the driver circuit. A reference voltage signal transmission structure A30 is electrically connected to the driver circuit and is used to supply a reference voltage signal Vref to the driver circuit. A second power supply signal transmission structure A40 is electrically connected to the second electrode of the light-emitting element and is used to supply a second power supply signal VSS to the second electrode.

[0102] At least one of the first initialization signal transmission structure A10, the second initialization signal transmission structure A20, the reference voltage signal transmission structure A30, and the second power signal transmission structure A40 has a grid-like structure. For example, referring to FIG3 , the orthographic projection of the first initialization signal transmission structure A10 on the substrate is in a grid shape, the orthographic projection of the second initialization signal transmission structure A20 on the substrate is in a grid shape, the orthographic projection of the reference voltage signal transmission structure A30 on the substrate is in a grid shape, and the orthographic projection of the second power signal transmission structure A40 on the substrate is in a grid shape. By configuring the first initialization signal transmission structure A10, the second initialization signal transmission structure A20, the reference voltage signal transmission structure A30, and the second power signal transmission structure A40 into a grid-like structure, the uniformity of the distribution of the first initialization signal Vinit1, the second initialization signal Vinit2, the reference voltage signal Vref, and the second power signal VSS within the display area can be effectively improved, thereby improving the display uniformity of the display substrate.

[0103] According to some exemplary embodiments, referring to FIG3 , the first initialization signal transmission structure A10 includes a plurality of first initialization signal lines 31 located in the second conductive layer and a plurality of first initialization grid lines 421 located in the first conductive layer. The plurality of first initialization signal lines 31 extend along the first direction X and are arranged along the second direction Y. The plurality of first initialization grid lines 421 extend along the second direction Y and are arranged along the first direction X. The plurality of first initialization grid lines 421 extending along the second direction Y and the plurality of first initialization signal lines 31 extending along the first direction X are crisscrossed to form a grid-like first initialization signal transmission structure A10. The first initialization grid line 421 is electrically connected to at least one first initialization signal line 31. Exemplarily, a first insulating layer is provided between the first conductive layer and the second conductive layer, the first insulating layer having a plurality of first vias V01 therein. The first initialization grid lines 421 are electrically connected to the plurality of first initialization signal lines 31 through the plurality of first vias V01.

[0104] According to some exemplary embodiments, referring to FIG. 3 , the second initialization signal transmission structure A20 includes a plurality of second initialization signal lines 32 located in the second conductive layer and a plurality of second initialization grid lines 422 located in the first conductive layer. The plurality of second initialization signal lines 32 extend along the first direction X and are arranged along the second direction Y. The plurality of second initialization grid lines 422 extend along the second direction Y and are arranged along the first direction X. The plurality of second initialization grid lines 422 extending along the second direction Y and the plurality of second initialization signal lines 32 extending along the first direction X are crisscrossed to form a grid-like second initialization signal transmission structure A20. The second initialization grid lines 422 are electrically connected to at least one of the second initialization signal lines 32. Exemplarily, a first insulating layer is provided between the first conductive layer and the second conductive layer, the first insulating layer having a plurality of second vias V02 therein. The second initialization grid lines 422 are electrically connected to the plurality of second initialization signal lines 32 via the plurality of second vias V02.

[0105] According to some exemplary embodiments, referring to FIG. 3 , a reference voltage signal transmission structure A30 includes a plurality of reference voltage signal lines 34 located in a second conductive layer and a plurality of reference voltage grid lines 423 located in a first conductive layer. The plurality of reference voltage signal lines 34 extend along a first direction X and are arranged along a second direction Y. The plurality of reference voltage grid lines 423 extend along the second direction Y and are arranged along the first direction X. The plurality of reference voltage grid lines 423 extending along the second direction Y and the plurality of reference voltage signal lines 34 extending along the first direction X are crisscrossed to form a grid-like reference voltage signal transmission structure A30. The reference voltage grid lines 423 are electrically connected to at least one of the reference voltage signal lines 34. Exemplarily, a first insulating layer is provided between the first conductive layer and the second conductive layer. The first insulating layer includes a plurality of third vias V03. The reference voltage grid lines 423 are electrically connected to the plurality of reference voltage signal lines 34 through the plurality of third vias V03.

[0106] According to some exemplary embodiments, referring to FIG. 3 , a second power signal transmission structure A40 includes a plurality of second power signal lines 41 located in a first conductive layer and a plurality of second power grid lines 36 located in a second conductive layer. The plurality of second power signal lines 41 extend along a second direction Y and are arranged along a first direction X. The plurality of second power grid lines 36 extend along the first direction X and are arranged along a second direction Y. The plurality of second power grid lines 36 extending along the first direction X and the plurality of second power signal lines 41 extending along the second direction Y are crisscrossed to form a grid-like second power signal transmission structure A40. The second power grid lines 36 are electrically connected to at least one second power signal line 41. Exemplarily, a first insulating layer is provided between the first conductive layer and the second conductive layer. The first insulating layer includes a plurality of fourth vias V04. The second power grid lines 36 are electrically connected to the plurality of second power signal lines 41 through the plurality of fourth vias V04.

[0107] According to some exemplary embodiments, referring to FIG. 3 , the first conductive layer includes a plurality of first routing groups G1 arranged along a first direction X. The first routing group G1 includes three second power signal lines 41 and three grid lines 42. The three second power signal lines 41 and the three grid lines 42 are alternately arranged along the first direction X. The three grid lines 42 include a first initialization grid line 421, a second initialization grid line 422, and a reference voltage grid line 423.

[0108] According to some exemplary embodiments, referring to FIG. 3 , the first routing group G1 includes three first routing sub-groups G11 arranged along a first direction X. The first routing sub-group G11 includes a second power signal line 41 and a grid line 42. In addition, each first routing sub-group G11 also includes a first power signal line 43 and a data line 44. The first power signal line 43 and the data line 44 are located on one side of the grid line 42 and the second power signal line 41 along the first direction X. With reference to FIG. 2 and FIG. 3 , the first power signal line 43 is electrically connected to the driving circuit and is used to supply the first power signal VDD to the driving circuit. The data line 44 is electrically connected to the driving circuit and is used to supply the data signal Vdata to the driving circuit.

[0109] For example, referring to FIG. 3 , the first routing subgroup G11 includes four routing lines, which are sequentially arranged along the first direction X as a data line 44 , a first power signal line 43 , a grid line 42 , and a second power signal line 41 .

[0110] For example, referring to Figure 3, the first routing group G1 includes 12 routing lines, which are, along the first direction X, the data line 44, the first power signal line 43, the first initialization grid line 421, the second power signal line 41, the data line 44, the first power signal line 43, the second initialization grid line 422, the second power signal line 41, the data line 44, the first power signal line 43, the reference voltage grid line 423 and the second power signal line 41.

[0111] FIG4 schematically shows a plan view of the superposition of a third conductive layer, a second conductive layer, and a first conductive layer in a display substrate according to some embodiments of the present disclosure.

[0112] According to some exemplary embodiments, referring to FIG. 4 , the first conductive layer includes a plurality of first routing groups G1 arranged along a first direction X. The first routing group G1 includes a second power signal line 41 and three grid lines 42. The three grid lines 42 include a first initialization grid line 421, a second initialization grid line 422, and a reference voltage grid line 423. The second power signal line 41 is located on one side of the three grid lines 42 along the first direction X, or the second power signal line 41 is located between two of the three grid lines 42. Exemplarily, the second power signal line 41 is located between the second initialization grid line 422 and the reference voltage grid line 423.

[0113] According to some exemplary embodiments, referring to FIG. 4 , the first routing group G1 includes three first routing sub-groups G11 arranged along a first direction X. Two of the first routing sub-groups G11 each include a grid line 42, and the remaining first routing sub-group G11 includes a grid line 42 and a second power signal line 41. The first routing sub-group G11 also includes a first power signal line 43 and a data line 44. The first power signal line 43 and the data line 44 are located on one side of the grid line 42 along the first direction X, or the first power signal line 43 and the data line 44 are located on one side of the grid line 42 along the first direction X. Alternatively, the first power signal line 43 and the data line 44 are located on one side of the grid line and the second power signal line 41 along the first direction X.

[0114] For example, referring to Figure 4, the first routing group G1 includes 10 routing lines, which are, along the first direction X, the data line 44, the first power signal line 43, the first initialization grid line 421, the data line 44, the first power signal line 43, the second initialization grid line 422, the data line 44, the first power signal line 43, the second power signal line 41 and the reference voltage grid line 423.

[0115] According to some exemplary embodiments, referring to Figure 3 or Figure 4, the second conductive layer includes a plurality of second routing groups G2 arranged along the second direction Y, and the second routing group G2 includes a first initialization signal line 31, a second initialization signal line 32, a reference voltage signal line 34 and a second power grid line 36 arranged along the second direction Y.

[0116] According to some exemplary embodiments, with reference to FIG3 or FIG4 , the display substrate further includes a first power signal transmission structure A50 located on the base substrate. The orthographic projection of the first power signal transmission structure A50 on the base substrate is in the form of a grid. Referring to FIG2 , the first power signal transmission structure A50 is electrically connected to the drive circuit and is used to provide the first power signal VDD to the drive circuit. By configuring the first power signal transmission structure A50 in a grid-like structure, the uniformity of the distribution of the first power signal VDD within the display area can be effectively improved, thereby improving the display uniformity of the display substrate.

[0117] According to some exemplary embodiments, referring to FIG. 3 or FIG. 4 , a first power signal transmission structure A50 includes a plurality of first power signal lines 43 located on a first conductive layer, a plurality of first power signal connection portions 372 located on a second conductive layer, and a plurality of first power grid lines 21 located on a third conductive layer. The plurality of first power signal lines 43 are arranged along a first direction X and extend along a second direction Y. The plurality of first power grid lines 21 are arranged along a second direction Y and extend along the first direction X. The plurality of first power signal lines 43 extending along the second direction Y and the plurality of first power grid lines 21 extending along the first direction X are crisscrossed to form a grid-like first power signal transmission structure A50. The first power grid lines 21 are electrically connected to at least one first power signal line 43 via at least one first power signal connection portion 372. The first power signal connection portion 372 is electrically connected to a driving circuit and is used to provide the first power signal to the driving circuit. For example, the first power grid lines 21 are electrically connected to each of the plurality of first power signal lines 43 via the plurality of first power signal connection portions 372.

[0118] According to some exemplary embodiments, referring to FIG. 3 or FIG. 4 , the first power signal connection portion 372 is in the shape of a strip extending along the second direction Y, and the orthographic projection of the first power signal connection portion 372 on the base substrate is located within the orthographic projection of the first power signal line 43 on the base substrate.

[0119] 5A-5D are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0120] 5A illustrates a superimposed plan view of the active layer, the fourth conductive layer, the third conductive layer, the second conductive layer and the first conductive layer; FIG. 5B illustrates the fourth conductive layer; FIG. 5C illustrates the second insulating layer; and FIG. 5D illustrates the second conductive layer.

[0121] According to some exemplary embodiments, referring to FIG2 , the driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a first storage capacitor C1. A first electrode of the first transistor T1 is configured to receive a data signal Vdata, and a second electrode of the first transistor T1 is electrically connected to the second plate of the first storage capacitor C1. A first electrode of the second transistor T2 is electrically connected to a second electrode of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to a gate of the third transistor T3. A first electrode of the third transistor T3 is configured to receive a first power supply signal VDD, and a gate of the third transistor T3 is electrically connected to the first plate of the first storage capacitor C1. The gates of the first transistor T1 and the second transistor T2 are respectively configured to receive a scan signal Gate.

[0122] According to some exemplary embodiments, referring to FIG. 5A , the active portion of the first transistor T1 and the active portion of the second transistor T2 are located in an active layer, and the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 are located in a fourth conductive layer. The fourth conductive layer includes a first conductive portion 11. The first conductive portion 11 includes the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2, i.e., the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 are connected as an integral structure. The display substrate further includes a scan signal line 35 located in the second conductive layer. The scan signal line 35 extends along a first direction X. The scan signal line 35 is electrically connected to the first conductive portion 11, i.e., the scan signal line 35 is electrically connected to the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2, respectively. The scan signal line 35 is used to input a scan signal to the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2. The sheet resistance of the fourth conductive layer is greater than the sheet resistance of the second conductive layer. For example, the fourth conductive layer is a single-layer film composed of metallic molybdenum, while the second conductive layer is a laminated film composed of a titanium layer, an aluminum layer, and a titanium layer. This arrangement effectively reduces the routing resistance of the scan signal line 35 that transmits the scan signal, thereby reducing the voltage drop (IR drop) during scan signal transmission, improving the distribution uniformity of the scan signal, and thereby improving the display uniformity of the display substrate.

[0123] The "integrated structure" in the embodiments of the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process to be connected to each other, and their materials may be the same or different.

[0124] According to some exemplary embodiments, referring to FIG. 5A , the second transistor T2 is a dual-gate transistor, and the gate of the second transistor T2 includes a first gate G21 and a second gate G22 .

[0125] According to some exemplary embodiments, referring to Figures 5B to 5D, a second insulating layer is provided between the fourth conductive layer and the second conductive layer, the second insulating layer has a plurality of fifth vias V05, the fifth vias V05 expose at least a portion of the first conductive portion 11, and the scanning signal line 35 is electrically connected to the plurality of first conductive portions 11 through the plurality of fifth vias V05.

[0126] According to some exemplary embodiments, referring to FIG2 , the driving circuit further includes a fourth transistor T4, a fifth transistor T5, and an eighth transistor T8. A first electrode S4 of the fourth transistor T4 is configured to receive a first initialization signal Vinit1, and a second electrode D4 of the fourth transistor T4 is electrically connected to the gate of the third transistor T3. A first electrode S5 of the fifth transistor T5 is configured to receive a reference voltage signal Vref, and a second electrode D5 of the fifth transistor T5 is electrically connected to the second electrode D1 of the first transistor T1. A first electrode S8 of the eighth transistor T8 is configured to receive a second initialization signal Vinit2, and a second electrode D8 of the eighth transistor T8 is electrically connected to the first electrode of the light-emitting element. The gates of the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are each configured to receive a reset signal Reset.

[0127] According to some exemplary embodiments, referring to Figures 5A and 8A , the active portion of the fourth transistor T4, the active portion of the fifth transistor T5, and the active portion of the eighth transistor T8 are located in the active layer, and the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, and the gate G8 of the eighth transistor T8 are located in the fourth conductive layer. Referring to Figures 5A and 8B , the fourth conductive layer includes a third conductive portion 13, which includes the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, and the gate G8 of the eighth transistor T8. That is, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, and the gate G8 of the eighth transistor T8 are connected as an integrated structure. The display substrate also includes a reset signal line 33 located in the second conductive layer. The reset signal line 33 extends along the first direction X. The reset signal line 33 is electrically connected to the third conductive portion 13, that is, the reset signal line 33 is electrically connected to the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, and the gate G8 of the eighth transistor T8, respectively. The reset signal line 33 is used to respectively connect the reset signal to the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, and the gate G8 of the eighth transistor T8. Exemplarily, the fourth conductive layer is a single-layer film layer composed of metal molybdenum, and the second conductive layer is a stacked film layer composed of a titanium layer / aluminum layer / titanium layer. Since the square resistance of the fourth conductive layer is greater than the square resistance of the second conductive layer, the above-mentioned arrangement can effectively reduce the routing resistance of the reset signal line 33 that transmits the reset signal, thereby reducing the voltage drop (IR Drop) during the reset signal transmission process, improving the distribution uniformity of the reset signal, and thereby improving the display uniformity of the display substrate.

[0128] According to some exemplary embodiments, referring to FIG. 5A and FIG. 8A , the fourth transistor T4 is a dual-gate transistor, and the gate of the fourth transistor T4 includes a first gate G41 and a second gate G42 .

[0129] According to some exemplary embodiments, referring to Figures 5B to 5D, a second insulating layer is provided between the fourth conductive layer and the second conductive layer, the second insulating layer has a plurality of sixth vias V06, the sixth vias V06 expose at least a portion of the third conductive portion 13, and the reset signal line 33 is electrically connected to the plurality of third conductive portions 13 through the plurality of sixth vias V06.

[0130] FIG6 schematically shows a plan view of an overlay of an active layer and a fourth conductive layer in a display substrate according to some embodiments of the present disclosure.

[0131] According to some exemplary embodiments, referring to FIG6 , the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes a first driving circuit DC1 and a first light-emitting element electrically connected to the first driving circuit DC1. The second sub-pixel includes a second driving circuit DC2 and a second light-emitting element electrically connected to the second driving circuit DC2. The third sub-pixel includes a third driving circuit DC3 and a third light-emitting element electrically connected to the third driving circuit DC3. A third transistor T3 includes an active portion and a gate G3. The portion of the active portion of the third transistor T3 that overlaps with the gate G3 serves as a channel CH3 of the third transistor T3. The active portion of the third transistor T3 also includes a first electrode S3 and a second electrode D3. The first electrode S3 and the second electrode D3 are respectively connected to opposite sides of the channel CH3 along the first direction X.

[0132] The third transistor T3 in the first drive circuit DC1 has a first channel portion CH31, the third transistor T3 in the second drive circuit DC2 has a second channel portion CH32, and the third transistor T3 in the third drive circuit DC3 has a third channel portion CH33. Because the emission currents of the first, second, and third light-emitting elements are different, the channel sizes of the third transistors T3 (i.e., the drive transistors) in the first, second, and third drive circuits DC1, DC2, and DC3 can be adjusted based on the emission currents of the first, second, and third light-emitting elements, respectively.

[0133] 6 , a ratio of a dimension W1 of the first channel portion CH31 in the first direction X to a dimension L1 of the second direction Y is different from a ratio of a dimension W2 of the second channel portion CH32 in the first direction X to a dimension L2 of the second direction Y.

[0134] 6 , a ratio of a dimension W1 of the first channel portion CH31 in the first direction X to a dimension L1 of the second direction Y is different from a ratio of a dimension W3 of the third channel portion CH33 in the first direction X to a dimension L3 of the second direction Y.

[0135] 6 , a ratio of a dimension W2 of the second channel portion CH32 in the first direction X to a dimension L2 in the second direction Y is different from a ratio of a dimension W3 of the third channel portion CH33 in the first direction X to a dimension L3 in the second direction Y.

[0136] According to some exemplary embodiments, referring to FIG6 , the first light-emitting element emits red light, the second light-emitting element emits green light, and the third light-emitting element emits blue light. Because the light-emitting current of the third light-emitting element emitting blue light is greater than the light-emitting current of the second light-emitting element emitting green light and the light-emitting current of the first light-emitting element emitting red light, the size of the third channel portion CH33 can be set to be different from that of the second channel portion CH32 and the first channel portion CH31.

[0137] For example, a ratio of a dimension W3 of the third channel portion CH33 in the first direction X to a dimension L3 in the second direction Y is greater than a ratio of a dimension W1 of the first channel portion CH31 in the first direction X to a dimension L1 of the first channel portion CH31 in the second direction Y.

[0138] For example, a ratio of a dimension W3 of the third channel portion CH33 in the first direction X to a dimension L3 in the second direction Y is greater than a ratio of a dimension W2 of the second channel portion CH32 in the first direction X to a dimension L2 in the second direction Y.

[0139] According to some exemplary embodiments, referring to FIG6 , a dimension W3 of the third channel portion CH33 along the first direction X is equal to a dimension W1 of the first channel portion CH31 along the first direction X, and a dimension L3 of the third channel portion CH33 along the second direction Y is smaller than a dimension L1 of the first channel portion CH31 along the second direction Y. The dimension W3 of the third channel portion CH33 along the first direction X is equal to a dimension W2 of the second channel portion CH32 along the first direction X, and the dimension L3 of the third channel portion CH33 along the second direction Y is smaller than a dimension L2 of the second channel portion CH32 along the second direction Y.

[0140] According to some exemplary embodiments, a dimension of the third channel portion along the first direction is larger than a dimension of the first channel portion along the first direction, and a dimension of the third channel portion along the second direction is smaller than a dimension of the first channel portion along the second direction. The dimension of the third channel portion along the first direction is larger than a dimension of the second channel portion along the first direction, and a dimension of the third channel portion along the second direction is smaller than a dimension of the second channel portion along the second direction.

[0141] According to some exemplary embodiments, a dimension of the third channel portion along the first direction is greater than a dimension of the first channel portion along the first direction, and a dimension of the third channel portion along the second direction is equal to a dimension of the first channel portion along the second direction. A dimension of the third channel portion along the first direction is greater than a dimension of the second channel portion along the first direction, and a dimension of the third channel portion along the second direction is equal to a dimension of the second channel portion along the second direction.

[0142] According to some exemplary embodiments, referring to FIG. 6 , the shape of the channel portion CH3 of the third transistor T3 is a zigzag shape.

[0143] Figures 7A to 7G are plan views of some film layers located in the display area of ​​a display substrate according to some exemplary embodiments of the present disclosure; wherein, Figure 7A illustrates an overlaid plan view of the second conductive layer, the first conductive layer and the first electrode layer; Figure 7B illustrates the first electrode layer; Figure 7C illustrates the second planarization layer; Figure 7D illustrates the first conductive layer; Figure 7E illustrates the first planarization layer; Figure 7F illustrates the passivation layer; Figure 7G illustrates the second conductive layer; and Figure 7H illustrates an overlaid plan view of the active layer, the fourth conductive layer, the third conductive layer, the second conductive layer, the first conductive layer and the first electrode layer.

[0144] According to some exemplary embodiments, the display substrate includes a second conductive layer located on a base substrate, a first insulating layer located on a side of the second conductive layer away from the base substrate, the first conductive layer located on a side of the first insulating layer away from the base substrate, a third insulating layer located on a side of the first conductive layer away from the base substrate, and a first electrode layer located on a side of the third insulating layer away from the base substrate. Exemplarily, the first insulating layer includes a passivation layer located on a side of the second conductive layer away from the base substrate and a first planarization layer located on a side of the passivation layer away from the base substrate, and the third insulating layer includes a second planarization layer.

[0145] 7B , the first electrode layer includes a plurality of first electrodes 61, each of which includes a first electrode main portion 61a and a first electrode connecting portion 61b connected to the first electrode main portion 61a. Referring to FIG7D , the first conductive layer includes a plurality of first transition portions 46. Referring to FIG7G , the second conductive layer includes a plurality of second transition portions 373. Referring to FIG7F , the passivation layer has a plurality of vias V31, and referring to FIG7E , the first planarization layer has a plurality of vias V41. Referring to FIG7E , FIG7F , and FIG7G , the orthographic projection of the via V41 on the base substrate overlaps the orthographic projection of the via V31 on the base substrate, and the via V41 and the via V31 jointly expose at least a portion of the second transition portion 373.

[0146] Referring to Figure 7A , the first electrode connecting portion 61b is electrically connected to the first adapter portion 46, which is electrically connected to the second adapter portion 373 via vias V41 and V31, and the second adapter portion 373 is electrically connected to the drive circuit. That is, the first electrode connecting portion 61b in the first electrode 61 is electrically connected to the drive circuit via the connection between the first adapter portion 46 and the second adapter portion 373. On this basis, the adapter structure used to connect the first electrode layer to the drive circuit is overlapped with the first electrode layer, so that the multiple first electrodes 61 in the first electrode layer can be arranged more densely, thereby improving the resolution of the display substrate.

[0147] For example, referring to Figures 7A, 7E and 7F, the vias V41 and the vias V31 are arranged to partially overlap with the first electrode main body 61a, that is, the orthographic projections of the multiple first electrode main bodies 61a on the base substrate cover at least a portion of the orthographic projections of the multiple vias V41 and the multiple vias V31 on the base substrate.

[0148] For example, referring to FIG. 7A , the first transition portions 46 are partially overlapped with the first electrode main portions 61 a , that is, the orthographic projections of the plurality of first electrode main portions 61 a on the base substrate cover at least a portion of the orthographic projections of the plurality of first transition portions 46 on the base substrate.

[0149] For example, referring to FIG. 7A , the second transition portions 373 are partially overlapped with the first electrode main portions 61 a , that is, the orthographic projections of the plurality of first electrode main portions 61 a on the base substrate cover at least a portion of the orthographic projections of the plurality of second transition portions 373 on the base substrate.

[0150] According to some exemplary embodiments, referring to FIG. 7A , FIG. 7A schematically illustrates a pixel unit in a display substrate. The pixel unit includes three sub-pixels, for example, a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes a first driving circuit DC1 and a first light-emitting element, the second sub-pixel includes a second driving circuit DC2 and a second light-emitting element, and the third sub-pixel includes a third driving circuit DC3 and a third light-emitting element. In this pixel unit, the first driving circuit DC1, the second driving circuit DC2, and the third driving circuit DC3 are arranged sequentially along a first direction X. The plurality of first electrodes 61 include a plurality of first sub-electrodes 611, a plurality of second sub-electrodes 612, and a plurality of third sub-electrodes 613. The first sub-electrodes 611 serve as anodes for the first light-emitting elements, the second sub-electrodes 612 serve as anodes for the second light-emitting elements, and the third sub-electrodes 613 serve as anodes for the third light-emitting elements. The plurality of first adapters 46 include a plurality of first adapter sub-sections 461, a plurality of second adapter sub-sections 462, and a plurality of third adapter sub-sections 43.

[0151] The first sub-electrode 611 and the third sub-electrode 613 are arranged with an interval along the second direction Y, and the second sub-electrode 612 is located to one side of the first sub-electrode 611 and the third sub-electrode 613 along the first direction X. The orthographic projection of the first sub-electrode 611 on the substrate partially overlaps with the orthographic projection of the first drive circuit DC1 and the orthographic projection of the second drive circuit DC2 on the substrate. The orthographic projection of the third sub-electrode 613 on the substrate partially overlaps with the orthographic projection of the first drive circuit DC1 and the orthographic projection of the second drive circuit DC2 on the substrate. The orthographic projection of the second sub-electrode 612 on the substrate partially overlaps with the orthographic projection of the third drive circuit DC3 and the orthographic projection of the second drive circuit DC2 on the substrate.

[0152] 7A-7H , the first sub-electrode 611 includes a first sub-electrode main portion 611a and a first sub-electrode connecting portion 611b. The first sub-electrode connecting portion 611b is connected to the side of the first sub-electrode main portion 611a near the third sub-electrode 613. One end of the first transition sub-portion 461 is electrically connected to the first sub-electrode connecting portion 611b via a first via hole V51 in the second planarization layer. The other end of the first transition sub-portion 461 extends along the second direction Y and is electrically connected to the first second transition portion 373a via a first via hole V411 in the first planarization layer and a first via hole V311 in the passivation layer.

[0153] 7A-7H , the second sub-electrode 612 includes a second sub-electrode main portion 612a and a second sub-electrode connecting portion 612b. The second sub-electrode connecting portion 612b is connected to the side of the second sub-electrode main portion 612a near the first sub-electrode 611 and the third sub-electrode 613. One end of the second transition sub-portion 462 is electrically connected to the second sub-electrode connecting portion 612b via a second via hole V52 in the second planarization layer. The other end of the second transition sub-portion 462 extends along the second direction Y and is electrically connected to the second second transition portion 373b via a second via hole V412 in the first planarization layer and a second via hole V312 in the passivation layer.

[0154] 7A-7H , the third sub-electrode 613 includes a third sub-electrode main portion 613a and a third sub-electrode connecting portion 613b. The third sub-electrode connecting portion 613b is connected to a corner of the second sub-electrode main portion 613a that is away from the first sub-electrode 611 and closer to the second sub-electrode 612. The third sub-electrode connecting portion 613b extends along the first direction X and is electrically connected to one end of the third transition sub-portion 463 through a third via hole V53 in the second planarization layer. The other end of the third transition sub-portion 463 extends along the second direction Y and is electrically connected to the third second transition portion 373c through a third via hole V413 in the first planarization layer and a third via hole V313 in the passivation layer.

[0155] Referring to Figure 7A , to arrange the sub-pixels in a pixel unit more closely, the transition structure electrically connecting the first electrode to the driving circuit can be overlapped with the first electrode layer. For example, the orthographic projection of the second sub-electrode main portion 612a on the substrate overlaps the orthographic projection of the third second transition portion 373c on the substrate, and the orthographic projection of the second sub-electrode main portion 612a on the substrate overlaps a portion of the orthographic projection of the third transition sub-portion 463 on the substrate. The orthographic projection of the second sub-electrode main portion 612a on the substrate overlaps a portion of the orthographic projection of the second second transition portion 373b on the substrate. The orthographic projection of the third sub-electrode main portion 613a on the substrate overlaps the orthographic projection of the first second transition portion 373a on the substrate, and the orthographic projection of the third sub-electrode main portion 613a on the substrate overlaps the orthographic projection of the first transition sub-portion 461 on the substrate.

[0156] According to some exemplary embodiments, referring to FIG. 7D , the first conductive layer includes a data line 44, a first power signal line 43, a grid line 42, and a second power signal line 41 arranged along a first direction X. The first transfer portion 46 is in the shape of a strip extending along a second direction Y. The first transfer portion 46 is located between the grid line 42 and the second power signal line 41.

[0157] According to some exemplary embodiments, referring to 7H, the display substrate may further include a shielding portion 24 located in the second conductive layer, wherein the orthographic projection of the shielding portion 24 on the base substrate at least partially overlaps with the orthographic projection of the channel portion of the second transistor T2 on the base substrate. The shielding portion 24 is used to block at least part of the light directed toward the channel portion of the second transistor T2, which can effectively reduce the leakage probability of the second transistor T2 and improve the operating stability of the driving circuit.

[0158] According to some exemplary embodiments, referring to FIG. 2 , the pixel circuit has a 9T1C pixel circuit structure, and the pixel circuit includes a storage capacitor C1 and nine transistors T1 to T9 . For example, all transistors are N-type transistors, wherein the third transistor T3 is a driving transistor, and the other transistors are switching transistors.

[0159] 2 , a first electrode of the first transistor T1 is configured to receive a data signal Vdata, and a second electrode of the first transistor T1 is electrically connected to the second plate of the first storage capacitor C1. A first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3. A first electrode of the third transistor T3 is configured to receive a first power supply signal VDD, and the gate of the third transistor T3 is electrically connected to the first plate of the storage capacitor C1. A first electrode of the fourth transistor T4 is configured to receive a first initialization signal Vinit1, and the second electrode of the fourth transistor T4 is electrically connected to the gate of the third transistor T3. A first electrode of the fifth transistor T5 is configured to receive a reference voltage signal Vref, and the second electrode of the fifth transistor T5 is electrically connected to the second electrode D1 of the first transistor T1. A first electrode of the sixth transistor T6 is configured to receive the reference voltage signal Vref, and the second electrode of the sixth transistor T6 is electrically connected to the second electrode of the first transistor T1. A first electrode of the seventh transistor T7 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the light-emitting element. The first electrode of the eighth transistor T8 is configured to receive the second initialization signal Vinit2, the second electrode of the eighth transistor T8 is electrically connected to the first electrode of the light emitting element, the first electrode of the ninth transistor T9 is electrically connected to the gate of the third transistor T3, and the second electrode of the ninth transistor T9 is floating.

[0160] The gates of the first transistor T1 and the second transistor T2 are respectively configured to receive a scan signal Gate. The gates of the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are respectively configured to receive a reset signal Reset. The gates of the sixth transistor T6 and the seventh transistor T7 are respectively configured to receive a light-emission control signal EM.

[0161] The gate of the third transistor T3, the first plate of the storage capacitor, the second electrode of the second transistor T2, and the first electrode of the ninth transistor T9 are connected to a first node N1. The second plate of the storage capacitor, the second electrode of the first transistor T1, the second electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 are connected to a second node N2. The second electrode of the seventh transistor T7, the second electrode D8 of the eighth transistor T8, and the first electrode of the light-emitting element are connected to a third node N3.

[0162] According to some exemplary embodiments, the driving process of the driving circuit includes three stages: stage 1, stage 2, and stage 3, which are described below in conjunction with FIG. 2 .

[0163] In the first phase, under the control of the reset signal Reset, the fourth transistor T4 turns on, and the first initialization signal Vinit1 initializes the first node N1. At this time, the potential of the first node N1 is the first initialization signal Vinit1. The fifth transistor T5 turns on, and the reference voltage signal Vref is written to the second node N2. The eighth transistor T8 turns on to release the residual charge displayed in the previous frame, and the second initialization signal Vinit2 is written to the third node N3, which is the first electrode of the light-emitting element.

[0164] In the second phase, under the control of the scan signal Gate, the first transistor T1 turns on, and the data signal Vdata is written to the second node N2. The second transistor T2 turns on, sampling the diode connection of the third transistor T3. The potential of the first node N1 rises to VDD + Vth, and the third transistor T3 gradually changes from the on state to the off state, compensating for the threshold voltage Vth of the driving transistor T3.

[0165] In the third phase, under the control of the light-emission control signal EM, the sixth transistor T6 turns on, and the reference voltage signal Vref is written to the second node N2. The ninth transistor T9 turns on, reducing leakage at the first node N1 during the light-emission phase. As the potential of the second node N2 jumps, the potential at N2 becomes VDD + Vth + Vref - Vdata. Simultaneously, the seventh transistor T7 turns on, driving current output, causing the light-emitting element to emit light.

[0166] According to some exemplary embodiments, a display substrate includes a base substrate, and an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a passivation layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a first electrode layer, a pixel defining layer, a light-emitting functional layer, and a second electrode layer, sequentially disposed on the base substrate in a direction away from the base substrate. The active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer, the interlayer insulating layer, the first source / drain metal layer, the passivation layer, the first planarization layer, and the second source / drain metal layer constitute a driving circuit layer; the first electrode layer, the pixel defining layer, the light-emitting functional layer, and the second electrode layer constitute a light-emitting element layer. The first gate metal layer serves as the fourth conductive layer in the aforementioned embodiment, the second gate metal layer serves as the third conductive layer in the aforementioned embodiment, the first source / drain metal layer serves as the second conductive layer in the aforementioned embodiment, and the second source / drain metal layer serves as the first conductive layer in the aforementioned embodiment.

[0167] 8A-8H are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0168] 8A illustrates an active layer; FIG. 8B illustrates a first gate metal layer; FIG. 8C illustrates a second gate metal layer; FIG. 8D illustrates an interlayer insulating layer; FIG. 8E illustrates a first source / drain metal layer; FIG. 8F illustrates a passivation layer; FIG. 8G illustrates a first planarization layer; and FIG. 8H illustrates a second source / drain metal layer.

[0169] According to some exemplary embodiments, referring to FIG8A , the active layer includes at least some of the active portions of the aforementioned transistors. Exemplarily, the active layer includes the active portions of a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The active portion of each transistor includes a channel portion and a first electrode and a second electrode connected to either side of the channel portion. The channel portions of the aforementioned transistors in the same pixel circuit are integrally formed with the first electrode and the second electrode. Specifically, the active portion of the first transistor T1 includes a channel portion CH1 and a first electrode S1 and a second electrode D1 connected to either side of the channel portion CH1. The active portion of the second transistor T2 includes a channel portion CH2 and a first electrode S2 and a second electrode D2 connected to either side of the channel portion CH2. The active portion of the third transistor T3 includes a channel portion CH3 and a first electrode S3 and a second electrode D3 connected to either side of the channel portion CH3. The active portion of the fourth transistor T4 includes a channel portion CH4, and a first electrode S4 and a second electrode D4 connected to both sides of the channel portion CH4. The active portion of the fifth transistor T5 includes a channel portion CH5, and a first electrode S5 and a second electrode D5 connected to both sides of the channel portion CH5. The active portion of the sixth transistor T6 includes a channel portion CH6, and a first electrode S6 and a second electrode D6 connected to both sides of the channel portion CH6. The active portion of the seventh transistor T7 includes a channel portion CH7, and a first electrode S7 and a second electrode D7 connected to both sides of the channel portion CH7. The active portion of the eighth transistor T8 includes a channel portion CH8, and a first electrode S8 and a second electrode D8 connected to both sides of the channel portion CH8. The active portion of the ninth transistor T9 includes a channel portion CH9, and a first electrode S9 and a second electrode D9 connected to both sides of the channel portion CH9.

[0170] For example, the second transistor T2 is a dual-gate dual-channel transistor, and the channel portion CH2 of the second transistor T2 includes a first sub-channel portion CH21 and a second sub-channel portion CH22 that are spaced apart. The first sub-channel portion CH21 and the second sub-channel portion CH22 are connected via a channel connecting portion CH23.

[0171] For example, the fourth transistor T4 is a dual-gate dual-channel transistor, and the channel portion CH4 of the fourth transistor T4 includes a first sub-channel portion CH41 and a second sub-channel portion CH42 that are spaced apart. The first sub-channel portion CH41 and the second sub-channel portion CH42 are connected via a channel connecting portion CH43.

[0172] For example, the active portion of the second transistor T2 , the active portion of the third transistor T3 , the active portion of the seventh transistor T7 , and the active portion of the eighth transistor T8 are connected to each other as an integrated structure.

[0173] For example, the active portion of the fourth transistor T4 and the active portion of the ninth transistor T9 are connected as an integrated structure.

[0174] For example, the active portion of the fifth transistor T5 and the active portion of the sixth transistor T6 are connected to form an integral structure.

[0175] For example, the active portions of the first transistor T1 and the third transistor T3 are arranged in a Z-shape, the active portions of the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are arranged in a U-shape, and the active portions of the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are arranged in a straight line.

[0176] According to some exemplary embodiments, referring to FIG. 8B , the first gate metal layer may include a scan signal line 15 , a reset signal line 16 , a third conductive portion 13 , and a light emitting control signal line 14 .

[0177] For example, referring to FIG8A and FIG8B , the main portion of the scan signal line 15 extends along the first direction X. The scan signal line 15 transmits a scan signal. The orthographic projection of the scan signal line 15 on the substrate overlaps with the orthographic projection of the active portion of the first transistor T1 on the substrate. The overlapping portion of the scan signal line 15 and the active portion of the first transistor T1 serves as the gate G1 of the first transistor T1, and the overlapping portion of the active portion of the first transistor T1 and the scan signal line 15 serves as the channel CH1 of the first transistor T1. There are two overlapping areas between the orthographic projection of the scanning signal line 15 on the substrate and the orthographic projection of the active part of the second transistor T2 on the substrate. The two parts where the scanning signal line 15 overlaps with the active part of the second transistor T2 serve as the first gate G21 and the second gate G22 of the second transistor T2, respectively. The two parts where the active part of the second transistor T2 overlaps with the scanning signal line 15 serve as the first sub-channel part CH21 and the second sub-channel part CH22 of the second transistor T2, respectively. The part connected between the first sub-channel part CH21 and the second sub-channel part CH22 is the channel connection part CH23. The first sub-channel part CH21, the second sub-channel part CH22 and the channel connection part CH23 together serve as the channel part CH2 of the second transistor T2.

[0178] For example, referring to FIG8A and FIG8B , the main portion of the reset signal line 16 extends along the first direction X. The reset signal line 16 transmits a reset signal. The orthographic projection of the reset signal line 16 on the substrate overlaps with the orthographic projection of the active portion of the fifth transistor T5 on the substrate. The overlapping portion of the reset signal line 16 and the active portion of the fifth transistor T5 serves as the gate G5 of the fifth transistor T5, and the overlapping portion of the active portion of the fifth transistor T5 and the reset signal line 16 serves as the channel CH5 of the fifth transistor T5. There are two overlapping areas between the orthographic projection of the reset signal line 16 on the substrate and the orthographic projection of the active part of the fourth transistor T4 on the substrate. The two parts where the reset signal line 16 overlaps with the active part of the second transistor T2 serve as the first gate G41 and the second gate G42 of the fourth transistor T4, respectively. The two parts where the active part of the fourth transistor T4 overlaps with the reset signal line 16 serve as the first sub-channel part CH41 and the second sub-channel part CH42 of the fourth transistor T4, respectively. The part connected between the first sub-channel part CH41 and the second sub-channel part CH42 is the channel connection part CH43. The first sub-channel part CH41, the second sub-channel part CH42 and the channel connection part CH43 together serve as the channel part CH4 of the fourth transistor T4. The orthographic projection of the reset signal line 16 on the substrate partially overlaps with the orthographic projection of the active portion of the eighth transistor T8 on the substrate. The overlapping portion of the reset signal line 16 and the active portion of the eighth transistor T8 serves as the gate G8 of the eighth transistor T8. The overlapping portion of the active portion of the eighth transistor T8 and the reset signal line 16 serves as the channel CH8 of the eighth transistor T8.

[0179] For example, referring to FIG8A and FIG8B , the orthographic projection of the third conductive portion 13 on the substrate partially overlaps the orthographic projection of the active portion of the third transistor T3 on the substrate. The portion where the reset signal line 16 overlaps with the active portion of the third transistor T3 serves as the gate G3 of the third transistor T3, and the portion where the active portion of the third transistor T3 overlaps with the reset signal line 16 serves as the channel CH3 of the third transistor T3. The third conductive portion 13 can also serve as the first substrate of a storage capacitor.

[0180] For example, referring to FIG8A and FIG8B , the main portion of the light-emission control signal line 14 extends along the first direction X. The light-emission control signal line 14 transmits a light-emission control signal. The light-emission control signal line 14 overlaps with the orthographic projection of the active portion of the sixth transistor T6 on the substrate. The overlapping portion of the light-emission control signal line 14 and the active portion of the sixth transistor T6 serves as the gate G6 of the sixth transistor T6. The overlapping portion of the active portion of the sixth transistor T6 and the light-emission control signal line 14 serves as the channel CH6 of the sixth transistor T6. The light-emission control signal line 14 overlaps with the orthographic projection of the active portion of the seventh transistor T7 on the substrate. The overlapping portion of the light-emission control signal line 14 and the active portion of the seventh transistor T7 serves as the gate G7 of the seventh transistor T7. The overlapping portion of the active portion of the seventh transistor T7 and the light-emission control signal line 14 serves as the channel CH7 of the seventh transistor T7. The light-emitting control signal line 14 overlaps with the positive projection of the active part of the ninth transistor T9 on the base substrate. The overlapping part of the light-emitting control signal line 14 and the active part of the ninth transistor T9 serves as the gate G9 of the ninth transistor T9. The overlapping part of the active part of the ninth transistor T9 and the light-emitting control signal line 14 is the channel CH9 of the ninth transistor T9.

[0181] According to some exemplary embodiments, referring to FIG. 8C , the second gate metal layer may include a first power grid line 21 , a fourth conductive portion 22 , and a second initialization connection portion 23 .

[0182] For example, referring to FIG. 8C , the first power grid line 21 extends along the first direction X, and the first power grid line 21 is configured to transmit a first power signal.

[0183] For example, referring to FIG8B and FIG8C , the orthographic projection of the fourth conductive portion 22 on the substrate at least partially overlaps with the orthographic projection of the third conductive portion 13 on the substrate, and the fourth conductive portion 22 serves as the second plate of the storage capacitor. The fourth conductive portion 22 has a hollow structure 221, and the orthographic projection of the hollow structure 221 on the substrate is located within the orthographic projection of the third conductive portion 13 on the substrate.

[0184] For example, referring to FIG. 8C , the second initialization connection portion 23 is in a strip shape extending along the second direction Y. The second initialization connection portion 23 is used to electrically connect to other structures located on an upper layer.

[0185] According to some exemplary embodiments, referring to Figure 8D, the interlayer insulating layer has multiple vias, for example, the interlayer insulating layer has a first via V11, a second via V12, a third via V13, a fourth via V14, a sixth via V16, a seventh via V17, an eighth via V18, a ninth via V19, a tenth via V20, an eleventh via V21, a twelfth via V22, a thirteenth via V23, a fourteenth via V24, a fifteenth via V25, a sixteenth via V26 and an eighteenth via V28.

[0186] According to some exemplary embodiments, referring to Figure 8E, the first source-drain metal layer may include a first initialization signal line 31, a second initialization signal line 32, a reference voltage signal line 34, a second power grid line 36, a first initialization connection portion 371, a first power signal connection portion 372, a second transfer portion 373, a fourth connection structure 374, a fifth connection structure 375 and a sixth connection structure 376.

[0187] For example, referring to Figures 8A, 8C, 8D, and 8E, the first initialization signal line 31 extends along the first direction X and is used to transmit a first initialization signal. The first initialization signal line 31 is electrically connected to the second initialization connection portion 23 via a first via V11. The first initialization connection portion 371 is electrically connected to the second initialization connection portion 23 via a third via V13. The first initialization connection portion 371 is electrically connected to the first electrode S4 of the fourth transistor T4 via a fourth via V14. In other words, the first initialization signal line 31 is electrically connected to the first electrode S4 of the fourth transistor T4 via the second initialization connection portion 23 and the first initialization connection portion 371.

[0188] 8A , 8D and 8E , the second initialization signal line 32 extends along the first direction X and is used to transmit the second initialization signal. The second initialization signal line 32 is electrically connected to the first electrode S8 of the eighth transistor T8 through the second via V12 .

[0189] 8A , 8D , and 8E , the reference voltage signal line 34 extends along the first direction X. The reference voltage signal line 34 is used to transmit a reference voltage signal. The reference voltage signal line 34 is electrically connected to the first electrode S5 of the fifth transistor T5 and the first electrode S6 of the sixth transistor T6 through a sixth via V16.

[0190] For example, referring to FIG. 8E , the second power grid line 36 extends along the first direction X, and the second power grid line 36 is used for the second power signal.

[0191] For example, referring to Figures 8A, 8C, 8D, and 8E, the first power signal connection portion 372 extends along the second direction Y. The first power signal connection portion 372 is electrically connected to the first power grid line 21 through the seventh via V17 and the eighth via V18. The first power signal connection portion 372 is electrically connected to the first electrode S3 of the third transistor T3 through the thirteenth via V23. In other words, the first power grid line 21 is electrically connected to the first electrode S3 of the third transistor T3 through the first power signal connection portion 372.

[0192] For example, referring to FIG. 8A , FIG. 8D , and FIG. 8E , the second transfer portion 373 is electrically connected to the second electrode D2 of the seventh transistor T7 through the eleventh via hole V21 .

[0193] For example, with reference to Figures 8A-8E , the fourth connection structure 374 is electrically connected to the first electrode S9 of the ninth transistor T9 through the tenth via V20, the fourth connection structure 374 is electrically connected to the gate G3 of the third transistor T3 through the fourth via V14 and the hollow structure 221 of the fourth conductive portion 22, and the fourth connection structure 374 is electrically connected to the second electrode D2 of the second transistor T2 through the fifteenth via V25. That is, through the connection of the fourth connection structure 374, the first electrode S9 of the ninth transistor T9, the gate G3 of the third transistor T3, and the second electrode D2 of the second transistor T2 are electrically connected to the same node.

[0194] For example, referring to FIG8A , FIG8C , FIG8D , and FIG8E , the fifth connection structure 375 is electrically connected to the second electrode D5 of the fifth transistor T5 and the second electrode D6 of the sixth transistor T6 through the ninth via V19, the fifth connection structure 375 is electrically connected to the fourth conductive portion 22 through the twelfth via V22, and the fifth connection structure 375 is electrically connected to the second electrode D1 of the first transistor T1 through the fifteenth via V25. That is, through the fifth connection structure 375, the second electrode D5 of the fifth transistor T5, the second electrode D6 of the sixth transistor T6, the second plate of the storage capacitor, and the second electrode D1 of the first transistor T1 are electrically connected to the same node.

[0195] For example, referring to FIG. 8A , FIG. 8D , and FIG. 8E , the sixth connection structure 376 is electrically connected to the first electrode S1 of the first transistor T1 through the eighteenth via hole V28 .

[0196] According to some exemplary embodiments, referring to FIG. 8F , the passivation layer has a first via hole V31 , a second via hole V32 , a third via hole V33 , a fourth via hole V34 , and a fifth via hole V35 .

[0197] According to some exemplary embodiments, referring to FIG8G , the first planarization layer has a first via V41, a second via V42, a third via V43, a fourth via V44, and a fifth via V45. Referring to FIG8F and FIG8G , the first via V41 is nested with the first via V31, i.e., the orthographic projection of the first via V41 on the substrate overlaps the orthographic projection of the first via V31 on the substrate. The second via V42 is nested with the second via V32, i.e., the orthographic projection of the second via V42 on the substrate overlaps the orthographic projection of the second via V32 on the substrate. The third via V43 is nested with the third via V33, i.e., the orthographic projection of the third via V43 on the substrate overlaps the orthographic projection of the third via V33 on the substrate. The fourth via V44 is nested with the fourth via V34, i.e., the orthographic projection of the fourth via V44 on the substrate overlaps the orthographic projection of the fourth via V34 on the substrate. The fifth via hole V45 is nested with the fifth via hole V35 , that is, the orthographic projection of the fifth via hole V45 on the base substrate covers the orthographic projection of the fifth via hole V35 on the base substrate.

[0198] According to some exemplary embodiments, referring to FIG. 8H , the second source / drain metal layer may include a second power signal line 41 , a grid line 42 , a first power signal line 43 , a data line 44 , and a first electrode connection portion 45 .

[0199] According to some exemplary embodiments, with reference to FIG8E , FIG8F , FIG8G , and FIG8H , a second power signal line 41 extends along a second direction Y. The second power signal line 41 is configured to transmit a second power signal. The second power signal line 41 passes through the fifth via V45 , the fifth via V35 , and the second power grid line 36 .

[0200] 8E and 8H , the grid lines 42 extend along the second direction Y. A portion of the grid lines 42 may be electrically connected to the first initialization signal line 31 , a portion of the grid lines 42 may be electrically connected to the second initialization signal line 32 , and a portion of the grid lines 42 may be electrically connected to the reference voltage signal line 34 .

[0201] According to some exemplary embodiments, with reference to FIG8E , FIG8F , FIG8G , and FIG8H , the first power signal line 43 extends along the second direction Y. The first power signal line 43 is configured to transmit a first power signal. The first power signal line 43 is electrically connected to the third via V33 via the third via V43, and to the second via V32 via the second via V42 and the first power signal connection portion 372 via the first via V43. That is, the first power signal line 43 is electrically connected to the first power grid line 21 via the first power signal connection portion 372.

[0202] According to some exemplary embodiments, with reference to FIG8E , FIG8F , FIG8G , and FIG8H , the data line 44 extends along the second direction Y and is configured to transmit a data signal. The data line 44 is electrically connected to the sixth connection structure 376 through the fourth via V44 and the fourth via V34. Specifically, the data line 44 is electrically connected to the first electrode S1 of the first transistor T1 through the sixth connection structure 376.

[0203] According to some exemplary embodiments, with reference to Figures 8E, 8F, 8G and 8H, the first electrode connecting portion 45 is electrically connected to the third connection structure 373 through the first via V41, the first via V31, and the third connection structure 373, that is, the first electrode connecting portion 45 is electrically connected to the second electrode D2 of the seventh transistor T7 through the third connection structure 373, and the first electrode connecting portion 45 is also used to be electrically connected to the first electrode located on the upper side.

[0204] According to some exemplary embodiments, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the passivation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer structure, or a composite layer. The first planarization layer and the second planarization layer may be made of organic materials, such as resin.

[0205] At least some embodiments of the present disclosure further provide a display device comprising the display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0206] It should be understood that the display panel and display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above. For details, please refer to the above description and will not be repeated here. Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged along a first direction and / or a second direction, the first direction intersecting the second direction, the sub-pixels comprising a light-emitting element and a driving circuit electrically connected to the light-emitting element; a first initialization signal transmission structure, located on the base substrate, the first initialization signal transmission structure being electrically connected to the driving circuit and configured to input a first initialization signal to the driving circuit; a second initialization signal transmission structure, located on the base substrate, the second initialization signal transmission structure being electrically connected to the driving circuit and configured to input a second initialization signal to the driving circuit; a reference voltage signal transmission structure, located on the base substrate, the reference voltage signal transmission structure being electrically connected to the driving circuit and configured to provide the driving circuit with a reference voltage signal; and a second power signal transmission structure, located on the base substrate, the second power signal transmission structure being electrically connected to the second electrode of the light-emitting element and being used to connect a second power signal to the second electrode; The orthographic projection of at least one of the first initialization signal transmission structure, the second initialization signal transmission structure, the reference voltage signal transmission structure and the second power signal transmission structure on the base substrate is in a grid shape.

2. The display substrate according to claim 1, wherein The display substrate includes a first conductive layer located on the base substrate and a second conductive layer located between the first conductive layer and the base substrate; The first initialization signal transmission structure includes a plurality of first initialization signal lines located in the second conductive layer and a plurality of first initialization grid lines located in the first conductive layer, the plurality of first initialization signal lines extending along the first direction and arranged along the second direction, the plurality of first initialization grid lines extending along the second direction and arranged along the first direction, the first initialization grid line being electrically connected to at least one of the first initialization signal lines; and / or The second initialization signal transmission structure includes a plurality of second initialization signal lines located in the second conductive layer and a plurality of second initialization grid lines located in the first conductive layer, wherein the plurality of second initialization signal lines extend along the first direction and are arranged along the second direction, and the plurality of second initialization grid lines extend along the second direction. The first initialization grid lines are arranged along the first direction, and the second initialization grid lines are electrically connected to at least one second initialization signal line; and / or The reference voltage signal transmission structure includes a plurality of reference voltage signal lines located in the second conductive layer and a plurality of reference voltage grid lines located in the first conductive layer, the plurality of reference voltage signal lines extending along the first direction and arranged along the second direction, the plurality of reference voltage grid lines extending along the second direction and arranged along the first direction, the reference voltage grid line being electrically connected to at least one of the reference voltage signal lines; and / or The second power signal transmission structure includes a plurality of second power signal lines located in the first conductive layer and a plurality of second power grid lines located in the second conductive layer, the plurality of second power signal lines extending along the second direction and arranged along the first direction, the plurality of second power grid lines extending along the first direction and arranged along the second direction, and the second power grid line is electrically connected to at least one second power signal line.

3. The display substrate according to claim 2, wherein: The first conductive layer includes a plurality of first routing groups arranged along the first direction, the first routing groups include three second power signal lines and three grid lines, the three second power signal lines and the three grid lines are alternately arranged along the first direction, and the three grid lines include one first initialization grid line, one second initialization grid line and one reference voltage grid line.

4. The display substrate according to claim 3, wherein: The first routing group includes three first routing subgroups arranged along the first direction, and the first routing subgroup includes one second power signal line and one grid line; The first wiring subgroup further includes a first power signal line and a data line, and the first power signal line and the data line are located on one side of the grid line and the second power signal line along the first direction.

5. The display substrate according to claim 2, wherein: The first conductive layer includes a plurality of first routing groups arranged along the first direction, the first routing group includes one second power signal line and three grid lines, the three grid lines include one first initialization grid line, one second initialization grid line, and one reference voltage grid line; The second power signal line is located on one side of the three grid lines along the first direction, or the second power signal line is located between two of the three grid lines. The display substrate according to claim 5 , wherein: The first routing group includes three first routing sub-groups arranged in the first direction, two of the first routing sub-groups each include one of the grid lines, and the remaining first routing sub-group includes one of the grid lines and one of the second power signal lines; In which, the first routing subgroup also includes a first power signal line and a data line, the first power signal line and the data line are located on one side of the grid line along the first direction, or the first power signal line and the data line are located on one side of the grid line and the second power signal line along the first direction.

7. The display substrate according to any one of claims 2 to 6, wherein: The second conductive layer includes a plurality of second wiring groups arranged along the second direction, and the second wiring groups include one first initialization signal line, one second initialization signal line, one reference voltage signal line, and one second power grid line arranged along the second direction.

8. The display substrate according to any one of claims 1 to 7, wherein: The display substrate also includes a first power signal transmission structure located on the base substrate. The first power signal transmission structure is electrically connected to the driving circuit and is used to connect a first power signal to the driving circuit. The orthographic projection of the first power signal transmission structure on the base substrate is in a grid shape.

9. The display substrate according to claim 8, wherein: The display substrate includes a first conductive layer located on the base substrate, a second conductive layer located between the first conductive layer and the base substrate, and a third conductive layer located between the second conductive layer and the base substrate; The first power signal transmission structure includes a plurality of first power signal lines located in the first conductive layer, a plurality of first power signal connection portions located in the second conductive layer, and a plurality of first power grid lines located in the third conductive layer, the plurality of first power signal lines being arranged along the first direction and extending along the second direction, and the plurality of first power grid lines being arranged along the second direction and extending along the first direction; The first power grid line is electrically connected to at least one first power signal line through at least one first power signal connection portion. The first power signal connection portion is electrically connected to the driving circuit and is used to connect the first power signal to the driving circuit.

10. The display substrate according to claim 9, wherein: The orthographic projection of the first power signal connection portion on the base substrate is located within the orthographic projection of the first power signal line on the base substrate.

11. The display substrate according to any one of claims 1 to 10, wherein: The driving circuit includes a first transistor, a second transistor, a third transistor and a first storage capacitor; The first electrode of the first transistor is configured to receive a data signal, and the second electrode of the first transistor is electrically connected to the second plate of the first storage capacitor; The first electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the gate of the third transistor; as well as The first electrode of the third transistor is configured to receive a first power supply signal, and the gate of the third transistor is electrically connected to the first plate of the first storage capacitor; The gate of the first transistor and the gate of the second transistor are respectively configured to receive a scan signal.

12. The display substrate according to claim 11, wherein: The display substrate includes a second conductive layer located on the base substrate and a fourth conductive layer located between the second conductive layer and the base substrate, and the gate of the first transistor and the gate of the second transistor are located in the fourth conductive layer; and The display substrate further includes a scanning signal line located in the second conductive layer, the scanning signal line being electrically connected to the gate of the first transistor and the gate of the second transistor respectively, and the scanning signal line being used to connect a scanning signal to the gate of the first transistor and the gate of the second transistor.

13. The display substrate according to claim 11, wherein: The driving circuit further includes a fourth transistor, a fifth transistor and an eighth transistor; A first electrode of the fourth transistor is configured to receive a first initialization signal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor; A first electrode of the fifth transistor is configured to receive a reference voltage signal, and a second electrode of the fifth transistor is electrically connected to the second electrode of the first transistor; and The first electrode of the eighth transistor is configured to receive the second initialization signal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element; The gate of the fourth transistor, the gate of the fifth transistor and the gate of the eighth transistor are respectively configured to receive a reset signal.

14. The display substrate according to claim 13, wherein: The display substrate includes a second conductive layer located on the base substrate and a fourth conductive layer located between the second conductive layer and the base substrate, wherein the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the eighth transistor are located in the fourth conductive layer; and The display substrate also includes a reset signal line located in the second conductive layer, the reset signal line is electrically connected to the gate of the fourth transistor, the gate of the fifth transistor and the gate of the eighth transistor, respectively, and the reset signal line is used to connect the scanning signal to the gate of the fourth transistor, the gate of the fifth transistor and the gate of the eighth transistor.

15. The display substrate according to any one of claims 11 to 14, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel including a first driving circuit and a first light-emitting element electrically connected to the first driving circuit, the second sub-pixel including a second driving circuit and a second light-emitting element electrically connected to the second driving circuit, and the third sub-pixel including a third driving circuit and a third light-emitting element electrically connected to the third driving circuit; The active portion of the third transistor comprises a channel portion, a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively connected to two sides of the channel portion along the first direction; as well as The third transistor in the first driving circuit has a first channel portion, the third transistor in the second driving circuit has a second channel portion, and the third transistor in the third driving circuit has a third channel portion; wherein a ratio of a size of the first channel portion along the first direction to a size of the second channel portion along the second direction is different from a ratio of a size of the second channel portion along the first direction to a size of the second direction; and / or A ratio of a size of the first channel portion along the first direction to a size of the second direction is different from a ratio of a size of the third channel portion along the first direction to a size of the second direction; and / or A ratio of a size of the second channel portion along the first direction to a size of the second direction is different from a ratio of a size of the third channel portion along the first direction to a size of the second direction.

16. The display substrate according to claim 15, wherein: The first light emitting element emits red light, the second light emitting element emits green light, and the third light emitting element emits blue light; The ratio of the size of the third channel portion along the first direction to the size along the second direction is greater than a ratio of a dimension of the first channel portion along the first direction to a dimension of the first channel portion along the second direction; and / or A ratio of a dimension of the third channel portion along the first direction to a dimension of the third channel portion along the second direction is greater than a ratio of a dimension of the second channel portion along the first direction to a dimension of the second channel portion along the second direction.

17. The display substrate according to claim 16, wherein: The dimension of the third channel portion along the first direction is equal to the dimension of the first channel portion along the first direction, and the dimension of the third channel portion along the second direction is smaller than the dimension of the first channel portion along the second direction; and / or A size of the third channel portion along the first direction is equal to a size of the second channel portion along the first direction, and a size of the third channel portion along the second direction is smaller than a size of the second channel portion along the second direction.

18. The display substrate according to any one of claims 1 to 17, wherein: The display substrate comprises a second conductive layer located on the base substrate, an insulating layer located on a side of the second conductive layer away from the base substrate, a first conductive layer located on a side of the insulating layer away from the base substrate, and a first electrode layer located on a side of the first conductive layer away from the base substrate; The first electrode layer includes a plurality of first electrodes, each of the first electrodes including a first electrode main body and a first electrode connecting portion connected to the first electrode main body; The first conductive layer includes a plurality of first transition portions, the second conductive layer includes a plurality of second transition portions, the insulating layer has a plurality of via holes, and the plurality of via holes respectively expose at least a portion of the plurality of second transition portions; and The first electrode connecting portion is electrically connected to the first transition portion, the first transition portion is electrically connected to the second transition portion through the via hole, and the second transition portion is electrically connected to the driving circuit; wherein the orthographic projections of the plurality of first electrode main bodies on the base substrate cover at least a portion of the orthographic projections of the plurality of via holes on the base substrate; and / or The orthographic projections of the plurality of first electrode main bodies on the base substrate cover at least a portion of the orthographic projections of the plurality of first transition portions on the base substrate; and / or The orthographic projections of the plurality of first electrode main bodies on the base substrate cover at least a portion of the orthographic projections of the plurality of second transition portions on the base substrate.

19. The display substrate according to claim 18, wherein: The plurality of first electrodes include a plurality of first sub-electrodes, a plurality of second sub-electrodes, and a plurality of third sub-electrodes; the plurality of first transition portions include a plurality of first transition sub-portions, a plurality of second transition sub-portions, and a plurality of third transition sub-portions; The first sub-electrode and the third sub-electrode are arranged at intervals along the second direction, and the second sub-electrode is located on one side of the first sub-electrode and the third sub-electrode along the first direction; The first sub-electrode includes a first sub-electrode main portion and a first sub-electrode connecting portion connected to a side of the first sub-electrode main portion close to the third sub-electrode, one end of the first adapter sub-portion is electrically connected to the first sub-electrode connecting portion, and the other end of the first adapter sub-portion extends along the second direction and is electrically connected to the second adapter portion; The second sub-electrode includes a second sub-electrode main portion and a second sub-electrode connecting portion connected to a side of the second sub-electrode main portion close to the first sub-electrode and the third sub-electrode, one end of the second transition sub-portion is electrically connected to the second sub-electrode connecting portion, and the other end of the second transition sub-portion extends along the second direction and is electrically connected to the second transition portion; and The third sub-electrode includes a third sub-electrode main portion and a third sub-electrode connecting portion connected to a corner of the second sub-electrode main portion away from the first sub-electrode and close to the second sub-electrode, the third sub-electrode connecting portion extending along the first direction and electrically connected to one end of the third adapter sub-portion, and the other end of the third adapter sub-portion extending along the second direction and electrically connected to the second adapter portion; Among them, the orthographic projection of the second adapter portion electrically connected to the first adapter sub-portion on the base substrate is located within the orthographic projection of the third sub-electrode main portion on the base substrate; the orthographic projection of the second adapter portion electrically connected to the third adapter sub-portion on the base substrate is located within the orthographic projection of the second sub-electrode main portion on the base substrate.

20. A display device, wherein: The display device includes the display substrate according to any one of claims 1 to 19.

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