Display substrate, manufacturing method therefor, and display apparatus

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of repeating units (100); at least one repeating unit (100) comprises a display area (110) and a light-transmitting area (120); the display area (100) comprises a plurality of sub-pixels; at least one sub-pixel comprises a pixel driving circuit and a light-emitting device connected to the pixel driving circuit; the pixel driving circuit is separately connected to a first power line (71), data signal lines (61-64) and a compensation signal line (73); the light-emitting device is connected to a second power line (72); the display area comprises a first area (110-1) and a second area (110-2); the pixel driving circuits of the plurality of sub-pixels are arranged in the first area (110-1), and the first power line (71), the second power line (72), the compensation signal line (73) and the data signal lines (61-64) are arranged in the second area (110-2).

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of active light emission, ultra-thin, wide viewing angle, high brightness, high contrast, low power consumption, extremely high response speed, light and thin, special shape and flexible display, and has gradually become the next generation display technology with great development prospects. Among them, an active matrix (AM) OLED is a current driven device, which uses an independent transistor (TFT) to control each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light.

[0003] With the continuous development of display technology, OLED technology is more and more applied to transparent display. Transparent display is an important personalized display field of display technology, which refers to image display in a transparent state. The viewer can not only see the image in the display device, but also see the scene behind the display device, which can realize virtual reality (VR) and augmented reality (AR) and 3D display functions. The transparent display device using OLED technology usually divides each sub-pixel into a display area and a light transmission area. The display area sets a pixel driving circuit and a light emitting device to realize image display, and the light transmission area realizes light transmission.

[0004] SUMMARY

[0005] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0006] In one aspect, the present disclosure provides a display substrate, comprising a plurality of repeating units arranged regularly, at least one repeating unit comprising a display area and a light-transmitting area arranged on a side of the display area in a first direction or a side of the display area in a reverse direction of the first direction, the display area being configured to display an image, the light-transmitting area being configured to transmit light, the display area comprising a plurality of sub-pixels arranged in sequence along a second direction, the first direction and the second direction intersecting; at least one sub-pixel comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit being connected to a first power line, a data signal line and a compensation signal line respectively, the light-emitting device being connected to a second power line; the display area comprising a first area and a second area arranged on a side of the first area away from the light-transmitting area, the pixel driving circuits of the plurality of sub-pixels being arranged in the first area, the first power line, the second power line, the data signal line and the compensation signal line being arranged in the second area.

[0007] In an exemplary embodiment, in the first direction, the compensation signal line is arranged between the data signal line and the first power line, and the first power line is arranged between the compensation signal line and the second power line.

[0008] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers arranged on a substrate, the first power line and the data signal line are arranged in the same conductive layer, the compensation signal line and the second power line are arranged in the same conductive layer, and the first power line and the second power line are arranged in different conductive layers.

[0009] In an exemplary embodiment, the data signal line comprises a first data signal line, a second data signal line, a third data signal line and a fourth data signal line arranged in sequence along the first direction; the first distance between adjacent data signal lines, the second distance between the fourth data signal line and the compensation signal line, the third distance between the first power line and the compensation signal line, and the fourth distance between the first power line and the second power line, the second distance being smaller than the first distance, the third distance being smaller than the first distance, and the fourth distance being smaller than the first distance.

[0010] In an exemplary embodiment, the pixel driving circuit comprises at least a first transistor, a second transistor, a third transistor and a storage capacitor, a first electrode of the first transistor is connected with the data signal line, a second electrode of the first transistor is connected with a gate electrode of the second transistor and a first end of the storage capacitor respectively, a first electrode of the second transistor is connected with the first power supply line, a second electrode of the second transistor is connected with a second electrode of the third transistor and a second end of the storage capacitor respectively, a first electrode of the third transistor is connected with the compensation signal line; in the plurality of sub-pixels of at least one repeating unit, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected with the same scan signal line.

[0011] In an exemplary embodiment, in at least one repeating unit, the scan signal line comprises a scan transmission line arranged in the light-transmitting region and a first annular structure and a second annular structure arranged in the display region, a first end of the scan transmission line is connected with the second annular structure in the repeating unit, and a second end of the scan transmission line is connected with the second annular structure in the repeating unit adjacent to the first direction.

[0012] In an exemplary embodiment, in at least one repeating unit and the repeating unit adjacent to the first direction, the scan transmission lines in the two repeating units are not on the same straight line extending along the first direction.

[0013] In an exemplary embodiment, the display region comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along the second direction, the first annular structure is arranged in the first sub-pixel and the second sub-pixel, the second annular structure is in the third sub-pixel and the fourth sub-pixel, and the first annular structure and the second annular structure are connected with each other through a ring connection line.

[0014] In an exemplary embodiment, in at least one repeating unit, the first annular structure, the second annular structure and the ring connection line are an integrated structure connected with each other.

[0015] In an exemplary embodiment, the first ring-shaped structure or the second ring-shaped structure comprises at least two gate electrode lines, a first scan connection line and a second scan connection line, the gate electrode lines are in a shape of a straight line or a broken line extending along the first direction, the two gate electrode lines are respectively arranged in two sub-pixels, the first scan connection line and the second scan connection line are in a shape of a straight line or a broken line extending along the second direction, the first scan connection line is connected with the end part of the two gate electrode lines in the opposite direction of the first direction respectively, and the second scan connection line is connected with the end part of the two gate electrode lines in the first direction respectively, thereby forming the first ring-shaped structure or the second ring-shaped structure.

[0016] In an exemplary embodiment, in at least one repeating unit, the two gate electrode lines, the first scan connection line and the second scan connection line in the first ring-shaped structure or the second ring-shaped structure are an integrated structure connected with each other.

[0017] In an exemplary embodiment, the first ring-shaped structure and the second ring-shaped structure are in a shape of a ring, and the first ring-shaped structure and the second ring-shaped structure are in a shape of a ring.

[0018] In an exemplary embodiment, the first ring-shaped structure is provided with a first protruding structure protruding towards the light-transmitting area, and a projection of the first protruding structure on a display substrate plane at least partially overlaps with a projection of the light-transmitting area on the display substrate plane; and / or, the second ring-shaped structure is provided with a second protruding structure protruding towards the light-transmitting area, and a projection of the second protruding structure on the display substrate plane at least partially overlaps with the projection of the light-transmitting area on the display substrate plane.

[0019] In an exemplary embodiment, in at least one repeating unit, the protruding lengths of the first protruding structure and the second protruding structure are different, and the protruding length is a dimension of the first direction.

[0020] In an exemplary embodiment, in at least one repeating unit, a first protruding width and a second protruding width in the first protruding structure are different, the first protruding width is a dimension of the first protruding structure on a side of the gate electrode line away from the ring connection line, and the second protruding width is a dimension of the first protruding structure on a side of the gate electrode line close to the ring connection line; and / or, a third protruding width and a fourth protruding width in the second protruding structure are different, the third protruding width is a dimension of the second protruding structure on a side of the gate electrode line close to the ring connection line, and the fourth protruding width is a dimension of the second protruding structure on a side of the gate electrode line away from the ring connection line.

[0021] In an exemplary embodiment, in at least one repeating unit, a third protruding structure is further included, the third protruding structure is disposed on a side of the pixel driving circuit away from the first protruding structure or the second protruding structure, the third protruding structure protrudes towards the light-transmitting region, a normal projection of the third protruding structure on a display substrate plane at least partially overlaps with a normal projection of the light-transmitting region on the display substrate plane; the plate connection electrode includes a plate connection strip and a plate connection block, a first end of the plate connection strip is connected to a fifth plate of the storage capacitor, a second end of the plate connection strip extends to the light-transmitting region and is connected to the plate connection block; the anode connection electrode includes a first sub-connection electrode, a second sub-connection electrode, and a third sub-connection electrode, a first end of the first sub-connection electrode is connected to a first sub-anode of the light-emitting device, a first end of the second sub-connection electrode is connected to a second sub-anode of the light-emitting device, a second end of the first sub-connection electrode and a second end of the second sub-connection electrode extend to the light-transmitting region and are respectively connected to a first end and a second end of the third sub-connection electrode, the third sub-connection electrode is connected to the plate connection block through a via hole; a fifth protruding width is provided between the first sub-connection electrode and the plate connection strip or between the second sub-connection electrode and the plate connection strip, the first protruding width is greater than the fifth protruding width, the second protruding width is greater than the fifth protruding width, the third protruding width is greater than the fifth protruding width, and the fourth protruding width is greater than the fifth protruding width.

[0022] In an exemplary embodiment, the storage capacitor includes a first capacitor and a second capacitor in parallel, the first capacitor includes a first plate and a second plate stacked, the first plate and the second plate have an overlapping area in the orthographic projection on the display substrate plane, the second capacitor includes a third plate, a fourth plate and a fifth plate stacked, the third plate, the fourth plate and the fifth plate have an overlapping area in the orthographic projection on the display substrate plane; the first plate and the third plate are connected, the third plate and the fifth plate are connected, and the second plate and the fourth plate are connected.

[0023] In an exemplary embodiment, in the direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a base, a first conductive layer disposed on the side of the first transparent conductive layer away from the base, and a semiconductor layer disposed on the side of the first conductive layer away from the base; the first plate is disposed in the first transparent conductive layer, and the second plate is disposed in the semiconductor layer, forming a transparent first capacitor.

[0024] In an exemplary embodiment, the orthographic projection of the first plate and the second plate on the base at least partially overlaps the orthographic projection of the light-transmitting area on the base.

[0025] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the base, and a third conductive layer disposed on the side of the second conductive layer away from the base; the third plate is disposed in the first conductive layer, the fourth plate is disposed in the second conductive layer, and the fifth plate is disposed in the third conductive layer.

[0026] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the base, and a third conductive layer disposed on the side of the second conductive layer away from the base; the third plate is disposed in the first conductive layer, the fourth plate is disposed in the semiconductor layer, and the fifth plate is disposed in the third conductive layer.

[0027] In another aspect, the present disclosure also provides a display device including the aforementioned display substrate.

[0028] In yet another aspect, the present disclosure also provides a method for manufacturing a display substrate, the display substrate comprising a plurality of repeating units arranged in a regular pattern, at least one repeating unit comprising a display area and a light-transmitting area disposed on a side of the display area in a first direction or a side of the display area in a reverse direction of the first direction, the display area being configured to display an image, the light-transmitting area being configured to transmit light, the display area comprising a plurality of sub-pixels disposed in sequence along a second direction, the first direction and the second direction being intersected; the method comprising:

[0029] forming a pixel driving circuit and a light-emitting device connected to the pixel driving circuit in at least one sub-pixel, the pixel driving circuit being connected to a first power line, a data signal line and a compensation signal line respectively, the light-emitting device being connected to a second power line; the display area comprising a first area and a second area disposed on a side of the first area away from the light-transmitting area, the pixel driving circuit of the plurality of sub-pixels being disposed in the first area, the first power line, the second power line, the data signal line and the compensation signal line being disposed in the second area.

[0030] Other aspects can become apparent after reading the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0032] FIG. 1 is a structural schematic diagram of a display device;

[0033] FIG. 2 is a planar structural schematic diagram of a display substrate;

[0034] FIG. 3 is a schematic diagram of the arrangement of sub-pixels in a repeating unit according to an exemplary embodiment of the present disclosure;

[0035] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0036] FIG. 5 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] FIG. 6 is a structural schematic diagram of a storage capacitor according to an exemplary embodiment of the present disclosure;

[0038] FIG. 7 is a schematic diagram of a display substrate after forming a first transparent conductive layer pattern according to the present disclosure;

[0039] FIGS. 8A and 8B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0040] FIGS. 9A and 9B are schematic diagrams of a display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0041] FIGS. 10A and 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0042] FIG. 10C is a schematic diagram of a display substrate for repairing a short circuit defect according to the present disclosure;

[0043] FIG. 11 is a schematic diagram of a display substrate after forming a third insulating layer pattern according to the present disclosure;

[0044] FIGS. 12A and 12B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0045] FIG. 13 is a schematic diagram of a display substrate after forming a fourth insulating layer and a first planarization layer pattern according to the present disclosure;

[0046] FIGS. 14A and 14B are schematic diagrams of a display substrate after forming a second transparent conductive layer pattern according to the present disclosure;

[0047] FIG. 15 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0048] FIG. 16 is a schematic diagram of another structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0049] FIG. 17 is a schematic diagram of another structure of a storage capacitor according to an exemplary embodiment of the present disclosure;

[0050] FIGS. 18A and 18B are schematic diagrams of another display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0051] FIGS. 19A and 19B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0052] FIG. 20 is a schematic diagram of another display substrate after forming a third insulating layer pattern according to the present disclosure;

[0053] FIGS. 21A and 21B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure.

[0054] Explanation of reference numerals: 10-1 - first capacitor; 10-2 - second capacitor; 11 - first plate; 12 - second plate; 13 - third plate; 14 - fourth plate; 15 - fifth plate; 21 - first active layer; 22 - second active layer; 23 - third active layer; 30 - scan signal line; 30A - first ring structure; 30B - second ring structure; 31 - gate electrode line; 32 - second gate electrode; 33 - first scan connection line; 34 - second scan connection line; 35 - ring connection line; 36 - scan transfer line; 37 - first protruding structure; 38 - second protruding structure; 41 - first connection electrode; 42 - second connection electrode; 43 - third connection electrode; 44 - fourth connection electrode; 45 - fifth connection electrode; 46 - sixth connection electrode; 47 - seventh connection electrode; 48 - eighth connection electrode; 49 - ninth connection electrode; 50 - tenth connection electrode; 51 - eleventh connection electrode; 52 - twelfth connection electrode; 53 - thirteenth connection electrode; 54 - fourteenth connection electrode; 55 - fifteenth connection electrode; 56 - sixteenth connection electrode; 61 - first data signal line; 62 - second data signal line; 63 - third data signal line; 64 - fourth data signal line; 71 - first power supply line; 72 - second power supply line; 73 - compensation signal line; 81 - plate connection electrode; 82 - auxiliary connection electrode; 91 - anode; 92 - anode connection electrode; 93 - auxiliary cathode; 100 - repeating unit; 110 - display area; 110-1 - first area; 110-2 - second area; 120 - transparent area; 300 - substrate; 301 - first insulating layer; 302 - second insulating layer; 303 - third insulating layer. DETAILED DESCRIPTION

[0055] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be combined with the accompanying drawings to describe embodiments of the present disclosure in detail. It is noted that the embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the means and content can be varied into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0056] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0057] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of constituent elements, and are not intended to be limiting in terms of number.

[0058] In the present specification, for the convenience of description, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the constituent elements with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0059] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0060] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0061] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor having opposite polarity or in the case where the direction of current changes in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0062] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0063] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0064] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0065] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or deformation.

[0066] In this specification, "about" means not strictly limited to the limit and allows a range of values within a process and measurement error.

[0067] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the OLED display device can include a timing controller, a data driver, a scan driver, and a pixel array, the timing controller is connected to the data driver and the scan driver respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively, and the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively. The pixel array can include a plurality of sub-pixels Pxij, each of the sub-pixels Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, i and j can be natural numbers. At least one of the sub-pixels Pxij can include at least a circuit unit and a display unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line and the data signal line respectively, the display unit can include at least a light emitting device, the light emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel Pxij can refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, and can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller, n can be a natural number. For example, the data driver can sample the gray value using the clock signal, and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixels. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, etc. from the timing controller. For example, the scan driver can sequentially provide the scan signal having a turn-on level pulse to the scan signal lines S1 to Sm, m can be a natural number. The scan driver can be configured in the form of a shift register, and can generate the scan signal in such a way that the scan start signal provided in the form of a turn-on level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0068] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, in an exemplary embodiment, the display substrate can include a plurality of repeating units 100 arranged regularly, and at least one repeating unit 100 can include a display area 110 and a light-transmitting area 120. The display area 110 can include a plurality of sub-pixels, and at least one sub-pixel can include a circuit unit and a light-emitting unit. The circuit unit can include at least a pixel driving circuit, and the light-emitting unit can include at least a light-emitting device. The light-emitting device of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit, and the display area 110 is configured to display images. The light-transmitting area 120 can be located on at least one side of the display area 110 in the repeating unit 100, and the light-transmitting area 120 is configured to transmit light, so that the repeating unit 100 can realize image display in a transparent state, i.e., transparent display. In an exemplary embodiment, the repeating unit is a basic unit that constitutes the display substrate, and the display substrate is formed by repeatedly and continuously arranging the repeating units in at least one direction.

[0069] An exemplary embodiment of the present disclosure provides a display substrate including a plurality of repeating units arranged regularly, and at least one repeating unit including a display area and a light-transmitting area arranged on a first direction side or a reverse direction side of the display area. The display area is configured to display images, and the light-transmitting area is configured to transmit light. The display area includes a plurality of sub-pixels arranged in sequence along a second direction, and the first direction and the second direction intersect. At least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit is connected to a first power line, a data signal line, and a compensation signal line, respectively. The light-emitting device is connected to a second power line. The display area includes a first area and a second area arranged on a side of the first area away from the light-transmitting area. The pixel driving circuit of the plurality of sub-pixels is arranged in the first area, and the first power line, the second power line, the data signal line, and the compensation signal line are arranged in the second area.

[0070] In an exemplary embodiment, in the first direction, the compensation signal line is arranged between the data signal line and the first power line, and the first power line is arranged between the compensation signal line and the second power line.

[0071] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers arranged on a substrate. The first power line and the data signal line are arranged in the same conductive layer, the compensation signal line and the second power line are arranged in the same conductive layer, and the first power line and the second power line are arranged in different conductive layers.

[0072] In an example embodiment, the storage capacitor includes a first capacitor and a second capacitor in parallel, the first capacitor includes a first plate and a second plate stacked, the first plate and the second plate have an overlapping area in a projection on a display substrate plane, the second capacitor includes a third plate, a fourth plate and a fifth plate stacked, the third plate, the fourth plate and the fifth plate have an overlapping area in a projection on a display substrate plane; the first plate and the third plate are connected, the third plate and the fifth plate are connected, and the second plate and the fourth plate are connected.

[0073] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a base, a first conductive layer disposed on a side of the first transparent conductive layer away from the base, and a semiconductor layer disposed on a side of the first conductive layer away from the base; the first plate is disposed in the first transparent conductive layer, and the second plate is disposed in the semiconductor layer, forming a transparent first capacitor.

[0074] In an example embodiment, the display substrate further includes a second conductive layer disposed on a side of the semiconductor layer away from the base, and a third conductive layer disposed on a side of the second conductive layer away from the base; the third plate is disposed in the first conductive layer, the fourth plate is disposed in the second conductive layer, and the fifth plate is disposed in the third conductive layer.

[0075] In an example embodiment, the display substrate further includes a second conductive layer disposed on a side of the semiconductor layer away from the base, and a third conductive layer disposed on a side of the second conductive layer away from the base; the third plate is disposed in the first conductive layer, the fourth plate is disposed in the semiconductor layer, and the fifth plate is disposed in the third conductive layer.

[0076] The display substrate of the present disclosure is illustrated below through some example embodiments.

[0077] The display substrate according to an example embodiment of the present disclosure can include a plurality of repeating units arranged regularly in a plane parallel to the display substrate, at least one of the repeating units can include a display area configured to realize image display and a light-transmitting area configured to realize light transmission to realize transparent display. In a direction perpendicular to the display substrate, the display substrate can include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate. In at least one of the repeating units, the driving circuit layer of the display area can include a plurality of circuit units, and the light-emitting structure layer of the display area can include a plurality of light-emitting units. The circuit units can include at least pixel driving circuits, and the light-emitting units can include at least light-emitting devices connected to the pixel driving circuits of the corresponding circuit units.

[0078] In an example embodiment, the circuit unit refers to an area divided according to the pixel driving circuit, and the light-emitting unit refers to an area divided according to the light-emitting device. In an example embodiment, the position of the light-emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light-emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0079] In an example embodiment of the present disclosure, the position of the circuit unit orthogonally projected on the substrate corresponds to the position of the light-emitting unit orthogonally projected on the substrate, and the circuit unit and the light-emitting unit form a sub-pixel. Therefore, in the following content, the sub-pixel is used to refer to the circuit unit and the light-emitting unit.

[0080] FIG. 3 is a schematic view of an arrangement of sub-pixels in a repeating unit according to an example embodiment of the present disclosure, illustrating a structure of a repeating unit. As shown in FIG. 3, the repeating unit can include a display area 110 and a light-transmitting area 120. The light-transmitting area 120 can be located on one side of the display area 110 in a first direction X or on the side opposite to the first direction X.

[0081] In an example embodiment, the display area 110 can include four sub-pixels, which are a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The four sub-pixels are arranged in a vertical manner along a second direction Y. Compared with a horizontal manner and a square manner, the vertical manner of the sub-pixels can effectively increase the area of the light-transmitting area and improve the transmittance.

[0082] In an example embodiment, the second sub-pixel P2 can be arranged at one side of the first sub-pixel P1 in the second direction Y, the third sub-pixel P3 can be arranged at one side of the second sub-pixel P2 in the second direction Y, and the fourth sub-pixel P4 can be arranged at one side of the third sub-pixel P3 in the second direction Y.

[0083] In an example embodiment, the first direction X and the second direction Y are perpendicular to each other.

[0084] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light, and the fourth sub-pixel P4 can be a white sub-pixel (W) emitting white light.

[0085] In some possible embodiments, the arrangement of the four sub-pixels can be adjusted according to actual needs, which is not limited in the present disclosure.

[0086] In some possible embodiments, the display area 110 can include three sub-pixels arranged in a vertical manner, which is not limited in the present disclosure.

[0087] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment of the present disclosure. As shown in FIG. 4, the pixel driving circuit according to the present disclosure can be a 3T1C structure, and can include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C. The pixel driving circuit is connected with a scan signal line S, a first power supply line VDD, a data signal line D, and a compensation signal line B, respectively.

[0088] In an example embodiment, the pixel driving circuit can include at least a first node N1 and a second node N2. The first node N1 is connected with a second electrode of the first transistor T1, a gate electrode of the second transistor T2, and a first end of the storage capacitor C, respectively. The second node N2 is connected with a second electrode of the second transistor T2, a second electrode of the third transistor T3, and a second end of the storage capacitor C, respectively.

[0089] In an example embodiment, the first end of the storage capacitor C is connected with the first node N1, and the second end of the storage capacitor C is connected with the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0090] In an example embodiment, the gate electrode of the first transistor T1 is connected with the scan signal line S, the first electrode of the first transistor T1 is connected with the data signal line D, and the second electrode of the first transistor T1 is connected with the first node N1. The gate electrode of the second transistor T2 is connected with the first node N1, the first electrode of the second transistor T2 is connected with the first power supply line VDD, and the second electrode of the second transistor T2 is connected with the second node N2. The gate electrode of the third transistor T3 is connected with the scan signal line S, the first electrode of the third transistor T3 is connected with the compensation signal line B, and the second electrode of the third transistor T3 is connected with the second node N2.

[0091] In an example embodiment, in the pixel driving circuit of the at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected with the same scan signal line S.

[0092] In an example embodiment, the first electrode of the light emitting device EL is connected with the second node N2, and the second electrode of the light emitting device EL is connected with the second power supply line VSS. The light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0093] In an example embodiment, the signal of the first power supply line VDD is a high level signal continuously provided, and the signal of the second power supply line VSS is a low level signal continuously provided.

[0094] In an example embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0095] In an example embodiment, the first transistor T1 to the third transistor T3 can be low temperature poly-silicon transistors, or can be oxide transistors, or can be low temperature poly-silicon transistors and oxide transistors. The active layer of the low temperature poly-silicon transistor uses low temperature poly-silicon (LTPS), and the active layer of the oxide transistor uses oxide semiconductor (Oxide). The low temperature poly-silicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon transistor and the oxide transistor on one display substrate, i.e., an LTPO display substrate, can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0096] FIG. 5 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. As shown in FIG. 5, the repeating unit can include a display area 110 and a light-transmitting area 120, the light-transmitting area 120 can be located on the side opposite to the display area 110 in the first direction X, the display area 110 can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 arranged in a vertical manner, and at least one sub-pixel can include a pixel driving circuit and a light-emitting device.

[0097] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel can be connected with a first power line 71, a compensation signal line 73 and a corresponding data signal line respectively, the first power line 71 is configured to provide a first power signal to the connected pixel driving circuit, the compensation signal line 73 is configured to provide a compensation signal to the connected pixel driving circuit, and the data signal line is configured to provide a data signal to the connected pixel driving circuit. The light-emitting device of at least one sub-pixel can be connected with a second power line 72, and the second power line 72 is configured to provide a second power signal to the connected light-emitting device.

[0098] In an exemplary embodiment, at least one repeating unit can include one first power line 71, one compensation signal line 73 and four data signal lines, the first power line 71 simultaneously provides a first power signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4, forming a one-to-four structure of the first power line 71, the compensation signal line 73 simultaneously provides a compensation signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4, forming a one-to-four structure of the compensation signal line 73, and the four data signal lines respectively provide data signals to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4.

[0099] In an exemplary embodiment, the four data signal lines in at least one repeating unit can be a first data signal line 61, a second data signal line 62, a third data signal line 63 and a fourth data signal line 64 respectively. The first data signal line 61 is configured to provide a data signal to the pixel driving circuit in the fourth sub-pixel P4, the second data signal line 62 is configured to provide a data signal to the pixel driving circuit in the third sub-pixel P3, the third data signal line 63 is configured to provide a data signal to the pixel driving circuit in the second sub-pixel P2, and the fourth data signal line 64 is configured to provide a data signal to the pixel driving circuit in the first sub-pixel P1.

[0100] In an exemplary embodiment, the at least one display area 110 can be divided into a first area 110-1 and a second area 110-2, the second area 110-2 can be disposed on a side of the first area 110-1 away from the light-transmissive area 120, the first area 110-1 is configured to accommodate pixel driving circuits of a plurality of sub-pixels, and the second area 110-2 is configured to accommodate the first to fourth data signal lines 61 to 64, the first power supply line 71, the second power supply line 72, and the compensation signal line 73, that is, the plurality of pixel driving circuits can be disposed on a side of the display area 110 close to the light-transmissive area 120, and the plurality of signal lines can be disposed on a side of the display area 110 away from the light-transmissive area 120.

[0101] In an exemplary embodiment, the first to fourth data signal lines 61 to 64, the first power supply line 71, the second power supply line 72, and the compensation signal line 73 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, the first data signal line 61 can be disposed on a side of the second area 110-2 close to the first area 110-1, the second data signal line 62 can be disposed on a side of the first data signal line 61 away from the first area 110-1, the third data signal line 63 can be disposed on a side of the second data signal line 62 away from the first area 110-1, the fourth data signal line 64 can be disposed on a side of the third data signal line 63 away from the first area 110-1, the compensation signal line 73 can be disposed on a side of the fourth data signal line 64 away from the first area 110-1, the first power supply line 71 can be disposed on a side of the compensation signal line 73 away from the first area 110-1, and the second power supply line 72 can be disposed on a side of the first power supply line 71 away from the first area 110-1, that is, the first to fourth data signal lines 61 to 64, the compensation signal line 73, the first power supply line 71, and the second power supply line 72 can be sequentially disposed along the first direction X.

[0102] In an exemplary embodiment, in the first direction X, the compensation signal line 73 can be disposed between the fourth data signal line 64 and the first power supply line 71, and the first power supply line 71 can be disposed between the compensation signal line 73 and the second power supply line 72.

[0103] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate can include a plurality of conductive layers disposed on the base, the first to fourth data signal lines 61 to 64 and the first power supply line 71 can be disposed in the same conductive layer, the second power supply line 72 and the compensation signal line 73 can be disposed in the same conductive layer, and the first power supply line 71 and the second power supply line 72 can be disposed in different conductive layers.

[0104] In an example embodiment, the at least one pixel driving circuit can include at least a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, and a third transistor T3 as a sensing transistor. The first electrode of the first transistor T1 is connected with a corresponding data signal line, the second electrode of the first transistor T1 is connected with the gate electrode of the second transistor T2, the first electrode of the second transistor T2 is connected with a first power supply line 71, the second electrode of the second transistor is connected with the second electrode of the third transistor T3, and the first electrode of the third transistor T3 is connected with a compensation signal line 73.

[0105] In an example embodiment, in the at least one repeating unit, the positions of the transistors in adjacent sub-pixels can be arranged in pairs of symmetry. For example, the positions of the first transistor T1, the second transistor T2, and the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2 can be arranged substantially symmetrically with respect to a sub-pixel center line. For another example, the positions of the first transistor T1, the second transistor T2, and the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to a sub-pixel center line. For yet another example, the positions of the first transistor T1, the second transistor T2, and the third transistor T3 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to a sub-pixel center line. The sub-pixel center line can be a straight line located between adjacent sub-pixels and extending along the first direction X.

[0106] In an example embodiment, in the at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected with the same scan signal line 30.

[0107] In an example embodiment, in the at least one repeating unit, the gate electrodes of the four first transistors T1 and the gate electrodes of the four third transistors T3 are connected with the same scan signal line 30.

[0108] In an example embodiment, in the at least one repeating unit, the scan signal line 30 can include at least a first ring structure 30A, a second ring structure 30B, a ring connection line 35, and a scan transmission line 36. The first ring structure 30A, the second ring structure 30B, and the ring connection line 35 can be arranged in the display area 110, and the scan transmission line 36 can be arranged in the light-transmissive area 120.

[0109] In the example embodiment, the first ring-shaped structure 30A can be arranged in the first sub-pixel P1 and the second sub-pixel P2, the second ring-shaped structure 30B can be arranged in the third sub-pixel P3 and the fourth sub-pixel P4, the shape of the ring connection line 35 can be a straight line or a broken line with a main body extending along the second direction Y, the ring connection line 35 can be arranged between the first ring-shaped structure 30A and the second ring-shaped structure 30B, the first end of the ring connection line 35 is connected with the first ring-shaped structure 30A, and the second end of the ring connection line 35 is connected with the second ring-shaped structure 30B, so that the first ring-shaped structure 30A and the second ring-shaped structure 30B are connected with each other through the ring connection line 35.

[0110] In the example embodiment, the first ring-shaped structure 30A, the second ring-shaped structure 30B and the ring connection line 35 in at least one repeating unit can be an integrated structure connected with each other.

[0111] In the example embodiment, the shape of the scan transmission line 36 can be a straight line or a broken line with a main body extending along the first direction X, the first end of the scan transmission line 36 is connected with the second ring-shaped structure 30B in the current repeating unit, and the second end of the scan transmission line 36 is connected with the second ring-shaped structure 30B in the adjacent repeating unit along the first direction X.

[0112] In the example embodiment, in the two adjacent repeating units along the first direction X, the scan transmission lines 36 in the two light-transmitting regions 120 can be arranged staggered, i.e. the scan transmission lines 36 in the two light-transmitting regions 120 are not on the same straight line extending along the first direction X.

[0113] In the example embodiment, the first ring-shaped structure 30A, the second ring-shaped structure 30B, the ring connection line 35 and the scan transmission line 36 in at least one repeating unit can be an integrated structure connected with each other.

[0114] In the example embodiment, the first ring-shaped structure 30A can include at least two gate electrode lines 31, a first scan connection line 33 and a second scan connection line 34, the shape of the gate electrode line 31 is a straight line or a broken line extending along the first direction X, the two gate electrode lines are arranged in the first sub-pixel P1 and the second sub-pixel P2 respectively, the shape of the first scan connection line 33 and the second scan connection line 34 is a straight line or a broken line extending along the second direction Y, and both of them are arranged across the first sub-pixel P1 and the second sub-pixel P2, the first scan connection line 34 is connected with the end of the two gate electrode lines in the opposite direction of the first direction X respectively, and the second scan connection line 35 is connected with the end of the two gate electrode lines in the first direction X respectively, thereby forming the first ring-shaped structure 30A.

[0115] In the example embodiment, the second ring structure 30B can include at least two gate electrode lines 31, a first scan connection line 33 and a second scan connection line 34. The gate electrode lines 31 are in the shape of a straight line or a broken line extending along the first direction X, and are arranged in the third sub-pixel P3 and the fourth sub-pixel P4, respectively. The first scan connection line 33 and the second scan connection line 34 are in the shape of a straight line or a broken line extending along the second direction Y, and are arranged across the third sub-pixel P3 and the fourth sub-pixel P4. The first scan connection line 34 is connected to the end of the gate electrode line in the opposite direction of the first direction X, and the second scan connection line 35 is connected to the end of the gate electrode line in the first direction X, thereby forming the second ring structure 30B.

[0116] In the example embodiment, in at least one repeating unit, all the longitudinal signal lines are located between the first scan connection line 33 and the second scan connection line 34, and the orthographic projection of the first ring structure 30A and the second ring structure 30B on the display substrate plane at least partially overlaps the orthographic projection of the first data signal line 61, the second data signal line 62, the third data signal line 63, the fourth data signal line 64, the compensation signal line 73, the first power line 71 and the second power line 72 on the display substrate plane, i.e., all the longitudinal signal lines are located within the first ring structure 30A and the second ring structure 30B.

[0117] In the example embodiment, the first ring structure 30A can be provided with a first protruding structure 37. The first protruding structure 37 can be arranged on one side of the first ring structure 30A in the first direction X, and protrudes towards the light-transmitting region 120 in the adjacent repeating unit in the first direction X. The orthographic projection of the first protruding structure 37 on the display substrate plane at least partially overlaps the orthographic projection of the light-transmitting region 120 on the display substrate plane.

[0118] In the example embodiment, the second ring structure 30B can be provided with a second protruding structure 38. The second protruding structure 38 can be arranged on one side of the second ring structure 30B in the first direction X, and protrudes towards the light-transmitting region 120 in the adjacent repeating unit in the first direction X. The orthographic projection of the second protruding structure 38 on the display substrate plane at least partially overlaps the orthographic projection of the light-transmitting region 120 on the display substrate plane.

[0119] In the example embodiment, in at least one repeating unit, the protruding lengths of the first protruding structure 37 and the second protruding structure 38 are different. The protruding length can be the dimension of the first direction X.

[0120] FIG. 6 is a schematic diagram of a structure of a storage capacitor according to an example embodiment of the present disclosure, which is a cross-sectional view along A-A in FIG. 5. As shown in FIGS. 5 and 6, the at least one pixel driving circuit can further include a first capacitor 10-1 and a second capacitor 10-2, which are in a parallel structure and together form a storage capacitor of the pixel driving circuit.

[0121] In an example embodiment, the first capacitor 10-1 can include a first plate 11 and a second plate 12 stacked together, and the first plate 11 and the second plate 12 have an overlapping area in a projection on a display substrate plane. The second capacitor 10-2 can include a third plate 13, a fourth plate 14, and a fifth plate 15 stacked together, and the third plate 13, the fourth plate 14, and the fifth plate 15 have an overlapping area in a projection on the display substrate plane.

[0122] In an example embodiment, the first plate 11 is connected to the third plate 13, the third plate 13 is connected to the fifth plate 15, and the second plate 12 is connected to the fourth plate 14, so that the first plate 11, the third plate 13, and the fifth plate 15 have the same potential, and the second plate 12 and the fourth plate 14 have the same potential, and the first capacitor 10-1 and the second capacitor 10-2 in the parallel structure form a complete storage capacitor.

[0123] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate can include at least a substrate 300, a first transparent conductive layer disposed on the substrate 300, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate 300, a first insulating layer 301 disposed on a side of the first conductive layer away from the substrate 300, a semiconductor layer disposed on a side of the first insulating layer 301 away from the substrate 300, a second insulating layer 302 disposed on a side of the semiconductor layer away from the substrate 300, a second conductive layer disposed on a side of the second insulating layer 302 away from the substrate 300, a third insulating layer 303 disposed on a side of the second conductive layer away from the substrate 300, and a third conductive layer disposed on a side of the third insulating layer 303 away from the substrate 300.

[0124] In an example embodiment, the first transparent conductive layer can include at least the first plate 11, the first plate 11 can be disposed in the display area 110 and the light-transmitting area 120, and the first plate 11 can serve as a transparent lower plate of the first capacitor 10-1.

[0125] In an example embodiment, the first conductive layer can include at least the third plate 13, the third plate 13 can serve as a lower plate of the second capacitor 10-2, and the third plate 13 is overlapped with the first plate 11, so that the first plate 11 and the third plate 13 have the same potential.

[0126] In the example embodiment, the semiconductor layer can at least include the second plate 12, the second active layer 22 and the third active layer 23, the second plate 12 can serve as a transparent upper plate of the first capacitor 10-1, and the first plate 11 and the second plate 12 constitute the first capacitor 10-1.

[0127] In the example embodiment, the orthographic projection of the first plate 11 and the second plate 12 on the substrate at least partially overlaps with the orthographic projection of the light-transmitting region 120 on the substrate.

[0128] In the example embodiment, the second conductive layer can at least include the fourth plate 14 and the second gate electrode 32, the fourth plate 14 can serve as an intermediate plate of the second capacitor 10-2, and the fourth plate 14 and the second gate electrode 32 can be an integrated structure connected with each other.

[0129] In the example embodiment, the third conductive layer can at least include the fifth plate 15 and the eighth connection electrode 48, the fifth plate 15 can serve as an upper plate of the second capacitor 10-2, the fifth plate 15 is connected with the third active layer 23 and the third plate 13 through the sixth via V6, so that the third plate 13 and the fifth plate 15 have the same potential, and the third plate 13, the fourth plate 14 and the fifth plate 15 constitute the second capacitor 10-2. The eighth connection electrode 48 is connected with the second plate 12 and the second gate electrode 32 through the seventh via V7. Since the second gate electrode 32 is connected with the fourth plate 14, the second plate 12 and the fourth plate 14 have the same potential.

[0130] In the example embodiment, the first data signal line 61 to the fourth data signal line 64 and the first power supply line 71 can be arranged in the first conductive layer, the scan signal line 30 can be arranged in the second conductive layer, and the second power supply line 72 and the compensation signal line 73 can be arranged in the third conductive layer.

[0131] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, the etching can adopt any one or more of dry etching and wet etching, and the present disclosure does not make any limitation. The "thin film" refers to a thin film of a certain material on a substrate made by deposition, coating or other processes. If the "thin film" does not need a patterning process in the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0132] In the exemplary embodiments, taking four sub-pixels (the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4) of one repeating unit as an example, the preparation process of the display substrate can include the following operations.

[0133] (11) Forming a first transparent conductive layer pattern. In the exemplary embodiments, forming the first transparent conductive layer pattern can include: depositing a first transparent conductive thin film on the substrate, patterning the first transparent conductive thin film by a patterning process, and forming the first transparent conductive layer pattern on the substrate, as shown in FIG. 7. In the exemplary embodiments, the first transparent conductive layer can be referred to as a 1st ITO layer.

[0134] In the exemplary embodiments, the first transparent conductive layer pattern of each sub-pixel in the display substrate can include at least a first plate 11 of a storage capacitor.

[0135] In the exemplary embodiments, the shape of the first plate 11 can be a strip shape (such as a rectangular shape) extending along the first direction X, the corner of the strip shape can be provided with a chamfer or a groove, the edge of the strip shape can be a fold line, and the first plate 11 can be provided in the display area 110 and the light-transmitting area 120. The first plate 11 can serve as a transparent lower plate of the first capacitor, and the first plate 11 and the subsequently formed second plate constitute a first capacitor of a storage capacitor.

[0136] In an example embodiment, in the first direction X, the first plate 11 can extend from the display area 110 to the light-transmitting area 120, or the first plate 11 can extend from the light-transmitting area 120 to the display area 110. In the second direction Y, the first plate 11 can be disposed on one side of each sub-pixel in the second direction Y. For example, the first plate 11 in the first sub-pixel P1 can be located away from the second sub-pixel P2, and the first plate 11 in the second sub-pixel P2 can be located away from the first sub-pixel P1. For another example, the first plate 11 in the third sub-pixel P3 can be located away from the fourth sub-pixel P4, and the first plate 11 in the fourth sub-pixel P4 can be located away from the third sub-pixel P3.

[0137] In an example embodiment, the first plate 11 in the first sub-pixel P1 and the second sub-pixel P2 can be substantially symmetrically disposed relative to a sub-pixel center line, the first plate 11 in the second sub-pixel P2 and the third sub-pixel P3 can be substantially symmetrically disposed relative to the sub-pixel center line, and the first plate 11 in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially symmetrically disposed relative to the sub-pixel center line. The sub-pixel center line can be a straight line located between adjacent sub-pixels and extending along the first direction X.

[0138] In an example embodiment, the material of the first transparent conductive layer can adopt a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO, etc.

[0139] (12) Forming a first conductive layer pattern. In an example embodiment, forming the first conductive layer pattern includes: depositing a first conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the first conductive thin film by a patterning process to form the first conductive layer pattern on the first transparent conductive layer, as shown in FIGS. 8A and 8B. In an example embodiment, the first conductive layer can be referred to as a shadowing metal (SHL) layer.

[0140] In an example embodiment, the first conductive layer of each sub-pixel in the display substrate can at least include a third plate 13 storing a capacitance, a first connection electrode 41, and a second connection electrode 42.

[0141] In an example embodiment, the third plate 13 can have a rectangular shape, and the corner of the rectangular shape can be provided with a chamfer or a groove. The third plate 13 can serve as a lower plate of a second capacitance, and the third plate 13 is configured to constitute a first sub-capacitance of the second capacitance together with a fourth plate formed subsequently.

[0142] In an exemplary embodiment, in the first direction X, the third plate 13 can be disposed in the display area 110. In the second direction Y, the third plate 13 can be disposed on the side of each sub-pixel close to the first plate 11.

[0143] In an exemplary embodiment, the third plate 13 in the first sub-pixel P1 can be located in an area away from the second sub-pixel P2 and overlap with the first plate 11 in the first sub-pixel P1. The third plate 13 in the second sub-pixel P2 can be located in an area away from the first sub-pixel P1 and overlap with the first plate 11 in the second sub-pixel P2. The third plate 13 in the third sub-pixel P3 can be located in an area away from the fourth sub-pixel P4 and overlap with the first plate 11 in the third sub-pixel P3. The third plate 13 in the fourth sub-pixel P4 can be located in an area away from the third sub-pixel P3 and overlap with the first plate 11 in the fourth sub-pixel P4.

[0144] In an exemplary embodiment, since the first plate 11 and the third plate 13 in each sub-pixel overlap together, the first plate 11 and the third plate 13 in each sub-pixel have the same electric potential.

[0145] In an exemplary embodiment, the third plate 13 in each sub-pixel is also configured to shade the second transistor T2 in the sub-pixel in which it is located, reduce the light intensity shining on the second transistor T2, reduce the leakage current of the second transistor T2, and thus reduce the influence of light on the characteristics of the second transistor T2.

[0146] In an exemplary embodiment, the first connecting electrode 41 can be in the shape of a block (such as a rectangle) and can be disposed on the side of the third plate 13 away from the first plate 11.

[0147] In an exemplary embodiment, the second connecting electrode 42 can be in the shape of a block (such as a rectangle) and can be disposed on the side of the third plate 13 away from the first plate 11.

[0148] In an exemplary embodiment, in the first direction X, the first connecting electrode 41 can be disposed on the side of the second connecting electrode 42 in the first direction X, and in the second direction Y, the first connecting electrode 41 and the second connecting electrode 42 can be substantially flush.

[0149] In an exemplary embodiment, the first conductive layer of each repeating unit in the display substrate can further include a first data signal line 61, a second data signal line 62, a third data signal line 63, a fourth data signal line 64, and a first power supply line 71.

[0150] In an example embodiment, the first data signal line 61 can be in a linear or zigzag shape with a main body extending along the second direction Y, and can be disposed on one side of the third polar plate 13 in the first direction X.

[0151] In an example embodiment, the first data signal line 61 can be in a linear or zigzag shape with a main body extending along the second direction Y, and can be disposed on one side of the third polar plate 13 in the first direction X.

[0152] In an example embodiment, the first data signal line 61, the first data connection block 61-1, and the first connection electrode 41 in the fourth sub-pixel P4 can be in an integrated structure connected to each other in at least one repeating unit.

[0153] In an example embodiment, the second data signal line 62 can be in a linear or zigzag shape with a main body extending along the second direction Y, and can be disposed on one side of the first data signal line 61 in the first direction X.

[0154] In an example embodiment, the second data signal line 62 can be in a linear or zigzag shape with a main body extending along the second direction Y, and can be disposed on one side of the first data signal line 61 in the first direction X.

[0155] In an example embodiment, the second data signal line 62 and the second data connection block 62-1 can be in an integrated structure connected to each other in at least one repeating unit.

[0156] In an example embodiment, the third data signal line 63 can be in a linear or zigzag shape with a main body extending along the second direction Y, and can be disposed on one side of the second data signal line 62 in the first direction X.

[0157] In an example embodiment, the third data signal line 63 can be in a linear or zigzag shape with a main body extending along the second direction Y, and can be disposed on one side of the second data signal line 62 in the first direction X.

[0158] In the example embodiment, the third data signal line 63 and the third data connection block 63-1 can be an integrated structure connected to each other in at least one repeating unit.

[0159] In the example embodiment, the fourth data signal line 64 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and can be arranged on one side of the third data signal line 63 in the first direction X.

[0160] In the example embodiment, the fourth data signal line 64 can be provided with a fourth data connection block 64-1. The fourth data connection block 64-1 can have a shape of a block (e.g., a rectangle), and can be arranged in the first sub-pixel P1 and connected to the fourth data signal line 64. The fourth data signal line 64 can be configured to be connected to the first connection electrode 41 in the first sub-pixel P1 through a subsequently formed connection electrode.

[0161] In the example embodiment, the fourth data signal line 64 and the fourth data connection block 64-1 can be an integrated structure connected to each other in at least one repeating unit.

[0162] In the example embodiment, the first data signal line 61, the second data signal line 62, the third data signal line 63, and the fourth data signal line 64 can have substantially the same first interval S1 between each other in at least one repeating unit. The first interval S1 can be a dimension in the first direction X.

[0163] In the example embodiment, the first interval S1 can be the minimum interval between adjacent data signal lines. For example, the first interval S1 can be the minimum interval between the edge of the first data signal line 61 on the side close to the second data signal line 62 and the edge of the second data signal line 62 on the side close to the first data signal line 61.

[0164] In the example embodiment, the first power supply line 71 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and can be arranged on one side of the fourth data signal line 64 in the first direction X.

[0165] In the example embodiment, the first data signal line 61, the second data signal line 62, the third data signal line 63, the fourth data signal line 64, and the first power supply line 71 can all be arranged on one side of the third electrode plate 13 in the first direction X. The overall layout of the repeating unit of the present disclosure can have all the longitudinal wires arranged on the same side, which can maximize the area of the light transmission region and improve the transmittance.

[0166] In the example embodiment, in at least one repeating unit, the display region can include a circuit region (first region) and a trace region (second region) disposed on the first direction X side of the circuit region, the circuit region can be configured to dispose a storage capacitor and a plurality of transistors, and the trace region can be configured to dispose a plurality of signal lines. In this way, in the first direction X, the repeating unit can only include three regions: a region that transmits light, a region that is configured to dispose a storage capacitor and a plurality of transistors, and a region that is configured to dispose a signal line, which can effectively reduce the area occupied by the display region and maximize the area of the light transmission region.

[0167] In the example embodiment, the third electrode plate 13, the first connection electrode 41, and the second connection electrode 42 in the first sub-pixel P1 and the second sub-pixel P2 can be substantially symmetrically disposed relative to the sub-pixel center line, the third electrode plate 13, the first connection electrode 41, and the second connection electrode 42 in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially symmetrically disposed relative to the sub-pixel center line, and the third electrode plate 13, the first connection electrode 41, and the second connection electrode 42 in the second sub-pixel P2 and the third sub-pixel P3 can be substantially symmetrically disposed relative to the sub-pixel center line.

[0168] (13) Forming a semiconductor layer pattern. In the example embodiment, forming a semiconductor layer pattern can include: sequentially depositing a first insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process, forming a first insulating layer covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIGS. 9A and 9B, FIG. 9B is a schematic view of the semiconductor layer in FIG. 9A.

[0169] In the example embodiment, the semiconductor layer of each sub-pixel in the display substrate can include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode plate 12 of a storage capacitor, the first active layer 21 can serve as an active layer of a first transistor T1, the second active layer 22 can serve as an active layer of a second transistor T2, and the third active layer 23 can serve as an active layer of a third transistor T3.

[0170] In the example embodiment, the second electrode plate 12 can have a strip shape (e.g., a rectangular shape) extending along the first direction X, the corners of the strip shape can be provided with chamfers or grooves, the edges of the strip shape can be broken lines, the second electrode plate 12 can be disposed in the display region 110 and the light transmission region 120, the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps the orthographic projection of the first electrode plate 11 on the substrate, and the second electrode plate 12 can serve as a transparent upper electrode plate of the first capacitor, and the first electrode plate 11 and the second electrode plate 12 constitute the first capacitor of the storage capacitor.

[0171] In the exemplary embodiments, in the first direction X, the second plate 12 can extend from the display area 110 to the light-transmissive area 120, or the second plate 12 can extend from the light-transmissive area 120 to the display area 110. In the second direction Y, the second plate 12 can be disposed on one side of each sub-pixel in the second direction Y. For example, the second plate 12 in the first sub-pixel P1 can be located on the side away from the second sub-pixel P2, and the second plate 12 in the second sub-pixel P2 can be located on the side away from the first sub-pixel P1. For another example, the second plate 12 in the third sub-pixel P3 can be located on the side away from the fourth sub-pixel P4, and the second plate 12 in the fourth sub-pixel P4 can be located on the side away from the third sub-pixel P3. The present disclosure can effectively increase the capacity of the first capacitance by disposing a portion of the transparent first plate 11 and the second plate 12 in the light-transmissive area 120, and has less impact on the transmittance.

[0172] In the exemplary embodiments, the shapes of the first active layer 21 and the third active layer 23 can be strip shapes extending along the second direction Y, and the first active layer 21 and the third active layer 23 can be disposed on the side of the sub-pixel away from the second plate 12. The shape of the second active layer 22 can be a rectangular shape or a “T” shape, and the second active layer 22 can be disposed on the side of the sub-pixel close to the second plate 12.

[0173] In the exemplary embodiments, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region.

[0174] In the exemplary embodiments, in the first direction X, the first active layer 21 can be disposed on the side of the third active layer 23 close to the first data signal line 61. In the second direction Y, the first region 21-1 of the first active layer can be located on the side of the channel region of the first active layer away from the third plate 13, the second region 21-2 of the first active layer can be located on the side of the channel region of the first active layer close to the third plate 13, the orthographic projection of the first region 21-1 of the first active layer on the base at least partially overlaps the orthographic projection of the first connection electrode 41 on the base, and the orthographic projection of the channel region of the first active layer and the second region 21-2 of the first active layer on the base does not overlap the orthographic projection of the third plate 13 on the base.

[0175] In the exemplary embodiments, in the first direction X, the first region 22-1 of the second active layer can be located on one side of the channel region of the second active layer close to the first data signal line 61, and the second region 22-2 of the second active layer can be located on the other side of the channel region of the second active layer away from the first data signal line 61, and the orthographic projection of the channel region of the second active layer and the second region 22-2 of the second active layer on the substrate at least partially overlaps with the orthographic projection of the third plate 13 on the substrate, so that the third plate 13 as a shielding layer can shield the channel region of the second transistor T2 to avoid the influence of light on the channel, and ensure the electrical performance of the second transistor T2.

[0176] In the exemplary embodiments, in the first direction X, the third active layer 23 can be arranged on the side of the first active layer 21 away from the first data signal line 61. In the second direction Y, the first region 23-1 of the third active layer can be located on one side of the channel region of the third active layer away from the third plate 13, and the second region 23-2 of the third active layer can be located on the other side of the channel region of the third active layer close to the third plate 13, and the orthographic projection of the first region 23-1 of the third active layer on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 42 on the substrate, and the orthographic projection of the second region 23-2 of the third active layer on the substrate at least partially overlaps with the orthographic projection of the third plate 13 on the substrate.

[0177] In the exemplary embodiments, the shape of the first active layer 21 in the first sub-pixel P1 to the fourth sub-pixel P4 can be substantially the same, the shape of the third active layer 23 in the first sub-pixel P1 to the fourth sub-pixel P4 can be substantially the same, and the shape of the second active layer 22 in the first sub-pixel P1 to the fourth sub-pixel P4 can be different.

[0178] In the exemplary embodiments, the shape of the second active layer 22 in the first sub-pixel P1 can be a rectangular shape, the shape of the second active layer 22 in the second sub-pixel P2 to the fourth sub-pixel P4 can be a “T” shape, and the active width of the second active layer 22 in the first sub-pixel P1 can be greater than the active width of the second active layer 22 in the second sub-pixel P2 to the fourth sub-pixel P4. In the case where the active length is substantially the same, the aspect ratio of the second transistor T2 in the first sub-pixel P1 can be greater than the aspect ratio of the second transistor T2 in the second sub-pixel P2 to the fourth sub-pixel P4. Wherein, the active width can be the dimension of the channel region of the active layer in the second direction Y, and the active length can be the dimension of the channel region of the active layer in the first direction X.

[0179] In the exemplary embodiments, the first active layer 21, the third active layer 23 and the second plate 12 in the first sub-pixel P1 and the second sub-pixel P2 can be substantially symmetrically arranged with respect to the sub-pixel center line, the semiconductor layer in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially symmetrically arranged with respect to the sub-pixel center line, and the semiconductor layer in the second sub-pixel P2 and the third sub-pixel P3 can be substantially symmetrically arranged with respect to the sub-pixel center line.

[0180] In the exemplary embodiments, the semiconductor layer can be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0181] (14) Forming a second conductive layer pattern. In the exemplary embodiments, forming the second conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a second insulating thin film and a second conductive thin film, patterning the second conductive thin film by a patterning process, forming a second insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 10A and 10B, FIG. 10B is a schematic view of the second conductive layer in FIG. 10A.

[0182] In the exemplary embodiments, the second conductive layer of each sub-pixel in the display substrate can at least include a fourth plate 14 of a storage capacitor, a gate electrode line 31, a second gate electrode 32, a third connection electrode 43 and a fourth connection electrode 44.

[0183] In the exemplary embodiments, the fourth plate 14 can be in a rectangular shape, the corner of the rectangular shape can be provided with a chamfer or a groove, and can be disposed in the area where the third plate 13 is located. The orthographic projection of the fourth plate 14 on the substrate at least partially overlaps the orthographic projection of the third plate 13 on the substrate. The fourth plate 14 can serve as an intermediate plate of the second capacitor. The fourth plate 14 is configured to form a first sub-capacitor of the second capacitor together with the third plate 13, and is also configured to form a second sub-capacitor of the second capacitor together with a fifth plate to be formed subsequently.

[0184] In the example embodiment, the shape of the gate electrode line 31 can be a straight line or a broken line shape with a main body extending along the first direction X, the orthographic projection of the gate electrode line 31 on the substrate at least partially overlaps the orthographic projection of the first active layer 21 on the substrate, the overlapping region serves as the gate electrode of the first transistor T1, the orthographic projection of the gate electrode line 31 on the substrate at least partially overlaps the orthographic projection of the third active layer 23 on the substrate, the overlapping region serves as the gate electrode of the third transistor T3, and the gate electrode lines 31 transmitting the same scanning signal can simultaneously control the conduction or disconnection of the first transistor T1 and the third transistor T3 in the sub-pixel.

[0185] In the example embodiment, the shape of the second gate electrode 32 can be a strip shape extending along the second direction Y, and the second gate electrode 32 can be located on the side of the fourth plate 14 away from the gate electrode line 31, the first end of the second gate electrode 32 is connected to the fourth plate 14, and the second end of the second gate electrode 32 extends away from the gate electrode line 31, the orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps the orthographic projection of the second active layer 22 on the substrate, and the second gate electrode 32 serves as the gate electrode of the second transistor T2.

[0186] In the example embodiment, the orthographic projection of the second end of the second gate electrode 32 on the substrate at least partially overlaps the orthographic projection of the second plate 12 on the substrate.

[0187] In the example embodiment, in at least one sub-pixel, the fourth plate 14 and the second gate electrode 32 can be an integrated structure connected to each other.

[0188] In the example embodiment, the shape of the third connection electrode 43 can be a strip shape extending along the second direction Y, and the third connection electrode 43 can be located on the side of the fourth plate 14 close to the gate electrode line 31, the first end of the third connection electrode 43 is connected to the fourth plate 14, and the second end of the third connection electrode 43 extends towards the gate electrode line 31, and the orthographic projection of the second end of the third connection electrode 43 on the substrate at least partially overlaps the orthographic projection of the second region of the first active layer on the substrate.

[0189] In the example embodiment, in at least one sub-pixel, the fourth plate 14, the second gate electrode 32, and the third connection electrode 43 can be an integrated structure connected to each other.

[0190] In the example embodiment, the shape of the fourth connection electrode 44 can be a strip shape extending along the first direction X, and the fourth connection electrode 44 can be arranged across the second active layer 22 and the first power supply line 71, the orthographic projection of the first end of the fourth connection electrode 44 on the substrate at least partially overlaps the orthographic projection of the second active layer 22 on the substrate, and the orthographic projection of the second end of the fourth connection electrode 44 on the substrate at least partially overlaps the orthographic projection of the first power supply line 71 on the substrate.

[0191] In the example embodiment, the second conductive layer of each of the repeating units in the display substrate can further include two first scan connection lines 33, two second scan connection lines 34, one ring connection line 35, and one scan transfer line 36.

[0192] In the example embodiment, the first scan connection line 33 can have a shape of a straight line or a broken line in which a main body portion extends along the second direction Y. In the first direction X, the first scan connection line 33 can be disposed at the boundary region between the display region 110 and the light-transmissive region 120 in the present repeating unit. In the second direction Y, one of the first scan connection lines 33 can be disposed between the gate electrode line 31 of the first sub-pixel P1 and the gate electrode line 31 of the second sub-pixel P2, and connected to the end portions of the gate electrode lines 31 of the two sub-pixels in the opposite direction of the first direction X, respectively, and the other of the first scan connection lines 33 can be disposed between the gate electrode line 31 of the third sub-pixel P3 and the gate electrode line 31 of the fourth sub-pixel P4, and connected to the end portions of the gate electrode lines 31 of the two sub-pixels in the opposite direction of the first direction X, respectively.

[0193] In the example embodiment, the second scan connection line 34 can have a shape of a straight line or a broken line in which a main body portion extends along the second direction Y. In the first direction X, the second scan connection line 34 can be disposed at the boundary region between the display region 110 of the present repeating unit and the light-transmissive region 120 of the adjacent repeating unit in the first direction X. In the second direction Y, one of the second scan connection lines 34 can be disposed between the gate electrode line 31 of the first sub-pixel P1 and the gate electrode line 31 of the second sub-pixel P2, and connected to the end portions of the gate electrode lines 31 of the two sub-pixels in the first direction X, respectively, and the other of the second scan connection lines 34 can be disposed between the gate electrode line 31 of the third sub-pixel P3 and the gate electrode line 31 of the fourth sub-pixel P4, and connected to the end portions of the gate electrode lines 31 of the two sub-pixels in the first direction X, respectively.

[0194] In the example embodiment, in the first sub-pixel P1 and the second sub-pixel P2, the two gate electrode lines 31 extending along the first direction X (the gate electrode line 31 of the first sub-pixel P1 and the gate electrode line 31 of the second sub-pixel P2), and the two scan connection lines 33 and 34 extending along the second direction Y are sequentially connected, thereby forming a first ring-shaped structure 30A. In the example embodiment, the first ring-shaped structure 30A disposed in the first sub-pixel P1 and the second sub-pixel P2 can be a rectangular ring-shaped structure, or can be a polygonal ring-shaped structure.

[0195] In the at least one repeating unit, the gate electrode lines 31 of the first sub-pixels P1, the gate electrode lines 31 of the second sub-pixels P2, the first scan connection lines 33 and the second scan connection lines 34 in the first annular structure 30A can be an integrated structure connected with each other.

[0196] In the third sub-pixels P3 and the fourth sub-pixels P4, two gate electrode lines 31 extending along the first direction X (the gate electrode line 31 of the third sub-pixel P3 and the gate electrode line 31 of the fourth sub-pixel P4), and two scan connection lines (the first scan connection line 33 and the second scan connection line 34) extending along the second direction Y are sequentially connected to form the second annular structure 30B. In the example embodiment, the second annular structure 30B provided in the third sub-pixels P3 and the fourth sub-pixels P4 can be a rectangular annular structure, or can be a polygonal annular structure.

[0197] In the at least one repeating unit, the gate electrode lines 31 of the third sub-pixels P3, the gate electrode lines 31 of the fourth sub-pixels P4, the first scan connection lines 33 and the second scan connection lines 34 in the second annular structure 30B can be an integrated structure connected with each other.

[0198] In the example embodiment, the shape of the ring connection line 35 can be a straight line or a broken line with a main part extending along the second direction Y. In the first direction X, the ring connection line 35 can be arranged at the boundary region between the display region 110 of the present repeating unit and the light-transmissive region 120 of the adjacent repeating unit in the first direction X. In the second direction Y, the ring connection line 35 can be arranged between the first annular structure 30A and the second annular structure 30B, and connected with the two annular structures respectively, thereby connecting the first annular structure 30A and the second annular structure 30B.

[0199] In the at least one repeating unit, the first annular structure 30A, the second annular structure 30B and the ring connection line 35 can be an integrated structure connected with each other.

[0200] In the example embodiment, the shape of the scan transmission line 36 can be a straight line or a broken line with a main part extending along the first direction X. The scan transmission line 36 can be arranged in the light-transmissive region 120, the first end of the scan transmission line 36 is connected with the second annular structure 30B in the present repeating unit, and the second end of the scan transmission line 36 is connected with the second annular structure 30B in the repeating unit adjacent in the first direction X.

[0201] In the example embodiment, in two adjacent repeating units in the first direction X, the scan transmission lines 36 in the light-transmitting regions 120 in the two repeating units can be arranged staggered, i.e., the scan transmission lines 36 in the light-transmitting regions 120 in the two repeating units are not on the same straight line extending along the first direction X, which can effectively weaken the diffraction effect, avoid the phenomenon of blurring of the object behind the screen, and improve the transparent display effect.

[0202] In the example embodiment, in at least one repeating unit, the first ring structure 30A, the second ring structure 30B, the scan transmission line 36, and the ring connection line 35 can be an integrated structure connected with each other.

[0203] In the example embodiment, the display region 110 is provided with two ring structures connected with each other, and the light-transmitting region 120 is provided with only one signal line, and the two ring structures of the display region 110 and the single signal line of the light-transmitting region 120 constitute a continuous scan signal line.

[0204] In the example embodiment, the scan signal lines transmitting the same scan signal can simultaneously control the turn-on or turn-off of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0205] In the example embodiment, for a plurality of repeating units arranged in sequence in the first direction X, the scan signal lines in the plurality of repeating units can be an integrated structure connected with each other.

[0206] In the example embodiment, in at least one repeating unit, the first region of the first active layer, the first region of the third active layer, the first connection electrode 41, and the second connection electrode 42 in the first sub-pixel P1 and the second sub-pixel P2 can be located within the range of the projection on the substrate of the area surrounded by the first ring structure, and the first region of the first active layer, the first region of the third active layer, the first connection electrode 41, and the second connection electrode 42 in the third sub-pixel P3 and the fourth sub-pixel P4 can be located within the range of the projection on the substrate of the area surrounded by the second ring structure.

[0207] In the example embodiment, in at least one repeating unit, the projection on the substrate of the third data connection block 63-1 and the fourth data connection block 64-1 can be located within the range of the projection on the substrate of the area surrounded by the first ring structure, and the projection on the substrate of the first data connection block 61-1 and the second data connection block 62-1 can be located within the range of the projection on the substrate of the area surrounded by the second ring structure.

[0208] In the at least one repeating unit, all the longitudinal signal lines are located between the first scan connection line 33 and the second scan connection line 34, and the orthographic projections of the first ring-shaped structure 30A and the second ring-shaped structure 30B on the substrate at least partially overlap the orthographic projections of the first data signal line 61, the second data signal line 62, the third data signal line 63, the fourth data signal line 64 and the first power supply line 71 on the substrate, i.e., all the longitudinal signal lines are located within the first ring-shaped structure 30A and the second ring-shaped structure 30B.

[0209] In the at least one repeating unit, the position where the first ring-shaped structure 30A and the ring connection line 35 are connected can be provided with a first protruding structure 37, the first protruding structure 37 can protrude toward the light-transmitting region 120 of the adjacent repeating unit in the first direction X, and the orthographic projection of the first protruding structure 37 on the substrate at least partially overlaps the orthographic projection of the light-transmitting region 120 on the substrate. In the at least one repeating unit, the position where the second ring-shaped structure 30B and the ring connection line 35 are connected can be provided with a second protruding structure 38, the second protruding structure 38 can protrude toward the light-transmitting region 120 of the adjacent repeating unit in the first direction X, and the orthographic projection of the second protruding structure 38 on the substrate at least partially overlaps the orthographic projection of the light-transmitting region 120 on the substrate. The first protruding structure 37 and the second protruding structure 38 can change the light-transmitting region into an irregular shape. When light passes through the light-transmitting region with an irregular shape, the directions of the diffraction fringes are different due to the different positions of the diffraction fringes, and thus the diffraction fringes of the light are not diffused in one direction but in multiple directions, which greatly weakens the diffraction effect, avoids the phenomenon of blurring of the object behind the screen, and improves the transparent display effect.

[0210] In the at least one repeating unit, the end of the second scan connection line 34 close to the ring connection line 35 in the first ring-shaped structure can be provided as a first fold line 37-1 protruding in a direction away from the first scan connection line 33, and the end of the ring connection line 35 close to the first ring-shaped structure can be provided as a second fold line 37-2 protruding in a direction away from the first scan connection line 33, and the first fold line 37-1 and the second fold line 37-2 form the first protruding structure 37.

[0211] In the at least one repeating unit, the end of the second scan connection line 34 close to the ring connection line 35 in the first ring-shaped structure can be provided as a first fold line 37-1 protruding in a direction away from the first scan connection line 33, and the end of the ring connection line 35 close to the first ring-shaped structure can be provided as a second fold line 37-2 protruding in a direction away from the first scan connection line 33, and the first fold line 37-1 and the second fold line 37-2 form the first protruding structure 37.

[0212] In the at least one repeating unit, the end of the second scan connection line 34 close to the ring connection line 35 in the first ring-shaped structure can be provided as a first fold line 37-1 protruding in a direction away from the first scan connection line 33, and the end of the ring connection line 35 close to the first ring-shaped structure can be provided as a second fold line 37-2 protruding in a direction away from the first scan connection line 33, and the first fold line 37-1 and the second fold line 37-2 form the first protruding structure 37.

[0213] In the example embodiment, the second fold line 37-2 can include a third sub-line and a fourth sub-line, a first end of the third sub-line is connected with the ring connection line 35, a second end of the third sub-line is connected with a first end of the fourth sub-line after extending along the first direction X, a second end of the fourth sub-line is connected with the gate electrode line 31 in the second sub-pixel P2 after extending along the opposite direction of the second direction Y.

[0214] In the example embodiment, the third sub-line has a second protruding width D2 between an edge of the third sub-line close to the gate electrode line 31 and an edge of the gate electrode line 31 close to the third sub-line.

[0215] In the example embodiment, the first protruding width D1 and the second protruding width D2 can be different, which is conducive to weakening the diffraction effect and improving the transparent display effect.

[0216] In the example embodiment, an end of the second scan connection line 34 close to the ring connection line 35 in the second ring structure can be provided as a third fold line 38-3 protruding in a direction away from the first scan connection line 33, an end of the ring connection line 35 close to the second ring structure can be provided as a fourth fold line 38-4 protruding in a direction away from the first scan connection line 33, and the third fold line 38-3 and the fourth fold line 38-4 form a second protruding structure 38.

[0217] In the example embodiment, the third fold line 38-3 can include at least a fifth sub-line and a sixth sub-line, a first end of the fifth sub-line is connected with the ring connection line 35, a second end of the fifth sub-line is connected with a first end of the sixth sub-line after extending along the first direction X, and a second end of the sixth sub-line is connected with the gate electrode line 31 in the third sub-pixel P3 after extending along the second direction Y.

[0218] In the example embodiment, the fifth sub-line has a third protruding width D3 between an edge of the fifth sub-line close to the gate electrode line 31 and an edge of the gate electrode line 31 close to the fifth sub-line.

[0219] In the example embodiment, the fourth fold line 38-4 can include a seventh sub-line and an eighth sub-line, a first end of the seventh sub-line is connected with the second scan connection line 34, a second end of the seventh sub-line is connected with a first end of the eighth sub-line after extending along the first direction X, and a second end of the eighth sub-line is connected with the gate electrode line 31 in the third sub-pixel P3 after extending along the opposite direction of the second direction Y.

[0220] In the example embodiment, the seventh sub-line has a fourth protruding width D4 between an edge of the seventh sub-line close to the gate electrode line 31 and an edge of the gate electrode line 31 close to the seventh sub-line.

[0221] In an example embodiment, the third protrusion width D3 and the fourth protrusion width D4 can be different, which is beneficial for weakening the diffraction effect and improving the transparent display effect.

[0222] In an example embodiment, in a plane parallel to the substrate, the shape of the first protrusion structure 37 and the second protrusion structure 38 can include any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, and a hexagon, which is not limited in the present disclosure.

[0223] In an example embodiment, in at least one repeating unit, the shape of the first protrusion structure 37 and the second protrusion structure 38 can be substantially the same, but the protrusion lengths of the two can be different, and the protrusion length can be the dimension of the first direction X.

[0224] In an example embodiment, the first protrusion structure 37 can have a first protrusion length L1, and the second protrusion structure 38 can have a second protrusion length L2, and the first protrusion length L1 can be greater than the second protrusion length L2, which is beneficial for weakening the diffraction effect and improving the transparent display effect.

[0225] In an example embodiment, since the scanning signal line overlaps with the plurality of signal lines, various malfunctions can easily occur in the manufacturing process of the display substrate, such as short circuit in the overlapping area. The present disclosure sets two annular structures connected to each other, which not only ensures that the scanning signal line drives all pixel drive circuits in the repeating area, but also repairs all position malfunctions, realizes full signal malfunction repair, avoids product scrapping, and effectively improves product yield.

[0226] FIG. 10C is a schematic diagram of short circuit malfunction repair of a display substrate according to the present disclosure. As shown in FIG. 10C, when a short circuit point 200 occurs between the gate electrode line 31 of the first sub-pixel P1 and the third data signal line 63, the gate electrode line 31 on both sides of the short circuit point 200 can be cut off by laser cutting, and two cutting points 210 are formed on both sides of the short circuit point 200, so as to isolate the short circuit point 200. Since the gate electrode line 31 of the first sub-pixel P1 and the second sub-pixel P2 is a double-line structure with a double-channel function, whether a short circuit point occurs on the gate electrode line 31 of the first sub-pixel P1 or the gate electrode line 31 of the second sub-pixel P2, the cutting point can ensure that the short circuit point is isolated and will not affect the normal work of the pixel drive circuit in the first sub-pixel P1 and the second sub-pixel P2.

[0227] In the example embodiment, since the gate electrode lines 31 of the third sub-pixel P3 and the fourth sub-pixel P4 are double-line structures, having a double-channel function, whether a short-circuit point occurs on the gate electrode line 31 of the third sub-pixel P3 or on the gate electrode line 31 of the fourth sub-pixel P4, the cut-off point can ensure that the short-circuit point is isolated, and the normal operation of the pixel driving circuit in the third sub-pixel P3 and the fourth sub-pixel P4 is not affected.

[0228] In the example embodiment, according to the actual defective condition, maintenance can be performed on the four positions of the two first scanning connection lines 33 and the two second scanning connection lines 34, full-signal defective maintenance is realized, product scrapping is avoided, and product yield is effectively improved.

[0229] In the example embodiment, the second conductive film and the second insulating film can be patterned at the same time in the process, so that the second insulating layer pattern is the same as the second conductive layer pattern.

[0230] In the example embodiment, after the second conductive layer pattern is formed, the second conductive layer can be used as a shield to perform conductorization processing on the semiconductor layer. The semiconductor layer in the area shielded by the second conductive layer forms the channel region of the first transistor T1 to the third transistor T3, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized.

[0231] (15) Forming a third insulating layer pattern. In the example embodiment, forming the third insulating layer pattern can include: depositing a third insulating film on the substrate on which the aforementioned patterns are formed, and patterning the third insulating film by a patterning process to form a third insulating layer pattern covering the second conductive layer, the third insulating layer being provided with a plurality of vias, as shown in FIG. 11.

[0232] In the example embodiment, the plurality of vias of each sub-pixel in the display substrate at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0233] In the example embodiment, the orthographic projection of the first via V1 on the substrate at least partially overlaps the orthographic projection of the first region of the first active layer and the first connection electrode 41 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer in the first via V1 are etched away, at the same time exposing the surface of the first region of the first active layer and the surface of the first connection electrode 41. The first via V1 is a switching via composed of two half-holes, one half-hole exposing the surface of the first region of the first active layer, and the other half-hole exposing the surface of the first connection electrode 41. In the example embodiment, the first via V1 is configured to allow the subsequently formed connection electrode to connect with the first region of the first active layer and the first connection electrode 41 through the via.

[0234] In the example embodiment, the first via V1 in the first sub-pixel P1 and the second sub-pixel P2 can have a projection on the substrate within the projection on the substrate of the area surrounded by the first annular structure, and the first via V1 in the third sub-pixel P3 and the fourth sub-pixel P4 can have a projection on the substrate within the projection on the substrate of the area surrounded by the second annular structure.

[0235] In the example embodiment, the second via V2 has a projection on the substrate at least partially overlapping the projection on the substrate of the second region of the first active layer and the third connecting electrode 43, and the third insulating layer and the second insulating layer in the second via V2 are etched to expose the surface of the second region of the first active layer and the surface of the third connecting electrode 43. The second via V2 is a transfer via composed of two half-holes, one of which exposes the surface of the second region of the first active layer, and the other of which exposes the surface of the third connecting electrode 43. In the example embodiment, the second via V2 is configured to allow the fifth connecting electrode formed subsequently to pass through the via and connect with the second region of the first active layer and the third connecting electrode 43.

[0236] In the example embodiment, the third via V3 has a projection on the substrate at least partially overlapping the projection on the substrate of the first region of the second active layer and the fourth connecting electrode 44, and the third insulating layer and the second insulating layer in the third via V3 are etched to expose the surface of the first region of the second active layer and the surface of the fourth connecting electrode 44. The third via V3 is a transfer via composed of two half-holes, one of which exposes the surface of the first region of the second active layer, and the other of which exposes the surface of the fourth connecting electrode 44. In the example embodiment, the third via V3 is configured to allow the seventh connecting electrode formed subsequently to pass through the via and connect with the first region of the second active layer and the fourth connecting electrode 44. In the example embodiment, there can be multiple third vias V3, and the multiple third vias V3 can be arranged in sequence along the second direction Y to increase the connection reliability.

[0237] In the example embodiment, the fourth via V4 has a projection on the substrate that at least partially overlaps with the projection on the substrate of the second region of the second active layer and the third plate 13. The third insulating layer, the second insulating layer and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the second active layer and the surface of the third plate 13. The fourth via V4 is a transfer via, consisting of two half-holes, one of which exposes the surface of the second region of the second active layer, and the other of which exposes the surface of the third plate 13. In the example embodiment, the fourth via V4 is configured to allow the fifth plate formed subsequently to pass through the via while connecting with the second region of the second active layer and the third plate 13. In the example embodiment, there can be multiple fourth vias V4, which can be arranged in sequence along the second direction Y to increase the connection reliability.

[0238] In the example embodiment, the fifth via V5 has a projection on the substrate that at least partially overlaps with the projection on the substrate of the first region of the third active layer and the second connection electrode 42. The third insulating layer, the second insulating layer and the first insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the third active layer and the surface of the second connection electrode 42. The fifth via V5 is a transfer via, consisting of two half-holes, one of which exposes the surface of the first region of the third active layer, and the other of which exposes the surface of the second connection electrode 42. In the example embodiment, the fifth via V5 is configured to allow the ninth connection electrode formed subsequently to pass through the via while connecting with the first region of the third active layer and the second connection electrode 42.

[0239] In the example embodiment, the projection on the substrate of the fifth via V5 in the first sub-pixel P1 and the second sub-pixel P2 can be located within the projection on the substrate of the area enclosed by the first annular structure, and the projection on the substrate of the fifth via V5 in the third sub-pixel P3 and the fourth sub-pixel P4 can be located within the projection on the substrate of the area enclosed by the second annular structure.

[0240] In the example embodiment, the sixth via V6 has a projection on the substrate that at least partially overlaps with the projection on the substrate of the second region of the third active layer and the third plate 13. The third insulating layer, the second insulating layer and the first insulating layer within the sixth via V6 are etched away, exposing the surface of the second region of the third active layer and the surface of the third plate 13. The sixth via V6 is a transfer via, consisting of two half-holes, one of which exposes the surface of the second region of the third active layer, and the other of which exposes the surface of the third plate 13. In the example embodiment, the sixth via V6 is configured to allow the fifth plate formed subsequently to pass through the via while connecting with the second region of the third active layer and the third plate 13.

[0241] In the example embodiment, the normal projection of the seventh via V7 on the substrate at least partially overlaps the normal projection of the second plate 12 and the second gate electrode 32 on the substrate, and the third insulating layer and the second insulating layer in the seventh via V7 are etched away, exposing the surface of the second plate 12 and the surface of the second gate electrode 32. The seventh via V7 is a transfer via, composed of two half-holes, one of which exposes the surface of the second plate 12, and the other of which exposes the surface of the second gate electrode 32. In the example embodiment, the seventh via V7 is configured to allow the eighth connection electrode formed subsequently to pass through the via while connecting with the second plate 12 and the second gate electrode 32.

[0242] In the example embodiment, the normal projection of the eighth via V8 on the substrate is within the range of the normal projection of the first power line 71 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighth via V8 are etched away, exposing the surface of the first power line 71, and the eighth via V8 is configured to allow the sixth connection electrode formed subsequently to pass through the via and connect with the first power line 71.

[0243] In the example embodiment, the normal projection of the ninth via V9 on the substrate is within the range of the normal projection of the fourth connection electrode 44 on the substrate, the third insulating layer and the second insulating layer in the ninth via V9 are etched away, exposing the surface of the fourth connection electrode 44, and the ninth via V9 is configured to allow the sixth connection electrode formed subsequently to pass through the via and connect with the fourth connection electrode 44.

[0244] In the example embodiment, the at least one repeating unit can further include a tenth via V10 disposed in the first sub-pixel P1, an eleventh via V11 disposed in the second sub-pixel P2, and a twelfth via V12 disposed in the third sub-pixel P3.

[0245] In the example embodiment, the normal projection of the tenth via V10 on the substrate is within the range of the normal projection of the fourth data connection block 64-1 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via V10 are etched away, exposing the surface of the fourth data connection block 64-1, and the tenth via V10 is configured to allow the eleventh connection electrode formed subsequently to pass through the via and connect with the fourth data connection block 64-1.

[0246] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is within the range of the normal projection of the third data connection block 63-1 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eleventh via V11 are etched away, exposing the surface of the third data connection block 63-1, and the eleventh via V11 is configured to allow the twelfth connection electrode formed subsequently to pass through the via and connect with the third data connection block 63-1.

[0247] In an example embodiment, the orthogonal projection of the twelfth via V12 on the substrate is located within the range of the orthogonal projection of the second data connection block 62-1 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the twelfth via V12 are etched away to expose the surface of the second data connection block 62-1, and the twelfth via V12 is configured to connect the thirteenth connection electrode formed subsequently therethrough to the second data connection block 62-1.

[0248] In an example embodiment, the present patterning process can adopt a half tone mask process.

[0249] (16) Forming a third conductive layer pattern. In an example embodiment, forming a third conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a third conductive thin film, patterning the third conductive thin film by a patterning process, and forming a third conductive layer pattern on the third insulating layer, as shown in FIGS. 12A and 12B, FIG. 12B is a schematic diagram of the third conductive layer in FIG. 12A.

[0250] In an example embodiment, the third conductive layer of each sub-pixel in the display substrate can at least include a fifth electrode plate 15 for storing a capacitance, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a ninth connection electrode 49, a second power supply line 72, a compensation signal line 73, and an electrode plate connection electrode 81.

[0251] In an example embodiment, the shape of the second power supply line 72 can be a straight line or a broken line with a main body portion extending along the second direction Y, and the second power supply line 72 can be located on the side of the first power supply line 71 away from the fourth data signal line 64, and the second power supply line 72 is configured to provide a second power supply signal to the light emitting device of each sub-pixel.

[0252] In an example embodiment, considering the problem of voltage drop (IR Drop) existing in large-size transparent display, the present disclosure embodiment is provided with a second power supply line for transmitting a low-voltage signal in each repeating unit, and the second power supply line is connected to the cathode of the light emitting device formed subsequently, which can effectively reduce the voltage drop of the second power supply signal and effectively solve the problem of voltage drop existing in large-size transparent display, thereby ensuring display uniformity.

[0253] In an example embodiment, the shape of the compensation signal line 73 can be a straight line or a broken line with a main body portion extending along the second direction Y, and the compensation signal line 73 can be located between the fourth data signal line 64 and the first power supply line 71, and the compensation signal line 73 is configured to provide a compensation signal to the pixel driving circuit of each sub-pixel.

[0254] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0255] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0256] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0257] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0258] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0259] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0260] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0261] In the at least one repeating unit, the second power line 72 and the compensation signal line 73 can have a second spacing S2 therebetween, the second spacing S2 can be the minimum spacing between the edge of the fourth data signal line 64 close to the compensation signal line 73 and the edge of the compensation signal line 73 close to the fourth data signal line 64, which is the dimension of the first direction X.

[0262] In the example embodiment, the fifth plate 15 can be rectangular in shape, and the corners of the rectangular shape can be chamfered or recessed. The fifth plate 15 can be arranged in the region where the third plate 13 is located. The orthographic projection of the fifth plate 15 on the substrate at least partially overlaps the orthographic projection of the fourth plate 14 on the substrate. The fifth plate 15 can serve as the upper plate of the second capacitor. The fifth plate 15 is configured to form a second sub-capacitor of the second capacitor together with the fourth plate 14.

[0263] In the example embodiment, the fifth plate 15 is connected to the second region of the second active layer and the third plate 13 at the same time through the fourth via V4, and is connected to the second region of the third active layer and the third plate 13 at the same time through the sixth via V6. This not only realizes the connection between the second electrode of the second transistor T2, the second electrode of the third transistor T3, the third plate 13, and the fifth plate 15, forming the second node N2 of the pixel driving circuit, but also makes the third plate 13 and the fifth plate 15 of the second capacitor have the same potential of the second node N2.

[0264] In the example embodiment, the entire plate connection electrode 81 is in the shape of a "T" and protrudes towards the light-transmitting region 120 of the present repeating unit. The orthographic projection of the plate connection electrode 81 on the substrate at least partially overlaps the orthographic projection of the light-transmitting region 120 on the substrate. The plate connection electrode 81 can include a plate connection strip 81-1 and a plate connection block 81-2. The plate connection strip 81-1 can be in the shape of a strip extending along the first direction X. The first end of the plate connection strip 81-1 is connected to the fifth plate 15, and the second end of the plate connection strip 81-1 extends away from the fifth plate 15 to the adjacent light-transmitting region 120 and is connected to the plate connection block 81-2. The plate connection block 81-2 can be in the shape of a block (e.g., a rectangle) and is arranged in the light-transmitting region 120. The plate connection block 81-2 is configured to be connected to the anode connection electrode formed subsequently.

[0265] In the example embodiment, in at least one sub-pixel, the plate connection strip 81-1 and the plate connection block 81-2 can be an integrated structure connected to each other.

[0266] In the example embodiment, in at least one sub-pixel, the fifth plate 15 and the plate connection electrode 81 can be an integrated structure connected to each other.

[0267] In the example embodiment, the fifth connection electrode 45 can be in the shape of a block (such as a rectangle), and the fifth connection electrode 45 is connected to the second region of the first active layer and the third connection electrode 43 through the second via V2. Since the third connection electrode 43 is connected to the fourth plate 14, and the fourth plate 14 is connected to the second gate electrode 32, the fifth connection electrode 45 realizes the interconnection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the fourth plate 14 in each sub-pixel, forming the first node N1 of the pixel driving circuit.

[0268] In the example embodiment, the sixth connection electrode 46 can be in the shape of a block (such as a rectangle), and the sixth connection electrode 46 is connected to the first power line 71 through the eighth via V8 and connected to the fourth connection electrode 44 through the ninth via V9.

[0269] In the example embodiment, the seventh connection electrode 47 can be in the shape of a block (such as a rectangle), and the seventh connection electrode 47 is connected to the first region of the second active layer and the fourth connection electrode 44 through the third via V3. Since the fourth connection electrode 44 is connected to the first power line 71, the first power line 71 realizes the writing of the first power signal to the first electrode of the second transistor T2.

[0270] In the example embodiment, since the first electrode of the second transistor T2 in each sub-pixel is connected to the first power line 71 through the fourth connection electrode 44, the sixth connection electrode 46, and the seventh connection electrode 47, four pixel driving circuits in one display area 110 can share one first power line 71, i.e., the first power line 71 in one repeating unit is in a one-to-four structure. The display substrate of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, fully utilizes the layout space, improves the space utilization rate, and is conducive to improving the resolution and transparency by designing the first power line 71 in a one-to-four structure.

[0271] In the example embodiment, the eighth connection electrode 48 can be in the shape of a block (such as a rectangle), and the eighth connection electrode 48 is connected to the second plate 12 and the second gate electrode 32 through the seventh via V7. Since the second gate electrode 32 is connected to the fourth plate 14, the eighth connection electrode 48 realizes that the second plate 12 of the first capacitor and the fourth plate 14 of the second capacitor have the same potential of the first node N1.

[0272] In the example embodiment, the ninth connection electrode 49 can be in the shape of a block (such as a rectangle), and the ninth connection electrode 49 is connected to the first region of the third active layer and the second connection electrode 42 through the fifth via V5.

[0273] In an example embodiment, the ninth connection electrodes 49 in the first sub-pixel P1 and the second sub-pixel P2 can be an integral structure connected to each other, and the ninth connection electrodes 49 in the third sub-pixel P3 and the fourth sub-pixel P4 can be an integral structure connected to each other.

[0274] In an example embodiment, the third conductive layer of each repeating unit in the display substrate can further include an eleventh connection electrode 51, a twelfth connection electrode 52, a thirteenth connection electrode 53, and a fourteenth connection electrode 54.

[0275] In an example embodiment, the eleventh connection electrode 51 can be in a strip shape extending along the first direction X, and can be disposed in the first sub-pixel P1. A first end of the eleventh connection electrode 51 is connected to the first region of the first active layer and the first connection electrode 41 in the first sub-pixel P1 through the first via V1, and a second end of the eleventh connection electrode 51 is connected to the fourth data connection block 64-1 through the tenth via V10. Since the fourth data connection block 64-1 is connected to the fourth data signal line 64, the fourth data signal line 64 writes the fourth data signal to the first electrode of the first transistor T1 in the first sub-pixel P1 is achieved.

[0276] In an example embodiment, the twelfth connection electrode 52 can be in a strip shape extending along the first direction X, and can be disposed in the second sub-pixel P2. A first end of the twelfth connection electrode 52 is connected to the first region of the first active layer and the first connection electrode 41 in the second sub-pixel P2 through the first via V1, and a second end of the twelfth connection electrode 52 is connected to the third data connection block 63-1 through the eleventh via V11. Since the third data connection block 63-1 is connected to the third data signal line 63, the third data signal line 63 writes the third data signal to the first electrode of the first transistor T1 in the second sub-pixel P2 is achieved.

[0277] In an example embodiment, the thirteenth connection electrode 53 can be in a strip shape extending along the first direction X, and can be disposed in the third sub-pixel P3. A first end of the thirteenth connection electrode 53 is connected to the first region of the first active layer and the first connection electrode 41 in the third sub-pixel P3 through the first via V1, and a second end of the thirteenth connection electrode 53 is connected to the second data connection block 62-1 through the twelfth via V12. Since the second data connection block 62-1 is connected to the second data signal line 62, the second data signal line 62 writes the second data signal to the first electrode of the first transistor T1 in the third sub-pixel P3 is achieved.

[0278] In an example embodiment, the fourteenth connection electrode 54 can be in the shape of a block (e.g., a rectangle), and can be disposed in the fourth sub-pixel P4. The fourteenth connection electrode 54 is connected to the first region of the first active layer and the first connection electrode 41 in the fourth sub-pixel P4 through the first via V1. Since the first connection electrode 41 in the fourth sub-pixel P4 is connected to the first data signal line 61 through the first data connection block, the first data signal line 61 writes the first data signal to the first electrode of the first transistor T1 in the fourth sub-pixel P4.

[0279] In an example embodiment, the third conductive layer of each repeating unit in the display substrate can further include a fifteenth connection electrode 55 and a sixteenth connection electrode 56.

[0280] In an example embodiment, the fifteenth connection electrode 55 can be in the shape of a strip extending along the first direction X, and can be disposed in the region between the first sub-pixel P1 and the second sub-pixel P2. The first end of the fifteenth connection electrode 55 is connected to the compensation signal line 73, and the second end of the fifteenth connection electrode 55 is connected to the ninth connection electrode 49 in the first sub-pixel P1 and the ninth connection electrode 49 in the second sub-pixel P2, respectively. Since the ninth connection electrode 49 is connected to the first region of the third active layer and the second connection electrode 42, the compensation signal line 73 writes the compensation signal to the first electrode of the third transistor T3 in the first sub-pixel P1 and the first electrode of the third transistor T3 in the second sub-pixel P2.

[0281] In an example embodiment, since the third transistors T3 in the first sub-pixel P1 and the second sub-pixel P2 are adjacent to each other, the third transistors T3 in the two sub-pixels can share the same fifteenth connection electrode 55 as the lateral compensation connection line, the number of lateral compensation connection lines can be reduced, the layout space can be saved, and the yield can be improved.

[0282] In an example embodiment, in at least one repeating unit, the ninth connection electrode 49, the fifteenth connection electrode 55, and the compensation signal line 73 of the integrated structure in the first sub-pixel P1 and the second sub-pixel P2 can be an integrated structure connected to each other.

[0283] In the example embodiment, the shape of the sixteenth connection electrode 56 can be a strip shape extending along the first direction X, the sixteenth connection electrode 56 can be arranged in the region between the third sub-pixel P3 and the fourth sub-pixel P4, the first end of the sixteenth connection electrode 56 is connected with the compensation signal line 73, and the second end of the sixteenth connection electrode 56 is connected with the ninth connection electrode 49 in the third sub-pixel P3 and the ninth connection electrode 49 in the fourth sub-pixel P4, respectively. Since the ninth connection electrode 49 is connected with the first region of the third active layer and the second connection electrode 42 at the same time, the compensation signal line 73 writes the compensation signal to the first electrode of the third transistor T3 in the third sub-pixel P3 and the first electrode of the third transistor T3 in the fourth sub-pixel P4 is realized.

[0284] In the example embodiment, since the third transistors T3 in the third sub-pixel P3 and the fourth sub-pixel P4 are adjacent to each other, the third transistors T3 of the two sub-pixels can share the same sixteenth connection electrode 56 as the lateral compensation connection line, the number of lateral compensation connection lines can be reduced, the layout space can be saved, and the yield can be improved.

[0285] In the example embodiment, in at least one repeating unit, the ninth connection electrode 49, the fifteenth connection electrode 55 and the compensation signal line 73 of the integrated structure in the third sub-pixel P3 and the fourth sub-pixel P4 can be an integrated structure connected with each other.

[0286] In the example embodiment, the fifteenth connection electrode 55, the sixteenth connection electrode 56 and the compensation signal line 73 can be an integrated structure connected with each other. Compared with the structure that the lateral compensation connection line and the compensation signal line are connected through the via hole, the number of via holes is reduced, the occupied space is reduced, the connection structure is simplified, and the resolution and transparency are improved.

[0287] In the example embodiment, the orthographic projection of the fifteenth connection electrode 55 and the sixteenth connection electrode 56 on the substrate at least partially overlaps with the orthographic projection of the first data signal line 61 to the fourth data signal line 64 on the substrate. Since the first data signal line 61 to the fourth data signal line 64 are arranged in the first conductive layer, the fifteenth connection electrode 55 and the sixteenth connection electrode 56 are arranged in the third conductive layer, and the first conductive layer and the third conductive layer are separated by the first insulating layer, the second insulating layer and the third insulating layer, the occurrence of cross-line defects can be effectively reduced.

[0288] In the example embodiment, since the fifteenth connection electrode 55 and the sixteenth connection electrode 56 are both connected with the compensation signal line 73, the compensation signal line 73 can provide the compensation signal to the pixel driving circuit in each sub-pixel through the fifteenth connection electrode 55 and the sixteenth connection electrode 56, and thus four pixel driving circuits in one display area 110 can share one compensation connection line 73, that is, the compensation connection line in one repeating unit is a one-to-four structure. The display substrate of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, fully utilizes the layout space, improves the space utilization rate, and is conducive to improving the resolution and transparency by designing the compensation signal line as a one-to-four structure.

[0289] In the example embodiment, since the fourth data signal line 64 and the first power line 71 are arranged in one conductive layer, and the second power line 72 and the compensation signal line 73 are arranged in another conductive layer, the structure that the compensation signal line 73 is arranged between the fourth data signal line 64 and the first power line 71, and the structure that the first power line 71 is arranged between the compensation signal line 73 and the second power line 72, can effectively reduce the distance between the fourth data signal line 64 and the compensation signal line 73, reduce the distance between the first power line 71 and the compensation signal line 73, reduce the distance between the first power line 71 and the second power line 72, reduce the occupied area of the plurality of signal lines, reduce the area of the display area, and improve the area of the light transmission area.

[0290] In the example embodiment, in at least one repeating unit, the ninth connection electrode 49 in the integrated structure in the first sub-pixel P1 and the second sub-pixel P2 and the ninth connection electrode 49 in the integrated structure in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the sub-pixel center line between the second sub-pixel P2 and the third sub-pixel P3, and the fifteenth connection electrode 55 and the sixteenth connection electrode 56 can be arranged substantially symmetrically with respect to the sub-pixel center line between the second sub-pixel P2 and the third sub-pixel P3. The present disclosure can ensure that the RC delay of the compensation signal written to the third transistor T3 is substantially the same through the symmetric structure that the third transistor T3 is connected with the compensation connection line, and ensures the display uniformity.

[0291] In the example embodiment, since the first plate 11 is overlapped with the third plate 13, the first plate 11 has the potential of the second node N2. Since the second plate 12 and the fourth plate 14 are connected through the eighth connection electrode 48, the second plate 12 has the potential of the first node N1. In this way, the first plate 11 having the potential of the second node N2 and the second plate 12 having the potential of the first node N1 form the first capacitor.

[0292] In the example embodiment, since the third plate 13 as the lower plate has the potential of the second node N2, and the fourth plate 14 as the intermediate plate has the potential of the first node N1, the third plate 13 having the potential of the second node N2 and the fourth plate 14 having the potential of the first node N1 constitute a first sub-capacitance of the second capacitance. Since the fourth plate 14 as the intermediate plate has the potential of the first node N1, and the fifth plate 15 as the upper plate has the potential of the second node N2, the fourth plate 14 having the potential of the first node N1 and the fifth plate 15 having the potential of the second node N2 constitute a second sub-capacitance of the second capacitance.

[0293] In the example embodiment, the first sub-capacitance and the second sub-capacitance are in a parallel structure. The disclosure forms the first sub-capacitance and the second sub-capacitance in a parallel structure by the first conductive layer, the second conductive layer and the third conductive layer, and the first sub-capacitance and the second sub-capacitance in a parallel structure constitute the second capacitance, which on the one hand can effectively increase the capacitance value of the second capacitance, and on the other hand can reduce the plate area while ensuring the capacitance value of the second capacitance, effectively reducing the occupied area.

[0294] In the example embodiment, the first capacitance and the second capacitance are in a parallel structure. The disclosure forms the first capacitance and the second capacitance in a parallel structure, and the first capacitance and the second capacitance in a parallel structure constitute the storage capacitance of the pixel driving circuit, which on the one hand can effectively increase the capacitance value of the storage capacitance, and on the other hand can reduce the plate area while ensuring the storage capacitance, effectively reducing the occupied area. In addition, the first capacitance is a transparent capacitance, and part of the transparent capacitance is arranged in the light transmission region, which can effectively increase the capacity of the storage capacitance with less impact on the transmittance.

[0295] In the example embodiment, the first capacitance can have a first capacitance value Cst1, and the second capacitance can have a second capacitance value Cst2, and the storage capacitance value Cst of the storage capacitance is Cst1+Cst2. Since the first capacitance is arranged in the light transmission region, the first capacitance value Cst1 can be determined by the size of the storage capacitance value Cst and the second capacitance value Cst2, and the area of the two transparent plates of the first capacitance can be adjusted in the light transmission region according to actual conditions. Since the second capacitance is arranged in the display region, the size of the second capacitance value Cst2 is actually determined by the sub-pixel layout space. When the horizontal space in the sub-pixel is relatively sufficient, the area of the three plates of the second capacitance can be appropriately increased in the first direction X. When the vertical space in the sub-pixel is relatively sufficient, the area of the three plates of the second capacitance can be appropriately increased in the second direction Y. In this way, the area of the three plates of the second capacitance can be minimized to maximize the area of the light transmission region.

[0296] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate can further include at least one auxiliary connection electrode 82.

[0297] In an exemplary embodiment, the auxiliary connection electrode 82 can have an overall "T" shape, and can include an auxiliary connection strip 82-1 and an auxiliary connection block 82-2. The auxiliary connection strip 82-1 can have a strip shape extending along the first direction X, with a first end connected to the second power line 72 and a second end extending into the adjacent light-transmissive region 120 away from the second power line 72 and connected to the auxiliary connection block 82-2. The auxiliary connection block 82-2 can have a block shape (e.g., a rectangular shape) disposed in the light-transmissive region 120 and configured to be connected to a subsequently formed auxiliary cathode.

[0298] In an exemplary embodiment, there can be five auxiliary connection electrodes 82 in at least one repeating unit. For example, there can be two auxiliary connection electrodes 82 in the first sub-pixel P1, two auxiliary connection electrodes 82 in the fourth sub-pixel P4, and one auxiliary connection electrode 82 between the second sub-pixel P2 and the third sub-pixel P3.

[0299] In an exemplary embodiment, the auxiliary connection strip 82-1 and the auxiliary connection block 82-2 can be an integrated structure connected to each other in at least one sub-pixel.

[0300] In an exemplary embodiment, the second power line 72 and the auxiliary connection electrode 82 can be an integrated structure connected to each other in at least one repeating unit.

[0301] (17) Forming a fourth insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the fourth insulating layer and the first planar layer pattern can include: on a substrate on which the aforementioned patterns are formed, first depositing a fourth insulating thin film, then coating a first planar thin film, and patterning the fourth insulating thin film and the first planar thin film by a patterning process to form a fourth insulating layer covering the third conductive layer and a first planar layer pattern disposed on the fourth insulating layer, with a plurality of vias disposed on the fourth insulating layer and the first planar layer, as shown in FIG. 13.

[0302] In an exemplary embodiment, at least one repeating unit can include four twenty-first vias V21 and five twenty-second vias V22.

[0303] In an example embodiment, the orthogonal projection of each twenty-first via V21 on the substrate is within the orthogonal projection of the plate connecting block 81-2 of the plate connecting electrode 81 on the substrate, the fourth insulating layer and the first planar layer within the twenty-first via V21 are removed to expose the surface of the plate connecting block 81-2, and the twenty-first via V21 is configured to allow the anode connecting electrode formed subsequently to connect with the plate connecting block 81-2 through the via.

[0304] In an example embodiment, the orthogonal projection of each twenty-second via V22 on the substrate is within the orthogonal projection of the auxiliary connecting block 82-2 of the auxiliary connecting electrode 82 on the substrate, the fourth insulating layer and the first planar layer within the twenty-second via V22 are removed to expose the surface of the auxiliary connecting block 82-2, and the twenty-second via V22 is configured to allow the auxiliary cathode formed subsequently to connect with the auxiliary connecting block 82-2 through the via.

[0305] In an example embodiment, the present patterning process can employ a half tone mask process.

[0306] In an example embodiment, the display substrate can further include a color filter layer. On the substrate with the aforementioned pattern, the fourth insulating layer is formed first, and then the color filter layer is formed on the fourth insulating layer by a patterning process. The color filter layer can include at least red filter, blue filter and green filter. Subsequently, a planar film is coated, and the planar film and the fourth insulating film are patterned by a patterning process to form a fourth insulating layer covering the third conductive layer, a color filter layer disposed on the fourth insulating layer, and a planar layer covering the color filter layer pattern. The planar layer and the fourth insulating layer are provided with a plurality of vias.

[0307] In an example embodiment, the first planar layer and the color filter layer can be provided only in the display area 110, and the first planar layer and the color filter layer located in the light-transmitting area 120 are removed completely, including the area where the plate connecting electrode 81 and the auxiliary connecting electrode 82 are located.

[0308] (18) Forming a second transparent conductive layer pattern. In an example embodiment, forming the second transparent conductive layer pattern can include: on the substrate with the aforementioned pattern, depositing a second transparent conductive film, and patterning the second transparent conductive film by a patterning process to form a second transparent conductive layer pattern. As shown in FIG. 14A and FIG. 14B, FIG. 14B is a schematic view of the second transparent conductive layer in FIG. 14A. In an example embodiment, the second transparent conductive layer can be referred to as a 2st ITO layer.

[0309] In an example embodiment, the second transparent conductive layer of each sub-pixel in the display substrate can include at least an anode 91 and an anode connecting electrode 92.

[0310] In an exemplary embodiment, the anode 91 in the at least one sub-pixel can include a first sub-anode 91-1 and a second sub-anode 91-2 arranged separately, shapes of the first sub-anode 91-1 and the second sub-anode 91-2 can be rectangular, the first sub-anode 91-1 and the second sub-anode 91-2 can be located in the display area 110 and arranged on the first flat layer, and the first sub-anode 91-1 and the second sub-anode 91-2 can be arranged in sequence along the second direction Y.

[0311] In an exemplary embodiment, a shape of the anode connecting electrode 92 can be a "C" shape, the anode connecting electrode 92 is arranged on the fourth insulating layer and protrudes towards the light-transmitting area 120 of the present repeating unit, and a normal projection of the anode connecting electrode 92 on the substrate at least partially overlaps with a normal projection of the light-transmitting area 120 on the substrate. The anode connecting electrode 92 can include a first sub-connecting electrode 92-1, a second sub-connecting electrode 92-2, and a third sub-connecting electrode 92-3, shapes of the first sub-connecting electrode 92-1 and the second sub-connecting electrode 92-2 can be strip shapes extending along the first direction X, and a shape of the third sub-connecting electrode 92-3 can be a strip shape extending along the second direction Y. A first end of the first sub-connecting electrode 92-1 is connected with the first sub-anode 91-1, a first end of the second sub-connecting electrode 92-2 is connected with the second sub-anode 91-2, and second ends of the first sub-connecting electrode 92-1 and the second sub-connecting electrode 92-2 are connected with first and second ends of the third sub-connecting electrode 92-3, respectively, after extending to the light-transmitting area 120 of the present repeating unit, and the third sub-connecting electrode 92-3 is connected with the plate connecting block 81-2 through the twenty-first via hole V21. In an exemplary embodiment, the anode connecting electrode 92 realizes the mutual connection between the first sub-anode 91-1 and the second sub-anode 91-2, and the anode 91 is connected with the fifth plate 15 through the plate connecting block 81-2 and the plate connecting strip 81-1, so that the anode 91 is connected with the fifth plate 15 of the storage capacitor.

[0312] In an exemplary embodiment, the plate connecting electrode 81 and the anode connecting electrode 92 can be the third protruding structure of the present disclosure, that is, the third protruding structure can include the plate connecting electrode 81 and the anode connecting electrode 92 located on different conductive layers. The third protruding structure protrudes towards the light-transmitting area 120 of the present repeating unit, and a normal projection of the third protruding structure on the substrate at least partially overlaps with a normal projection of the light-transmitting area 120 on the substrate, so as to weaken the diffraction effect and improve the transparent display effect.

[0313] In an example embodiment, the first sub-connection electrode 92-1 can have a fifth protruding width D5 between the edge of the first sub-connection electrode 92-1 close to the edge of the plate connecting strip 81-1 and the edge of the plate connecting strip 81-1 close to the first sub-connection electrode 92-1, or the second sub-connection electrode 92-2 can have a fifth protruding width D5 between the edge of the second sub-connection electrode 92-2 close to the edge of the plate connecting strip 81-1 and the edge of the plate connecting strip 81-1 close to the second sub-connection electrode 92-2.

[0314] In an example embodiment, the first protruding width D1 can be greater than the fifth protruding width D5, the second protruding width D2 can be greater than the fifth protruding width D5, the third protruding width D3 can be greater than the fifth protruding width D5, and the fourth protruding width D4 can be greater than the fifth protruding width D5, which not only helps to weaken the diffraction effect and improve the transparent display effect, but also facilitates the repair of the scanning signal line.

[0315] In an example embodiment, when a bright spot defect occurs in the display substrate, the anode connecting electrode 92 can be cut off by a laser cutting method, so that one of the first sub-anode 91-1 and the second sub-anode 91-2 is connected to the fifth plate 15, and the other is floating, thereby repairing the bright spot defect.

[0316] In an example embodiment, the twenty-first via hole V21 can be referred to as an anode via hole, and the orthogonal projection of the anode via hole on the base does not overlap with the orthogonal projection of the first sub-anode 91-1 and the second sub-anode 91-2 on the base, which not only can improve the success rate of repairing the bright spot defect and avoid the influence of repair on the pixel driving circuit, but also can ensure the flatness of the anode and improve the light-emitting quality of the light-emitting device and the display effect.

[0317] In an example embodiment, the four anodes 91 in the repeating unit are arranged in a vertical manner, the anode 91 in the first sub-pixel P1 is connected to the pixel driving circuit in the sub-pixel, the anode 91 in the second sub-pixel P2 is connected to the pixel driving circuit in the sub-pixel, the anode 91 in the third sub-pixel P3 is connected to the pixel driving circuit in the sub-pixel, and the anode 91 in the fourth sub-pixel P4 is connected to the pixel driving circuit in the sub-pixel. In some possible implementations, the arrangement of the anode can be adjusted according to actual needs, which is not limited in the present disclosure.

[0318] In an example embodiment, the first sub-anode 91-1, the second sub-anode 91-2, and the anode connecting electrode 92 in each sub-pixel can be an integrated structure connected to each other.

[0319] In the example embodiment, the second transparent conductive layer of the at least one repeating unit can further include an auxiliary cathode 93. The auxiliary cathode 93 can be in a block shape (e.g., a rectangular shape), a normal projection of the auxiliary cathode 93 on the substrate at least partially overlaps a normal projection of the auxiliary connecting block 82-2 on the substrate, the auxiliary cathode 93 can be connected to the auxiliary connecting block 82-2 through the twenty-second via hole V22, and the auxiliary cathode 93 is configured to be connected to a subsequently formed cathode.

[0320] In the example embodiment, the auxiliary cathode 93 can adopt a resistive island (RIB) structure, and a cross-sectional shape of the auxiliary cathode 93 can be an inverted trapezoid, so that a subsequently formed organic light-emitting layer can be disconnected at a side edge of the auxiliary cathode 93 to form isolated and separated organic light-emitting blocks, effectively avoiding interference of the organic light-emitting blocks with the emitted light, improving the quality of the emitted light, and being conducive to improving display quality.

[0321] In the example embodiment, the auxiliary cathode is further configured to reduce a diffraction effect of the transparent area. By arranging the auxiliary cathode in the transparent area, the transparent area is changed from a regular rectangle to an irregular shape, and different positions of the transparent area have different slit widths. When light passes through the transparent area in the irregular shape, the diffraction fringes are generated in different directions due to different positions of the diffraction fringes, so the diffraction fringes of the light are not diffused in one direction but in multiple directions, greatly weakening the diffraction effect, avoiding the phenomenon of virtualization of objects behind the screen, and improving the transparent display effect.

[0322] In the example embodiment, in a plane parallel to the substrate, the shape of the auxiliary cathode can include any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, and a hexagon.

[0323] In the example embodiment, the material of the second transparent conductive layer can adopt a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0324] (19) Forming a pixel definition layer. In the example embodiment, forming a pixel definition layer pattern can include: on the substrate on which the aforementioned pattern is formed, applying a pixel definition film, and patterning the pixel definition film through a patterning process to form the pixel definition layer, as shown in FIG. 15.

[0325] In the example embodiment, the pixel definition layer of each sub-pixel in the display substrate is provided with a first pixel opening K1 and a second pixel opening K2, the pixel definition film in the first pixel opening K1 is removed to expose part of the surface of the first sub-anode 91-1 in the anode 91, and the pixel definition film in the second pixel opening K2 is removed to expose part of the surface of the second sub-anode 91-2 in the anode 91.

[0326] In an exemplary embodiment, the orthographic projection of the first pixel opening K1 on the substrate is within the range of the orthographic projection of the first sub-anode 91-1 on the substrate, and the orthographic projection of the second pixel opening K2 on the substrate is within the range of the orthographic projection of the second sub-anode 91-2 on the substrate.

[0327] In an exemplary embodiment, the shape of the first pixel opening K1 and the second pixel opening K2 can be similar to the shape of the sub-anode in a plane parallel to the substrate, and the cross-sectional shape of the first pixel opening K1 and the second pixel opening K2 can be rectangular or trapezoidal, etc. in a direction perpendicular to the substrate.

[0328] In an exemplary embodiment, the pixel definition layer of the light-transmitting region 120 is substantially removed to form a plurality of light-transmitting openings T.

[0329] In an exemplary embodiment, at least one light-transmitting opening T near one side of the display region 110 can be provided with a groove recessed toward the direction away from the display region 110, and the orthographic projection of the groove on the substrate contains the orthographic projection of the anode connecting electrode 92, the first protruding structure and the second protruding structure on the substrate, i.e. the area where the anode connecting electrode 92, the first protruding structure and the second protruding structure in the light-transmitting region 120 are covered by the pixel definition layer.

[0330] In an exemplary embodiment, the orthographic projection of the light-transmitting opening T on the substrate does not overlap with the orthographic projection of the scan transmission line 36 on the substrate, i.e. the area where the scan transmission line 36 in the light-transmitting region 120 is covered by the pixel definition layer.

[0331] In an exemplary embodiment, the orthographic projection of the light-transmitting opening T in the light-transmitting region 120 on the substrate contains the orthographic projection of the auxiliary cathode 93 on the substrate, i.e. the surface of the plurality of auxiliary cathodes 93 is exposed by the light-transmitting opening T.

[0332] In an exemplary embodiment, the pixel definition layer can be polyimide, acrylic or polyethylene terephthalate, etc.

[0333] Subsequently, the organic light-emitting layer pattern and the cathode pattern are formed. In an exemplary embodiment, forming the organic light-emitting layer and the cathode pattern can include: first forming the organic light-emitting layer pattern in the display region, and the organic light-emitting layer is connected with the first sub-anode and the second sub-anode through the first pixel opening and the second pixel opening respectively. Subsequently, the cathode is formed, and in the display region, the cathode is connected with the organic light-emitting layer, and in the light-transmitting region, the cathode is connected with the plurality of auxiliary cathodes. Since the auxiliary cathode is connected with the auxiliary connecting electrode, and the auxiliary connecting electrode is connected with the second power supply line, the connection of the cathode with the second power supply line is realized.

[0334] In an exemplary embodiment, the organic light-emitting layer can include an emission layer (EML), and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer can be formed by fine metal mask (FMM) or open mask evaporation, or by an inkjet process.

[0335] In an exemplary embodiment, the preparation process of the display substrate can further include forming a pattern of the encapsulation structure layer. Forming the pattern of the encapsulation structure layer can include: first depositing a first inorganic thin film using an open mask to form a first encapsulation layer. Subsequently, inkjet printing an organic material on the first encapsulation layer using an inkjet printing process, and after curing the film, forming a second encapsulation layer. Subsequently, depositing a second inorganic thin film using an open mask to form a third encapsulation layer, the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer forming the encapsulation structure layer. The first encapsulation layer and the third encapsulation layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbon nitride (SiCN), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The second encapsulation layer can be a resin material, forming a stack structure of inorganic material / organic material / inorganic material, with the organic material layer disposed between the two inorganic material layers, which can prevent external water vapor from entering the light-emitting device.

[0336] At this point, the preparation of the display substrate of the present embodiment is completed.

[0337] In an exemplary embodiment, the display substrate can include at least: a substrate, a first transparent conductive layer disposed on the substrate, a first conductive layer disposed on a side of the first transparent conductive layer distal from the substrate, a first insulating layer disposed on a side of the first conductive layer distal from the substrate, a semiconductor layer disposed on a side of the first insulating layer distal from the substrate, a second insulating layer disposed on a side of the semiconductor layer distal from the substrate, a second conductive layer disposed on a side of the second insulating layer distal from the substrate, a third insulating layer disposed on a side of the second conductive layer distal from the substrate, a third conductive layer disposed on a side of the third insulating layer distal from the substrate, a fourth insulating layer disposed on a side of the third conductive layer distal from the substrate, a first planarization layer disposed on a side of the fourth insulating layer distal from the substrate, and a second transparent conductive layer disposed on a side of the first planarization layer distal from the substrate.

[0338] In the exemplary embodiment, the first transparent conductive layer can include at least the first plate 11, the first conductive layer can include at least the third plate 13, the first to fourth data signal lines 61 to 64, and the first power supply line 71, the semiconductor layer can include at least the second plate 12, the first to third active layers 21 to 23, the second conductive layer can include at least the fourth plate 14, the second gate electrode 32, and the scan signal line 30, the third conductive layer can include at least the fifth plate 15, the second power supply line 72, the compensation signal line 73, and the plurality of connection electrodes, and the second transparent conductive layer can include at least the anode 91 and the anode connection electrode 92.

[0339] In the exemplary embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In the exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0340] In the exemplary embodiment, the first, second, and third conductive layers can employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first, second, third, and fourth insulating layers can employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), can be a single layer, a multi-layer, or a composite layer. The first planar layer can employ an organic material, such as resin, etc.

[0341] The display substrate provided by the embodiment of the present disclosure can maximize the area of the light-transmitting region and improve the transmittance by arranging all the pixel driving circuits on one side and all the vertical wires on the other side through the overall layout of the repeating unit.

[0342] The display substrate provided by the present disclosure adopts a pixel driving circuit with one scanning signal line, and the scanning signal line is connected with the first transistor and the third transistor in the pixel driving circuit. By reducing the number of scanning signal lines, the structure of the pixel driving circuit can be simplified, the occupied area of the pixel driving circuit can be reduced, high-resolution display can be achieved, the light-transmitting area of the light-transmitting region can be effectively increased, the space proportion of the light-transmitting region can be improved, and high-transparency display can be achieved. In addition, since only one scanning signal line is needed to drive one repeating unit, the number of corresponding gate driving circuits (GOA) and clock signal lines (CLK) can be reduced by several times, the occupied area of the gate driving circuit and the clock signal line can be effectively reduced, narrow frame can be achieved, and product advantages can be improved.

[0343] The display substrate provided by the present disclosure adopts a single-line structure of the scanning transmission line in the light-transmitting region and a double-ring structure of the first ring-shaped structure and the second ring-shaped structure in the display region. The single-line structure can not only ensure that the scanning signal line drives all the pixel driving circuits in the repeating region, but also realize the multi-channel function, repair the signal line at all positions, realize the full-signal bad repair, and effectively improve the product yield.

[0344] The display substrate provided by the present disclosure adopts a single-line structure of the scanning transmission line in the light-transmitting region and a double-ring structure of the first ring-shaped structure and the second ring-shaped structure in the display region. The single-line structure can not only ensure that the scanning signal line drives all the pixel driving circuits in the repeating region, but also realize the multi-channel function, repair the signal line at all positions, realize the full-signal bad repair, and effectively improve the product yield.

[0345] The display substrate provided by the present disclosure adopts a single-line structure of the scanning transmission line in the light-transmitting region and a double-ring structure of the first ring-shaped structure and the second ring-shaped structure in the display region. The single-line structure can not only ensure that the scanning signal line drives all the pixel driving circuits in the repeating region, but also realize the multi-channel function, repair the signal line at all positions, realize the full-signal bad repair, and effectively improve the product yield.

[0346] The display substrate of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, fully utilizes the layout space, improves the space utilization, and is beneficial to improving the resolution by setting a one-to-four structure of the first power line and a one-to-four structure of the compensation signal line.

[0347] The display substrate of the present disclosure can improve the success rate of repairing the bright spot defect, avoid the influence on the pixel driving circuit, and will not cause other defects, has a high repair success rate, can ensure the flatness of the anode, improve the light emitting quality of the light emitting device, and improve the display effect by setting the anode connecting electrode to connect the first sub-anode and the second sub-anode.

[0348] The display substrate of the present disclosure can effectively reduce the voltage drop of the second power supply and ensure the display uniformity by setting the second power line and the auxiliary cathode, and connecting the second power line with the cathode through the auxiliary cathode.

[0349] The display substrate of the present disclosure changes the light transmission area into an irregular shape by setting the anode connecting electrode, the auxiliary cathode, the first protruding structure and the second protruding structure in the light transmission area, and when the light passes through the light transmission area with an irregular shape, the diffraction fringes are generated in different directions due to the different positions of the diffraction fringes, so the diffraction fringes are diffused in multiple directions instead of one direction, the diffraction effect is greatly weakened, the object behind the screen is not blurred, and the transparent display effect is improved.

[0350] The preparation process of the example embodiment of the present disclosure is compatible with the existing preparation process, has a simple process, is easy to implement, has high production efficiency, low production cost, and high yield.

[0351] FIG. 16 is a structural schematic diagram of another display substrate according to an example embodiment of the present disclosure, which illustrates the structure of a repeating unit. As shown in FIG. 16, the main structure of the display substrate of the present embodiment is basically the same as that of the embodiment shown in FIG. 5, and the difference is that the second capacitor of the present embodiment is formed by the first conductive layer, the semiconductor layer and the third conductive layer.

[0352] FIG. 17 is a structural schematic diagram of another storage capacitor according to an example embodiment of the present disclosure, which is a sectional view in the direction of B-B in FIG. 16. As shown in FIG. 16 and FIG. 17, the at least one pixel driving circuit can include a first capacitor 10-1 and a second capacitor 10-2, and the first capacitor 10-1 and the second capacitor 10-2 are in parallel structure and together constitute the storage capacitor of the pixel driving circuit.

[0353] In the example embodiment, the first capacitor 10-1 can include the first and second plates 11 and 12 stacked together, the second capacitor 10-2 can include the third, fourth and fifth plates 13, 14 and 15 stacked together, the first plate 11 is connected to the third plate 13, the third plate 13 is connected to the fifth plate 15, and the second plate 12 is connected to the fourth plate 14, so that the first, third and fifth plates 11, 13 and 15 have the same electric potential, and the second and fourth plates 12 and 14 have the same electric potential, and the first and second capacitors 10-1 and 10-2 in parallel form a complete storage capacitor.

[0354] In the example embodiment, the display substrate can include at least the base 300, the first transparent conductive layer, the first conductive layer, the first insulating layer 301, the semiconductor layer, the second insulating layer 302, the second conductive layer, the third insulating layer 303, and the third conductive layer in the direction perpendicular to the display substrate.

[0355] In the example embodiment, the first transparent conductive layer can include at least the first plate 11, the first conductive layer can include at least the third plate 13, and the third plate 13 is overlapped with the first plate 11.

[0356] In the example embodiment, the semiconductor layer can include at least the second plate 12, the fourth plate 14, the second and third active layers 22 and 23, the second conductive layer can include at least the second gate electrode 32, and the third conductive layer can include at least the fifth plate 15, the eighth connection electrode 48 and the tenth connection electrode, the fifth plate 15 is connected to the third active layer 23 and the third plate 13 through the sixth via V6, the eighth connection electrode 48 is connected to the second plate 12 and the second gate electrode 32 through the seventh via V7, and the tenth connection electrode is connected to the fourth plate 14 and the second gate electrode 32 through the via, so that the third plate 13 and the fifth plate 15 have the same electric potential, and the second plate 12 and the fourth plate 14 have the same electric potential.

[0357] In the example embodiment, the preparation process of the display substrate can include the following operations.

[0358] (21) Forming a first transparent conductive layer pattern. In the example embodiment, the process of forming the first transparent conductive layer and the formed first transparent conductive layer pattern are basically the same as those in the embodiment shown in FIG. 5, and will not be described here again.

[0359] (22) Forming a first conductive layer pattern. In the example embodiment, the process of forming the first conductive layer and the formed first conductive layer pattern are basically the same as those in the embodiment shown in FIG. 5, and will not be described here again.

[0360] (23) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a first insulating thin film and a semiconductor thin film, patterning the semiconductor thin film by a patterning process, forming a first insulating layer covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIGS. 18A and 18B, FIG. 18B being a schematic view of the semiconductor layer in FIG. 18A.

[0361] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate can include at least a first active layer 21, a second active layer 22, a third active layer 23, a second plate 12 of a storage capacitor, and a fourth plate 14 of the storage capacitor. The structures of the first active layer 21, the second active layer 22, the third active layer 23, and the second plate 12 are substantially the same as those of the embodiment shown in FIG. 5.

[0362] In an exemplary embodiment, the first active layer 21 and the third active layer 23 can have a strip shape extending along the second direction Y, and the second active layer 22 can have a strip shape extending along the first direction X or a rectangular shape.

[0363] In an exemplary embodiment, the fourth plate 14 can have a rectangular shape, and a corner of the rectangular shape can be provided with a chamfer or a groove. A normal projection of the fourth plate 14 on the substrate at least partially overlaps a normal projection of the third plate 13 on the substrate. The fourth plate 14 can serve as an intermediate plate of the second capacitor. The fourth plate 14 is configured to form a first sub-capacitor of the second capacitor together with the third plate 13, and is further configured to form a second sub-capacitor of the second capacitor together with a fifth plate to be formed subsequently.

[0364] In an exemplary embodiment, in at least one sub-pixel, the second region of the first active layer can be connected to the fourth plate 14.

[0365] In an exemplary embodiment, in at least one sub-pixel, the fourth plate 14 and the first active layer 21 can be an integrated structure connected to each other.

[0366] (24) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a second insulating thin film and a second conductive thin film, patterning the second conductive thin film by a patterning process, forming a second insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 19A and 19B, FIG. 19B being a schematic view of the second conductive layer in FIG. 19A.

[0367] In the exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate can at least include the gate electrode line 31, the second gate electrode 32 and the fourth connection electrode 44, the structure of the gate electrode line 31 and the fourth connection electrode 44 and their connection relationship are basically the same as those of the embodiment shown in FIG. 5. Different from the embodiment shown in FIG. 5 is that, since the fourth plate is disposed in the semiconductor layer, the fourth plate and the first active layer are an integrated structure connected with each other, thus the second conductive layer of the present embodiment does not dispose the fourth plate and the third connection electrode.

[0368] In the exemplary embodiment, the shape of the second gate electrode 32 can be an "L" shape extending along the second direction Y, the orthographic projection of the first end of the second gate electrode 32 on the base at least partially overlaps the orthographic projection of the fourth plate 14 on the base, the orthographic projection of the second end of the second gate electrode 32 on the base at least partially overlaps the orthographic projection of the second plate 12 on the base, the orthographic projection of the region between the first end and the second end of the second gate electrode 32 on the base at least partially overlaps the orthographic projection of the second active layer 22 on the base, and the second gate electrode 32 serves as the gate electrode of the second transistor T2.

[0369] In the exemplary embodiment, the second conductive layer of each repeating unit in the display substrate can further include two first scan connection lines 33, two second scan connection lines 34, one ring connection line 35 and one scan transfer line 36, the above structure and its connection relationship are basically the same as those of the embodiment shown in FIG. 5, in the first sub-pixel P1 and the second sub-pixel P2, the two gate electrode lines 31, the first scan connection line 33 and the second scan connection line 34 form the first ring structure 30A, in the third sub-pixel P3 and the fourth sub-pixel P4, the two gate electrode lines 31, the first scan connection line 33 and the second scan connection line 34 form the second ring structure 30B.

[0370] In the exemplary embodiment, each repeating unit in the display substrate can further include a first protruding structure 37 and a second protruding structure 38, the above structure and its connection relationship are basically the same as those of the embodiment shown in FIG. 5.

[0371] (25) Forming a third insulating layer pattern. In the exemplary embodiment, forming the third insulating layer pattern can include: on the base on which the aforementioned pattern is formed, depositing a third insulating thin film, patterning the third insulating thin film by a patterning process, forming the third insulating layer pattern covering the second conductive layer, and the third insulating layer is provided with a plurality of vias, as shown in FIG. 20.

[0372] In the example embodiment, the plurality of vias of each sub-pixel in the display substrate at least includes: a first via V1, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a thirteenth via V13. Among them, the structures and connection relationships of the first via V1, the third via V3 to the ninth via V9 are basically the same as those of the embodiment shown in FIG. 5, that is, the embodiment does not provide the second via V2, but provides the thirteenth via V13.

[0373] In the example embodiment, the orthographic projection of the thirteenth via V13 on the substrate at least partially overlaps the orthographic projection of the first end of the second gate electrode 32 and the fourth plate 14 on the substrate on the substrate. The third insulating layer and the second insulating layer in the thirteenth via V13 are etched away, and the surface of the second gate electrode 32 and the fourth plate 14 is exposed. The thirteenth via V13 is a switching via, which is composed of two half-holes, one of which exposes the surface of the second gate electrode 32, and the other of which exposes the surface of the fourth plate 14. In the example embodiment, the thirteenth via V13 is configured to allow the tenth connection electrode formed subsequently to pass through the via and be connected to the fourth plate 14 and the second gate electrode 32.

[0374] In the example embodiment, the at least one repeating unit can further include a tenth via V10 provided in the first sub-pixel P1, an eleventh via V11 provided in the second sub-pixel P2, and a twelfth via V12 provided in the third sub-pixel P3. The structures and connection relationships of the above vias are basically the same as those of the embodiment shown in FIG. 5.

[0375] (26) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer pattern can include: depositing a third conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the third conductive thin film by a patterning process, and forming the third conductive layer pattern on the third insulating layer, as shown in FIGS. 21A and 21B, FIG. 21B is a schematic view of the third conductive layer in FIG. 21A.

[0376] In the example embodiment, the third conductive layer of each sub-pixel in the display substrate can at least include a fifth plate 15 for storing a capacitance, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a ninth connection electrode 49, a tenth connection electrode 50, a second power supply line 72, a compensation signal line 73, and a plate connection electrode 81. Among them, the structure of the tenth connection electrode 50 and its connection relationship are basically the same as those of the embodiment shown in FIG. 5. Different from the embodiment shown in FIG. 5 is that, since the fourth plate is provided in the semiconductor layer, the fourth plate and the first active layer are an integrated structure connected to each other, so that the third conductive layer of the embodiment does not provide the fifth connection electrode, but provides the tenth connection electrode 50.

[0377] In the example embodiment, the tenth connection electrode 50 can be in a block shape (e.g., a rectangular shape), and the tenth connection electrode 50 is connected to the fourth plate 14 and the second gate electrode 32 through the thirteenth via hole V13. Since the second gate electrode 32 is connected to the second plate 12, the fourth plate 14 and the first active layer are an integrated structure connected to each other, thereby realizing the connection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, the second plate 12, and the fourth plate 14 in each sub-pixel, and forming the first node N1 of the pixel driving circuit.

[0378] In the example embodiment, the third conductive layer of each repeating unit in the display substrate can further include an eleventh connection electrode 51, a twelfth connection electrode 52, a thirteenth connection electrode 53, a fourteenth connection electrode 54, a fifteenth connection electrode 55, a sixteenth connection electrode 56, and an auxiliary connection electrode 82, and the above structure and the connection relationship thereof are substantially the same as those of the embodiment shown in FIG. 5.

[0379] In the example embodiment, since the first plate 11 is overlapped with the third plate 13, the first plate 11 has the potential of the second node N2. Since the second plate 12 and the fourth plate 14 are connected through the eighth connection electrode 48 and the tenth connection electrode 50, the second plate 12 has the potential of the first node N1. In this way, the first plate 11 having the potential of the second node N2 and the second plate 12 having the potential of the first node N1 constitute the first capacitor.

[0380] In the example embodiment, since the third plate 13 as a lower plate has the potential of the second node N2 and the fourth plate 14 as an intermediate plate has the potential of the first node N1, the third plate 13 having the potential of the second node N2 and the fourth plate 14 having the potential of the first node N1 constitute a first sub-capacitor of the second capacitor. Since the fourth plate 14 as an intermediate plate has the potential of the first node N1 and the fifth plate 15 as an upper plate has the potential of the second node N2, the fourth plate 14 having the potential of the first node N1 and the fifth plate 15 having the potential of the second node N2 constitute a second sub-capacitor of the second capacitor.

[0381] In the example embodiment, the first sub-capacitor and the second sub-capacitor are in a parallel structure, and the first capacitor and the second capacitor are in a parallel structure.

[0382] In the example embodiment, the second capacitor in the embodiment shown in FIG. 5 is formed by the structure of the first conductive layer, the second conductive layer and the third conductive layer stacked together, compared with the structure of the first conductive layer and the second conductive layer of the first sub-capacitor being separated by the first insulating layer and then the second insulating layer. The second capacitor in the embodiment is formed by the structure of the first conductive layer, the semiconductor layer and the third conductive layer stacked together, and the first conductive layer and the semiconductor layer of the first sub-capacitor are separated only by the first insulating layer. Therefore, on the one hand, the structure of the embodiment can effectively increase the capacity of the first sub-capacitor, can effectively increase the capacity of the second capacitor, and then increase the capacity of the storage capacitor, and on the other hand, can reduce the area of the plate under the condition of ensuring the capacitance value of the storage capacitor, effectively reduce the area occupied by the pixel driving circuit, and is conducive to realizing high-resolution display.

[0383] In the example embodiment, the subsequent preparation process can include forming a fourth insulating layer and a first planar layer pattern, forming a second transparent conductive layer, forming a pixel definition layer, forming an organic light-emitting layer, forming a cathode, and forming an encapsulation structure layer, etc. The forming process is basically the same as that of the embodiment shown in FIG. 5, and will not be described here.

[0384] So far, the preparation of the display substrate of the embodiment is completed. In the example embodiment, the structure of the display substrate of the embodiment is basically the same as that of the embodiment shown in FIG. 5. The difference is that the fourth plate of the embodiment is arranged in the semiconductor layer.

[0385] The example embodiment of the present disclosure provides a top-emitting display substrate, which not only has the technical effects of the embodiment shown in FIG. 5, but also can effectively increase the capacity of the storage capacitor by forming the second capacitor in a sandwich structure of the first conductive layer, the semiconductor layer and the third conductive layer.

[0386] The structure shown in the foregoing of the present disclosure and the preparation process thereof are only an example of illustration, and in the example embodiment, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs, which is not limited in the present disclosure.

[0387] In the example embodiment, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0388] The present disclosure also provides a preparation method of a display substrate for preparing the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a plurality of repeating units arranged regularly, at least one repeating unit including a display area configured to display an image and a light-transmitting area disposed on a side of the display area in a first direction or a side of the display area in a reverse direction of the first direction, the display area including a plurality of sub-pixels disposed in sequence along a second direction, the first direction and the second direction being intersected; and the preparation method can include:

[0389] forming a pixel driving circuit and a light emitting device connected with the pixel driving circuit in at least one sub-pixel, the pixel driving circuit being connected with a first power line, a data signal line and a compensation signal line respectively, the light emitting device being connected with a second power line; the display area including a first area and a second area disposed on a side of the first area away from the light-transmitting area, the pixel driving circuit of the plurality of sub-pixels being disposed in the first area, the first power line, the second power line, the data signal line and the compensation signal line being disposed in the second area.

[0390] The present disclosure also provides a display device including the display substrate described above. The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited thereto.

[0391] Although the embodiments of the present disclosure are disclosed as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions and omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units arranged regularly, at least one of the repeating units comprising a display area configured to display an image and a light-transmitting area disposed on one side of the display area in a first direction or on a side opposite to the display area in the first direction, the display area comprising a plurality of sub-pixels disposed in sequence along a second direction, the first direction and the second direction being perpendicular to each other; at least one of the sub-pixels comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit being connected to a first power line, a data signal line and a compensation signal line respectively, and the light-emitting device being connected to a second power line; the display area comprising a first area and a second area disposed on a side of the first area away from the light-transmitting area, the pixel driving circuits of the plurality of sub-pixels being disposed in the first area, and the first power line, the second power line, the data signal line and the compensation signal line being disposed in the second area. 2.The display substrate of claim 1, wherein, In the first direction, the compensation signal line is disposed between the data signal line and the first power line, and the first power line is disposed between the compensation signal line and the second power line. 3.The display substrate of claim 2, wherein, In a direction perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers disposed on a substrate, the first power line and the data signal line being disposed in the same conductive layer, the compensation signal line and the second power line being disposed in the same conductive layer, and the first power line and the second power line being disposed in different conductive layers. 4.The display substrate of claim 2, wherein, The data signal line comprises a first data signal line, a second data signal line, a third data signal line and a fourth data signal line disposed in sequence along the first direction; a first spacing is provided between adjacent data signal lines, a second spacing is provided between the fourth data signal line and the compensation signal line, a third spacing is provided between the first power line and the compensation signal line, and a fourth spacing is provided between the first power line and the second power line, the second spacing being smaller than the first spacing, the third spacing being smaller than the first spacing, and the fourth spacing being smaller than the first spacing. 5.The display substrate of claim 1, wherein, The pixel driving circuit comprises at least a first transistor, a second transistor, a third transistor and a storage capacitor, a first electrode of the first transistor being connected to the data signal line, a second electrode of the first transistor being connected to a gate electrode of the second transistor and a first terminal of the storage capacitor respectively, a first electrode of the second transistor being connected to the first power line, a second electrode of the second transistor being connected to a second electrode of the third transistor and a second terminal of the storage capacitor respectively, and a first electrode of the third transistor being connected to the compensation signal line; in the plurality of sub-pixels of at least one of the repeating units, gate electrodes of a plurality of first transistors and gate electrodes of a plurality of third transistors are connected to the same scan signal line. 6.The display substrate of claim 5, wherein, In at least one of the repeating units, the scan signal line comprises a scan transmission line disposed in the light-transmissive region and a first ring structure and a second ring structure disposed in the display region, a first end of the scan transmission line is connected to the second ring structure in the current repeating unit, and a second end of the scan transmission line is connected to the second ring structure in the repeating unit adjacent to the first direction. 7.The display substrate of claim 6, wherein, In at least one of the repeating units and the repeating unit adjacent to the first direction, the scan transmission lines in the two repeating units are not on the same straight line extending along the first direction. 8.The display substrate of claim 6, wherein, The display region comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel disposed in sequence along the second direction, the first ring structure is disposed in the first sub-pixel and the second sub-pixel, the second ring structure is in the third sub-pixel and the fourth sub-pixel, and the first ring structure and the second ring structure are connected to each other by a ring connection line. 9.The display substrate of claim 8, wherein, In at least one of the repeating units, the first ring structure, the second ring structure and the ring connection line are an integrated structure connected to each other. 10.The display substrate of claim 8, wherein, The first ring structure or the second ring structure comprises at least two gate electrode lines, a first scan connection line and a second scan connection line, the gate electrode lines are in the shape of a straight line or a broken line extending along the first direction, the two gate electrode lines are disposed in two sub-pixels respectively, the first scan connection line and the second scan connection line are in the shape of a straight line or a broken line extending along the second direction, the first scan connection line is connected to the end part of the two gate electrode lines in the opposite direction of the first direction respectively, and the second scan connection line is connected to the end part of the two gate electrode lines in the first direction respectively, thereby forming the first ring structure or the second ring structure. 11.The display substrate of claim 10, wherein, In at least one of the repeating units, the two gate electrode lines, the first scan connection line and the second scan connection line in the first ring structure or the second ring structure are an integrated structure connected to each other. 12.The display substrate of claim 10, wherein, Orthographic projections of the first ring structure and the second ring structure on the display substrate plane at least partially overlap with orthographic projections of the first power supply line, the second power supply line, the data signal line and the compensation signal line on the display substrate plane. 13.The display substrate of claim 10, wherein, A first protruding structure is disposed on the first ring structure, the first protruding structure protrudes towards the light-transmissive region, and an orthographic projection of the first protruding structure on the display substrate plane at least partially overlaps with an orthographic projection of the light-transmissive region on the display substrate plane. And / or, a second protruding structure is disposed on the second ring structure, the second protruding structure protrudes towards the light-transmissive region, and an orthographic projection of the second protruding structure on the display substrate plane at least partially overlaps with an orthographic projection of the light-transmissive region on the display substrate plane. 14.The display substrate of claim 13, wherein, In at least one of the repeating units, the protruding lengths of the first protruding structure and the second protruding structure are different, and the protruding length is the dimension of the first direction. 15.The display substrate of claim 13, wherein, In at least one repeating unit, a first protruding width and a second protruding width in the first protruding structure are different, the first protruding width being a dimension of the first protruding structure on a side of the gate electrode line away from the ring connection line, and the second protruding width being a dimension of the first protruding structure on a side of the gate electrode line close to the ring connection line; and / or, a third protruding width and a fourth protruding width in the second protruding structure are different, the third protruding width being a dimension of the second protruding structure on a side of the gate electrode line close to the ring connection line, and the fourth protruding width being a dimension of the second protruding structure on a side of the gate electrode line away from the ring connection line. 16.The display substrate of claim 15, wherein, In at least one repeating unit, a third protruding structure is further included, the third protruding structure being disposed on a side of the pixel driving circuit away from the first protruding structure or the second protruding structure, the third protruding structure protruding towards the light-transmitting area, a normal projection of the third protruding structure on a display substrate plane at least partially overlapping a normal projection of the light-transmitting area on the display substrate plane; the plate connection electrode includes a plate connection strip and a plate connection block, a first end of the plate connection strip being connected to a fifth plate of the storage capacitor, a second end of the plate connection strip being connected to the plate connection block after extending to the light-transmitting area; the anode connection electrode includes a first sub-connection electrode, a second sub-connection electrode and a third sub-connection electrode, a first end of the first sub-connection electrode being connected to a first sub-anode of the light-emitting device, a first end of the second sub-connection electrode being connected to a second sub-anode of the light-emitting device, second ends of the first sub-connection electrode and the second sub-connection electrode being respectively connected to first and second ends of the third sub-connection electrode after extending to the light-transmitting area, the third sub-connection electrode being connected to the plate connection block through a via hole; a fifth protruding width is provided between the first sub-connection electrode and the plate connection strip or between the second sub-connection electrode and the plate connection strip, the first protruding width being greater than the fifth protruding width, the second protruding width being greater than the fifth protruding width, the third protruding width being greater than the fifth protruding width, and the fourth protruding width being greater than the fifth protruding width.

17. The display substrate according to any one of claims 1 to 16, wherein, The storage capacitor includes a first capacitor and a second capacitor connected in parallel, the first capacitor including a first plate and a second plate stacked, a normal projection of the first plate on a display substrate plane and a normal projection of the second plate on the display substrate plane having an overlapping area, the second capacitor including a third plate, a fourth plate and a fifth plate stacked, a normal projection of the third plate on the display substrate plane, a normal projection of the fourth plate on the display substrate plane and a normal projection of the fifth plate on the display substrate plane having an overlapping area; the first plate and the third plate are connected, the third plate and the fifth plate are connected, and the second plate and the fourth plate are connected. 18.The display substrate of claim 17, wherein, The display substrate comprises, in a direction perpendicular to the display substrate, a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, and a semiconductor layer disposed on a side of the first conductive layer away from the substrate; the first electrode plate is disposed in the first transparent conductive layer, and the second electrode plate is disposed in the semiconductor layer, forming a transparent first capacitor.

19. The display substrate of claim 18, wherein, The first electrode plate and the second electrode plate are at least partially overlapped with the orthographic projection of the light-transmitting region on the substrate.

20. The display substrate of claim 18, wherein, The display substrate further comprises a second conductive layer disposed on a side of the semiconductor layer away from the substrate, and a third conductive layer disposed on a side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the second conductive layer, and the fifth electrode plate is disposed in the third conductive layer. 21.The display substrate of claim 18, wherein, The display substrate further comprises a second conductive layer disposed on a side of the semiconductor layer away from the substrate, and a third conductive layer disposed on a side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the semiconductor layer, and the fifth electrode plate is disposed in the third conductive layer.

22. A display device comprising: The display substrate comprises a plurality of repeating units arranged in a regular pattern, at least one of the repeating units comprising a display region and a light-transmitting region disposed on a side of the display region in a first direction or on a side of the display region in a direction opposite to the first direction, the display region being configured to display an image, and the light-transmitting region being configured to transmit light, the display region comprising a plurality of sub-pixels arranged in a second direction, the first direction and the second direction being perpendicular to each other. The display substrate comprises a plurality of repeating units arranged in a regular pattern, at least one of the repeating units comprising a display region and a light-transmitting region disposed on a side of the display region in a first direction or on a side of the display region in a direction opposite to the first direction, the display region being configured to display an image, and the light-transmitting region being configured to transmit light, the display region comprising a plurality of sub-pixels arranged in a second direction, the first direction and the second direction being perpendicular to each other. The display substrate comprises a plurality of repeating units arranged in a regular pattern, at least one of the repeating units comprising a display region and a light-transmitting region disposed on a side of the display region in a first direction or on a side of the display region in a direction opposite to the first direction, the display region being configured to display an image, and the light-transmitting region being configured to transmit light, the display region comprising a plurality of sub-pixels arranged in a second direction, the first direction and the second direction being perpendicular to each other. The display substrate comprises a plurality of repeating units arranged in a regular pattern, at least one of the repeating units comprising a display region and a light-transmitting region disposed on a side of the display region in a first direction or on a side of the display region in a direction opposite to the first direction, the display region being configured to display an image, and the light-transmitting region being configured to transmit light, the display region comprising a plurality of sub-pixels arranged in a second direction, the first direction and the second direction being perpendicular to each other.

Images