Display device and electronic device

Abstract

A display device according to the present invention includes a display panel and an input sensing layer disposed on the display panel. The input sensing layer includes a plurality of sensing electrodes and a plurality of dummy electrodes respectively overlapping the plurality of sensing electrodes. The plurality of sensing electrodes include a first sensing electrode and a second sensing electrode electrically separated from the first sensing electrode and having a smaller area than the first sensing electrode. The plurality of dummy electrodes include a first dummy electrode overlapping the first sensing electrode and a second dummy electrode overlapping the second sensing electrode. The first and second dummy electrodes are connected to each other in a boundary area between the first and second sensing electrodes.

Description

Display devices and electronic devices

[0001] The present invention relates to a display device and an electronic device, and more particularly, to a display device having uniform sensing performance and an electronic device including the same.

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles are equipped with display devices to display images. Display devices are also provided inside automobiles.

[0003] The display device may be equipped with an input sensing layer that can provide a touch-based input method that allows a user to intuitively and conveniently input information or commands in addition to conventional input methods such as buttons, keyboards, and mice.

[0004] The present invention aims to provide a display device capable of having uniform sensing performance over the entire area and an electronic device including the same.

[0005] A display device according to one aspect of the present invention includes a display panel and an input sensing layer disposed on the display panel. The input sensing layer includes a plurality of sensing electrodes, and a plurality of dummy electrodes disposed on a different layer from the plurality of sensing electrodes and overlapping each of the plurality of sensing electrodes.

[0006] The plurality of sensing electrodes include a first sensing electrode, and a second sensing electrode adjacent to the first sensing electrode, electrically separated from the first sensing electrode, and having a smaller area than the first sensing electrode. The plurality of dummy electrodes include a first dummy electrode overlapping the first sensing electrode, and a second dummy electrode overlapping the second sensing electrode.

[0007] The first and second dummy electrodes are connected to each other at a boundary region between the first and second sensing electrodes.

[0008] A display device according to one aspect of the present invention includes a display panel, and an input sensing layer disposed on the display panel and including a plurality of sensing electrodes.

[0009] The plurality of sensing electrodes include a first sensing electrode, a second sensing electrode adjacent to the first sensing electrode, electrically separated from the first sensing electrode, and having a smaller area than the first sensing electrode, and a third sensing electrode adjacent to the first sensing electrode, electrically separated from the first and second sensing electrodes, and having the same area as the first sensing electrode.

[0010] In the boundary region between the first and third sensing electrodes, the first and third sensing electrodes are spaced apart by a first interval, and in the boundary region between the first and second sensing electrodes, the first and second sensing electrodes are spaced apart by a second interval that is smaller than the first interval.

[0011] As described above, the second sensing electrodes positioned adjacent to the hole area and the corner portion may be formed with a smaller area than the first sensing electrode due to spatial constraints. In this case, a connecting portion connecting the dummy electrodes to each other may be formed in the boundary area between the first and second sensing electrodes, or the gap between the first and second sensing electrodes may be reduced in the boundary area. Accordingly, the problem of deterioration of sensing performance in the hole area and the corner portion that may occur due to a reduction in the area of ​​the second sensing electrode can be prevented, and as a result, the display device can have uniform sensing performance in the entire area.

[0012] FIG. 1a is a drawing showing the interior of a vehicle in which a display device according to an embodiment of the present invention is arranged.

[0013] Figure 1b is a perspective view of the display device illustrated in Figure 1a.

[0014] FIG. 2A is a cross-sectional view of a display device according to one embodiment of the present invention.

[0015] Figure 2b is a cross-sectional view of a display device according to one embodiment of the present invention.

[0016] Fig. 3a is an enlarged cross-sectional view of a portion of the display device illustrated in Fig. 2a.

[0017] Fig. 3b is an enlarged cross-sectional view of a portion of the display device illustrated in Fig. 2b.

[0018] Figure 4 is an exploded perspective view of a display device according to one embodiment of the present invention.

[0019] Figure 5 is a plan view of the display panel illustrated in Figure 4.

[0020] Fig. 6 is a plan view of the input sensing layer illustrated in Fig. 4.

[0021] Fig. 7 is a drawing showing the connection of the sensing electrodes and trace lines arranged in the A1 area illustrated in Fig. 6.

[0022] FIG. 8a is a drawing showing sensing electrodes arranged in some areas shown in FIG. 6.

[0023] Figure 8b is a waveform diagram showing voltages applied to the sensing electrodes illustrated in Figure 8a.

[0024] Fig. 8c is a circuit diagram showing a sensing capacitor in the charging section shown in Fig. 8b.

[0025] Figure 8d is a circuit diagram showing a sensing capacitor in the discharge section illustrated in Figure 8b.

[0026] Figure 9 is a plan view showing the A2 area illustrated in Figure 6.

[0027] Figure 10a is an enlarged view showing the B1 area of ​​Figure 9.

[0028] Figure 10b is an enlarged view showing the B2 area of ​​Figure 9.

[0029] Figure 11a is an enlarged view showing area B11 of Figure 10a.

[0030] Figure 11b is a cross-sectional view taken along line I-I' of Figure 11a.

[0031] Figure 12a is an enlarged view showing area B21 of Figure 10b.

[0032] Fig. 12b is a cross-sectional view taken along line II-II' of Fig. 12a.

[0033] Figure 13 is a plan view showing the A3 area illustrated in Figure 6.

[0034] Figure 14a is an enlarged view showing the C1 area of ​​Figure 13.

[0035] Figure 14b is an enlarged view of the C1 region according to another embodiment of the present invention.

[0036] Figure 15a is an enlarged view showing the C11 area of ​​Figure 14a.

[0037] Figure 15b is a cross-sectional view taken along line III-III' of Figure 15a.

[0038] Figure 16a is an enlarged view showing the C12 area of ​​Figure 14b.

[0039] Fig. 16b is a cross-sectional view taken along line IV-IV' of Fig. 16a.

[0040] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0041] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0042] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0043] Additionally, terms such as "below," "below," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0044] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0046] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0047] FIG. 1A is a drawing illustrating the interior of a vehicle in which a display device according to an embodiment of the present invention is arranged. FIG. 1B is a perspective view of the display device illustrated in FIG. 1A.

[0048] Referring to Fig. 1a, a display device (DD) may be placed inside a vehicle (AM). The display device (DD) may be placed inside the vehicle (AM) to provide various information to the driver (DV) (or user). The display device (DD) may provide images such as weather, speed, maps, or movies to the driver (DV). The display device (DD) may be a touch-based display device that can operate according to touch input from the driver (DV).

[0049] Referring to FIGS. 1A and 1B , the display device (DD) may have a plane defined by a first direction (DR1) and a second direction (DR2) that intersect each other. The display device (DD) may have long sides extending in the first direction (DR1) and short sides extending in the second direction (DR2). The corners of the display device (DD) connecting the long sides and the short sides may have a curved shape.

[0050] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In addition, in this specification, the meaning of when viewed on a plane is defined as a state viewed from the third direction (DR3).

[0051] The front surface of the display device (DD) can be defined as a display surface (DS) and can have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated in the display device (DD) can be provided to a user through the display surface (DS).

[0052] A display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may display an image, and the non-display area (NDA) may not display an image. The non-display area (NDA) may define a border of the display device (DD) that surrounds the display area (DA) and is printed in a predetermined color.

[0053] By way of example, a vehicle display device (DD) is illustrated, but embodiments of the present invention are not limited thereto. For example, a display device (DD) according to an embodiment of the present invention may be used in electronic devices such as smartphones, digital cameras, laptop computers, monitors, and smart televisions that provide images to users.

[0054] Fig. 2a is a cross-sectional view of a display device according to one embodiment of the present invention, and Fig. 2b is a cross-sectional view of a display device according to one embodiment of the present invention. Fig. 3a is an enlarged cross-sectional view of a portion of the display device illustrated in Fig. 2a, and Fig. 3b is an enlarged cross-sectional view of a portion of the display device illustrated in Fig. 2b.

[0055] Referring to FIG. 2A, the display device (DD) may include a display panel (DP) and an input sensing layer (ISP). The input sensing layer (ISP) may be referred to as an input sensing panel.

[0056] A display panel (DP) may include a first base layer (BS1), a display circuit layer (DP_CL), a display element layer (DP_ED), a second base layer (BS2), and a bonding member (SLM). An input sensing layer (ISP) may be disposed on the second base layer (BS2).

[0057] Each of the first base layer (BS1) and the second base layer (BS2) may be a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a laminated structure including a plurality of insulating layers.

[0058] The display circuit layer (DP_CL) may be disposed on the first base layer (BS1). The display circuit layer (DP_CL) may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the display circuit layer (DP_CL) may constitute signal lines or a control circuit of a pixel.

[0059] The display element layer (DP_ED) may be disposed on the display circuit layer (DP_CL). The display element layer (DP_ED) may include light-emitting elements. For example, the display element layer (DP_ED) may include an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0060] The second base layer (BS2) may be disposed on the display element layer (DP_ED). A predetermined space may be defined between the second base layer (BS2) and the display element layer (DP_ED). The space may be filled with air or an inert gas. In addition, in one embodiment of the present invention, the space may be filled with a filling layer (FL, see FIG. 3a) such as a silicone-based polymer, an epoxy-based resin, or an acrylic resin.

[0061] A bonding member (SLM) may be disposed between the first base layer (BS1) and the second base layer (BS2). The bonding member (SLM) may bond the first base layer (BS1) and the second base layer (BS2). The bonding member (SLM) may include an organic material such as a photocurable resin or a photoplastic resin, or an inorganic material such as a frit seal, and is not limited to any one embodiment.

[0062] The input sensing layer (ISP) may include a plurality of insulating layers and a plurality of conductive layers. The plurality of conductive layers may comprise sensing electrodes that sense external inputs, sensing wires electrically connected to the sensing electrodes, and sensing pads electrically connected to the sensing wires.

[0063] Referring to FIG. 2b, the display device (DD_1) may include a display panel (DP_1) and an input sensing layer (ISP_1).

[0064] The display panel (DP_1) may include a base layer (BS), a display circuit layer (DP_CL), a display element layer (DP_ED), and an encapsulation layer (TFE). The base layer (BS) may be of a flexible type. The input sensing layer (ISP_1) may be disposed on the encapsulation layer (TFE). According to an embodiment of the present invention, the display panel (DP_1) and the input sensing layer (ISP_1) may be formed through a continuous process. That is, the input sensing layer (ISP_1) may be formed directly on the encapsulation layer (TFE).

[0065] Referring to FIGS. 2A and 3A, at least one inorganic layer may be formed on an upper surface of a first base layer (BS1) in a display panel (DP). The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, silicon nitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In the present embodiment, the display panel (DP) is illustrated as including a buffer layer (BFL).

[0066] The buffer layer (BFL) can improve the bonding strength between the first base layer (BS1) and the semiconductor pattern. The buffer layer (BFL) can include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer can be alternately stacked.

[0067] The semiconductor pattern may be disposed on a buffer layer (BFL). The semiconductor pattern may include polysilicon. However, the semiconductor pattern is not limited thereto, and may also include amorphous silicon, low-temperature crystalline silicon, or an oxide semiconductor.

[0068] FIG. 3A only illustrates a portion of a semiconductor pattern, and additional semiconductor patterns may be arranged in other areas. The semiconductor patterns may be arranged in a specific order across the pixels. The semiconductor patterns may have different electrical properties depending on doping. The semiconductor pattern may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region or may be doped at a lower concentration than the first region.

[0069] The conductivity of the first region is greater than that of the second region, and can substantially function as an electrode or signal line. The second region may substantially correspond to a channel region of the transistor. In other words, a portion of the semiconductor pattern may be a channel region of the transistor, another portion may be a source or drain of the transistor, and still another portion may be a connecting electrode or a connecting signal line.

[0070] Each pixel may have an equivalent circuit including a plurality of transistors, at least one capacitor, and a light-emitting element, and the equivalent circuit of the pixel may be modified in various forms. FIG. 3A illustrates an example of one transistor (100PC) and a light-emitting element (100PE) included in a pixel.

[0071] The transistor (100PC) may include a source (S1), a channel portion (CH1), a drain (D1), and a gate (G1). The source (S1), the channel portion (CH1), and the drain (D1) may be formed from a semiconductor pattern. The source (S1) and the drain (D1) may extend in opposite directions from the channel portion (CH1) in a cross-section. Fig. 3a illustrates a portion of a connection signal line (SCL) formed from a semiconductor pattern. Although not separately illustrated, the connection signal line (SCL) may be electrically connected to the drain (D1) of the transistor (100PC) in a plane.

[0072] The first insulating layer (10) may be disposed on a buffer layer (BFL). The first insulating layer (10) may overlap a plurality of pixels in common and cover a semiconductor pattern. The first insulating layer (10) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer (10) may be a single-layer silicon oxide layer. Not only the first insulating layer (10), but also the insulating layers of the display circuit layer (DP_CL) described below may be inorganic layers and / or organic layers, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-described materials, but is not limited thereto.

[0073] The gate (G1) is positioned on the first insulating layer (10). The gate (G1) may be a part of a metal pattern. The gate (G1) overlaps the channel portion (CH1). In the process of doping the semiconductor pattern, the gate (G1) may function as a mask.

[0074] The second insulating layer (20) is disposed on the first insulating layer (10) and can cover the gate (G1). The second insulating layer (20) can overlap pixels in common. The second insulating layer (20) can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The second insulating layer (20) can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the present embodiment, the second insulating layer (20) can have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0075] The third insulating layer (30) may be disposed on the second insulating layer (20). The third insulating layer (30) may have a single-layer or multi-layer structure. For example, the third insulating layer (30) may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0076] The first connection electrode (CNE1) may be placed on the third insulating layer (30). The first connection electrode (CNE1) may be connected to the connection signal line (SCL) through a contact hole (CNT-1) penetrating the first, second, and third insulating layers (10, 20, 30).

[0077] The fourth insulating layer (40) may be disposed on the third insulating layer (30). The fourth insulating layer (40) may be a single-layer silicon oxide layer. The fifth insulating layer (50) may be disposed on the fourth insulating layer (40). The fifth insulating layer (50) may be an organic layer.

[0078] The second connection electrode (CNE2) may be placed on the fifth insulating layer (50). The second connection electrode (CNE2) may be connected to the first connection electrode (CNE1) through a contact hole (CNT-2) penetrating the fourth insulating layer (40) and the fifth insulating layer (50).

[0079] The sixth insulating layer (60) is placed on the fifth insulating layer (50) and can cover the second connection electrode (CNE2). The sixth insulating layer (60) may be an organic layer.

[0080] The display element layer (DP_ED) may be disposed on the display circuit layer (DP_CL). The display element layer (DP_ED) may include a light-emitting element (100PE) and a pixel definition layer (70). For example, the display element layer (DP_ED) may include an organic light-emitting material, an inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED. Hereinafter, the light-emitting element (100PE) is described as an example of an organic light-emitting element, but is not particularly limited thereto.

[0081] The light-emitting element (100PE) may include a first electrode (AE), a light-emitting layer (EL), and a second electrode (CE). The first electrode (AE) may be disposed on a sixth insulating layer (60). The first electrode (AE) may be connected to a second connection electrode (CNE2) through a contact hole (CNT-3) penetrating the sixth insulating layer (60).

[0082] The pixel defining film (70) is disposed on the sixth insulating layer (60) and can cover a portion of the first electrode (AE). An opening (70-OP) is defined in the pixel defining film (70). The opening (70-OP) of the pixel defining film (70) exposes at least a portion of the first electrode (AE).

[0083] The display area (DA, see FIG. 1b) may include a light-emitting area (PXA) and a non-light-emitting area (NPXA) adjacent to the light-emitting area (PXA). The non-light-emitting area (NPXA) may surround the light-emitting area (PXA). In the present embodiment, the light-emitting area (PXA) is defined to correspond to a portion of the first electrode (AE) exposed by the opening (70-OP).

[0084] The light-emitting layer (EL) may be disposed on the first electrode (AE). The light-emitting layer (EL) may be disposed in an area corresponding to the opening (70-OP). That is, the light-emitting layer (EL) may be formed separately for each pixel. When the light-emitting layer (EL) is formed separately for each pixel, each of the light-emitting layers (EL) may emit light of at least one color among blue, red, and green. However, the present invention is not limited thereto, and the light-emitting layer (EL) may be connected to the pixels and provided in common. In this case, the light-emitting layer (EL) may provide blue light or white light.

[0085] The second electrode (CE) may be disposed on the light-emitting layer (EL). The second electrode (CE) may have an integral shape and may be disposed commonly across a plurality of pixels.

[0086] Although not shown, a hole control layer may be disposed between the first electrode (AE) and the light-emitting layer (EL). The hole control layer may be commonly disposed in the light-emitting area (PXA) and the non-light-emitting area (NPXA). The hole control layer includes a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light-emitting layer (EL) and the second electrode (CE). The electron control layer includes an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer may be commonly formed in a plurality of pixels using an open mask.

[0087] The second base layer (BS2) may be disposed on the display element layer (DP-ED). As an example of the present invention, the first and second base layers (BS1, BS2) may be of a rigid type.

[0088] A filling layer (FL) may be placed between the first and second base layers (BS1, BS2). The filling layer (FL) may be placed in a space sealed by a bonding member (SLM, see FIG. 2a) between the first and second base layers (BS1, BS2). The filling layer (FL) may include a thermosetting material.

[0089] The input sensing layer (ISP) can be positioned directly on the display panel (DP). For example, the input sensing layer (ISP) can be positioned directly on the second base layer (BS2).

[0090] Referring to FIGS. 2B and 3B, the encapsulation layer (TFE) may be disposed on the display element layer (DP_ED). The encapsulation layer (TFE) may include sequentially stacked inorganic layers, organic layers, and inorganic layers, but the layers constituting the encapsulation layer (TFE) are not limited thereto.

[0091] The inorganic layers can protect the display element layer (DP_ED) from moisture and oxygen, and the organic layers can protect the display element layer (DP_ED) from foreign substances such as dust particles. The inorganic layers can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer can include, but is not limited to, an acrylic organic layer.

[0092] The input sensing layer (ISP_1) may be formed on the display panel (DP_1) through a continuous process. In this case, the input sensing layer (ISP_1) may be expressed as being directly disposed on the display panel (DP_1) (e.g., the encapsulation layer (TFE)). The term “directly disposed” may mean that no third component is disposed between the input sensing layer (ISP_1) and the display panel (DP_1). In other words, a separate adhesive member or a bonding member may not be disposed between the input sensing layer (ISP_1) and the display panel (DP_1). Alternatively, the input sensing layer (ISP_1) may be bonded to the display panel (DP_1) through an adhesive member or a bonding member. The adhesive member may include a typical adhesive or adhesive.

[0093] Referring to FIGS. 3A and 3B, the input sensing layer (ISP, ISP_1) may include a base insulating layer (201), a first conductive layer (202), a middle insulating layer (203), a second conductive layer (204), and a cover insulating layer (205).

[0094] The base insulating layer (201) may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the base insulating layer (201) may be an organic layer including an epoxy resin, an acrylic resin, or an imide-based resin. The base insulating layer (201) may have a single-layer structure or a multi-layer structure laminated along the third direction (DR3).

[0095] Each of the first conductive layer (202) and the second conductive layer (204) may have a single-layer structure or a multi-layer structure laminated along the third direction (DR3).

[0096] The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, etc.

[0097] The multilayer conductive layer may include metal layers. The metal layers may have a three-layer structure of, for example, titanium / aluminum / titanium. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0098] At least one of the intermediate insulating layer (203) and the cover insulating layer (205) may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0099] At least one of the intermediate insulating layer (203) and the cover insulating layer (205) may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0100] Figure 4 is an exploded perspective view of a display device according to one embodiment of the present invention.

[0101] Referring to FIG. 4, the display device (DD) may include a display panel (DP) and an input sensing layer (ISP).

[0102] The display panel (DP) may be a configuration that actually generates an image. The display panel (DP) may be an emissive display panel, for example, the display panel (DP) may be an organic light-emitting display panel, a quantum dot display panel, a micro LED display panel, or a nano LED display panel.

[0103] A display panel (DP) includes a display area (DP_DA) that displays an image (IM, see FIG. 1b) and a non-display area (DP_NDA) adjacent to the display area (DP_DA). The display area (DP_DA) may correspond to the display area (DA) illustrated in FIG. 1b, and the non-display area (DP_NDA) may correspond to the non-display area (NDA) illustrated in FIG. 1b. The display area (DP_DA) is an area where an image is actually displayed, and the non-display area (DP_NDA) is a bezel area where an image is not displayed. Although FIG. 4 illustrates a structure in which the non-display area (DP_NDA) is arranged to surround the display area (DP_DA), the present invention is not limited thereto. The non-display area (DP_NDA) may be arranged on at least one side of the display area (DP_DA).

[0104] A display panel (DP) includes a plurality of pixels (PX) and signal lines connected to the plurality of pixels (PX). Each of the plurality of pixels (PX) may include a light-emitting element. The signal lines may include data lines, scan lines, light-emitting control lines, and power lines.

[0105] An input sensing layer (ISP) may be disposed on a display panel (DP). The input sensing layer (ISP) may sense an input applied from the outside. In an example of the present invention, the input sensing layer (ISP) may be disposed to overlap a display area (DP_DA). The input sensing layer (ISP) may include a plurality of regions. FIG. 4 exemplarily illustrates that the input sensing layer (ISP) is divided into two regions by a virtual boundary line (BL), but the number of regions provided to the input sensing layer (ISP) is not limited thereto. Hereinafter, the two regions are referred to as a first sensing region (SA1) and a second sensing region (SA2), respectively. The first and second sensing regions (SA1, SA2) may be adjacent to each other in the first direction (DR1).

[0106] The display device (DD) may further include a plurality of display driving chips (hereinafter, referred to as first to third display driving chips (DDV1 to DDV3)) and a plurality of flexible circuit films (hereinafter, referred to as first to third flexible circuit films (FCB1 to FCB3)). The first to third display driving chips (DDV1 to DDV3) may be mounted on a non-display area (DP_NDA) of the display panel (DP). The first to third flexible circuit films (FCB1 to FCB3) may be attached (or coupled) to one side of the display panel (DP) and electrically connected to the first to third display driving chips (DDV1 to DDV3), respectively.

[0107] Although FIG. 4 illustrates a structure in which the first to third display driving chips (DDV1 to DDV3) are mounted on a display panel (DP), the present invention is not limited thereto. That is, the first to third display driving chips (DDV1 to DDV3) may be mounted on the first to third flexible circuit films (FCB1 to FCB3) in a chip-on-film (COF) manner, respectively.

[0108] The display device (DD) may further include a first sensor controller (TIC1) and a second sensor controller (TIC2) for controlling the operation of the input sensing layer (ISP). As an example of the present invention, two sensor controllers (TIC1, TIC2) are illustrated, but the present invention is not limited thereto. When the size of the input sensing layer (ISP) increases, the number of sensor controllers (TIC1, TIC2) may further increase.

[0109] The first sensor controller (TIC1) controls the operation of the first sensing area (SA1) of the input sensing layer (ISP), and the second sensor controller (TIC2) can control the operation of the second sensing area (SA2) of the input sensing layer (ISP). Each of the first and second sensor controllers (TIC1, TIC2) is configured in the form of a chip and can be mounted on the first and second touch flexible circuit films (TFCB1, TFCB2), respectively. In Fig. 4, the first and second touch flexible circuit films (TFCB1, TFCB2) are provided as separate configurations from the first to third flexible circuit films (FCB1 to FCB3), but the present invention is not limited thereto. For example, when the first touch flexible circuit film (TFCB1) is formed integrally with the first or second flexible circuit film (FCB1, FCB2), the first sensor controller (TIC1) can be mounted on the first or second flexible circuit film (FCB1, FCB2).

[0110] The first and second sensor controllers (TIC1, TIC2) calculate input coordinate information based on received signals from the input sensing layer (ISP), and the display device (DD) executes an operation corresponding to the input based on the coordinate signals.

[0111] Figure 5 is a plan view of the display panel illustrated in Figure 4.

[0112] Referring to FIG. 5, the display device (DD) may include a display panel (DP), a scan driving circuit (SDV), a plurality of display driving chips (DDV1 to DDV3), an emission driving circuit (EDV), and a plurality of pads (D-PD).

[0113] The display panel (DP) may have long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2). Corners of the display panel (DP) connecting the long sides and the short sides may have an outwardly convex curved shape.

[0114] A display panel (DP) may include a display area (DP_DA) and a non-display area (DP_NDA) surrounding the display area (DP_DA). The display area (DP_DA) may have a shape corresponding to the display panel (DP). Accordingly, the display area (DP_DA) has long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2), and corners of the display area (DP_DA) connecting the long sides and the short sides may have an outwardly convex curved shape.

[0115] A display panel (DP) may include a plurality of pixels (PX), a plurality of scan lines (SL1 to SLm), a plurality of data lines (DL1 to DLn), and a plurality of emission control lines (EL1 to ELm). m and n are natural numbers.

[0116] Pixels (PX) may be arranged in a display area (DP_DA). Scan driving circuits (SDV) and emission driving circuits (EDV) may be arranged in non-display areas (DP_NDA) adjacent to opposite sides of a display panel (DP) that are opposite to each other in a first direction (DR1). Display driving chips (DDV1 to DDV3) may be arranged in non-display areas (DP_NDA) adjacent to one side of opposite sides of a display panel (DP) that are opposite to each other in a second direction (DR2). When viewed in a plan view, the display driving chips (DDV1 to DDV3) may be adjacent to a bottom of the display panel (DP).

[0117] Scan lines (SL1 to SLm) may extend in a first direction (DR1) and be connected to pixels (PX) and a scan driving circuit (SDV). Data lines (DL1 to DLn) may extend in a second direction (DR2) and be connected to pixels (PX) and display driving chips (DDV1 to DDV3). Light emission control lines (EL1 to ELm) may extend in a first direction (DR1) and be connected to pixels (PX) and a light emission driving circuit (EDV).

[0118] The display driving chips (DDV1 to DDV3) may be arranged in a first direction (DR1). A predetermined number of data lines may be connected to each of the display driving chips (DDV1 to DDV3). By way of example, three display driving chips (DDV1 to DDV3) are illustrated, but the number of the display driving chips (DDV1 to DDV3) is not limited thereto. For example, as the left and right areas of the display panel (DP) increase, the number of the display driving chips (DDV1 to DDV3) may also increase.

[0119] The pads (D-PD) are arranged in a non-display area (DP_NDA) adjacent to the bottom of the display panel (DP), and the pads (D-PD) may be provided at positions adjacent to the display driving chips (DDV1 to DDV3). The display driving chips (DDV1 to DDV3) may be arranged between the pads (D-PD) and the data lines (DL1 to DLn). The input terminals of each of the display driving chips (DDV1 to DDV3) may be electrically connected to the pads (D-PD), and the output terminals may be electrically connected to the data lines (DL1 to DLn). The pads (D-PD) may be connected to the flexible circuit films (FCB1 to FCB3) illustrated in FIG. 4.

[0120] The scan driving circuit (SDV) generates a plurality of scan signals, and the scan signals can be applied to the pixels (PX) through scan lines (SL1 to SLm). The display driving chips (DDV1 to DDV3) generate a plurality of data voltages, and the data voltages can be applied to the pixels (PX) through data lines (DL1 to DLn). The emission driving circuit (EDV) generates a plurality of emission control signals, and the emission control signals can be applied to the pixels (PX) through emission control lines (EL1 to ELm).

[0121] Pixels (PX) can receive data voltages in response to scan signals. Pixels (PX) can display images by emitting light with a brightness corresponding to the data voltages in response to light emission control signals.

[0122] A hole area (DP_HA) may be defined in a display panel (DP). The hole area (DP_HA) may be defined within a display area (DP_DA). The hole area (DP_HA) may be adjacent to an upper corner of the display area (DP_DA), but the location of the hole area (DP_HA) is not limited thereto. For example, the hole area (DP_HA) may be adjacent to an upper center of the display area (DP_DA). The hole area (DP_HA) may be defined by penetrating a portion of the display panel (DP) in a third direction (DR3).

[0123] Fig. 6 is a plan view of the input sensing layer illustrated in Fig. 4. Fig. 7 is a drawing showing the connection of sensing electrodes and trace lines arranged in the A1 region illustrated in Fig. 6.

[0124] Referring to FIG. 6, the input sensing layer (ISP) may include a plurality of sensing electrodes (SE).

[0125] The input sensing layer (ISP) may have long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2). Corners of the input sensing layer (ISP) connecting the long sides and short sides of the input sensing layer (ISP) may have an outwardly convex curved shape.

[0126] The input sensing layer (ISP) may include an active area (AA) and a non-active area (NAA) surrounding the active area (AA). The non-active area (NAA) may surround the active area (AA). The active area (AA) may overlap the display area (DP_DA) (see FIG. 5), and the non-active area (NAA) may overlap the non-display area (DP_NDA) (see FIG. 5).

[0127] The active area (AA) may have a shape corresponding to the input sensing layer (ISP). The active area (AA) may have long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2). The active area (AA) may include at least one corner portion having a curved shape. As an example of the present invention, the active area (AA) includes four corner portions (hereinafter referred to as first to fourth corner portions (CRN1 to CRN4)). For example, each of the first to fourth corner portions (CRN1 to CRN4) of the active area (AA) connecting the long sides and the short sides of the active area (AA) may have an outwardly convex curved shape.

[0128] The sensing electrodes (SE) can be arranged in the active area (AA). The sensing electrodes (SE) can be arranged in a first direction (DR1) and a second direction (DR2). The sensing electrodes (SE) can be arranged in a matrix form to have unique coordinate information. The sensing electrodes (SE) can be electrically separated (or insulated) from each other. For example, the boundary between the sensing electrodes (SE) is drawn as a line, and in practice, the sensing electrodes (SE) can be arranged in an island form without contacting each other and spaced apart from each other.

[0129] The sensing electrodes (SE) may have the same shape. Each of the sensing electrodes (SE) may have two sides (referred to as the first side and the second side) facing each other, each having a shape in which the sides protrude in a sawtooth shape. For example, each of the sensing electrodes (SE) may include a first side protruding in a sawtooth shape in a second direction (DR2) and a second side protruding in a sawtooth shape in a direction opposite to the second direction (DR2). That is, when the first and second sides of each of the sensing electrodes (SE) are formed in a concave-convex structure, the lengths of the first and second sides may be longer than when they have a straight structure. As a result, the size of the electrostatic capacitance formed between two adjacent sensing electrodes (SE) may increase, and a large electrostatic capacitance may be secured without increasing the area of ​​each of the sensing electrodes (SE) within an active area (AA) of a limited size.

[0130] A hole area (ISP_HA) may be defined in the input sensing layer (ISP). The hole area (ISP_HA) may be defined within the active area (AA). The hole area (ISP_HA) may be defined by penetrating a portion of the input sensing layer (ISP) in a third direction (DR3). The hole area (ISP_HA) may correspond to the hole area (DP_HA) of the display panel (DP).

[0131] The sensing electrodes (SE) excluding the sensing electrodes (SE) adjacent to the hole area (ISP_HA) and the sensing electrodes (SE) adjacent to the corners (CRN1 to CRN4) (i.e., referred to as regular sensing electrodes) may have the same shape and the same area. The regular sensing electrodes (SE) may be referred to as first sensing electrodes. The sensing electrodes (SE) adjacent to the hole area (ISP_HA) and the sensing electrodes (SE) adjacent to the corners (CRN1 to CRN4) (i.e., referred to as atypical sensing electrodes) may have an atypical shape, unlike the regular sensing electrodes. The atypical sensing electrodes (SE) may be referred to as second sensing electrodes. In one example of the present invention, the atypical sensing electrodes (SE) have a smaller area than the regular sensing electrodes (SE).

[0132] Referring to FIGS. 6 and 7, the sensing electrodes (SE) can be connected to trace lines (SNL). By way of example, the trace lines (SNL) are illustrated in the passive area (NAA) adjacent to the bottom of the input sensing layer (ISP), but in practice, the trace lines (SNL) can be respectively connected to the sensing electrodes (SE) in the active area (AA) and extend into the passive area (NAA).

[0133] The trace lines (SNL) are connected to the sensing electrodes (SE) in a one-to-one correspondence. The trace lines (SNL) and the sensing electrodes (SE) can be arranged on different layers within an effective area (AA) of an input sensing layer (ISP). Each of the trace lines (SNL) is connected to a corresponding one of the plurality of sensing electrodes (SE) through a contact hole (SCNT). Each of the trace lines (SNL) can overlap with other non-corresponding sensing electrodes among the plurality of sensing electrodes (SE) within the effective area (AA).

[0134] The pads (I-PD) may be arranged in the non-active area (NAA) adjacent to the bottom of the input sensing layer (ISP). The trace lines (SNL) may be connected to the pads (I-PD). The pads (I-PD) may be arranged at positions that do not overlap on a plane with the pads (D-PD) illustrated in FIG. 5. The pads (I-PD) may be connected to the touch flexible circuit films (TFCB1, TFCB2) illustrated in FIG. 4. Accordingly, the trace lines (SNL) may be electrically connected to the sensor controllers (TIC1, TIC2) through the pads (I-PD) and the touch flexible circuit films (TFCB1, TFCB2).

[0135] The input sensing layer (ISP) according to an embodiment of the present invention can be operated in self-sensing mode and acquire coordinate information using a self-capture method. The self-sensing mode will be described in detail with reference to FIGS. 8A to 8C.

[0136] Fig. 8a is a diagram showing sensing electrodes arranged in some areas shown in Fig. 6. Fig. 8b is a waveform diagram showing voltages applied to the sensing electrodes shown in Fig. 8a. Fig. 8c is a circuit diagram showing a sensing capacitor in the charging section shown in Fig. 8b, and Fig. 8d is a circuit diagram showing a sensing capacitor in the discharging section shown in Fig. 8b.

[0137] FIG. 8A exemplarily illustrates four sensing electrode rows (SEC1 to SEC4) and seven sensing electrodes (SEk-3 to SEk+3) included in each sensing electrode row (SEC1 to SEC4). Among the seven sensing electrodes (SEk-3 to SEk+3), the k-th sensing electrode (SEk) is a target sensing electrode to be sensed, the k-2, k-1, k+1, and k+2 sensing electrodes (SEk-2, SEk-2, SEk+1, SEk+2) are adjacent sensing electrodes adjacent to the k-th sensing electrode (SEk), and the k-3 and k+3 sensing electrodes (SEk-3, SEk+3) are non-adjacent sensing electrodes that are not adjacent to the k-th sensing electrode (SEk).

[0138] In self-sensing mode, the sensor controller (TIC1) (see FIG. 4) can detect the amount of charge change of the target sensing electrode (SEk) among the sensing electrodes (SE) in units of sensing frames (SF). The sensing frame (SF) can include a charging section (CT) and a discharging section (DT).

[0139] The sensor controller (TIC1) can apply a pre-charge voltage (Vpre) to the target sensing electrode (SEk) during the charging period (CT). The sensor controller (TIC1) can apply a driving voltage (Vdrv) to the adjacent sensing electrodes (SEk-2, SEk-1, SEk+1, SEk+2) during the charging period (CT). The sensor controller (TIC1) can electrically float the target sensing electrode (SEk) during the discharging period (DT). In addition, the sensor controller (TIC1) can apply a reference voltage (e.g., a ground voltage (0 V)) to the adjacent sensing electrodes (SEk-2, SEk-1, SEk+1, SEk+2) during the discharging period (DT).

[0140] Meanwhile, a reference voltage (0 V) can be applied to non-adjacent sensing electrodes (SEk-3, SEk+3) during the charging period (CT) and the discharging period (DT).

[0141] Referring to FIGS. 8c and 8d, the target detection electrode (SEk) forms a parasitic capacitor (Cb) with the second electrode (CE) (see FIG. 3a) of the display panel (DP) (see FIG. 3a), and forms a sensing capacitor (Cp) with adjacent detection electrodes (SEk-1, SEk+1). In addition, when a user's input (e.g., a touch input using a user's finger) occurs, the target detection electrode (SEk) can form a touch capacitor (Ct) with the user's finger.

[0142] Here, the amount of charge charged in the sensing capacitor (Cp) during the charging period (CT) in which the pre-charge voltage (Vpre) is applied to the target sensing electrode (SEk) may be referred to as the first amount of charge (Q1), and the amount of charge charged in the sensing capacitor (Cp) during the discharging period (DT) in which the target sensing electrode (SEk) is in a floating state may be referred to as the second amount of charge (Q2).

[0143] The first charge amount (Q1) and the second charge amount (Q2) can be defined by the following mathematical expressions 1 and 2, respectively. Here, Db can be defined as sensing data output through the target sensing electrode (SEk) during the discharge period (DT).

[0144] [Mathematical Formula 1]

[0145]

[0146] [Equation 2]

[0147]

[0148] Since the first charge (Q1) and the second charge (Q2) are equal according to the law of conservation of charge, the sensing data (Db) satisfying the following mathematical expression 3 can be calculated using mathematical expressions 1 and 2.

[0149] [Equation 3]

[0150]

[0151] According to mathematical expression 3, the sensing data (Db) may vary depending on the size of the sensing capacitor (Cp). That is, when the sensing capacitor (Cp) increases, the size of the sensing data (Db) may decrease, and when the sensing capacitor (Cp) decreases, the size of the sensing data (Db) may increase. The size of the sensing capacitor (Cp) may be determined by the area of ​​the target sensing electrode (SEk) and the areas of the adjacent sensing electrodes (SEk-2, SEk-1, SEk+1, SEk+2).

[0152] Fig. 9 is a plan view showing area A2 shown in Fig. 6. Fig. 10a is an enlarged view showing area B1 of Fig. 9, and Fig. 10b is an enlarged view showing area B2 of Fig. 9. Fig. 11a is an enlarged view showing area B11 of Fig. 10a, and Fig. 11b is a cross-sectional view taken along line I-I' of Fig. 11a. Fig. 12a is an enlarged view showing area B21 of Fig. 10b, and Fig. 12b is a cross-sectional view taken along line II-II' of Fig. 12a.

[0153] Referring to FIG. 9, the sensing electrodes (SE) (see FIG. 6) include a first sensing electrode (SE1) and a second sensing electrode (SE2) arranged adjacent to the hole area (ISP_HA). The second sensing electrode (SE2) is adjacent to the first sensing electrode (SE1) and may have a smaller area than the first sensing electrode (SE1). The first sensing electrode (SE1) and the second sensing electrode (SE2) are arranged to be spaced apart from each other by a predetermined distance. The first sensing electrode (SE1) and the second sensing electrode (SE2) are electrically separated (or insulated) from each other. A boundary area (BA2) may be defined between the first sensing electrode (SE1) and the second sensing electrode (SE2). The sensing electrodes (SE) may further include a third sensing electrode (SE3) adjacent to the first sensing electrode (SE1) and having an area greater than or equal to the first sensing electrode (SE1). The third sensing electrode (SE3) is electrically separated (or insulated) from the first sensing electrode (SE1) and the second sensing electrode (SE2). A boundary area (BA1) may be defined between the first sensing electrode (SE1) and the third sensing electrode (SE3).

[0154] Each of the sensing electrodes (SE) may have a mesh shape. The first sensing electrode (SE1) includes a first mesh wire (ML1) defining a first opening (TOP1), and the second sensing electrode (SE2) includes a second mesh wire (ML2) defining a second opening (TOP2). The first mesh wire (ML1) and the second mesh wire (ML2) are spaced apart from each other in a boundary area (BA2). The third sensing electrode (SE3) includes a third mesh wire (ML3) defining a third opening (TOP3). The first mesh wire (ML1) and the third mesh wire (ML3) are spaced apart from each other in a boundary area (BA1).

[0155] Referring to FIGS. 10A to 11D, the input sensing layer (ISP) (see FIG. 6) is disposed on a different layer from the sensing electrodes (SE) and further includes a plurality of dummy electrodes each overlapping the sensing electrodes (SE). The dummy electrodes include a first dummy electrode (DE1) overlapping a first sensing electrode (SE1) and a second dummy electrode (DE2) overlapping a second sensing electrode (SE2). The dummy electrodes may further include a third dummy electrode (DE3) overlapping a third sensing electrode (SE3). The first and second dummy electrodes (DE1, DE2) are connected to each other at a boundary area (BA2) between the first and second sensing electrodes (SE1, SE2). The first and third dummy electrodes (DE1, DE3) are separated (or spaced) from each other at a boundary area (BA1) between the first and third sensing electrodes (SE1, SE3).

[0156] As illustrated in FIGS. 11B and 12B, the first to third dummy electrodes (DE1, DE2, DE3) are disposed on the base insulating layer (201) and covered by the intermediate insulating layer (203). The first to third sensing electrodes (SE1, SE2, SE3) are disposed on the intermediate insulating layer (203). The first to third sensing electrodes (SE1, SE2, SE3) are electrically insulated from the first to third dummy electrodes (DE1, DE2, DE3) by the intermediate insulating layer (203), respectively. The trace lines (SNL) (see FIG. 7) may be disposed on the same layer as the first to third dummy electrodes (DE1, DE2, DE3). That is, the trace lines (SNL) and the first to third dummy electrodes (DE1, DE2, DE3) are disposed on the base insulating layer (201) and covered by the intermediate insulating layer (203).

[0157] Each of the dummy electrodes may have a mesh shape. The first dummy electrode (DE1) includes a first dummy mesh wire (DML1) arranged along the first mesh wire (ML1), and the second dummy electrode (DE2) includes a second dummy mesh wire (DML2) arranged along the second mesh wire (ML2). The third dummy electrode (DE3) includes a third dummy mesh wire (DML3) arranged along the third mesh wire (ML3). The first to third dummy mesh wires (DML1, DML2, DML3) overlap the first to third mesh wires (ML1, ML2, ML3), respectively. The line width (W1) of each of the first to third mesh wires (ML1, ML2, ML3) may be greater than the line width (W2) of each of the first to third dummy mesh wires (DML1, DML2, DML3).

[0158] The first dummy mesh wiring (DML1) is connected to the second dummy mesh wiring (DML2) in the boundary area (BA2), and is separated (or spaced) from the third dummy mesh wiring (DML3) in the boundary area (BA1). The first dummy mesh wiring (DML1) may have an integral shape with the second dummy mesh wiring (DML2), and the connecting portion (CNP) connecting the first dummy mesh wiring (DML1) and the second dummy mesh wiring (DML2) may overlap the boundary area (BA1).

[0159] A first sensing capacitor (Cpb) is formed between the first sensing electrode (SE1) and the second sensing electrode (SE2), and a second sensing capacitor (Cpa) is formed between the first sensing electrode (SE1) and the third sensing electrode (SE3). Since the second sensing electrode (SE2) has a smaller area than the first and third sensing electrodes (SE1, SE3) due to the hole region (ISP_HA), the size of the first sensing capacitor (Cpb) may be smaller than the size of the second sensing capacitor (Cpa).

[0160] In order to compensate for the size of the first sensing capacitor (Cpb), the first and second dummy electrodes (DE1, DE2) may be connected to each other through a connecting portion (CNP). The connecting portion (CNP) and the first and second dummy electrodes (DE1, DE2) may be formed integrally with each other to form a single common dummy electrode. Accordingly, a first dummy capacitor (Cm1) is formed between the first sensing electrode (SE1) and the common dummy electrode, and a second dummy capacitor (Cm2) is formed between the second sensing electrode (SE2) and the common dummy electrode. The total capacitor formed between the first and second sensing electrodes (SE1, SE2) may increase by the first and second dummy capacitors (Cm1, Cm2). For example, the total capacitor of the first and second sensing electrodes (SE1, SE2) may have a size substantially the same as or similar to that of the second sensing capacitor (Cpa). Therefore, even if the size of the first sensing capacitor (Cpb) is smaller than the size of the second sensing capacitor (Cpa), the problem of the sensing performance being degraded around the hole area (ISP_HA) can be prevented.

[0161] Fig. 13 is a plan view showing area A3 shown in Fig. 6. Fig. 14a is an enlarged view showing area C1 of Fig. 13, and Fig. 14b is an enlarged view of area C1 according to another embodiment of the present invention. Fig. 15a is an enlarged view showing area C11 of Fig. 14a, and Fig. 15b is a cross-sectional view taken along line III-III' of Fig. 15a. Fig. 16a is an enlarged view showing area C12 of Fig. 14b, and Fig. 16b is a cross-sectional view taken along line IV-IV' of Fig. 15c.

[0162] Referring to FIGS. 13, 14a, 15a, and 15b, the sensing electrodes (SE) (see FIG. 6) include a first sensing electrode (SEa) and a second sensing electrode (SEb) disposed adjacent to a corner portion (e.g., a first corner portion (CRN1)). The second sensing electrode (SEb) is adjacent to the first sensing electrode (SEa) and may have a smaller area than the first sensing electrode (SEa). The first sensing electrode (SEa) and the second sensing electrode (SEb) are disposed to be spaced apart from each other by a predetermined distance. A boundary area (BAa) may be defined between the first sensing electrode (SEa) and the second sensing electrode (SEb). The sensing electrodes (SE) may further include a third sensing electrode (SEc) adjacent to the first sensing electrode (SEa) and having an area greater than or equal to the first sensing electrode (SEa). A boundary region can be defined between the first sensing electrode (SEa) and the third sensing electrode (SEc).

[0163] The arrangement structure of the first sensing electrode (SEa) and the third sensing electrode (SEc) is the same as the arrangement structure of the first sensing electrode (SE1) and the third sensing electrode (SE3) illustrated in FIGS. 10a, 11a, and 11b, so a detailed description of the arrangement structure of the first sensing electrode (SEa) and the third sensing electrode (SEc) is omitted.

[0164] In the boundary area BA1 between the first sensing electrode (SEa, SE1) and the third sensing electrode (SEc, SE3), the first sensing electrode (SEa, SE1) and the third sensing electrode (SEc, SE3) are spaced apart by a first gap (d1) (see FIG. 11a). Meanwhile, in the boundary area BAa between the first sensing electrode (SEa) and the second sensing electrode (SEb), the first sensing electrode (SEa) and the second sensing electrode (SEb) are spaced apart by a second gap (d2). In an example of the present invention, the second gap (d2) may be smaller than the first gap (d1).

[0165] Each of the sensing electrodes (SE) may have a mesh shape. The first sensing electrode (SEa) includes a first mesh wire (MLa) defining a first opening (TOPa), and the second sensing electrode (SEb) includes a second mesh wire (MLb) defining a second opening (TOPb). The first mesh wire (MLa) and the second mesh wire (MLb) are spaced apart from each other by a second gap (d2) in a boundary area (BAa). The third sensing electrode (SEc, SE3) includes a third mesh wire (ML3) (see FIG. 10a) defining a third opening (TOP3) (see FIG. 10a). The first mesh wire (ML1) and the third mesh wire (ML3) are spaced apart from each other by a first gap (d1) (see FIG. 11a) in a boundary area (BA1).

[0166] Referring to FIGS. 14a, 15a, and 15b, the input sensing layer (ISP) (see FIG. 6) is disposed on a different layer from the sensing electrodes (SE) and further includes a plurality of dummy electrodes each overlapping the sensing electrodes (SE). The dummy electrodes include a first dummy electrode (DEa) overlapping the first sensing electrode (SEa) and a second dummy electrode (DEb) overlapping the second sensing electrode (SEb). The first and second dummy electrodes (DEa, DEb) may be separated from each other at a boundary area (BAa) between the first and second sensing electrodes (SEa, SEb).

[0167] Each of the dummy electrodes may have a mesh shape. The first dummy electrode (DEa) includes a first dummy mesh wire (DMLa) arranged along the first mesh wire (MLa), and the second dummy electrode (DEb) includes a second dummy mesh wire (DMLb) arranged along the second mesh wire (MLb). The first dummy mesh wire (DMLa) may be separated from the second dummy mesh wire (DMLb) at a boundary area (BAa). In one example of the present invention, the first dummy mesh wire (DMLa) and the second dummy mesh wire (DMLb) are spaced apart from each other by a third distance (d3) at the boundary area (BAa). The third distance (d3) may be greater than the second distance (d2).

[0168] At the first corner (CRN1), the second sensing electrode (SEb) may have a smaller area than the first sensing electrode (SEa) due to the curved edge (CRN_EG). However, if the second gap (d2) between the first sensing electrode (SEa) and the second sensing electrode (SEb) is set to be smaller than the first gap (d1), the problem of the size of the first sensing capacitor (Cp1) becoming smaller than the size of the second sensing capacitor (Cpa) (see FIG. 11b) can be prevented (or improved). Accordingly, even if the second sensing electrode (SEb) has a smaller area than the first sensing electrode (SEa) around the first corner (CRN1), the problem of the sensing performance being deteriorated at the first corner (CRN1) can be prevented.

[0169] Referring to FIGS. 14b, 16a, and 16b, the input sensing layer (ISP) (see FIG. 6) is disposed on a different layer from the sensing electrodes (SE) and further includes a plurality of dummy electrodes each overlapping the sensing electrodes (SE). The dummy electrodes include a first dummy electrode (DEa1) overlapping the first sensing electrode (SEa) and a second dummy electrode (DEb1) overlapping the second sensing electrode (SEb). The first and second dummy electrodes (DEa1, DEb1) may be connected to each other at a boundary area (BAa) between the first and second sensing electrodes (SEa, SEb).

[0170] As illustrated in FIG. 16b, the first and second dummy electrodes (DEa1, DEb1) are disposed on the base insulating layer (201) and covered by the intermediate insulating layer (203). The first to third sensing electrodes (SEa, SEb) are disposed on the intermediate insulating layer (203).

[0171] Each of the dummy electrodes may have a mesh shape. The first dummy electrode (DEa1) includes a first dummy mesh wire (DMLa1) arranged along the first mesh wire (MLa), and the second dummy electrode (DEb1) includes a second dummy mesh wire (DMLb1) arranged along the second mesh wire (MLb). The first dummy mesh wire (DMLa1) is connected to the second dummy mesh wire (DMLb1) at a boundary area (BAa). The first dummy mesh wire (DMLa1) may have an integral shape with the second dummy mesh wire (DMLb1), and a connection portion (CNPa) connecting the first dummy mesh wire (DMLa1) and the second dummy mesh wire (DMLb1) may overlap the boundary area (BAa).

[0172] A first sensing capacitor (Cp1) is formed between a first sensing electrode (SEa) and a second sensing electrode (SEb). The size of the first sensing capacitor (Cp1) can be compensated for by adjusting the gap between the first sensing electrode (SEa) and the second sensing electrode (SEb). However, the size of the first sensing capacitor (Cp1) may not reach a desired size by adjusting the gap alone. In this case, the first and second dummy electrodes (DEa1, DEb1) can be connected to each other through a connecting portion (CNPa). The connecting portion (CNPa) and the first and second dummy electrodes (DEa1, DEb1) can be formed integrally with each other to form a single common dummy electrode. Accordingly, a first dummy capacitor (Cm3) is formed between the first sensing electrode (SEa) and the common dummy electrode, and a second dummy capacitor (Cm4) is formed between the second sensing electrode (SEb) and the common dummy electrode. The total capacitor formed between the first and second sensing electrodes (SEa, SEb) can be increased by the first and second dummy capacitors (Cm3, Cm4). For example, the total capacitor of the first and second sensing electrodes (SEa, SEb) can have a size substantially the same as or similar to that of the second sensing capacitor (Cpa) (see FIG. 11b). Therefore, even if the size of the first sensing capacitor (Cp1) is smaller than that of the second sensing capacitor (Cpa), the problem of the sensing performance being deteriorated around the first corner (CRN1) can be prevented.

[0173] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes may be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims to be described below.

[0174] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims.

[0175] Recently, display devices having an input sensing layer that detects input have been developed. When the display panel is implemented with a structure in which the corners of the display panel are rounded or holes or notches are formed in the display panel, the area of ​​the sensing electrodes may vary depending on the location. Sensing performance may be degraded in areas where the area of ​​the sensing electrode is small, but the present invention can prevent the problem of deterioration of the sensing performance by arranging dummy electrodes in areas where the area of ​​the sensing electrode is small, and as a result, the display device can have uniform sensing performance over the entire area, and therefore the present invention has high industrial applicability.

Claims

1. Display panel; and Including an input sensing layer arranged on the above display panel, The above input detection layer is, multiple sensing electrodes; and A plurality of dummy electrodes are disposed on a different layer from the plurality of sensing electrodes and overlap each of the plurality of sensing electrodes, The above plurality of sensing electrodes are, a first sensing electrode; and A second sensing electrode adjacent to the first sensing electrode, electrically separated from the first sensing electrode, and having a smaller area than the first sensing electrode, The above plurality of dummy electrodes are, a first dummy electrode overlapping the first sensing electrode; and including a second dummy electrode overlapping the second sensing electrode, A display device wherein the first and second dummy electrodes are connected to each other in a boundary region between the first and second sensing electrodes.

2. In the first paragraph, the first sensing electrode includes a first mesh wiring defining a first opening, The second sensing electrode comprises a second mesh wiring defining a second opening, A display device in which the first mesh wiring and the second mesh wiring are spaced apart from each other in the boundary area.

3. In the second paragraph, the first dummy electrode includes a first dummy mesh wiring arranged along the first mesh wiring, The second dummy electrode includes a second dummy mesh wiring arranged along the second mesh wiring, A display device in which the first dummy mesh wiring is connected to the second dummy mesh wiring in the boundary area.

4. In the third paragraph, a display device in which the line width of each of the first and second mesh wirings is greater than the line width of each of the first and second dummy mesh wirings.

5. In the first paragraph, the input sensing layer, a base insulating layer on which the plurality of dummy electrodes are arranged; and A display device further comprising an intermediate insulating layer covering the plurality of dummy electrodes and on which the plurality of sensing electrodes are arranged.

6. In the first paragraph, the plurality of sensing electrodes are arranged in a first direction and a second direction intersecting the first direction, A display device in which the plurality of sensing electrodes are electrically separated from each other.

7. In the first paragraph, the input sensing layer includes an active area in which a hole area is defined and an inactive area arranged around the active area, The above plurality of sensing electrodes are arranged within the active area, The display device wherein the first and second sensing electrodes are adjacent to the hole region.

8. In the first paragraph, the input sensing layer includes an active area having a curved edge in part and an inactive area disposed around the active area, The display device wherein the first and second sensing electrodes are adjacent to the curved edge.

9. In the first paragraph, the plurality of sensing electrodes, Further comprising a third sensing electrode adjacent to the first sensing electrode and having an area equal to or larger than the first sensing electrode; In the boundary region between the first and third sensing electrodes, the first and third sensing electrodes are spaced apart by a first interval, A display device in which the first and second sensing electrodes are spaced apart by a second interval smaller than the first interval in the boundary region between the first and second sensing electrodes.

10. In paragraph 1, The above dummy electrodes are electrically floating display devices.

11. In the first paragraph, further comprising a sensor controller that drives the input sensing layer, The above input detection layer is, A display device further comprising a plurality of trace lines electrically connecting the plurality of sensing electrodes to the sensor controller.

12. In the 11th paragraph, a display device in which each of the trace lines is connected to a corresponding one of the plurality of sensing electrodes and overlaps with other non-corresponding sensing electrodes of the plurality of sensing electrodes.

13. In the 11th paragraph, the trace lines and the plurality of dummy electrodes are arranged on the same layer, A display device wherein the plurality of dummy electrodes do not overlap with the trace lines.

14. Display panel; and An input sensing layer disposed on the display panel and including a plurality of sensing electrodes, The above plurality of sensing electrodes are, First sensing electrode; A second sensing electrode adjacent to the first sensing electrode, electrically separated from the first sensing electrode, and having a smaller area than the first sensing electrode; and A third sensing electrode adjacent to the first sensing electrode, electrically separated from the first and second sensing electrodes, and having the same area as the first sensing electrode, In the boundary region between the first and third sensing electrodes, the first and third sensing electrodes are spaced apart by a first interval, A display device in which the first and second sensing electrodes are spaced apart by a second interval smaller than the first interval in the boundary region between the first and second sensing electrodes.

15. In the 14th paragraph, the plurality of sensing electrodes are arranged in a first direction and a second direction intersecting the first direction, A display device in which the plurality of sensing electrodes are electrically separated from each other.

16. In the 14th paragraph, the input sensing layer includes an active area in which a hole area is defined and an inactive area arranged around the active area, The above plurality of sensing electrodes are arranged within the active area, The display device wherein the first and second sensing electrodes are adjacent to the hole region.

17. In the 14th paragraph, the input sensing layer includes an active area having a curved edge in part and an inactive area arranged around the active area, The display device wherein the first and second sensing electrodes are adjacent to the curved edge.

18. In the 14th paragraph, further comprising a sensor controller that drives the input sensing layer, The above input detection layer is, A display device further comprising a plurality of trace wires electrically connecting the plurality of sensing electrodes to the sensor controller.

19. In the 18th paragraph, a display device in which each of the trace wires is connected to a corresponding one of the plurality of sensing electrodes and overlaps with other non-corresponding sensing electrodes of the plurality of sensing electrodes.

20. In the 19th paragraph, the input sensing layer, Further comprising a plurality of dummy electrodes arranged on the same layer as the above trace wires and overlapping the plurality of sensing electrodes, A display device in which the above plurality of dummy electrodes do not overlap with the above trace wires.

21. In an electronic device including a display device, The above display device, display panel; and Including an input sensing layer arranged on the above display panel, The above input detection layer is, multiple sensing electrodes; and A plurality of dummy electrodes are disposed on a different layer from the plurality of sensing electrodes and overlap each of the plurality of sensing electrodes, The above plurality of sensing electrodes are, a first sensing electrode; and A second sensing electrode adjacent to the first sensing electrode, electrically separated from the first sensing electrode, and having a smaller area than the first sensing electrode, The above plurality of dummy electrodes are, a first dummy electrode overlapping the first sensing electrode; and including a second dummy electrode overlapping the second sensing electrode, An electronic device wherein the first and second dummy electrodes are connected to each other in a boundary region between the first and second sensing electrodes.

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