Display substrate and display device

Abstract

A display substrate comprises: a base substrate (10), the base substrate (10) comprising a display area (11) and a peripheral area (12) surrounding the display area (11); and pixel driving circuits (20), wherein each pixel driving circuit (20) comprises a control module (21) and a gating module (22), the control module (21) is located in the peripheral area (12), the gating module (22) is located in the display area (11), and the gating module (22) is connected to a plurality of light-emitting devices (30); the control module (21) is configured to provide a driving current to the gating module (22) on the basis of a data voltage signal (Data); the gating module (22) is configured to, in response to different gating signals, drive different light-emitting devices (30) to emit light.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] With the development of display technology, touch screen smart phones, tablets, televisions and other display devices have gradually developed. Without considering energy consumption, cost, performance, portability and other external conditions, the screen is naturally higher resolution and larger screen. With the increasing demand of users for screen size and resolution, users require display devices to be more lightweight and portable while requiring display devices to have better display effects. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and proposes a display substrate and a display device.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present disclosure, a display substrate is provided, comprising:

[0005] a substrate substrate having a display area and a peripheral area surrounding the display area;

[0006] a pixel driving circuit, the pixel driving circuit comprising a control module and a gating module, the control module being located in the peripheral area, the gating module being located in the display area, and the gating module being connected with a plurality of light emitting devices, wherein

[0007] the control module is configured to provide driving current to the gating module according to a data voltage signal;

[0008] the gating module is configured to drive different light emitting devices to emit light in response to different gate signals.

[0009] In some optional embodiments, the gating module and the control module are connected to a first node, the gating module comprises a plurality of control transistors, a first electrode of each control transistor is connected to the first node, a plurality of control transistors correspond to a plurality of light emitting devices one by one, a second electrode of each control transistor is connected to a corresponding light emitting device, and different control transistors are connected to different gate signal lines.

[0010] In some optional embodiments, the control module comprises at least one control submodule, and each control submodule provides driving current to at least one light emitting device.

[0011] In some optional embodiments, the control submodule comprises a drive transistor, a first reset subcircuit, a data write subcircuit and an energy storage element, a control electrode of the drive transistor is connected with a first electrode plate of the energy storage element, wherein,

[0012] The first reset subcircuit is configured to write a first initialization voltage signal to the first electrode plate of the energy storage element and the control electrode of the drive transistor in response to a first reset signal.

[0013] The data write subcircuit is configured to write a data voltage signal to the energy storage element and a threshold voltage signal of the drive transistor in response to a scan signal.

[0014] In some optional embodiments, the first reset subcircuit comprises a first transistor, a control electrode of the first transistor is connected with a first reset signal line, a first electrode of the first transistor is connected with a first initialization voltage signal line, and a second electrode of the first transistor is connected with the control electrode of the drive transistor.

[0015] In some optional embodiments, the data write subcircuit comprises a second transistor and a third transistor, a control electrode of the second transistor and a control electrode of the third transistor are both connected with a scan signal line, wherein,

[0016] a first electrode of the second transistor is connected with the first electrode plate of the energy storage element, and a second electrode of the second transistor is connected with a second electrode of the drive transistor;

[0017] a first electrode of the third transistor is connected with a data voltage signal line, and a second electrode of the third transistor is connected with a second electrode plate of the energy storage element.

[0018] In some optional embodiments, the second electrode plate of the energy storage element is connected with a first power supply line, and the control submodule further comprises a first control subcircuit, the first control subcircuit writes a first power supply signal to the drive transistor in response to a light-emitting control signal.

[0019] In some optional embodiments, the first control subcircuit comprises a fourth transistor, a control electrode of the fourth transistor is connected with a light-emitting control signal line, a first electrode of the fourth transistor is connected with the first power supply line, and a second electrode of the fourth transistor is connected with a first electrode of the drive transistor.

[0020] In some optional embodiments, the control submodule further comprises a second reset subcircuit and a third reset subcircuit, wherein,

[0021] the second reset subcircuit writes a reference voltage to the second electrode plate of the energy storage element in response to a first reset signal;

[0022] The third reset sub-circuit writes a reference voltage to the second electrode plate of the energy storage element in response to a light emission control signal.

[0023] In some optional embodiments, the second reset sub-circuit includes a fifth transistor, a control electrode of the fifth transistor is connected with a first reset signal line, a first electrode of the fifth transistor is connected with a reference voltage line, and a second electrode of the fifth transistor is connected with the second electrode plate of the energy storage element.

[0024] In some optional embodiments, the third reset sub-circuit includes a sixth transistor, a control electrode of the sixth transistor is connected with a light emission control signal line, a first electrode of the sixth transistor is connected with a reference voltage line, and a second electrode of the sixth transistor is connected with the second electrode plate of the energy storage element.

[0025] In some optional embodiments, the pixel driving circuit further includes a reset module, the reset module is connected with the first node, and the reset module is configured to write a first initialization voltage signal to the gate control module in response to a second reset signal.

[0026] In some optional embodiments, the reset module includes a seventh transistor, a control electrode of the seventh transistor is connected with a second reset signal line, a first electrode of the seventh transistor is connected with a first initialization voltage signal line, and a second electrode of the seventh transistor is connected with the first node.

[0027] In some optional embodiments, the control submodule further includes a second control sub-circuit, the second control sub-circuit turns on the driving transistor and the gate control module in response to a light emission control signal.

[0028] In some optional embodiments, the second control sub-circuit includes an eighth transistor, a control electrode of the eighth transistor is connected with a light emission control signal line, a first electrode of the eighth transistor is connected with a second electrode of the driving transistor, and a second electrode of the eighth transistor is connected with the first node.

[0029] In some optional embodiments, the control submodule is multiple, multiple control submodules correspond to multiple light emitting devices one-to-one, the light emission control signal includes multiple light emission control sub-signals, different control submodules receive different light emission control sub-signals, and the timing of the light emission control sub-signal received by the control submodule corresponding to the control submodule corresponding to the light emitting device to be turned on is the same as the timing of the gate control signal.

[0030] In some optional embodiments, at least two control submodules in the same pixel driving circuit are located on opposite sides of the display area.

[0031] In some alternative embodiments, the pixel driving circuit is multiple, and the control modules of at least two pixel driving circuits are respectively located on opposite sides of the display area.

[0032] In some alternative embodiments, the substrate is a stretchable substrate, and the display area is provided with a plurality of pixel islands arranged in an array and spaced apart from each other, openings arranged between adjacent pixel islands, and connecting bridges connecting adjacent pixel islands, at least a part of the gate driving module is located on the pixel islands, and each pixel island has at least one light emitting device.

[0033] According to another aspect of the present disclosure, a display device is provided, comprising the display substrate as described above. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification, and are used to explain the present disclosure together with the following detailed description, but do not constitute a limitation of the present disclosure. In the drawings:

[0035] FIG. 1 shows a schematic diagram of the positional relationship between the pixel driving circuit and the substrate in the display substrate according to an alternative embodiment of the present disclosure;

[0036] FIG. 2 shows a schematic diagram of the positional relationship between the pixel driving circuit and the substrate in the display substrate according to another alternative embodiment of the present disclosure;

[0037] FIG. 3 shows a schematic diagram of the structure of the pixel driving circuit according to an alternative embodiment of the present disclosure;

[0038] FIG. 4 shows a schematic diagram of the structure of the pixel driving circuit according to another alternative embodiment of the present disclosure;

[0039] FIG. 5 shows a schematic diagram of the structure of the pixel driving circuit according to another alternative embodiment of the present disclosure;

[0040] FIG. 6 shows a schematic diagram of the structure of the pixel driving circuit according to another alternative embodiment of the present disclosure;

[0041] FIG. 7 shows a schematic diagram of the structure of the pixel driving circuit according to another alternative embodiment of the present disclosure;

[0042] FIG. 8 shows a schematic diagram of the structure of the pixel driving circuit according to another alternative embodiment of the present disclosure;

[0043] FIG. 9 shows a schematic diagram of the structure of the pixel driving circuit according to another alternative embodiment of the present disclosure;

[0044] FIG. 10 shows a schematic diagram of the structure of the pixel driving circuit according to another alternative embodiment of the present disclosure;

[0045] FIG. 11 shows a structural schematic diagram of a display substrate according to an optional embodiment of the present disclosure;

[0046] FIG. 12 shows an enlarged view of A in FIG. 11;

[0047] FIG. 13 shows a working timing diagram of the pixel driving circuit in FIG. 5;

[0048] FIG. 14 shows a working timing diagram of the pixel driving circuit in FIG. 8. DETAILED DESCRIPTION

[0049] The specific embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0050] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the common meanings thereof by those of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0052] As used herein, "parallel," "perpendicular" include the recited condition and conditions that are approximately the recited condition, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with a particular measurement (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, where the acceptable deviation range for approximately perpendicular can also be, for example, within 5°.

[0053] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layer and regions are shown in each figure. Thus, the thicknesses of the layers and regions can be exaggerated for clarity. It will be understood that changes in the sizes of the layers and regions can occur when the exemplary embodiments are manufactured and used. Thus, the exemplary embodiments should not be construed as limited to the shapes and regions shown in the figures. The regions shown in the figures are intended to be illustrative and not limiting of the regions of the devices actually used in the exemplary embodiments. Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and similar terms are used herein to distinguish one element from another, but do not otherwise limit the elements. The terms "including," "containing," and similar terms are used herein to encompass the elements listed thereafter, and are not meant to exclude other elements. The terms "connected" and "coupled" and similar terms are used herein to encompass a physical or mechanical connection, electrical connection, whether direct or indirect, or the like. The terms "upper," "lower," "left," "right," and the like are used herein for ease of description to describe the orientations of elements as they are shown in the figures, and are not meant to restrict the positions of the elements in actual use. The terms "on," "above," "under," and the like are used herein to encompass a direct contact between elements, as well as an indirect contact where one or more intervening elements can also be present.

[0055] It should be noted that the film layers in the embodiments of the present disclosure are schematically illustrated, and do not represent the actual thickness of the film layers.

[0056] In addition, each transistor involved in the embodiments of the present disclosure can be independently selected from one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. The "first electrode" in the present disclosure specifically refers to one of the source electrode or the drain electrode of the transistor, and the corresponding "second electrode" specifically refers to the other of the drain electrode or the source electrode. Of course, it should be known by those skilled in the art that the "first electrode" and the "second electrode" can be interchanged.

[0057] In addition, the working level state refers to a level state capable of turning on the first electrode and the second electrode of the transistor, and the non-working level state refers to a level state capable of turning off the first electrode and the second electrode of the transistor. The transistor can be divided into an N-type transistor and a P-type transistor, and each transistor in the present disclosure can be independently selected from an N-type transistor or a P-type transistor. For the N-type transistor, the working level state is a high level state, and the non-working level state is a low level state. For the P-type transistor, the working level state is a low level state, and the non-working level state is a high level state. In the following embodiments, all the transistors in the pixel unit will be exemplarily described as N-type transistors, and the transistors in the pixel driving circuit 20 can be prepared simultaneously by using the same preparation process.

[0058] With the increasing requirements of users for screen size and resolution, users require display devices to be more lightweight and portable, and at the same time, the display effect of the display device is required to be better. How to improve the pixel density without increasing the screen area of the display device has become a problem to be solved.

[0059] In addition, with the development of display technology, stretchable display devices are also gradually developing, and OLED flexible display devices with bending and foldability have gradually realized productization. At the same time, the stretchable form of flexible display devices is paid more and more attention by enterprises and institutions, and is an important development direction of future display technology.

[0060] At present, the stretchable display device composed of pixel islands, connection bridges, and hollowed-out parts is a common method in design. The width of the connection bridge in the stretchable structure design directly affects the stretching effect of the stretchable display screen. The smaller the width of the connection bridge, the smaller the strain generated by the connection bridge during stretching, and the stretchability can be improved. However, the signal lines of each display island are conducted through the connection bridge, and the number of signal leads is a key factor restricting the width of the connection bridge. Therefore, how to design to maintain high display effect while improving the stretchability of the display device is particularly important.

[0061] FIG. 1 shows a schematic diagram of a position relationship between a pixel driving circuit and a substrate in a display substrate according to an embodiment of the present disclosure; FIG. 2 shows a schematic diagram of a position relationship between a pixel driving circuit and a substrate in a display substrate according to another embodiment of the present disclosure; FIG. 3 shows a schematic diagram of a structure of a pixel driving circuit according to an embodiment of the present disclosure; FIG. 4 shows a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present disclosure; FIG. 5 shows a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present disclosure; FIG. 6 shows a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present disclosure; FIG. 7 shows a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present disclosure; FIG. 8 shows a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present disclosure; FIG. 9 shows a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present disclosure; FIG. 10 shows a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present disclosure; FIG. 11 shows a schematic diagram of a structure of a display substrate according to an embodiment of the present disclosure; FIG. 12 shows an enlarged view of A in FIG. 11; FIG. 13 shows a timing diagram of a working process of a pixel driving circuit according to an embodiment of the present disclosure; and FIG. 14 shows a timing diagram of a working process of a pixel driving circuit according to another embodiment of the present disclosure.

[0062] As shown in FIG. 1 and FIG. 2, the display substrate includes a substrate 10 and a pixel driving circuit 20. The substrate 10 has a display area 11 and a peripheral area 12 surrounding the display area 11. The pixel driving circuit 20 includes a control module 21 and a selection module 22, the control module 21 is located in the peripheral area 12, the selection module 22 is located in the display area 11, and the selection module 22 is connected with a plurality of light emitting devices 30. The control module 21 is configured to provide a driving current to the selection module 22 according to a data voltage signal Data; and the selection module 22 is configured to drive different light emitting devices 30 to emit light in response to different selection signals.

[0063] The selection module 22 in the pixel driving circuit 20 is connected with the plurality of light emitting devices 30, which can control the light emitting of the plurality of light emitting devices 30, and can reduce the area occupied by the pixel driving circuit 20 in the display area 11, which is conducive to increasing the number of light emitting devices 30 arranged in the display area 11 and improving the pixel density. In addition, the control module 21 in the pixel driving circuit 20 is arranged in the peripheral area 12, and only the selection module 22 is arranged in the display area 11, which further reduces the area occupied by the pixel driving circuit 20 in the display area 11, which is conducive to improving the pixel density and further improving the display effect.

[0064] In some optional embodiments, referring to FIG. 11 and FIG. 12, the substrate 10 is a stretchable substrate, the display area 11 is provided with a plurality of pixel islands 13 arranged in an array and spaced apart from each other, the openings 14 are arranged between the adjacent pixel islands 13, and the connecting bridges 15 are arranged to connect the adjacent pixel islands 13. At least a part of the gating module 22 is arranged on the pixel islands 13, and each pixel island 13 is provided with at least one light emitting device 30. When the substrate 10 is a stretchable substrate, the control module 21 in the pixel driving circuit 20 is arranged in the peripheral area 12, which can effectively reduce the number of signal leads in the display area 11, and further reduce the number of signal leads arranged on the connecting bridges 15, which is conducive to reducing the width of the connecting bridges 15, and further improving the stretchability of the substrate 10. In this way, the display effect of the display device can be improved while the stretchability of the display device is improved.

[0065] In some optional embodiments, referring to FIG. 1 and FIG. 2, the peripheral area 12 includes two pixel circuit areas 121, and the two pixel circuit areas 121 are symmetrically arranged on opposite sides of the display area 11. The control module is arranged in the pixel circuit area 121.

[0066] In some optional embodiments, the peripheral area 12 further includes two initial placement areas 122, and the two initial placement areas 122 are respectively arranged on the side away from the display area 11 of the two pixel circuit areas 121. The first initial voltage signal line is arranged in the initial placement area 122.

[0067] In some optional embodiments, the peripheral area 12 further includes two gate placement areas 123 for arranging the gate driving circuit and two array placement areas 124 for arranging the array emission driving circuit. The two gate placement areas 123 are respectively arranged on the side away from the display area 11 of the two initial placement areas 122. The two array placement areas 124 are respectively arranged on the side away from the display area 11 of the two gate placement areas 123. The gate driving circuit is arranged in the gate placement area 123, and the light emitting control circuit is arranged in the array placement area 124.

[0068] In some optional embodiments, as shown in FIG. 1, the gating module 22 and the control module 21 are connected to the first node M, the gating module 22 includes a plurality of control transistors, the first electrode of each control transistor is connected to the first node M, the plurality of control transistors correspond to the plurality of light emitting devices 30 one by one, the second electrode of each control transistor is connected to the corresponding light emitting device 30, and different control transistors are connected to different gate signal lines. The control transistors in the gating module 22, the gate signal lines, and the light emitting devices 30 are in a one-to-one correspondence, so that the gate signals on different gate signal lines control whether the light emitting devices 30 emit light. For example, the gate signal controls the corresponding control transistor to be turned on, and the driving current flows into the corresponding light emitting device 30 through the first node M to drive the corresponding light emitting device 30 to emit light.

[0069] In some embodiments, the light emitting device 30 can be a LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode), and in the embodiments of the present disclosure, the OLED is taken as an example for description.

[0070] Optionally, the first electrode of the light emitting device 30 is an anode, and the second electrode is a cathode. The first electrode of the light emitting device 30 is connected to the second electrode of the control transistor, and the second electrode of the light emitting device 30 can be connected to a second power supply line which can provide a second power supply signal VSS, and the second power supply signal VSS can be a low-level signal.

[0071] In some optional embodiments, as shown in FIG. 1 and FIG. 2, the control module 21 includes at least one control submodule 211, and each control submodule 211 provides a driving current to at least one light emitting device 30. For example, one pixel driving circuit 20 includes only one control submodule 211, and the control submodule 211 provides a driving current to a plurality of light emitting devices 30; for another example, one pixel driving circuit 20 includes a plurality of control submodules 211, and one control submodule 211 can provide a driving current to a plurality of light emitting devices 30, or one control submodule 211 can provide a driving current to one light emitting device 30, which is not specifically limited here.

[0072] In the specific embodiments shown in FIG. 3 to FIG. 10, the control submodule 211 includes a driving transistor T9, a first reset subcircuit 212, a data writing subcircuit 213 and an energy storage element Cst, the control electrode of the driving transistor is connected to the first electrode plate of the energy storage element Cst, wherein,

[0073] The first reset subcircuit 212 is configured to write a first initialization voltage signal Vinit to the first electrode plate of the energy storage element Cst and the control electrode of the driving transistor T9 in response to a first reset signal Reset;

[0074] The data writing subcircuit 213 is configured to write a data voltage signal Date and a threshold voltage signal of the driving transistor to the energy storage element Cst in response to a scanning signal Gate.

[0075] The pixel driving circuit 20 of the embodiments of the present disclosure can include a plurality of working stages, each of which includes a reset sub-stage, a data writing sub-stage and a light emitting sub-stage. In the reset sub-stage of each working stage, the first initialization voltage signal Vinit can be written to the control electrode of the driving transistor T9 and the first electrode plate of the energy storage element Cst by using the first reset sub-circuit 212, wherein the control electrode of the driving transistor T9 and the first electrode plate of the energy storage element Cst are connected to the N1 node, and the N1 node is reset. In the data writing sub-stage of each working stage, the data voltage signal Date and the threshold voltage signal of the driving transistor T9 can be written to the energy storage element Cst by using the data writing sub-circuit 213. In the light emitting sub-stage of different working stages, the driving transistor T9 is turned on with different light emitting devices 30 by using the selection module 22, so that different light emitting devices 30 emit light in different working stages.

[0076] In some optional embodiments, referring to FIGS. 3-10, the first reset sub-circuit 212 includes a first transistor T1, the control electrode of the first transistor T1 is connected with the first reset signal line, the first electrode of the first transistor T1 is connected with the first initialization voltage signal line, and the second electrode of the first transistor T1 is connected with the control electrode of the driving transistor T9. When the first reset signal Reset on the first reset signal line is in a working level state, the first electrode and the second electrode of the first transistor T1 are turned on, so that the first initialization voltage signal Vinit on the first initialization voltage signal line is written to the N1 node, and the N1 node is reset.

[0077] In some optional embodiments, referring to FIGS. 3-10, the data writing sub-circuit 213 includes a second transistor T2 and a third transistor T3, the control electrode of the second transistor T2 and the control electrode of the third transistor T3 are connected with the scanning signal Gate line, wherein the first electrode of the second transistor T2 is connected with the first electrode plate of the energy storage element Cst, and the second electrode of the second transistor T2 is connected with the second electrode of the driving transistor T9; the first electrode of the third transistor T3 is connected with the data voltage signal line, and the second electrode of the third transistor T3 is connected with the second electrode plate of the energy storage element Cst.

[0078] In the specific embodiment shown in FIG. 3 and FIG. 4, the second electrode plate of the energy storage element Cst is connected to the first power supply line, and the control sub-module 211 further comprises a first control sub-circuit 214, which is configured to turn on the driving transistor T9 in response to the light-emitting control signal EMc. In the light-emitting sub-stage of each working stage, the first control sub-circuit 214 is used to turn on the driving transistor T9 in response to the light-emitting control signal EMc, and in the light-emitting sub-stage of different working stages, the first node M of the driving transistor T9 is turned on by the gating module 22 in response to different light-emitting devices 30, so that different light-emitting devices 30 emit light in different working stages.

[0079] In the light-emitting sub-stage, the first control sub-circuit 214 is configured to turn on the first node M of the driving transistor T9 in response to the light-emitting control signal EMc; at the same time, the gating module 22 is configured to turn on one of the light-emitting devices 30 in response to the light-emitting control signal EMc, so as to provide a driving current for the light-emitting device 30.

[0080] In some alternative embodiments, referring to FIG. 3 and FIG. 4, the first control sub-circuit 214 comprises a fourth transistor T4, the control electrode of the fourth transistor T4 is connected to the light-emitting control signal line, the first electrode of the fourth transistor T4 is connected to the first power supply line, and the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T9. When the light-emitting control signal EMc on the light-emitting control signal line is in the working level state, the first electrode and the second electrode of the fourth transistor T4 are turned on, so as to transmit the first power supply signal VDD on the first power supply line to the first electrode of the driving transistor T9.

[0081] It should be noted that when any of the selection signals is in the working level state, the light-emitting control signal EMc is in the working level state.

[0082] In some alternative embodiments, referring to FIG. 3 and FIG. 4, the second electrode of the driving transistor T9 is connected to the gating module 22 at the first node M, and in this structure, the gating module 22 is configured to turn on the driving transistor T9 in response to different light-emitting devices 30, so that different light-emitting devices 30 emit light in different working stages.

[0083] In another embodiment, referring to FIG. 7 to FIG. 10, the control sub-module 211 comprises a second control sub-circuit 215, which is configured to turn on the driving transistor T9 in response to the light-emitting control signal EMc. In the light-emitting sub-stage of each working stage, the second control sub-circuit 215 is used to turn on the driving transistor T9 in response to the light-emitting control signal EMc, and in the light-emitting sub-stage of different working stages, the driving transistor T9 is turned on by the gating module 22 in response to different light-emitting devices 30, so that different light-emitting devices 30 emit light in different working stages.

[0084] In the specific embodiment shown in FIGS. 7-10, the second control sub-circuit 215 includes an eighth transistor T8, a control electrode of the eighth transistor T8 is connected with the light-emitting control signal line, a first electrode of the eighth transistor T8 is connected with the second electrode of the driving transistor T9, and a second electrode of the eighth transistor T8 is connected with the gating module 22. When the light-emitting control signal EMc on the light-emitting control signal line is in the working level state, the first electrode and the second electrode of the eighth transistor T8 are turned on, thereby turning on the second electrode of the driving transistor T9 and the gating module 22.

[0085] In some optional embodiments, referring to FIGS. 5-10, the control sub-circuit 211 includes a second reset sub-circuit 216 configured to write the reference voltage to the second electrode plate of the energy storage element Cst in response to the first reset signal.

[0086] In some optional embodiments, referring to FIGS. 5-10, the second reset sub-circuit 216 includes a fifth transistor T5, a control electrode of the fifth transistor T5 is connected with the first reset signal line, a first electrode of the fifth transistor T5 is connected with the reference voltage line, and a second electrode of the fifth transistor T5 is connected with the second electrode plate of the energy storage element Cst. When the first reset signal Reset on the first reset signal line is in the working level state, the first reset signal Reset writes the reference voltage Vref to the second electrode plate of the energy storage element Cst, thereby resetting the second electrode plate of the energy storage element Cst.

[0087] In some optional embodiments, referring to FIGS. 5-10, the control sub-circuit 211 further includes a third reset sub-circuit 217 configured to write the reference voltage to the second electrode plate of the energy storage element Cst in response to the light-emitting control signal EMc.

[0088] In some optional embodiments, referring to FIGS. 5-10, the third reset sub-circuit 217 includes a sixth transistor T6, a control electrode of the sixth transistor T6 is connected with the light-emitting control signal line, a first electrode of the sixth transistor T6 is connected with the reference voltage line, and a second electrode of the sixth transistor T6 is connected with the second electrode plate of the energy storage element Cst. When the light-emitting control signal EMc on the light-emitting control signal line is in the working level state, the light-emitting control signal EMc writes the reference voltage Vref to the second electrode plate of the energy storage element Cst, thereby resetting the second electrode plate of the energy storage element Cst. In some optional embodiments, the pixel driving circuit 20 further includes a reset module 23 connected with the first node M, the reset module 23 is configured to write the first initialization voltage signal Vinit to the gating module 22 in response to the second reset signal Reste-0.

[0089] In some optional embodiments, referring to FIG. 9 and FIG. 10, the reset module 23 includes a seventh transistor T7, a control electrode of the seventh transistor T7 is connected with the second reset signal line, a first electrode of the seventh transistor T7 is connected with the first initialization voltage signal line, and a second electrode of the seventh transistor T7 is connected with the first node M. When the second reset signal Reste-0 on the second reset signal line is in the working level state, the second reset signal Reste-0 writes the first initialization voltage signal Vinit into the first node M, thereby resetting the first node M.

[0090] In the specific embodiments shown in FIG. 4, FIG. 6, FIG. 8 and FIG. 10, the control sub-module 211 is multiple, the multiple control sub-modules 211 correspond to the multiple light emitting devices 30 one by one, the light emitting control signal EMc includes multiple light emitting control sub-signals, different control sub-modules 211 receive different light emitting control sub-signals, and the timing of the light emitting control sub-signal received by the control sub-module 211 corresponding to the corresponding open light emitting device 30 is the same as the timing of the selection signal. That is, the control sub-module 211, the light emitting control sub-signal, the selection signal, and the light emitting device 30 correspond one by one.

[0091] For example, one pixel driving circuit 20 includes three control sub-modules 211, three light emitting control sub-signals, three selection signals, and three light emitting devices 30, wherein the three control sub-modules 211 are respectively a first control sub-module 211, a second control sub-module 211 and a third control sub-module 211; the three light emitting control sub-signals are respectively a first light emitting control sub-signal EMc1, a second light emitting control sub-signal EMc2 and a third light emitting control sub-signal EMc3; the three selection signals are respectively a first selection signal EM1, a second selection signal EM2 and a third selection signal EM3; and the three light emitting devices 30 are respectively a first light emitting device 31, a second light emitting device 32 and a third light emitting device 33. The first control sub-module 211 provides a driving current for the first light emitting device 31, the first light emitting control sub-signal EMc1 serves as the light emitting control signal EMc provided by the first control sub-module 211, and the first selection signal EM1 controls the control transistor corresponding to the first light emitting device 31 to open, so that the driving current provided by the first control sub-module 211 flows into the first light emitting device 31. Here, it is not listed one by one.

[0092] FIG. 13 is a working timing diagram of the pixel driving circuit shown in FIG. 5. As shown in FIG. 13, the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2 and a light emitting sub-stage t3 in each display period (i.e., each sub-frame, such as sub-frame_1, sub-frame_2, sub-frame_3 and sub-frame_4). The working process of the pixel driving circuit in FIG. 5 is described below with reference to the working timing diagram in FIG. 13.

[0093] In the reset sub-stage t1, the first reset signal Reset on the first reset signal line is in the working level state, the first transistor T1 is turned on, so as to transmit the first initialization voltage signal Vinit on the first initialization voltage line to the N1 node, and then reset the N1 node. The fifth transistor T5 is turned on, so as to transmit the reference voltage signal Vref on the reference voltage line to the second electrode plate of the storage element Cst. In addition, the scan signal Gate on the scan signal line and the emission control signal EMc on the emission control line are all in the non-working level state, so that the second transistor T2, the third transistor T3 and the sixth transistor T6 are all turned off. The gate signal on the gate signal line is in the non-working level state, and the control transistor is turned off.

[0094] In the data writing sub-stage t2, the scan signal Gate on the scan signal line is in the working level state, so that the second transistor T2 and the third transistor T3 are turned on, the data voltage signal Date on the data voltage signal line is written to the second electrode plate of the storage element Cst, the potential of the second electrode plate of the storage element Cst is VData, the control electrode and the second electrode of the driving transistor T9 are short-circuited to form a diode, the power supply signal VDD on the power supply signal line is directly connected to the N1 node through the driving transistor T9 and the second transistor T2, and the potential of the storage element Cst reaches VDD-Vth. In addition, the first reset signal Reset on the first reset signal line and the emission control signal EMc on the emission control line are all in the non-working level state, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are all in the off state, the gate signal on the gate signal line is in the non-working level state, and the control transistor is turned off.

[0095] In the emission sub-stage t3, the emission control signal EMc on the emission control line and one gate signal are in the working level state, the first reset signal Reset on the first reset signal line and the scan signal Gate on the scan signal line are all in the non-working level state. At this time, the sixth transistor T6 is turned on, the potential of the second electrode plate of the storage element Cst jumps from VData to Vref, and under the voltage maintaining action of the storage capacitor Cst, the potential of the first electrode plate of the storage element Cst jumps from VDD-Vth to VDD-Vth+Vref-Vdata, that is, the data voltage signal Date is written to the gate of the driving transistor T9 at the same time, one gate signal is in the working level state, so as to drive one light emitting device to emit light. For example, the first gate signal EM1 is in the working level state, and the other gate signals are in the non-working state, so as to drive the light emitting device corresponding to the first gate signal EM1 to emit light.

[0096] FIG. 14 is a timing diagram of the pixel driving circuit shown in FIG. 8, as shown in FIG. 14, the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2 and an emitting sub-stage t3 in each display period (i.e., each sub-frame, for example, sub-frame_1, sub-frame_2, sub-frame_3).

[0097] In the reset sub-stage t1, the first reset signal Reset on the first reset signal line is in the working level state, the first transistor T1 is turned on, so as to transmit the first initialization voltage signal Vinit on the first initialization voltage line to the N1 node, and then reset the N1 node. The fifth transistor T5 is turned on, so as to transmit the reference voltage signal Vref on the reference voltage line to the second electrode plate of the storage element Cst. In addition, the scanning signal Gate on the scanning signal line and the emitting control sub-signal are in the non-working level state, so as to turn off the second transistor T2, the third transistor T3, the sixth transistor T6 and the eighth transistor T8. The gate signal on the gate signal line is in the non-working level state, and the control transistor is turned off.

[0098] In the data writing sub-stage t2, the scanning signal Gate on the scanning signal line is in the working level state, so as to turn on the second transistor T2 and the third transistor T3, the data voltage signal Date on the data voltage signal line is written to the second electrode plate of the storage element Cst, the potential of the second electrode plate of the storage element Cst is VData, the control electrode and the second electrode of the driving transistor T9 are short-circuited to form a diode, the power supply signal VDD on the power supply signal line is directly flowed to the N1 node through the driving transistor T9 and the second transistor T2, and the potential of the storage element Cst reaches VDD-Vth. In addition, the first reset signal Reset on the first reset signal line and the emitting control sub-signal are in the non-working level state, the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 are in the off state, the gate signal on the gate signal line is in the non-working level state, and the control transistor is turned off.

[0099] In the light emitting sub-stage t3, one light emitting control signal sub-signal, one selection signal are in the working level state, the first reset signal Reset on the first reset signal line and the scanning signal Gate on the scanning signal line are in the non-working level state. At this time, the sixth transistor T6 is turned on, the potential of the second electrode plate of the energy storage element Cst jumps from VData to Vref, under the voltage maintaining action of the storage capacitor Cst, the potential of the first electrode plate of the energy storage element Cst jumps from VDD-Vth to VDD-Vth+Vref-Vdata, that is, the data voltage signal Date is written to the gate of the driving transistor T9, the driving transistor T9 is turned on, the eighth transistor T8 is turned on, and at the same time one selection signal is in the working level state, and one light emitting device is turned on to emit light. For example, the first light emitting control sub-signal EMc1 is in the working level state, the first selection signal EM1 is in the working level state, and other light emitting control sub-signals and selection signals are in the non-working state, and the light emitting device corresponding to the first selection signal EM1 is turned on to emit light.

[0100] The timing of the first light emitting control sub-signal EMc1 is the same as that of the first selection signal EM1.

[0101] In some optional embodiments, at least two control sub-modules 211 in the same pixel driving circuit 20 are located on opposite sides of the display area 11. Such arrangement is conducive to rational use of space on the substrate 10 and improves the space utilization rate.

[0102] In some optional embodiments, there are multiple pixel driving circuits 20, and the multiple light emitting devices 30 connected to the selection module 22 of the same pixel driving circuit 20 are located in the same row. Such arrangement is conducive to driving the light emitting devices 30 row by row.

[0103] In some other optional embodiments, there are multiple pixel driving circuits 20, and the multiple light emitting devices 30 connected to the selection module 22 of the same pixel driving circuit 20 are located in the same column.

[0104] In some other optional embodiments, the multiple light emitting devices 30 connected to the selection module 22 of the same pixel driving circuit 20 are located in different rows and different columns, which is not specifically limited here and can be designed according to specific use requirements.

[0105] In some optional embodiments, there are multiple pixel driving circuits 20, and the control modules 21 of at least two pixel driving circuits 20 are located on opposite sides of the display area 11. Such arrangement is conducive to rational use of space on the substrate 10 and improves the space utilization rate.

[0106] In some alternative embodiments, the pixel driving circuit 20 is multiple, and the multiple light emitting devices 30 connected to the same gating module 22 of the pixel driving circuit 20 are located in the same row, and the light emitting colors of the multiple light emitting devices 30 connected to the same gating module 22 are all the same.

[0107] In some alternative embodiments, the pixel driving circuit 20 is multiple, and the multiple light emitting devices 30 connected to the same gating module 22 of the pixel driving circuit 20 are located in the same row, and the light emitting colors of the multiple light emitting devices 30 connected to the same gating module 22 are all the same.

[0108] According to another aspect of the present disclosure, a display device is provided, including the display substrate described above. The display device having the display substrate described above has the advantages of light and thin, high pixel density. The display device can include any device or product having a display function. For example, the display device can be a smart phone, a mobile phone, an electronic book reader, a desktop PC, a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0109] In some alternative embodiments, the display device is a stretchable display device.

[0110] It can be understood that the above embodiments are merely exemplary embodiments adopted for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising: a substrate substrate having a display area and a peripheral area surrounding the display area; a pixel driving circuit comprising a control module and a gate-on module, the control module being located in the peripheral area, the gate-on module being located in the display area, and the gate-on module being connected with a plurality of light emitting devices, wherein the control module is configured to provide a driving current to the gate-on module according to a data voltage signal; the gate-on module is configured to drive different light emitting devices to emit light in response to different gate-on signals. 2.The display substrate of claim 1, wherein, the gate-on module and the control module are connected to a first node, the gate-on module comprises a plurality of control transistors, a first electrode of each of the control transistors is connected to the first node, the plurality of control transistors correspond to the plurality of light emitting devices one by one, a second electrode of each of the control transistors is connected to a corresponding light emitting device, and different control transistors are connected to different gate-on signal lines. 3.The display substrate of claim 2, wherein, the control module comprises at least one control sub-module, and each control sub-module provides a driving current to at least one light emitting device. 4.The display substrate of claim 3, wherein, the control sub-module comprises a driving transistor, a first reset sub-circuit, a data writing sub-circuit and an energy storage element, a control electrode of the driving transistor is connected to a first electrode plate of the energy storage element, wherein the first reset sub-circuit is configured to write a first initialization voltage signal to the first electrode plate of the energy storage element and the control electrode of the driving transistor in response to a first reset signal; the data writing sub-circuit is configured to write a data voltage signal and a threshold voltage signal of the driving transistor to the energy storage element in response to a scanning signal. 5.The display substrate of claim 4, wherein, the first reset sub-circuit comprises a first transistor, a control electrode of the first transistor is connected to a first reset signal line, a first electrode of the first transistor is connected to a first initialization voltage signal line, and a second electrode of the first transistor is connected to the control electrode of the driving transistor. 6.The display substrate of claim 4, wherein, the data writing sub-circuit comprises a second transistor and a third transistor, a control electrode of the second transistor and a control electrode of the third transistor are both connected to a scanning signal line, wherein a first electrode of the second transistor is connected to the first electrode plate of the energy storage element, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; a first electrode of the third transistor is connected to a data voltage signal line, and a second electrode of the third transistor is connected to a second electrode plate of the energy storage element. 7.The display substrate of claim 4, wherein, a second electrode plate of the energy storage element is connected to a first power supply line, and the control sub-module further comprises a first control sub-circuit, the first control sub-circuit is configured to turn on the driving transistor in response to a light emitting control signal. 8.The display substrate of claim 7, wherein, the first control sub-circuit comprises a fourth transistor, a control electrode of the fourth transistor is connected to a light emitting control signal line, a first electrode of the fourth transistor is connected to the first power supply line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor. 9.The display substrate of claim 4, wherein, the control sub-module further comprises a second reset sub-circuit and a third reset sub-circuit, wherein The second reset sub-circuit writes a reference voltage to the second electrode plate of the energy storage element in response to a first reset signal; The third reset sub-circuit writes a reference voltage to the second electrode plate of the energy storage element in response to a light-emitting control signal. 10.The display substrate of claim 9, wherein, The second reset sub-circuit includes a fifth transistor, a control electrode of the fifth transistor is connected with a first reset signal line, a first electrode of the fifth transistor is connected with a reference voltage line, and a second electrode of the fifth transistor is connected with the second electrode plate of the energy storage element. 11.The display substrate of claim 9, wherein, The third reset sub-circuit includes a sixth transistor, a control electrode of the sixth transistor is connected with a light-emitting control signal line, a first electrode of the sixth transistor is connected with the reference voltage line, and a second electrode of the sixth transistor is connected with the second electrode plate of the energy storage element. 12.The display substrate according to any one of claims 2 to 11, wherein The pixel driving circuit further includes a reset module connected with the first node, and the reset module is configured to write a first initialization voltage signal to the gate module in response to a second reset signal. 13.The display substrate of claim 12, wherein, The reset module includes a seventh transistor, a control electrode of the seventh transistor is connected with a second reset signal line, a first electrode of the seventh transistor is connected with a first initialization voltage signal line, and a second electrode of the seventh transistor is connected with the first node. 14.The display substrate according to any one of claims 4 to 11, wherein The control sub-module further includes a second control sub-circuit, and the second control sub-circuit turns on the driving transistor and the gate module in response to a light-emitting control signal. 15.The display substrate of claim 14, wherein, The second control sub-circuit includes an eighth transistor, a control electrode of the eighth transistor is connected with a light-emitting control signal line, a first electrode of the eighth transistor is connected with a second electrode of the driving transistor, and a second electrode of the eighth transistor is connected with the first node. 16.The display substrate according to any one of claims 3 to 11, wherein The control sub-module is multiple, multiple control sub-modules correspond to multiple light-emitting devices one-to-one, the light-emitting control signal includes multiple light-emitting control sub-signals, different control sub-modules receive different light-emitting control sub-signals, and the timing of the light-emitting control sub-signal received by the control sub-module corresponding to the gate signal and the light-emitting device to be turned on is the same. 17.The display substrate of claim 16, wherein, At least two control sub-modules in the same pixel driving circuit are located on opposite sides of the display area. 18.The display substrate according to any one of claims 1-11, wherein, The pixel driving circuit is multiple, and the control modules of at least two pixel driving circuits are located on opposite sides of the display area. 19.The display substrate according to any one of claims 1-11, wherein, The substrate is a stretchable substrate, the display area is provided with multiple pixel islands arranged in an array and spaced apart from each other, an opening arranged between adjacent pixel islands, and a connecting bridge connecting adjacent pixel islands, at least part of the gate module is located on the pixel island, and each pixel island has at least one light-emitting device.

20. A display device comprising the display substrate of any one of claims 1 to 19.

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