Pixel driving circuit and driving method therefor, and display device

Abstract

A pixel driving circuit and a driving method therefor, and a display device. The pixel driving circuit comprises a first control sub-circuit, a second control sub-circuit, a driving sub-circuit, and a light-emitting control sub-circuit. The first control sub-circuit provides a signal to a first node under the control of signals of a first reference signal line, a first light-emitting signal line, a scanning signal line, a data signal line, a control signal line, a first power supply line and a fourth node; the second control sub-circuit provides a signal of the first power supply line or a second reference signal line to a fifth node and provides a signal of a first initialization signal line to a fourth node under the control of signals of the first light-emitting signal line, a first reset signal line and a second reset signal line; and the light-emitting control sub-circuit provides a signal of the fourth node or a second initialization signal line to first electrodes of at least two light-emitting devices under the control of signals of the first reset signal line and at least two light-emitting signal lines.

Description

Pixel driving circuit, driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202411109962.0, filed on August 13, 2024, and entitled "Pixel driving circuit, driving method thereof and display device", the content of which is to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but not limited to, display technology, in particular to a pixel driving circuit, a driving method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a pixel driving circuit, which is electrically connected with at least two light-emitting devices, the light-emitting device comprising a first electrode and a second electrode, the pixel driving circuit comprising: a first control sub-circuit, a second control sub-circuit, a driving sub-circuit and a light-emitting control sub-circuit.

[0006] The first control sub-circuit is electrically connected with a first reference signal line, a first light-emitting signal line, a scan signal line, a data signal line, a control signal line, a first power supply line, a first node and a fourth node, respectively, and is configured to provide a signal to the first node under the control of signals of the first reference signal line, the first light-emitting signal line, the scan signal line, the data signal line, the control signal line, the first power supply line and the fourth node.

[0007] The second control sub-circuit is electrically connected with the first power supply line, the first light-emitting signal line, the second reference signal line, the first reset signal line, the second reset signal line, the first initial signal line, the fifth node and the fourth node respectively, and is configured to provide the signal of the first power supply line or the second reference signal line to the fifth node and provide the signal of the first initial signal line to the fourth node under the control of the signals of the first light-emitting signal line, the first reset signal line and the second reset signal line.

[0008] The driving sub-circuit is electrically connected with the first node, the fourth node and the fifth node respectively, and is configured to provide the driving signal to the fourth node under the control of the signals of the first node and the fifth node.

[0009] The light-emitting control sub-circuit is electrically connected with the fourth node, the second initial signal line, the first reset signal line, at least two light-emitting signal lines and at least two light-emitting devices respectively, and is configured to provide the signal of the fourth node or the second initial signal line to the first electrode of the at least two light-emitting devices under the control of the signals of the first reset signal line and the at least two light-emitting signal lines.

[0010] In some possible implementation manners, the light-emitting control sub-circuit includes K groups of first light-emitting control sub-circuits, and K is greater than or equal to 2.

[0011] The i-th group of first light-emitting control sub-circuits are electrically connected with the fourth node, the i+1-th light-emitting signal line, the second initial signal line, the first reset signal line and the first electrode of the i-th light-emitting device respectively, and are configured to provide the signal of the fourth node or the second initial signal line to the first electrode of the i-th light-emitting device under the control of the signals of the i+1-th light-emitting signal line and the first reset signal line, where 1 is less than or equal to i and is less than or equal to K.

[0012] In some possible implementation manners, at least one group of first light-emitting control sub-circuits includes a sixth transistor and a seventh transistor.

[0013] For the i-th group of first light-emitting control sub-circuits, the control electrode of the sixth transistor is electrically connected with the i+1-th light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first electrode of the i-th light-emitting device; the control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the second initial signal line, and the second electrode of the seventh transistor is electrically connected with the first electrode of the i-th light-emitting device.

[0014] In some possible implementation manners, the light-emitting control sub-circuit includes K groups of first light-emitting control sub-circuits, and K is greater than or equal to 2.

[0015] The first group of first light emitting control sub-circuits are electrically connected with the fourth node, the third light emitting signal line and the first electrode of the first light emitting device respectively, and are configured to provide the signal of the fourth node to the first electrode of the first light emitting device under the control of the signal of the third light emitting signal line;

[0016] The jth group of first light emitting control sub-circuits are electrically connected with the fourth node, the j+2th light emitting signal line, one of the first reset signal line and the third reset signal line, the second initial signal line and the first electrode of the jth light emitting device respectively, and are configured to provide the signal of the fourth node or the second initial signal line to the first electrode of the jth light emitting device under the control of the signal of the j+2th light emitting signal line and the one of the first reset signal line and the third reset signal line, 2≤j≤K.

[0017] In some possible implementation manners, the first group of first light emitting control sub-circuits comprises a seventh transistor, the jth group of first light emitting control sub-circuits comprises an eleventh transistor and a twelfth transistor;

[0018] The control electrode of the seventh transistor is electrically connected with the third light emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light emitting device;

[0019] For the jth group of first light emitting control sub-circuits, the control electrode of the eleventh transistor is electrically connected with the j+2th light emitting signal line, the first electrode of the eleventh transistor is electrically connected with the fourth node, and the second electrode of the eleventh transistor is electrically connected with the first electrode of the jth light emitting device; the control electrode of the twelfth transistor is electrically connected with the third reset signal line, the first electrode of the twelfth transistor is electrically connected with the first electrode of the jth light emitting device, and the second electrode of the twelfth transistor is electrically connected with the second initial signal line.

[0020] In some possible implementation manners, the light emitting control sub-circuit further comprises a second light emitting control sub-circuit, and the K groups of first light emitting control sub-circuits are electrically connected with the fourth node through the second light emitting control sub-circuit;

[0021] The second light emitting control sub-circuit is electrically connected with the second light emitting signal line, the fourth node and the sixth node respectively, and is configured to provide the signal of the fourth node to the sixth node under the control of the signal of the second light emitting signal line;

[0022] The K groups of first light emitting control sub-circuits are electrically connected with the second light emitting control sub-circuit through the sixth node.

[0023] In some possible implementation manners, the second light emitting control sub-circuit comprises a sixth transistor, the first group of first light emitting control sub-circuits comprises a seventh transistor, and the jth group of first light emitting control sub-circuits comprises an eleventh transistor and a twelfth transistor;

[0024] The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the sixth node;

[0025] The control electrode of the seventh transistor is electrically connected with the third light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light-emitting device;

[0026] For the jth group of first light-emitting control sub-circuits, the control electrode of the eleventh transistor is electrically connected with the j+2 light-emitting signal line, the first electrode of the eleventh transistor is electrically connected with the sixth node, and the second electrode of the eleventh transistor is electrically connected with the first electrode of the jth light-emitting device; the control electrode of the twelfth transistor is electrically connected with the first reset signal line, the first electrode of the twelfth transistor is electrically connected with the first electrode of the jth light-emitting device, and the second electrode of the twelfth transistor is electrically connected with the second initial signal line.

[0027] In some possible implementation manners, the light-emitting control sub-circuit comprises: a second light-emitting control sub-circuit and M groups of first light-emitting control sub-circuits, where M is greater than or equal to 1;

[0028] The second light-emitting control sub-circuit is electrically connected with the fourth node, the second light-emitting signal line, the second initial signal line, the first reset signal line, and the first electrode of the first light-emitting device respectively, and is configured to provide the fourth node or the second initial signal line to the first electrode of the first light-emitting device under the control of signals of the second light-emitting signal line and the second initial signal line;

[0029] The jth group of first light-emitting control sub-circuits is electrically connected with the j+1 light-emitting signal line, the first electrode of the first light-emitting device, and the first electrode of the jth light-emitting device respectively, and is configured to connect the first electrode of the jth light-emitting device and the first electrode of the first light-emitting device under the control of the signal of the j+1 light-emitting signal line.

[0030] In some possible implementation manners, the second light-emitting control sub-circuit comprises: a sixth transistor and a seventh transistor, and the jth group of first light-emitting control sub-circuits comprises: an eleventh transistor;

[0031] The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first electrode of the first light-emitting device;

[0032] The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the first electrode of the first light-emitting device, and the second electrode of the seventh transistor is electrically connected with the second initial signal line;

[0033] For the jth group of the first light emitting control sub-circuit, the control electrode of the eleventh transistor is electrically connected with the j+1th light emitting signal line, the first electrode of the eleventh transistor is electrically connected with the first electrode of the first light emitting device, and the second electrode of the eleventh transistor is electrically connected with the first electrode of the jth light emitting device.

[0034] In some possible implementation manners, the first control sub-circuit comprises a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor.

[0035] The control electrode of the second transistor is electrically connected with the control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node.

[0036] The control electrode of the fourth transistor is electrically connected with the scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node.

[0037] The control electrode of the ninth transistor is electrically connected with the control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first power supply line.

[0038] The control electrode of the tenth transistor is electrically connected with the first light emitting signal line, the first electrode of the tenth transistor is electrically connected with the third node, and the second electrode of the tenth transistor is electrically connected with the first reference signal line.

[0039] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node.

[0040] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node.

[0041] In some possible implementation manners, the second control sub-circuit comprises a first transistor, a fifth transistor and an eighth transistor.

[0042] The control electrode of the first transistor is electrically connected with the second reset signal line, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first initial signal line.

[0043] The control electrode of the fifth transistor is electrically connected with the first light emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the fifth node.

[0044] The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the second reference signal line.

[0045] In some possible implementation manners, the first control sub-circuit comprises a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit comprises a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit comprises a third transistor; and the light-emitting control sub-circuit comprises K sixth transistors and K seventh transistors, K≥2.

[0046] The control electrode of the first transistor is electrically connected with the second reset signal line, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first initial signal line.

[0047] The control electrode of the second transistor is electrically connected with the control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node.

[0048] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the fifth node, and the second electrode of the third transistor is electrically connected with the fourth node.

[0049] The control electrode of the fourth transistor is electrically connected with the scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node.

[0050] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the fifth node.

[0051] The control electrode of the i th sixth transistor is electrically connected with the i+1 th light-emitting signal line, the second electrode is electrically connected with the first electrode of the i th light-emitting device, the first electrode is electrically connected with the fourth node, and 1≤i≤K.

[0052] The control electrode of the i th seventh transistor is electrically connected with the first reset signal line, the first electrode is electrically connected with the second initial signal line, and the second electrode is electrically connected with the first electrode of the i th light-emitting device.

[0053] The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the second reference signal line.

[0054] The control electrode of the ninth transistor is electrically connected with the control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first power supply line.

[0055] The control electrode of the tenth transistor is electrically connected with the first light-emitting signal line, the first electrode of the tenth transistor is electrically connected with the third node, and the second electrode of the tenth transistor is electrically connected with the first reference signal line.

[0056] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node.

[0057] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node.

[0058] In some possible implementation manners, the first control sub-circuit comprises a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit comprises a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit comprises a third transistor; and the light-emitting control sub-circuit comprises a sixth transistor, a seventh transistor, K-1 eleventh transistors and K-1 twelfth transistors, K≥2.

[0059] The control electrode of the first transistor is electrically connected with the second reset signal line, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first initial signal line.

[0060] The control electrode of the second transistor is electrically connected with the control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node.

[0061] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the fifth node, and the second electrode of the third transistor is electrically connected with the fourth node.

[0062] The control electrode of the fourth transistor is electrically connected with the scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node.

[0063] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the fifth node.

[0064] The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the sixth node.

[0065] The control electrode of the seventh transistor is electrically connected with the third light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light-emitting device.

[0066] The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the second reference signal line.

[0067] The control electrode of the ninth transistor is electrically connected with a control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with a first power supply line;

[0068] The control electrode of the jth eleventh transistor is electrically connected with a (j+2)th light-emitting signal line, the first electrode is electrically connected with the sixth node, and the second electrode is electrically connected with the first electrode of the jth light-emitting device, 2≤j≤K;

[0069] The control electrode of the jth twelfth transistor is electrically connected with a first reset signal line, the first electrode is electrically connected with the first electrode of the jth light-emitting device, and the second electrode is electrically connected with a second initial signal line;

[0070] The control electrode of the twelfth transistor is electrically connected with the first reset signal line, the first electrode of the twelfth transistor is electrically connected with the first electrode of the second light-emitting device, and the second electrode of the twelfth transistor is electrically connected with the second initial signal line;

[0071] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node;

[0072] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node.

[0073] In some possible implementation manners, the first control sub-circuit includes a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit includes a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit includes a third transistor; and the light-emitting control sub-circuit includes a seventh transistor, K-1 eleventh transistors and K-1 twelfth transistors, K≥2.

[0074] The control electrode of the first transistor is electrically connected with a second reset signal line, the first electrode of the first transistor is electrically connected with a fourth node, and the second electrode of the first transistor is electrically connected with a first initial signal line;

[0075] The control electrode of the second transistor is electrically connected with a control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node;

[0076] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with a fifth node, and the second electrode of the third transistor is electrically connected with the fourth node;

[0077] The control electrode of the fourth transistor is electrically connected with a scan signal line, the first electrode of the fourth transistor is electrically connected with a data signal line, and the second electrode of the fourth transistor is electrically connected with the third node;

[0078] The control electrode of the fifth transistor is electrically connected with a first emitting signal line, the first electrode of the fifth transistor is electrically connected with a first power supply line, and the second electrode of the fifth transistor is electrically connected with the fifth node;

[0079] The control electrode of the seventh transistor is electrically connected with a third emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light emitting device;

[0080] The control electrode of the eighth transistor is electrically connected with a first reset signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with a second reference signal line;

[0081] The control electrode of the ninth transistor is electrically connected with a control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first power supply line;

[0082] The control electrode of the tenth transistor is electrically connected with the first emitting signal line, the first electrode of the tenth transistor is electrically connected with the third node, and the second electrode of the tenth transistor is electrically connected with the first reference signal line;

[0083] The control electrode of the jth eleventh transistor is electrically connected with a (j+2)th emitting signal line, the first electrode is electrically connected with the fourth node, and the second electrode is electrically connected with the first electrode of the jth light emitting device, 2≤j≤K;

[0084] The control electrode of the jth twelfth transistor is electrically connected with a third reset signal line, the first electrode is electrically connected with the first electrode of the jth light emitting device, and the second electrode is electrically connected with a second initial signal line;

[0085] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node;

[0086] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node.

[0087] In some possible implementation manners, the first control sub-circuit includes: a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit includes: a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit includes: a third transistor; and the light emitting control sub-circuit includes: a sixth transistor, a seventh transistor and K-1 eleventh transistors, K≥2.

[0088] The control electrode of the first transistor is electrically connected to the second reset signal line, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the first initial signal line.

[0089] The control electrode of the second transistor is electrically connected to the control signal line, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first node.

[0090] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the fifth node, and the second electrode of the third transistor is electrically connected to the fourth node.

[0091] The control electrode of the fourth transistor is electrically connected to the scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the third node.

[0092] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the fifth node.

[0093] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the first light-emitting device.

[0094] The control electrode of the seventh transistor is electrically connected to the first reset signal line, the first electrode of the seventh transistor is electrically connected to the first electrode of the first light-emitting device, and the second electrode of the seventh transistor is electrically connected to the second initial signal line.

[0095] The control electrode of the eighth transistor is electrically connected to the first reset signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the second reference signal line.

[0096] The control electrode of the ninth transistor is electrically connected to the control signal line, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor is electrically connected to the first power supply line.

[0097] The control electrode of the tenth transistor is electrically connected to the first light-emitting signal line, the first electrode of the tenth transistor is electrically connected to the third node, and the second electrode of the tenth transistor is electrically connected to the first reference signal line.

[0098] The control electrode of the j-th eleventh transistor is electrically connected to the (j+1)-th light-emitting signal line, the first electrode is electrically connected to the first electrode of the first light-emitting device, and the second electrode is electrically connected to the first electrode of the j-th light-emitting device, where 2≤j≤K;

[0099] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node.

[0100] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node.

[0101] In some possible implementation manners, the second transistor and the ninth transistor are N-type transistors, and at least one of the first transistor, the third transistor to the eighth transistor, and the tenth transistor to the twelfth transistor is a P-type transistor.

[0102] In a second aspect, the embodiments of the present disclosure provide a display device, comprising the pixel driving circuit according to any one of the embodiments of the first aspect.

[0103] In a third aspect, the embodiments of the present disclosure provide a driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of the embodiments of the first aspect, and the method comprises:

[0104] The first control sub-circuit provides a signal to the first node under the control of signals of the first reference signal line, the first light-emitting signal line, the scan signal line, the data signal line, the control signal line, the first power supply line and the fourth node;

[0105] The second control sub-circuit provides a signal of the first power supply line or the second reference signal line to the fifth node and a signal of the first initial signal line to the fourth node under the control of signals of the first light-emitting signal line, the first reset signal line and the second reset signal line;

[0106] The driving sub-circuit provides a driving signal to the fourth node under the control of signals of the first node and the fifth node;

[0107] The light-emitting control sub-circuit provides a signal of the fourth node or the second initial signal line to the first electrode of the at least two light-emitting devices under the control of signals of the first reset signal line and the at least two light-emitting signal lines.

[0108] Other aspects can become apparent from the following detailed description, taken in conjunction with the accompanying drawings.

[0109] SUMMARY

[0110] The accompanying drawings are included to provide a further understanding of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0111] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an example embodiment of the present disclosure;

[0112] Figure 2 is an equivalent circuit diagram of a light emission control sub-circuit according to an example embodiment;

[0113] Figure 3 is an equivalent circuit diagram of a light emission control sub-circuit according to an example embodiment;

[0114] Figure 4 is an equivalent circuit diagram of a light emission control sub-circuit according to an example embodiment;

[0115] Figure 5 is an equivalent circuit diagram of a light emission control sub-circuit according to an example embodiment;

[0116] Figure 6 is an equivalent circuit diagram of a first control sub-circuit according to an example embodiment;

[0117] Figure 7 is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment;

[0118] Figure 8 is an equivalent circuit diagram of a drive sub-circuit according to an example embodiment;

[0119] Figure 9 is an equivalent circuit diagram of a pixel drive circuit according to an example embodiment;

[0120] Figure 10 is a timing diagram of the pixel drive circuit of Figure 9;

[0121] Figure 11 is an equivalent circuit diagram of a pixel drive circuit according to an example embodiment;

[0122] Figure 12 is a timing diagram of the pixel drive circuit of Figure 11;

[0123] Figure 13 is an equivalent circuit diagram of a pixel drive circuit according to an example embodiment;

[0124] Figure 14 is a timing diagram of the pixel drive circuit of Figure 13;

[0125] Figure 15 is an equivalent circuit diagram of a pixel drive circuit according to an example embodiment;

[0126] Figure 16 is a timing diagram of the pixel drive circuit of Figure 15.

[0127] Detailed description

[0128] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically describe the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the means and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0129] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams of structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0130] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limited in terms of quantity.

[0131] In the present specification, in order to facilitate the description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of the description of the present specification and the simplification of the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0132] In the present specification, unless otherwise explicitly specified and limited, the terms "mounting", "connection", and "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0133] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0134] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0135] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0136] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0137] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be changed into "a conductive film". Similarly, "an insulating film" can be changed into "an insulating layer".

[0138] In this specification, "formation in the same layer" means that two (or more) structures are formed by patterning at the same time, and the materials thereof can be the same or different. For example, the materials of precursors used for forming the two (or more) structures in the same layer are the same, and the materials of the formed structures can be the same or different.

[0139] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, or deformation.

[0140] In the present disclosure, "about" means not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0141] To meet the user's demand for display devices, display sub-pixels and anti-peep sub-pixels can be arranged in the display panel to realize the switching of different display states. However, due to the use of display sub-pixels and anti-peep sub-pixels in the display panel, the brightness of the emitted light in different display states is relatively low, and the anti-interference ability to external light is poor, thereby reducing the overall light efficiency of the display panel and affecting the visual experience and visual experience of the display panel.

[0142] Fig. 1 is a structural schematic diagram of a pixel driving circuit provided by an example embodiment of the present disclosure, the pixel driving circuit being electrically connected with at least two light emitting devices, the light emitting devices including a first electrode and a second electrode. As shown in Fig. 1, the pixel driving circuit can include a first control sub-circuit, a second control sub-circuit, a driving sub-circuit, and a light emitting control sub-circuit.

[0143] The first control sub-circuit is electrically connected with a first reference signal line Vref1, a first light emitting signal line EM1, a scan signal line Gate, a data signal line Data, a control signal line AZ, a first power supply line VDD, a first node N1, and a fourth node N4, respectively, and is configured to provide a signal to the first node N1 under the control of signals of the first reference signal line Vref1, the first light emitting signal line EM1, the scan signal line Gate, the data signal line Data, the control signal line AZ, the first power supply line VDD, and the fourth node N4.

[0144] The second control sub-circuit is electrically connected with the first power supply line VDD, the first light emitting signal line EM1, a second reference signal line Vref2, a first reset signal line Reset1, a second reset signal line Reset2, a first initial signal line Vinit1, a fifth node N5, and the fourth node N4, respectively, and is configured to provide a signal of the first power supply line VDD or the second reference signal line Vref2 to the fifth node N5 and a signal of the first initial signal line Vinit1 to the fourth node N4 under the control of signals of the first light emitting signal line EM1, the first reset signal line Reset1, and the second reset signal line Reset2.

[0145] The driving sub-circuit is electrically connected with the first node N1, the fourth node N4, and the fifth node N5, respectively, and is configured to provide a driving signal to the fourth node N4 under the control of signals of the first node N1 and the fifth node N5.

[0146] The light-emitting control sub-circuit is electrically connected with the fourth node N4, the second initial signal line Vinit2, the first reset signal line Reset1, at least two light-emitting signal lines (for example, the second light-emitting signal line EM2, the third light-emitting signal line EM3, …, the Kth light-emitting signal line EMk in FIG. 1, K is the total number of light-emitting signal lines, K≥2) and at least two light-emitting devices (for example, the first light-emitting device L1, the second light-emitting device L2, …, the K-1th light-emitting signal line Lk-1 in FIG. 1), and is configured to provide the signal of the fourth node N4 or the second initial signal line Vinit2 to the first electrode of the at least two light-emitting devices under the control of the signals of the first reset signal line Reset1 and the at least two light-emitting signal lines.

[0147] In an example embodiment, the signal of the first power supply line VDD can be a high-level signal.

[0148] In an example embodiment, the light-emitting device can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The OLED can include a first electrode (anode), an organic light-emitting layer and a second electrode (cathode) stacked.

[0149] In an example embodiment, as shown in FIG. 1, the second electrode of the light-emitting device can be electrically connected with the second power supply line VSS, and the signal of the second power supply line VSS is a low-level signal.

[0150] In the embodiments of the present disclosure, the pixel driving circuit is electrically connected with the at least two light-emitting devices, and the light-emitting control sub-circuit is configured to provide the signal to the first electrode of the at least two light-emitting devices, so as to selectively turn on the current of the at least two light-emitting devices, thereby realizing the driving of two or more groups of light-emitting devices by one group of pixel driving circuits, improving the overall light efficiency of the display panel and the visual experience of the display panel.

[0151] FIG. 2 is an equivalent circuit diagram of a light-emitting control sub-circuit provided by an example embodiment. As shown in FIG. 2, in an example embodiment, the light-emitting control sub-circuit can include K groups of first light-emitting control sub-circuits, K≥2.

[0152] In an example embodiment, as shown in FIG. 2, the i-th group of first light-emitting control sub-circuits are electrically connected with the fourth node N4, the i+1th light-emitting signal line EMi+1, the second initial signal line Vinit2, the first reset signal line Reset1 and the first electrode of the i-th light-emitting device Li, and are configured to provide the signal of the fourth node N4 or the second initial signal line Vinit2 to the first electrode of the i-th light-emitting device Li under the control of the signals of the i+1th light-emitting signal line EMi+1 and the first reset signal line Reset1, 1≤i≤K.

[0153] In an example embodiment, as shown in FIG. 2, the at least one first light emitting control sub-circuit can include a sixth transistor T6 and a seventh transistor T7. For the i-th first light emitting control sub-circuit, a control electrode of the sixth transistor T6 is electrically connected to an (i+1)-th light emitting signal line EMi+1, a first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and a second electrode of the sixth transistor T6 is electrically connected to a first electrode of the i-th light emitting device Li; a control electrode of the seventh transistor T7 is electrically connected to the first reset signal line Reset1, a first electrode of the seventh transistor T7 is electrically connected to the second initial signal line Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the first electrode of the i-th light emitting device Li.

[0154] In an example embodiment, signals of different light emitting signal lines are independent of each other in one frame time.

[0155] In the embodiments of the present disclosure, the first light emitting control sub-circuits of different groups are connected to different light emitting signal lines, i.e., the sixth transistors in different groups are connected to different light emitting signal lines. For example, the sixth transistors in the first group of first light emitting control sub-circuits can be connected to the second light emitting signal line, and the sixth transistors in the second group of first light emitting control sub-circuits can be connected to the third light emitting signal line. The first light emitting control sub-circuits of different groups being connected to different light emitting signal lines can enable the first light emitting control sub-circuits to be controlled independently, and ensure that the first light emitting control sub-circuits of different groups can perform current sharing control on different light emitting devices when turned on.

[0156] An example structure of the light emitting control sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the light emitting control sub-circuit is not limited to this.

[0157] FIG. 3 is an equivalent circuit diagram of the light emitting control sub-circuit according to an example embodiment. As shown in FIG. 3, in an example embodiment, the light emitting control sub-circuit can include K groups of first light emitting control sub-circuits, and K≥2.

[0158] In an example embodiment, as shown in FIG. 3, the first group of first light emitting control sub-circuits are electrically connected to the fourth node N4, the third light emitting signal line EM3 and the first electrode of the first light emitting device L1, respectively, and are configured to provide the signal of the fourth node N4 to the first electrode of the first light emitting device L1 under the control of the signal of the third light emitting signal line EM3; the jth group of first light emitting control sub-circuits are electrically connected to the fourth node N4, the j+2th light emitting signal line EMj+2, one of the first reset signal line Reset1 and the third reset signal line Reset3, the second initial signal line Vinit2 and the first electrode of the jth light emitting device Lj, respectively, and are configured to provide the signal of the fourth node N4 or the second initial signal line Vinit2 to the first electrode of the jth light emitting device Lj under the control of the signal of the j+2th light emitting signal line EMj+2 and one of the first reset signal line Reset1 and the third reset signal line Reset3, 2≤j≤K.

[0159] In an example embodiment, as shown in FIG. 3, the first group of first light emitting control sub-circuits can include the seventh transistor T7, and the jth group of first light emitting control sub-circuits can include the eleventh transistor T11 and the twelfth transistor T12.

[0160] In an example embodiment, as shown in FIG. 3, the control electrode of the seventh transistor T7 is electrically connected to the third light emitting signal line EM3, the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the first light emitting device L1; for the jth group of first light emitting control sub-circuits, the control electrode of the eleventh transistor T11 is electrically connected to the j+2th light emitting signal line EMj+2, the first electrode of the eleventh transistor T11 is electrically connected to the fourth node N4, and the second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the jth light emitting device Lj; the control electrode of the twelfth transistor T12 is electrically connected to the third reset signal line Reset3, the first electrode of the twelfth transistor T12 is electrically connected to the first electrode of the jth light emitting device Lj, and the second electrode of the twelfth transistor T12 is electrically connected to the second initial signal line Vinit2.

[0161] In an example embodiment, as shown in FIG. 3, the twelfth transistor T12 is electrically connected to the third reset signal line Reset3, and the signals of the first reset signal line Reset1 and the second reset signal line Reset2 are independent of each other, so as to prevent signal offset.

[0162] In an example embodiment, the signals of different light emitting signal lines are independent of each other within one frame of time.

[0163] In the embodiments of the present disclosure, the first light-emitting control sub-circuits in different groups are connected to different light-emitting signal lines, that is, the seventh transistor in the first light-emitting control sub-circuit in the first group is connected to a different light-emitting signal line from the eleventh transistor in the first light-emitting control sub-circuit in the jth group, for example, the seventh transistor in the first light-emitting control sub-circuit in the first group can be connected to the third light-emitting signal line, and the eleventh transistor in the first light-emitting control sub-circuit in the second group can be connected to the fourth light-emitting signal line. The first light-emitting control sub-circuits in different groups are connected to different light-emitting signal lines, so that the first light-emitting control sub-circuits in different groups are controlled by independent signals, and the first light-emitting control sub-circuits in different groups can be controlled to perform current sharing control on different light-emitting devices when turned on.

[0164] An exemplary structure of the light-emitting control sub-circuit is shown in FIG. 3. It is easy for those skilled in the art to understand that the implementation of the light-emitting control sub-circuit is not limited to this.

[0165] An equivalent circuit diagram of the light-emitting control sub-circuit provided by an exemplary embodiment is shown in FIG. 4. As shown in FIG. 4, in an exemplary embodiment, on the basis of the embodiment shown in FIG. 3, the light-emitting control sub-circuit can further include a second light-emitting control sub-circuit, and the K groups of first light-emitting control sub-circuits are electrically connected to the fourth node N4 through the second light-emitting control sub-circuit.

[0166] In an exemplary embodiment, as shown in FIG. 4, the second light-emitting control sub-circuit is electrically connected to the second light-emitting signal line EM2, the fourth node N4 and the sixth node N6, respectively, and is configured to provide the signal of the fourth node N4 to the sixth node N6 under the control of the signal of the second light-emitting signal line EM2; and the K groups of first light-emitting control sub-circuits are electrically connected to the second light-emitting control sub-circuit through the sixth node N6.

[0167] In an exemplary embodiment, as shown in FIG. 4, the second light-emitting control sub-circuit can include a sixth transistor T6, the first light-emitting control sub-circuit in the first group can include a seventh transistor T7, and the first light-emitting control sub-circuit in the jth group can include an eleventh transistor T11 and a twelfth transistor T12.

[0168] In an example embodiment, as shown in FIG. 4, the control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the sixth node N6; the control electrode of the seventh transistor T7 is electrically connected with the third light-emitting signal line EM3, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first electrode of the first light-emitting device L1; for the jth group of the first light-emitting control sub-circuit, the control electrode of the eleventh transistor T11 is electrically connected with the j+2th light-emitting signal line EMj+2, the first electrode of the eleventh transistor T11 is electrically connected with the sixth node N6, and the second electrode of the eleventh transistor T11 is electrically connected with the first electrode of the jth light-emitting device Lj; the control electrode of the twelfth transistor T12 is electrically connected with the first reset signal line Reset1, the first electrode of the twelfth transistor T12 is electrically connected with the first electrode of the jth light-emitting device Lj, and the second electrode of the twelfth transistor T12 is electrically connected with the second initial signal line Vinit2.

[0169] In an example embodiment, as shown in FIG. 4, the twelfth transistor T12 is electrically connected with the first reset signal line Reset1, and the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the third reset signal line Reset3 are independent of each other, so as to prevent signal offset.

[0170] In an example embodiment, the signals of different light-emitting signal lines are independent of each other within a frame time.

[0171] In the embodiments of the present disclosure, different groups of the first light-emitting control sub-circuit are connected with different light-emitting signal lines, that is, the seventh transistor in the first group of the first light-emitting control sub-circuit and the eleventh transistor in the jth group of the first light-emitting control sub-circuit are connected with different light-emitting signal lines, for example, the seventh transistor in the first group of the first light-emitting control sub-circuit can be connected with the third light-emitting signal line, and the eleventh transistor in the second group of the first light-emitting control sub-circuit can be connected with the fourth light-emitting signal line. The different groups of the first light-emitting control sub-circuit are connected with different light-emitting signal lines, so as to enable different first light-emitting control sub-circuits to be controlled by independent signals and ensure that different first light-emitting control sub-circuits perform shunt control on different light-emitting devices when being turned on.

[0172] An example structure of the light-emitting control sub-circuit is shown in FIG. 4. It is easy for those skilled in the art to understand that the implementation of the light-emitting control sub-circuit is not limited thereto.

[0173] FIG. 5 is an equivalent circuit diagram of the light-emitting control sub-circuit provided by an example embodiment. As shown in FIG. 5, in an example embodiment, the light-emitting control sub-circuit can include: a second light-emitting control sub-circuit and M groups of first light-emitting control sub-circuits, where M≥1.

[0174] In an example embodiment, M = K-1.

[0175] In an example embodiment, as shown in FIG. 5, the second light-emitting control sub-circuit is electrically connected with the fourth node N4, the second light-emitting signal line EM2, the second initial signal line Vinit2, the first reset signal line Reset1 and the first electrode of the first light-emitting device L1 respectively, and is configured to provide the signal of the fourth node N4 or the second initial signal line Vinit2 to the first electrode of the first light-emitting device L1 under the control of the signals of the second light-emitting signal line EM2 and the second initial signal line Vinit2; the jth group of first light-emitting control sub-circuits are electrically connected with the j+1th light-emitting signal line EMj+1, the first electrode of the first light-emitting device L1 and the first electrode of the jth light-emitting device Lj respectively, and are configured to connect the first electrode of the jth light-emitting device Lj and the first electrode of the first light-emitting device L1 under the control of the signal of the j+1th light-emitting signal line EMj+1.

[0176] In an example embodiment, as shown in FIG. 5, the second light-emitting control sub-circuit can include the sixth transistor T6 and the seventh transistor T7, and the jth group of first light-emitting control sub-circuits can include the eleventh transistor T11.

[0177] In an example embodiment, as shown in FIG. 5, the control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first electrode of the first light-emitting device L1; the control electrode of the seventh transistor T7 is electrically connected with the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected with the first electrode of the first light-emitting device L1, and the second electrode of the seventh transistor T7 is electrically connected with the second initial signal line Vinit2; for the jth group of first light-emitting control sub-circuits, the control electrode of the eleventh transistor T11 is electrically connected with the j+1th light-emitting signal line EMj+1, the first electrode of the eleventh transistor T11 is electrically connected with the first electrode of the first light-emitting device L1, and the second electrode of the eleventh transistor T11 is electrically connected with the first electrode of the jth light-emitting device Lj.

[0178] In an example embodiment of the present disclosure, when the sixth transistor T6 in the first group of first light-emitting control sub-circuits is turned on, the first light-emitting device L1 emits light, and the jth group of first light-emitting control sub-circuits selectively emit light through the turn-on or turn-off of the eleventh transistor T11 in the group.

[0179] In an example embodiment, the signals of different light-emitting signal lines are independent of each other within a frame time.

[0180] In the embodiments of the present disclosure, the first light-emitting control sub-circuits in different groups are connected to different light-emitting signal lines, that is, the sixth transistor in the first light-emitting control sub-circuit in the first group is connected to a different light-emitting signal line from the eleventh transistor in the first light-emitting control sub-circuit in the jth group, for example, the sixth transistor in the first light-emitting control sub-circuit in the first group can be connected to the second light-emitting signal line, and the eleventh transistor in the first light-emitting control sub-circuit in the second group can be connected to the third light-emitting signal line. The first light-emitting control sub-circuits in different groups are connected to different light-emitting signal lines, so that the first light-emitting control sub-circuits in different groups can be controlled by independent signals, and the first light-emitting control sub-circuits in different groups can be controlled to perform current sharing control on different light-emitting devices when the first light-emitting control sub-circuits in different groups are turned on.

[0181] An example structure of the light-emitting control sub-circuit is shown in FIG. 5. It is easy for those skilled in the art to understand that the implementation of the light-emitting control sub-circuit is not limited to this.

[0182] An example structure of the first control sub-circuit is shown in FIG. 6. As shown in FIG. 6, in an example embodiment, the first control sub-circuit can include a second transistor T2, a fourth transistor T4, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, and a second capacitor C2.

[0183] In an example embodiment, as shown in FIG. 6, the control electrode of the second transistor T2 is electrically connected to the control signal line AZ, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the ninth transistor T9 is electrically connected to the control signal line AZ, the first electrode of the ninth transistor T9 is electrically connected to the second node N2, and the second electrode of the ninth transistor T9 is electrically connected to the first power supply line VDD; the control electrode of the tenth transistor T10 is electrically connected to the first light-emitting signal line EM1, the first electrode of the tenth transistor T10 is electrically connected to the third node N3, and the second electrode of the tenth transistor T10 is electrically connected to the first reference signal line Vref1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the second node N2, and the second plate C12 of the first capacitor is electrically connected to the first node N1; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the third node N3, and the second plate C22 of the second capacitor is electrically connected to the second node N2.

[0184] An example structure of the first control sub-circuit is shown in FIG. 6. It is easy for those skilled in the art to understand that the implementation of the first control sub-circuit is not limited to this.

[0185] Fig. 7 is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment. As shown in Fig. 7, in an example embodiment, the second control sub-circuit can include a first transistor T1, a fifth transistor T5, and an eighth transistor T8.

[0186] In an example embodiment, as shown in Fig. 7, a control electrode of the first transistor T1 is electrically connected to a second reset signal line Reset2, a first electrode of the first transistor T1 is electrically connected to a fourth node N4, and a second electrode of the first transistor T1 is electrically connected to a first initial signal line Vinit1; a control electrode of the fifth transistor T5 is electrically connected to a first emitting signal line EM1, a first electrode of the fifth transistor T5 is electrically connected to a first power supply line VDD, and a second electrode of the fifth transistor T5 is electrically connected to a fifth node N5; a control electrode of the eighth transistor T8 is electrically connected to a first reset signal line Reset1, a first electrode of the eighth transistor T8 is electrically connected to the fifth node N5, and a second electrode of the eighth transistor T8 is electrically connected to a second reference signal line Vref2.

[0187] An example structure of the second control sub-circuit is shown in Fig. 7. It is easily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0188] Fig. 8 is an equivalent circuit diagram of a driving sub-circuit according to an example embodiment. As shown in Fig. 8, in an example embodiment, the driving sub-circuit can include a third transistor T3.

[0189] In an example embodiment, as shown in Fig. 8, a control electrode of the third transistor T3 is electrically connected to a first node N1, a first electrode of the third transistor T3 is electrically connected to a fifth node N5, and a second electrode of the third transistor T3 is electrically connected to a fourth node N4.

[0190] In an example embodiment, the third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines a driving current flowing between the fifth node N5 and the fourth node N4 according to a potential difference between its gate electrode (also the first node N1) and its first electrode (also the fifth node N5).

[0191] An example structure of the driving sub-circuit is shown in Fig. 8. It is easily understood by those skilled in the art that the implementation of the driving sub-circuit is not limited to this.

[0192] Figure 9 is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment. As shown in Figure 9, in an exemplary embodiment, the first control sub-circuit may include: a second transistor T2, a fourth transistor T4, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, and a second capacitor C2; the second control sub-circuit may include: a first transistor T1, a fifth transistor T5, and an eighth transistor T8; the driving sub-circuit may include: a third transistor T3; and the light emission control sub-circuit may include: K sixth transistors T6 and K seventh transistors T7, where K ≥ 2.

[0193] In an example embodiment, as shown in FIG. 9, the control electrode of the first transistor T1 is electrically connected with the second reset signal line Reset2, the first electrode of the first transistor T1 is electrically connected with the fourth node N4, and the second electrode of the first transistor T1 is electrically connected with the first initial signal line Vinit1; the control electrode of the second transistor T2 is electrically connected with the control signal line AZ, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the fifth node N5, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the third node N3; the control electrode of the fifth transistor T5 is electrically connected with the first emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the fifth node N5; the control electrode of the i-th sixth transistor is electrically connected with the i+1 emitting signal line, the second electrode is electrically connected with the first electrode of the i-th light emitting device, the first electrode is electrically connected with the fourth node, and 1≤i≤K; the control electrode of the i-th seventh transistor is electrically connected with the first reset signal line, the first electrode is electrically connected with the second initial signal line, and the second electrode is electrically connected with the first electrode of the i-th light emitting device; the control electrode of the eighth transistor T8 is electrically connected with the first reset signal line Reset1, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the second reference signal line Vref2; the control electrode of the ninth transistor T9 is electrically connected with the control signal line AZ, the first electrode of the ninth transistor T9 is electrically connected with the second node N2, and the second electrode of the ninth transistor T9 is electrically connected with the first power supply line VDD; the control electrode of the tenth transistor T10 is electrically connected with the first emitting signal line EM1, the first electrode of the tenth transistor T10 is electrically connected with the third node N3, and the second electrode of the tenth transistor T10 is electrically connected with the first reference signal line Vref1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first node N1; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the third node N3, and the second plate C22 of the second capacitor is electrically connected with the second node N2.

[0194] In an example embodiment, as shown in FIG. 9, the pixel driving circuit can be electrically connected with two light emitting devices, one of the sixth transistors T6 has its control electrode electrically connected with the second light emitting signal line EM2 and its second electrode electrically connected with the first electrode NL1 of the first light emitting device L1, and the other sixth transistor T6 has its control electrode electrically connected with the third light emitting signal line EM3 and its second electrode electrically connected with the first electrode NL2 of the second light emitting device L2, and each of the first electrodes of the sixth transistors T6 is electrically connected with the fourth node N4; each of the control electrodes of the seventh transistors T7 is electrically connected with the first reset signal line Reset1, and each of the first electrodes of the seventh transistors T7 is electrically connected with the second initial signal line Vinit2, and the second electrode of one of the seventh transistors T7 is electrically connected with the first electrode NL1 of the first light emitting device L1, and the second electrode of the other seventh transistor T7 is electrically connected with the first electrode NL2 of the second light emitting device L2.

[0195] In an example embodiment, as shown in FIG. 9, the second transistor T2 and the ninth transistor T9 can be N-type transistors, and at least one of the first transistor T1, the third transistor T3 to the eighth transistor T8, and the tenth transistor T10 can be a P-type transistor.

[0196] An example structure of the pixel driving circuit is shown in FIG. 9. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0197] FIG. 10 is a timing diagram of the pixel driving circuit provided in FIG. 9. The working process of the pixel driving circuit exemplified by FIG. 9 is described below to illustrate the example embodiments of the present disclosure, which can include:

[0198] In the first stage S1, the signal of the second reset signal line Reset2 is a low-level signal, and the signals of the first reset signal line Reset1, the scan signal line Gate, the control signal line AZ, the first light emitting signal line EM1 to the third light emitting signal line EM3 are all high-level signals. The signal of the second reset signal line Reset2 is a low-level signal, the first transistor T1 is turned on, and the signal of the first initial signal line Vinit1 is written to the fourth node N4. The signal of the control signal line AZ is a high-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the signal of the first power supply line VDD is written to the second node N2, and the signal of the fourth node N4 is written to the first node N1, which initializes the gate electrode (i.e., the first node N1) of the third transistor T3, for example, by emptying the pre-stored voltage inside it, and completes the initialization. At this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0199] In the second stage S2, the signals of the first reset signal line Reset1 and the control signal line AZ are low signals, and the signals of the second reset signal line Reset2, the scan signal line Gate, the first emitting signal line EM1 to the third emitting signal line EM3 are high signals. The signal of the first reset signal line Reset1 is a low signal, the eighth transistor T8 is turned on, the signal of the second reference signal line Vref2 is written to the fifth node N5, the fifth node N5 is initialized, and the charge of the fifth node N5 is cleared; the two seventh transistors T7 are turned on, the first electrode NL1 of the first light emitting device L1 is initialized, and the first electrode NL2 of the second light emitting device L2 is initialized. The first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the ninth transistor T9 and the tenth transistor T10 are turned off.

[0200] When the two seventh transistors T7 are turned on, the initial voltage of the second initial signal line Vinit2 is provided to the first electrode NL1 of the first light emitting device L1 and the first electrode NL2 of the second light emitting device L2, and the first electrode NL1 of the first light emitting device L1 and the first electrode NL2 of the second light emitting device L2 are initialized (reset), for example, the internal pre-stored voltage is emptied, the initialization is completed, and it is ensured that the first light emitting device L1 and the second light emitting device L2 do not emit light. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0201] In the third stage S3, the signal of the first emitting signal line EM1 is a low signal, the signals of the first reset signal line Reset1, the second reset signal line Reset2, the scan signal line Gate, the control signal line AZ, the second emitting signal line EM2 and the third emitting signal line EM3 are high signals. The signal of the first emitting signal line EM1 is a low signal, the fifth transistor T5 is turned on, the signal of the control signal line AZ is a high signal, the second transistor T2 and the ninth transistor T9 are turned on, and the signal of the first power supply end VDD is written to the fourth node N4 and the first node N1 through the turned-on fifth transistor T5 and the turned-on third transistor T3, until the voltage value V N1 of the signal of the first node N1 is V d +Vth (Vth is a negative value), V dVth is the power supply voltage output from the first power supply line VDD, and Vth is the threshold voltage of the third transistor T3. The tenth transistor T10 is turned on, and the signal from the first reference signal line Vref1 is written to the third node N3. The signal from the control signal line AZ is a high-level signal, the second transistor T2 and the ninth transistor T9 are turned on, and the signal from the first power supply line VDD is written to the second node N2. Meanwhile, the first transistor T1, the fourth transistor T4, the sixth transistors T6 through T8, and the tenth transistor T10 are turned off. During this stage, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0202] Phase 4 (S4): The scan signal line Gate is low, while the first reset signal line Reset1, the second reset signal line Reset2, the control signal line AZ, and the first light-emitting signal lines EM1 to EM3 are all high. With the scan signal line Gate low, the fourth transistor T4 is turned on, and the data voltage on the data signal line Data is written to the third node N3. The first transistor T1, the fifth transistors T5 to T8, and the tenth transistor T10 are turned off. During this phase, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0203] Phase 5 (S5): The signals of the first light-emitting signal line EM1 and the control signal line AZ are both low-level signals, while the signals of the first reset signal line Reset1, the second reset signal line Reset2, the scan signal line Gate, the second light-emitting signal line EM2, and the third light-emitting signal line EM3 are all high-level signals. With the first light-emitting signal line EM1 low-level, the fifth transistor T5 is turned on, and the signal of the first power supply terminal VDD is written to the fifth node N5. The tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written to the third node N3. Due to the signal jump at the third node N3, the signal at the second node N2 also jumps under the action of the second capacitor C2, and the voltage V at the second node N2... N2 =Vdata+V d -V f1 Vdata is the data voltage of the data signal line Data. d V is the voltage of the first power line VDD. f1 This is the voltage of the first reference signal line Vref1. Under the influence of the first capacitor C1, the signal at the first node N1 also changes, and the voltage Vref1 at the first node N1... N1 =V f1 -Vdata+V d +Vth. In this phase, transistors T1, T4, T6 through T9 are disconnected. During this stage, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0204] The sixth stage S6: the signals of the first reset signal line Reset1 and the control signal line AZ are low level signals, and the signals of the second reset signal line Reset2, the scan signal line Gate, the first emitting signal line EM1 to the third emitting signal line EM3 are high level signals. The signal of the first reset signal line Reset1 is a low level signal, the eighth transistor T8 is turned on, and the signal of the second reference signal line Vref2 is written into the fifth node N5; two seventh transistors T7 are turned on, the first electrode NL1 of the first light emitting device L1 is initialized, and the first electrode NL2 of the second light emitting device L2 is initialized. The first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the ninth transistor T9 and the tenth transistor T10 are turned off. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0205] The seventh stage S7: the signals of the control signal line AZ, the first emitting signal line EM1 to the third emitting signal line EM3 are low level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the scan signal line Gate are high level signals. The signal of the first emitting signal line EM1 is a low level signal, the tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written into the third node N3; the fifth transistor T5 is turned on, the signal of the second emitting signal line EM2 is a low level signal, and the power supply voltage output by the first power supply end VDD provides a driving voltage for the first electrode NL1 of the first light emitting device L1 through the turned-on fifth transistor T5, the turned-on third transistor T3 and one of the turned-on sixth transistors T6, so as to drive the first light emitting device L1 to emit light; the signal of the third emitting signal line EM3 is a low level signal, and the power supply voltage output by the first power supply end VDD provides a driving voltage for the first electrode NL2 of the second light emitting device L2 through the turned-on fifth transistor T5, the turned-on third transistor T3 and the other turned-on sixth transistor T6, so as to drive the second light emitting device L2 to emit light.

[0206] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode (that is, the first node N1) and the first electrode (that is, the fifth node N5). Since the voltage value V N1 =V d +Vth+V f1 -Vdata, the voltage value V N5 =V d of the fifth node N5, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[V d +Vth+Vf1 -Vdata-V d -Vth] 2 = K * (V f1 -Vdata) 2

[0207] wherein I is the driving current flowing through the third transistor T3, that is, the sum of the driving currents of the first light emitting device L1 and the second light emitting device L2, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, VDD is the power voltage output by the first power supply line VDD, Vref is the voltage of the first reference signal line Vref1, and Vdata-VDD-Vref. d f1

[0208] FIG. 11 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment. As shown in FIG. 11, in an exemplary embodiment, the first control sub-circuit includes the second transistor T2, the fourth transistor T4, the ninth transistor T9, the tenth transistor T10, the first capacitor C1 and the second capacitor C2; the second control sub-circuit includes the first transistor T1, the fifth transistor T5 and the eighth transistor T8; the driving sub-circuit includes the third transistor T3; and the light emitting control sub-circuit includes the sixth transistor T6, the seventh transistor T7, K-1 eleventh transistors T11 and K-1 twelfth transistors T12, K≥2.

[0209] ​​In an example embodiment, as shown in FIG. 11, the control electrode of the first transistor T1 is electrically connected with the second reset signal line Reset2, the first electrode of the first transistor T1 is electrically connected with the fourth node N4, and the second electrode of the first transistor T1 is electrically connected with the first initial signal line Vinit1; the control electrode of the second transistor T2 is electrically connected with the control signal line AZ, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the fifth node N5, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the third node N3; the control electrode of the fifth transistor T5 is electrically connected with the first emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected with the second emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the sixth node N6; the control electrode of the seventh transistor T7 is electrically connected with the third emitting signal line EM3, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first electrode NL1 of the first light emitting device L1; the control electrode of the eighth transistor T8 is electrically connected with the first reset signal line Reset1, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the second reference signal line Vref2; the control electrode of the ninth transistor T9 is electrically connected with the control signal line AZ, the first electrode of the ninth transistor T9 is electrically connected with the second node N2, and the second electrode of the ninth transistor T9 is electrically connected with the first power supply line VDD; the control electrode of the tenth transistor T10 is electrically connected with the first emitting signal line EM1, the first electrode of the tenth transistor T10 is electrically connected with the third node N3, and the second electrode of the tenth transistor T10 is electrically connected with the first reference signal line Vref1; the control electrode of the jth eleventh transistor is electrically connected with the j+2 emitting signal line, the first electrode is electrically connected with the sixth node, and the second electrode is electrically connected with the first electrode of the jth light emitting device, 2≤j≤K; the control electrode of the jth twelfth transistor is electrically connected with the first reset signal line, the first electrode is electrically connected with the first electrode of the jth light emitting device, and the second electrode is electrically connected with the second initial signal line; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first node N1.The second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the third node N3, and the second plate C22 of the second capacitor is electrically connected with the second node N2.

[0210] In an example embodiment, as shown in FIG. 11, the pixel driving circuit can be electrically connected with two light emitting devices, the control electrode of the eleventh transistor T11 is electrically connected with the fourth light emitting signal line EM4, the first electrode of the eleventh transistor T11 is electrically connected with the sixth node N6, and the second electrode of the eleventh transistor T11 is electrically connected with the first electrode NL2 of the second light emitting device L2; the control electrode of the twelfth transistor T12 is electrically connected with the first reset signal line Reset1, the first electrode of the twelfth transistor T12 is electrically connected with the first electrode NL2 of the second light emitting device L2, and the second electrode of the twelfth transistor T12 is electrically connected with the second initial signal line Vinit2.

[0211] In an example embodiment, as shown in FIG. 11, the second transistor T2 and the ninth transistor T9 can be N-type transistors; at least one of the first transistor T1, the third transistor T3 to the eighth transistor T8, and the tenth transistor T10 to the twelfth transistor T12 can be a P-type transistor.

[0212] An example structure of the pixel driving circuit is shown in FIG. 11. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0213] FIG. 12 is a timing diagram of the pixel driving circuit provided in FIG. 11. The working process of the pixel driving circuit shown in FIG. 11 is described below to illustrate the example embodiments of the present disclosure. The working process of the pixel driving circuit can include:

[0214] In the first stage S1, the signal of the second reset signal line Reset2 is a low-level signal, and the signals of the first reset signal line Reset1, the scan signal line Gate, the control signal line AZ, the first light emitting signal line EM1 to the fourth light emitting signal line EM4 are all high-level signals. The signal of the second reset signal line Reset2 is a low-level signal, the first transistor T1 is turned on, and the signal of the first initial signal line Vinit1 is written to the fourth node N4. The signal of the control signal line AZ is a high-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the signal of the first power supply line VDD is written to the second node N2, and the signal of the fourth node N4 is written to the first node N1. The gate electrode of the third transistor T3 (that is, the first node N1) is initialized, for example, the internal pre-stored voltage is emptied, and the initialization is completed. Among them, the fourth transistor T4 to the eighth transistor T8, the tenth transistor T10 to the twelfth transistor T12 are disconnected. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0215] The second stage S2: the signals of the first reset signal line Reset1 and the control signal line AZ are low level signals, and the signals of the second reset signal line Reset2, the scan signal line Gate, the first emitting signal line EM1 to the fourth emitting signal line EM4 are high level signals. The signal of the first reset signal line Reset1 is a low level signal, the eighth transistor T8 is turned on, the signal of the second reference signal line Vref2 is written to the fifth node N5, the fifth node N5 is initialized, and the charge of the fifth node N5 is cleared; the twelfth transistor T12 is turned on, and the signal of the second reference signal line Vinit2 is written to the first electrode NL2 of the second light emitting device L2, and the first electrode NL2 of the second light emitting device L2 is initialized. Wherein, the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the ninth transistor T9 to the eleventh transistor T11 are turned off.

[0216] When the twelfth transistor T12 is turned on, the initial voltage of the second initial signal line Vinit2 is provided to the first electrode NL2 of the second light emitting device L2, and the first electrode NL2 of the second light emitting device L2 is initialized (reset), for example: emptying the pre-stored voltage in its internal, completing initialization, and ensuring that the second light emitting device L2 does not emit light. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0217] The third stage S3: the signal of the first emitting signal line EM1 is a low level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the scan signal line Gate, the control signal line AZ, the second emitting signal line EM2 and the fourth emitting signal line EM4 are high level signals. The signal of the first emitting signal line EM1 is a low level signal, the fifth transistor T5 is turned on, and the signal of the first power supply end VDD is written to the fourth node N4 through the turned-on fifth transistor T5 and the turned-on third transistor T3, until the voltage value V N4 d +Vth, V d is the power supply voltage output by the first power supply line VDD, and Vth is the threshold voltage of the third transistor T3. The tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written to the third node N3. The signal of the control signal line AZ is a high level signal, the second transistor T2 and the ninth transistor T9 are turned on, the signal of the first power supply line VDD is written to the second node N2, the fourth node is in communication with the first node N1, and the voltage V N1 d ​​+Vth. During this phase, transistors T1, T4, T6 through T8, and T10 through T12 are disconnected. The first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0218] Phase 4 (S4): The scan signal line Gate is low, while the first reset signal line Reset1, the second reset signal line Reset2, the control signal line AZ, and the first to fourth light-emitting signal lines EM1 and EM4 are all high. With the scan signal line Gate low, the fourth transistor T4 is turned on, and the data voltage on the data signal line Data is written to the third node N3. Meanwhile, the first transistor T1, the fifth to eighth transistors T8, and the tenth to twelfth transistors T10 and T12 are turned off. During this phase, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0219] Phase 5 (S5): The signals of the first light-emitting signal line EM1 and the control signal line AZ are both low-level signals, while the signals of the first reset signal line Reset1, the second reset signal line Reset2, the scan signal line Gate, and the second to fourth light-emitting signal lines EM2 to EM4 are all high-level signals. With the first light-emitting signal line EM1 low-level, the fifth transistor T5 is turned on, and the signal at the first power supply terminal VDD is written to the fifth node N5. The tenth transistor T10 is turned on, and the signal at the first reference signal line Vref1 is written to the third node N3. Due to the signal jump at the third node N3, the signal at the second node N2 also jumps under the action of the second capacitor C2, and the voltage V at the second node N2... N2 =Vdata+V d -V f1 Vdata is the data voltage of the data signal line Data. d V is the voltage of the first power line VDD. f1 This is the voltage of the first reference signal line Vref1. Under the influence of the first capacitor C1, the signal at the first node N1 also changes, and the voltage Vref1 at the first node N1... N1 =V f1 -Vdata+V d +Vth. In this phase, transistors T1, T4, T6 through T9, T11, and T12 are disconnected. During this stage, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0220] In the sixth stage S6, the signals of the first reset signal line Reset1, the control signal line AZ, the third emission signal line EM3 and the fourth emission signal line EM4 are all low-level signals, and the signals of the second reset signal line Reset2, the scanning signal line Gate, the first emission signal line EM1 and the second emission signal line EM2 are all high-level signals. The signal of the first reset signal line Reset1 is a low-level signal, the eighth transistor T8 is turned on, the signal of the second reference signal line Vref2 is written to the fifth node N5, the twelfth transistor T12 is turned on, and the first electrode NL2 of the second light emitting device L2 is initialized; the third emission signal line EM3 is a low-level signal, the seventh transistor T7 is turned on, and the first electrode NL1 of the first light emitting device L1 is initialized; the fourth emission signal line EM4 is a low-level signal, the eleventh transistor T11 is turned on, and the first electrode NL1 of the first light emitting device L1 and the first electrode NL2 of the second light emitting device L2 are connected. The first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the ninth transistor T9 and the tenth transistor T10 are turned off. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0221] In the seventh stage S7, the signals of the control signal line AZ, the first emission signal line EM1 to the fourth emission signal line EM4 are all low-level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the scanning signal line Gate are all high-level signals. The signal of the first emission signal line EM1 is a low-level signal, the tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written to the third node N3; the fifth transistor T5 is turned on, the signals of the second emission signal line EM2 and the third emission signal line EM3 are low-level signals, and the power supply voltage output by the first power supply end VDD is provided to the first electrode NL1 of the first light emitting device L1 through the turned-on fifth transistor T5, the turned-on third transistor T3, the turned-on sixth transistor T6 and the turned-on seventh transistor T7 to drive the first light emitting device L1 to emit light; the signal of the fourth emission signal line EM4 is a low-level signal, and the power supply voltage output by the first power supply end VDD is provided to the first electrode NL2 of the second light emitting device L2 through the turned-on fifth transistor T5, the turned-on third transistor T3, the turned-on sixth transistor T6 and the turned-on eleventh transistor T11 to drive the second light emitting device L2 to emit light.

[0222] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode (that is, the first node N1) and the first electrode (that is, the fifth node N5). Since the voltage value V N1 = V d + Vth+ V f1Vdata, the voltage value V of the fifth node N5 N5 = V d Thus, the driving current of the third transistor T3 is: I = K*(Vgs-Vth) 2 = K*[V d +Vth+V f1 -Vdata-V d -Vth] 2 = K*(V f1 -Vdata) 2

[0223] wherein I is the driving current flowing through the third transistor T3, that is, the sum of the driving currents of the first light emitting device L1 and the second light emitting device L2, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, V d is the power voltage output by the first power supply line VDD, V f1 is the voltage of the first reference signal line Vref1.

[0224] FIG. 13 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment. As shown in FIG. 13, in an exemplary embodiment, the first control sub-circuit includes: a second transistor T2, a fourth transistor T4, a ninth transistor T9, a tenth transistor T10, a first capacitor C1 and a second capacitor C2; the second control sub-circuit includes: a first transistor T1, a fifth transistor T5 and an eighth transistor T8; the driving sub-circuit includes: a third transistor T3; and the light emitting control sub-circuit includes: a seventh transistor T7, K-1 eleventh transistors T11 and K-1 twelfth transistors T12.

[0225] In an example embodiment, as shown in FIG. 13, the control electrode of the first transistor T1 is electrically connected with the second reset signal line Reset2, the first electrode of the first transistor T1 is electrically connected with the fourth node N4, and the second electrode of the first transistor T1 is electrically connected with the first initial signal line Vinit1; the control electrode of the second transistor T2 is electrically connected with the control signal line AZ, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the fifth node N5, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the third node N3; the control electrode of the fifth transistor T5 is electrically connected with the first emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the third emitting signal line EM3, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the first electrode NL1 of the first light emitting device L1; the control electrode of the eighth transistor T8 is electrically connected with the first reset signal line Reset1, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the second reference signal line Vref2; the control electrode of the ninth transistor T9 is electrically connected with the control signal line AZ, the first electrode of the ninth transistor T9 is electrically connected with the second node N2, and the second electrode of the ninth transistor T9 is electrically connected with the first power supply line VDD; the control electrode of the tenth transistor T10 is electrically connected with the first emitting signal line EM1, the first electrode of the tenth transistor T10 is electrically connected with the third node N3, and the second electrode of the tenth transistor T10 is electrically connected with the first reference signal line Vref1; the control electrode of the jth eleventh transistor is electrically connected with the j+2 emitting signal line, the first electrode is electrically connected with the fourth node, and the second electrode is electrically connected with the first electrode of the jth light emitting device, 2≤j≤K; the control electrode of the jth twelfth transistor is electrically connected with the third reset signal line, the first electrode is electrically connected with the first electrode of the jth light emitting device, and the second electrode is electrically connected with the second initial signal line; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first node N1; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the third node N3, and the second plate C22 of the second capacitor is electrically connected with the second node N2.

[0226] In an example embodiment, as shown in FIG. 13, the pixel driving circuit can be electrically connected with two light emitting devices, the control electrode of the eleventh transistor T11 is electrically connected with the fourth light emitting signal line EM4, the first electrode of the eleventh transistor T11 is electrically connected with the fourth node N4, and the second electrode of the eleventh transistor T11 is electrically connected with the first electrode NL2 of the second light emitting device L2; the control electrode of the twelfth transistor T12 is electrically connected with the third reset signal line Reset3, the first electrode of the twelfth transistor T12 is electrically connected with the first electrode NL2 of the second light emitting device L2, and the second electrode of the twelfth transistor T12 is electrically connected with the second initial signal line Vinit2.

[0227] In an example embodiment, as shown in FIG. 13, the second transistor T2 and the ninth transistor T9 can be N-type transistors; at least one of the first transistor T1, the third transistor T3 to the eighth transistor T8, and the tenth transistor T10 to the twelfth transistor T12 can be a P-type transistor.

[0228] An example structure of the pixel driving circuit is shown in FIG. 13. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited thereto.

[0229] FIG. 14 is a timing diagram of the pixel driving circuit provided in FIG. 13. The working process of the pixel driving circuit exemplified by FIG. 13 is described below to illustrate the example embodiments of the present disclosure. The working process of the pixel driving circuit can include:

[0230] In the first stage S1, the signal of the second reset signal line Reset2 is a low-level signal, and the signals of the first reset signal line Reset1, the scan signal line Gate, the control signal line AZ, the first light emitting signal line EM1, the third light emitting signal line EM3, and the fourth light emitting signal line EM4 are all high-level signals. The signal of the second reset signal line Reset2 is a low-level signal, the first transistor T1 is turned on, and the signal of the first initial signal line Vinit1 is written to the fourth node N4. The signal of the control signal line AZ is a high-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the signal of the first power supply line VDD is written to the second node N2, the signal of the fourth node N4 is written to the first node N1, the gate electrode (i.e., the first node N1) of the third transistor T3 is initialized, for example, the internal pre-stored voltage is emptied, and the initialization is completed. Among them, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 to the twelfth transistor T12 are turned off. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0231] The signal of the first reset signal line Reset1, the signal of the third reset signal line Reset3 and the signal of the control signal line AZ are all low level signals, and the signal of the second reset signal line Reset2, the signal of the scan signal line Gate, the signal of the first emitting signal line EM1, the signal of the third emitting signal line EM3 and the signal of the fourth emitting signal line EM4 are all high level signals. The signal of the first reset signal line Reset1 is a low level signal, the eighth transistor T8 is turned on, the signal of the second reference signal line Vref2 is written to the fifth node N5, the fifth node N5 is initialized, and the charge of the fifth node N5 is cleared; the signal of the third reset signal line Reset3 is a low level signal, the twelfth transistor T12 is turned on, and the signal of the second reference signal line Vinit2 is written to the first electrode NL2 of the second light emitting device L2 to initialize the first electrode NL2 of the second light emitting device L2. The first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5, the ninth transistor T9 to the eleventh transistor T11 are turned off.

[0232] When the twelfth transistor T12 is turned on, the initial voltage of the second initial signal line Vinit2 is provided to the first electrode NL2 of the second light emitting device L2 to initialize (reset) the first electrode NL2 of the second light emitting device L2, for example, to empty the pre-stored voltage in the first electrode NL2, complete the initialization, and ensure that the second light emitting device L2 does not emit light. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0233] In the third stage S3, the signal of the first emitting signal line EM1 is a low level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the scan signal line Gate, the control signal line AZ, the third emitting signal line EM3 and the fourth emitting signal line EM4 are all high level signals. The signal of the first emitting signal line EM1 is a low level signal, the fifth transistor T5 is turned on, and the signal of the first power supply end VDD is written to the fourth node N4 through the turned-on fifth transistor T5 and the turned-on third transistor T3, until the voltage value V N4 of the signal of the fourth node N4 is V d +Vth, V d is the power supply voltage output by the first power supply line VDD, and Vth is the threshold voltage of the third transistor T3. The tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written to the third node N3. The signal of the control signal line AZ is a high level signal, the second transistor T2 and the ninth transistor T9 are turned on, the signal of the first power supply line VDD is written to the second node N2, the fourth node is in communication with the first node N1, and the voltage V N1 of the first node N1 becomes V d+Vth. In this phase, transistors T1, T4, T5, T7, T8, T10 through T12 are off. During this stage, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0234] Phase 4 (S4): The scan signal line Gate is low, while the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the control signal line AZ, the first light-emitting signal line EM1, the third light-emitting signal line EM3, and the fourth light-emitting signal line EM4 are all high. The scan signal line Gate is low, the fourth transistor T4 is turned on, and the data voltage on the data signal line Data is written to the third node N3. Specifically, the first transistor T1, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 through the twelfth transistor T12 are turned off. During this phase, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0235] Phase 5 (S5): The signals of the first light-emitting signal line EM1 and the control signal line AZ are both low-level signals. The signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the scan signal line Gate, the third light-emitting signal line EM3, and the fourth light-emitting signal line EM4 are all high-level signals. With the first light-emitting signal line EM1 low-level, the fifth transistor T5 is turned on, and the signal of the first power supply terminal VDD is written to the fifth node N5. The tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written to the third node N3. Due to the signal jump at the third node N3, the signal at the second node N2 also jumps under the action of the second capacitor C2, and the voltage V at the second node N2... N2 =Vdata+V d -V f1 Vdata is the data voltage of the data signal line Data. d V is the voltage of the first power line VDD. f1 This is the voltage of the first reference signal line Vref1. Under the influence of the first capacitor C1, the signal at the first node N1 also changes, and the voltage Vref1 at the first node N1... N1 =V f1 -Vdata+V d +Vth. In this phase, transistors T1, T4, T7 through T9, T11, and T12 are disconnected. During this stage, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0236] In the sixth stage S6, signals of the first reset signal line Reset1, the third reset signal line Reset3, the control signal line AZ, the third emission signal line EM3 and the fourth emission signal line EM4 are low level signals, and signals of the second reset signal line Reset2, the scanning signal line Gate and the first emission signal line EM1 are high level signals. The signal of the first reset signal line Reset1 is a low level signal, the eighth transistor T8 is turned on, and the signal of the second reference signal line Vref2 is written into the fifth node N5; the signal of the third reset signal line Reset3 is a low level signal, the twelfth transistor T12 is turned on, and the first electrode NL2 of the second light emitting device L2 is initialized; the third emission signal line EM3 is a low level signal, the seventh transistor T7 is turned on, and the first electrode NL1 of the first light emitting device L1 is initialized; the fourth emission signal line EM4 is a low level signal, the eleventh transistor T11 is turned on, and the first electrode NL1 of the first light emitting device L1 and the first electrode NL2 of the second light emitting device L2 are connected. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the ninth transistor T9 and the tenth transistor T10 are turned off. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0237] In the seventh stage S7, signals of the control signal line AZ, the first emission signal line EM1, the third emission signal line EM3 and the fourth emission signal line EM4 are low level signals, and signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3 and the scanning signal line Gate are high level signals. The signal of the first emission signal line EM1 is a low level signal, the tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written into the third node N3; the fifth transistor T5 is turned on, the signal of the third emission signal line EM3 is a low level signal, and the power supply voltage output by the first power supply end VDD provides a driving voltage for the first electrode NL1 of the first light emitting device L1 through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on seventh transistor T7, so as to drive the first light emitting device L1 to emit light; the signal of the fourth emission signal line EM4 is a low level signal, and the power supply voltage output by the first power supply end VDD provides a driving voltage for the first electrode NL2 of the second light emitting device L2 through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on eleventh transistor T11, so as to drive the second light emitting device L2 to emit light.

[0238] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode (i.e., the first node N1) and the first electrode (i.e., the fifth node N5). Since the voltage value V N1 = V d + Vth+ Vf1 Vdata, the voltage value V of the fifth node N5 N5 = V d Thus, the driving current of the third transistor T3 is: I = K*(Vgs-Vth) 2 = K*[V d +Vth+V f1 -Vdata-V d -Vth] 2 = K*(V f1 -Vdata) 2

[0239] wherein I is the driving current flowing through the third transistor T3, that is, the sum of the driving currents of the first light emitting device L1 and the second light emitting device L2, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, V d is the power voltage output by the first power supply line VDD, V f1 is the voltage of the first reference signal line Vref1.

[0240] FIG. 15 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment. As shown in FIG. 15, in an exemplary embodiment, the first control sub-circuit includes: a second transistor T2, a fourth transistor T4, a ninth transistor T9, a tenth transistor T10, a first capacitor C1 and a second capacitor C2; the second control sub-circuit includes: a first transistor T1, a fifth transistor T5 and an eighth transistor T8; the driving sub-circuit includes: a third transistor T3; and the light emitting control sub-circuit includes: a sixth transistor T6, a seventh transistor T7 and K-1 eleventh transistors T11, K≥2.

[0241] In an example embodiment, as shown in FIG. 15, the control electrode of the first transistor T1 is electrically connected with the second reset signal line Reset2, the first electrode of the first transistor T1 is electrically connected with the fourth node N4, and the second electrode of the first transistor T1 is electrically connected with the first initial signal line Vinit1; the control electrode of the second transistor T2 is electrically connected with the control signal line AZ, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the fifth node N5, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the third node N3; the control electrode of the fifth transistor T5 is electrically connected with the first emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected with the second emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first electrode NL1 of the first light emitting device L1; the control electrode of the seventh transistor T7 is electrically connected with the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected with the first electrode NL1 of the first light emitting device L1, and the second electrode of the seventh transistor T7 is electrically connected with the second initial signal line Vinit2; the control electrode of the eighth transistor T8 is electrically connected with the first reset signal line Reset1, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the second reference signal line Vref2; the control electrode of the ninth transistor T9 is electrically connected with the control signal line AZ, the first electrode of the ninth transistor T9 is electrically connected with the second node N2, and the second electrode of the ninth transistor T9 is electrically connected with the first power supply line VDD; the control electrode of the tenth transistor T10 is electrically connected with the first emitting signal line EM1, the first electrode of the tenth transistor T10 is electrically connected with the third node N3, and the second electrode of the tenth transistor T10 is electrically connected with the first reference signal line Vref1; the control electrode of the jth eleventh transistor is electrically connected with the j+1 emitting signal line, the first electrode is electrically connected with the first electrode of the first light emitting device, and the second electrode is electrically connected with the first electrode of the jth light emitting device, 2≤j≤K; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first node N1; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the third node N3, and the second plate C22 of the second capacitor is electrically connected with the second node N2.

[0242] In an example embodiment, as shown in FIG. 15, the pixel driving circuit can be electrically connected with two light emitting devices, the control electrode of the eleventh transistor T11 is electrically connected with the third light emitting signal line EM3, the first electrode of the eleventh transistor T11 is electrically connected with the first electrode NL1 of the first light emitting device L1, and the second electrode of the eleventh transistor T11 is electrically connected with the first electrode NL2 of the second light emitting device L2.

[0243] In an example embodiment, as shown in FIG. 15, the second transistor T2 and the ninth transistor T9 can be N-type transistors, and at least one of the first transistor T1, the third transistor T3 to the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 can be a P-type transistor.

[0244] An example structure of the pixel driving circuit is shown in FIG. 15. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited thereto.

[0245] FIG. 16 is a timing diagram of the pixel driving circuit provided in FIG. 15. The working process of the pixel driving circuit exemplified by FIG. 15 is described below to illustrate the example embodiments of the present disclosure, which can include:

[0246] In the first stage S1, the signal of the second reset signal line Reset2 is a low-level signal, and the signals of the first reset signal line Reset1, the scanning signal line Gate, the control signal line AZ, the first light emitting signal line EM1 to the third light emitting signal line EM3 are all high-level signals. The signal of the second reset signal line Reset2 is a low-level signal, the first transistor T1 is turned on, and the signal of the first initial signal line Vinit1 is written to the fourth node N4. The signal of the control signal line AZ is a high-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the signal of the first power supply line VDD is written to the second node N2, and the signal of the fourth node N4 is written to the first node N1, which initializes the gate electrode (i.e., the first node N1) of the third transistor T3, for example, to empty the internal pre-stored voltage, and completes the initialization. Among them, the fourth transistor T4 to the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 are disconnected. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0247] In the second stage S2, signals of the first reset signal line Reset1 and the control signal line AZ are low level signals, and signals of the second reset signal line Reset2, the scan signal line Gate, the first emitting signal line EM1 to the third emitting signal line EM3 are high level signals. The signal of the first reset signal line Reset1 is a low level signal, the eighth transistor T8 is turned on, the signal of the second reference signal line Vref2 is written to the fifth node N5, the fifth node N5 is initialized, and the charge of the fifth node N5 is cleared; the seventh transistor T7 is turned on, and the signal of the second initial signal line Vinit2 is written to the first electrode NL1 of the first light emitting device L1, and the first electrode NL1 of the first light emitting device L1 is initialized. Wherein, the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the ninth transistor T9 to the eleventh transistor T11 are turned off.

[0248] When the seventh transistor T7 is turned on, the initial voltage of the second initial signal line Vinit2 is provided to the first electrode NL1 of the first light emitting device L1, and the first electrode NL1 of the first light emitting device L1 is initialized (reset), for example: emptying the pre-stored voltage in the internal, completing the initialization, and ensuring that the first light emitting device L1 does not emit light. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0249] In the third stage S3, the signal of the first emitting signal line EM1 is a low level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the scan signal line Gate, the control signal line AZ, the second emitting signal line EM2 and the third emitting signal line EM3 are high level signals. The signal of the first emitting signal line EM1 is a low level signal, the fifth transistor T5 is turned on, and the signal of the first power supply end VDD is written to the fourth node N4 through the turned-on fifth transistor T5 and the turned-on third transistor T3, until the voltage value V N4 of the signal of the fourth node is V d +Vth, V d is the power supply voltage output by the first power supply line VDD, and Vth is the threshold voltage of the third transistor T3. The tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written to the third node N3. The signal of the control signal line AZ is a high level signal, the second transistor T2 and the ninth transistor T9 are turned on, the signal of the first power supply line VDD is written to the second node N2, the fourth node is in communication with the first node N1, and the voltage V N1 of the first node N1 becomes V d +Vth. Wherein, the first transistor T1, the fourth transistor T4, the sixth transistor T6 to the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 are turned off. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0250] Phase 4 (S4): The scan signal line Gate is low, while the first reset signal line Reset1, the second reset signal line Reset2, the control signal line AZ, and the first to third light-emitting signal lines EM1 and EM3 are all high. With the scan signal line Gate low, the fourth transistor T4 is turned on, and the data voltage on the data signal line Data is written to the third node N3. Meanwhile, the first transistor T1, the fifth to eighth transistors T8, the tenth transistor T10, and the eleventh transistor T11 are turned off. During this phase, the first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0251] Phase 5 (S5): The signals of the first light-emitting signal line EM1 and the control signal line AZ are both low-level signals, while the signals of the first reset signal line Reset1, the second reset signal line Reset2, the scan signal line Gate, the second light-emitting signal line EM2, and the third light-emitting signal line EM3 are all high-level signals. With the first light-emitting signal line EM1 low-level, the fifth transistor T5 is turned on, and the signal of the first power supply terminal VDD is written to the fifth node N5. The tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written to the third node N3. Due to the signal jump at the third node N3, the signal at the second node N2 also jumps under the action of the second capacitor C2, and the voltage V at the second node N2... N2 =Vdata+V d -V f1 Vdata is the data voltage of the data signal line Data. d V represents the voltage of the first power line VDD. f1 This is the voltage of the first reference signal line Vref1. Under the influence of the first capacitor C1, the signal at the first node N1 also changes, and the voltage Vref1 at the first node N1... N1 =V f1 -Vdata+V d +Vth. During this phase, transistors T1, T4, T6 through T9, and T11 are off. The first light-emitting device L1 and the second light-emitting device L2 do not emit light.

[0252] The sixth stage S6: the signals of the first reset signal line Reset1, the control signal line AZ and the third emitting signal line EM3 are low level signals, and the signals of the second reset signal line Reset2, the scanning signal line Gate, the first emitting signal line EM1 and the second emitting signal line EM2 are high level signals. The signal of the first reset signal line Reset1 is a low level signal, the eighth transistor T8 is turned on, the signal of the second reference signal line Vref2 is written into the fifth node N5, the seventh transistor T7 is turned on, the signal of the second reference signal line Vinit2 is written into the first electrode NL1 of the first light emitting device L1, and the first electrode NL1 of the first light emitting device L1 is initialized; the third emitting signal line EM3 is a low level signal, the eleventh transistor T11 is turned on, and the first electrode NL1 of the first light emitting device L1 and the first electrode NL2 of the second light emitting device L2 are connected. The first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the ninth transistor T9 and the tenth transistor T10 are turned off. In this stage, the first light emitting device L1 and the second light emitting device L2 do not emit light.

[0253] The seventh stage S7: the signals of the control signal line AZ, the first emitting signal line EM1 to the third emitting signal line EM3 are low level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the scanning signal line Gate are high level signals. The signal of the first emitting signal line EM1 is a low level signal, the tenth transistor T10 is turned on, and the signal of the first reference signal line Vref1 is written into the third node N3; the fifth transistor T5 is turned on, the signal of the second emitting signal line EM2 is a low level signal, and the power supply voltage output by the first power supply end VDD is provided to the first electrode NL1 of the first light emitting device L1 through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6 to drive the first light emitting device L1 to emit light; the signal of the third emitting signal line EM3 is a low level signal, and the power supply voltage output by the first power supply end VDD is provided to the first electrode NL2 of the second light emitting device L2 through the turned-on fifth transistor T5, the turned-on third transistor T3, the turned-on sixth transistor T6 and the turned-on eleventh transistor T11 to drive the second light emitting device L2 to emit light.

[0254] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode (that is, the first node N1) and the first electrode (that is, the fifth node N5). Since the voltage value V N1 = V d + Vth+ V f1 -Vdata, the voltage value V N5 = V dThus, the driving current of the third transistor T3 is: I = K * (Vgs-Vth) 2 = K * [V d + Vth + V f1 -Vdata-V d -Vth] 2 = K * (V f1 -Vdata) 2

[0255] Wherein, I is the driving current flowing through the third transistor T3, that is, the sum of the driving currents of the first light emitting device L1 and the second light emitting device L2, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, V d is the power voltage output by the first power supply line VDD, and V f1 is the voltage of the first reference signal line Vref1.

[0256] The display device provided by the embodiment of the present disclosure also includes a pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here.

[0257] The embodiment of the present disclosure also provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method of the pixel driving circuit can include:

[0258] The first control sub-circuit provides a signal to the first node under the control of signals of the first reference signal line, the first light emitting signal line, the scan signal line, the data signal line, the control signal line, the first power supply line, and the fourth node;

[0259] The second control sub-circuit provides a signal of the first power supply line or the second reference signal line to the fifth node and provides a signal of the first initial signal line to the fourth node under the control of signals of the first light emitting signal line, the first reset signal line, and the second reset signal line;

[0260] The driving sub-circuit provides a driving signal to the fourth node under the control of signals of the first node and the fifth node;

[0261] The light emitting control sub-circuit provides a signal of the fourth node or the second initial signal line to the first electrode of the at least two light emitting devices under the control of signals of the first reset signal line and the at least two light emitting signal lines.

[0262] The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here.

[0263] The drawings in the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0264] For clarity, the thickness and dimensions of the layers or microstructures are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0265] Although the embodiments disclosed in the present disclosure are as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

A pixel driving circuit electrically connected with at least two light emitting devices, the light emitting devices comprising a first electrode and a second electrode, the pixel driving circuit comprising: The first control sub-circuit, the second control sub-circuit, the driving sub-circuit and the light-emitting control sub-circuit; The first control sub-circuit is electrically connected with a first reference signal line, a first light-emitting signal line, a scan signal line, a data signal line, a control signal line, a first power supply line, a first node and a fourth node respectively, and is configured to provide a signal to the first node under the control of signals of the first reference signal line, the first light-emitting signal line, the scan signal line, the data signal line, the control signal line, the first power supply line and the fourth node; The second control sub-circuit is electrically connected with the first power supply line, the first light-emitting signal line, a second reference signal line, a first reset signal line, a second reset signal line, a first initial signal line, a fifth node and the fourth node respectively, and is configured to provide a signal of the first power supply line or the second reference signal line to the fifth node and a signal of the first initial signal line to the fourth node under the control of signals of the first light-emitting signal line, the first reset signal line and the second reset signal line; The driving sub-circuit is electrically connected with the first node, the fourth node and the fifth node respectively, and is configured to provide a driving signal to the fourth node under the control of signals of the first node and the fifth node; The light-emitting control sub-circuit is electrically connected with the fourth node, a second initial signal line, the first reset signal line, at least two light-emitting signal lines and at least two light-emitting devices respectively, and is configured to provide a signal of the fourth node or the second initial signal line to a first electrode of the at least two light-emitting devices under the control of signals of the first reset signal line and the at least two light-emitting signal lines. The pixel driving circuit according to claim 1, wherein The light-emitting control sub-circuit comprises K groups of first light-emitting control sub-circuits, and K is greater than or equal to 2. The i th group of first light-emitting control sub-circuits is electrically connected with the fourth node, an i+1 th light-emitting signal line, the second initial signal line, the first reset signal line and a first electrode of an i th light-emitting device respectively, and is configured to provide a signal of the fourth node or the second initial signal line to the first electrode of the i th light-emitting device under the control of signals of the i+1 th light-emitting signal line and the first reset signal line, wherein 1≤i≤K. The pixel driving circuit according to claim 2, wherein At least one group of first light-emitting control sub-circuits comprises a sixth transistor and a seventh transistor. For the i th group of first light-emitting control sub-circuits, a control electrode of the sixth transistor is electrically connected with the i+1 th light-emitting signal line, a first electrode of the sixth transistor is electrically connected with the fourth node, and a second electrode of the sixth transistor is electrically connected with the first electrode of the i th light-emitting device; a control electrode of the seventh transistor is electrically connected with the first reset signal line, a first electrode of the seventh transistor is electrically connected with the second initial signal line, and a second electrode of the seventh transistor is electrically connected with the first electrode of the i th light-emitting device. The pixel driving circuit according to claim 1, wherein The light-emitting control sub-circuit comprises K groups of first light-emitting control sub-circuits, and K is greater than or equal to 2. The first group of first light-emitting control sub-circuits is electrically connected with the fourth node, a third light-emitting signal line and a first electrode of a first light-emitting device respectively, and is configured to provide a signal of the fourth node to the first electrode of the first light-emitting device under the control of a signal of the third light-emitting signal line. The jth group of first light emitting control sub-circuits are electrically connected with the fourth node, the j+2th light emitting signal line, one of the first reset signal line and the third reset signal line, the second initial signal line and the first electrode of the jth light emitting device respectively, and are configured to provide the signal of the fourth node or the second initial signal line to the first electrode of the jth light emitting device under the control of the signals of the j+2th light emitting signal line and one of the first reset signal line and the third reset signal line, 2≤j≤K. The pixel driving circuit according to claim 4, wherein The first group of first light emitting control sub-circuits comprise a seventh transistor, the jth group of first light emitting control sub-circuits comprise an eleventh transistor and a twelfth transistor; the control electrode of the seventh transistor is electrically connected with the third light emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light emitting device; for the jth group of first light emitting control sub-circuits, the control electrode of the eleventh transistor is electrically connected with the j+2th light emitting signal line, the first electrode of the eleventh transistor is electrically connected with the fourth node, the second electrode of the eleventh transistor is electrically connected with the first electrode of the jth light emitting device, the control electrode of the twelfth transistor is electrically connected with the third reset signal line, the first electrode of the twelfth transistor is electrically connected with the first electrode of the jth light emitting device, and the second electrode of the twelfth transistor is electrically connected with the second initial signal line. The pixel driving circuit according to claim 4 or 5, wherein The light emitting control sub-circuit further comprises a second light emitting control sub-circuit, and the K groups of first light emitting control sub-circuits are electrically connected with the fourth node through the second light emitting control sub-circuit. The second light emitting control sub-circuit is electrically connected with the second light emitting signal line, the fourth node and the sixth node respectively, and is configured to provide the signal of the fourth node to the sixth node under the control of the signal of the second light emitting signal line. The K groups of first light emitting control sub-circuits are electrically connected with the second light emitting control sub-circuit through the sixth node. The pixel driving circuit according to claim 6, wherein The second light emitting control sub-circuit comprises a sixth transistor, the first group of first light emitting control sub-circuits comprise a seventh transistor, and the jth group of first light emitting control sub-circuits comprise an eleventh transistor and a twelfth transistor. the control electrode of the sixth transistor is electrically connected with the second light emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the sixth node; the control electrode of the seventh transistor is electrically connected with the third light emitting signal line, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light emitting device; for the jth group of first light emitting control sub-circuits, the control electrode of the eleventh transistor is electrically connected with the j+2th light emitting signal line, the first electrode of the eleventh transistor is electrically connected with the sixth node, the second electrode of the eleventh transistor is electrically connected with the first electrode of the jth light emitting device, the control electrode of the twelfth transistor is electrically connected with the first reset signal line, the first electrode of the twelfth transistor is electrically connected with the first electrode of the jth light emitting device, and the second electrode of the twelfth transistor is electrically connected with the second initial signal line. The pixel driving circuit according to claim 1, wherein The light emitting control sub-circuit comprises a second light emitting control sub-circuit and M groups of first light emitting control sub-circuits, M≥1. The second light-emitting control sub-circuit is electrically connected with the fourth node, the second light-emitting signal line, the second initial signal line, the first reset signal line and the first electrode of the first light-emitting device, and is configured to provide the signal of the fourth node or the second initial signal line to the first electrode of the first light-emitting device under the control of the signals of the second light-emitting signal line and the second initial signal line; The jth group of first light-emitting control sub-circuits are electrically connected with the j+1th light-emitting signal line, the first electrode of the first light-emitting device and the first electrode of the jth light-emitting device, and are configured to connect the first electrode of the jth light-emitting device and the first electrode of the first light-emitting device under the control of the signal of the j+1th light-emitting signal line. The pixel driving circuit according to claim 8, wherein The second light-emitting control sub-circuit comprises a sixth transistor and a seventh transistor, and the jth group of first light-emitting control sub-circuits comprise an eleventh transistor; The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first electrode of the first light-emitting device; The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the first electrode of the first light-emitting device, and the second electrode of the seventh transistor is electrically connected with the second initial signal line; For the jth group of first light-emitting control sub-circuits, the control electrode of the eleventh transistor is electrically connected with the j+1th light-emitting signal line, the first electrode of the eleventh transistor is electrically connected with the first electrode of the first light-emitting device, and the second electrode of the eleventh transistor is electrically connected with the first electrode of the jth light-emitting device. The pixel driving circuit according to claim 1, wherein The first control sub-circuit comprises a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; The control electrode of the second transistor is electrically connected with the control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node; The control electrode of the fourth transistor is electrically connected with the scanning signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node; The control electrode of the ninth transistor is electrically connected with the control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first power supply line; The control electrode of the tenth transistor is electrically connected with the first light-emitting signal line, the first electrode of the tenth transistor is electrically connected with the third node, and the second electrode of the tenth transistor is electrically connected with the first reference signal line; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node. The pixel driving circuit according to claim 1, wherein The second control sub-circuit comprises a first transistor, a fifth transistor and an eighth transistor; The control electrode of the first transistor is electrically connected with the second reset signal line, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first initial signal line; A control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, a first electrode of the fifth transistor is electrically connected with the first power supply line, and a second electrode of the fifth transistor is electrically connected with the fifth node; A control electrode of the eighth transistor is electrically connected with the first reset signal line, a first electrode of the eighth transistor is electrically connected with the fifth node, and a second electrode of the eighth transistor is electrically connected with the second reference signal line. The pixel driving circuit according to claim 1, wherein The first control sub-circuit comprises a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit comprises a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit comprises a third transistor; and the light-emitting control sub-circuit comprises K sixth transistors and K seventh transistors, K≥2; A control electrode of the first transistor is electrically connected with the second reset signal line, a first electrode of the first transistor is electrically connected with the fourth node, and a second electrode of the first transistor is electrically connected with the first initial signal line; A control electrode of the second transistor is electrically connected with the control signal line, a first electrode of the second transistor is electrically connected with the fourth node, and a second electrode of the second transistor is electrically connected with the first node; A control electrode of the third transistor is electrically connected with the first node, a first electrode of the third transistor is electrically connected with the fifth node, and a second electrode of the third transistor is electrically connected with the fourth node; A control electrode of the fourth transistor is electrically connected with the scanning signal line, a first electrode of the fourth transistor is electrically connected with the data signal line, and a second electrode of the fourth transistor is electrically connected with the third node; A control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, a first electrode of the fifth transistor is electrically connected with the first power supply line, and a second electrode of the fifth transistor is electrically connected with the fifth node; A control electrode of the i th sixth transistor is electrically connected with the i+1 light-emitting signal line, a second electrode of the i th sixth transistor is electrically connected with a first electrode of the i th light-emitting device, and a first electrode of the i th sixth transistor is electrically connected with the fourth node, 1≤i≤K; A control electrode of the i th seventh transistor is electrically connected with the first reset signal line, a first electrode of the i th seventh transistor is electrically connected with the second initial signal line, and a second electrode of the i th seventh transistor is electrically connected with a first electrode of the i th light-emitting device; A control electrode of the eighth transistor is electrically connected with the first reset signal line, a first electrode of the eighth transistor is electrically connected with the fifth node, and a second electrode of the eighth transistor is electrically connected with the second reference signal line. A control electrode of the ninth transistor is electrically connected with the control signal line, a first electrode of the ninth transistor is electrically connected with the second node, and a second electrode of the ninth transistor is electrically connected with the first power supply line; A control electrode of the tenth transistor is electrically connected with the first light-emitting signal line, a first electrode of the tenth transistor is electrically connected with the third node, and a second electrode of the tenth transistor is electrically connected with the first reference signal line; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node. The pixel driving circuit according to claim 1, wherein The first control sub-circuit comprises a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit comprises a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit comprises a third transistor; and the light-emitting control sub-circuit comprises a sixth transistor, a seventh transistor, K-1 eleventh transistors and K-1 twelfth transistors, wherein K is greater than or equal to 2. The control electrode of the first transistor is electrically connected with the second reset signal line, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first initial signal line. The control electrode of the second transistor is electrically connected with the control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node. The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the fifth node, and the second electrode of the third transistor is electrically connected with the fourth node. The control electrode of the fourth transistor is electrically connected with the scanning signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node. The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the fifth node. The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the sixth node. The control electrode of the seventh transistor is electrically connected with the third light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light-emitting device. The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the second reference signal line. The control electrode of the ninth transistor is electrically connected with the control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first power supply line. The control electrode of the tenth transistor is electrically connected with the first light-emitting signal line, the first electrode of the tenth transistor is electrically connected with the third node, and the second electrode of the tenth transistor is electrically connected with the first reference signal line. The control electrode of the jth eleventh transistor is electrically connected with the j+2 light-emitting signal line, the first electrode is electrically connected with the sixth node, and the second electrode is electrically connected with the first electrode of the jth light-emitting device, wherein 2≤j≤K. The control electrode of the jth twelfth transistor is electrically connected with the first reset signal line, the first electrode is electrically connected with the first electrode of the jth light-emitting device, and the second electrode is electrically connected with the second initial signal line. The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node. The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node. The pixel driving circuit according to claim 1, wherein The first control sub-circuit includes a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit includes a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit includes a third transistor; and the light emitting control sub-circuit includes a seventh transistor, K-1 eleventh transistors and K-1 twelfth transistors, K≥2. The control electrode of the first transistor is electrically connected with the second reset signal line, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first initial signal line. The control electrode of the second transistor is electrically connected with the control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node. The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the fifth node, and the second electrode of the third transistor is electrically connected with the fourth node. The control electrode of the fourth transistor is electrically connected with the scanning signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node. The control electrode of the fifth transistor is electrically connected with the first light emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the fifth node. The control electrode of the seventh transistor is electrically connected with the third light emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the first light emitting device. The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the second reference signal line. The control electrode of the ninth transistor is electrically connected with the control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first power supply line. The control electrode of the tenth transistor is electrically connected with the first light emitting signal line, the first electrode of the tenth transistor is electrically connected with the third node, and the second electrode of the tenth transistor is electrically connected with the first reference signal line. The control electrode of the jth eleventh transistor is electrically connected with the j+2 light emitting signal line, the first electrode is electrically connected with the fourth node, and the second electrode is electrically connected with the first electrode of the jth light emitting device, 2≤j≤K. The control electrode of the jth twelfth transistor is electrically connected with the third reset signal line, the first electrode is electrically connected with the first electrode of the jth light emitting device, and the second electrode is electrically connected with the second initial signal line. The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node. The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node. The pixel driving circuit according to claim 1, wherein The first control sub-circuit comprises a second transistor, a fourth transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor; the second control sub-circuit comprises a first transistor, a fifth transistor and an eighth transistor; the driving sub-circuit comprises a third transistor; and the light-emitting control sub-circuit comprises a sixth transistor, a seventh transistor and K-1 eleventh transistors, wherein K is greater than or equal to 2. The control electrode of the first transistor is electrically connected with the second reset signal line, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first initial signal line. The control electrode of the second transistor is electrically connected with the control signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the first node. The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the fifth node, and the second electrode of the third transistor is electrically connected with the fourth node. The control electrode of the fourth transistor is electrically connected with the scanning signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node. The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the fifth node. The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first electrode of the first light-emitting device. The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the first electrode of the first light-emitting device, and the second electrode of the seventh transistor is electrically connected with the second initial signal line. The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the second reference signal line. The control electrode of the ninth transistor is electrically connected with the control signal line, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first power supply line. The control electrode of the tenth transistor is electrically connected with the first light-emitting signal line, the first electrode of the tenth transistor is electrically connected with the third node, and the second electrode of the tenth transistor is electrically connected with the first reference signal line. The control electrode of the jth eleventh transistor is electrically connected with the j+1 light-emitting signal line, the first electrode of the jth eleventh transistor is electrically connected with the first electrode of the first light-emitting device, and the second electrode of the jth eleventh transistor is electrically connected with the first electrode of the jth light-emitting device, wherein 2≤j≤K. The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first node. The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the second node. The pixel driving circuit according to any one of claims 12 to 15, wherein The second transistor and the ninth transistor are N-type transistors; at least one transistor in the first transistor, the third transistor to the eighth transistor, and the tenth transistor to the twelfth transistor is a P-type transistor. A display device comprising: The pixel driving circuit according to any one of claims 1 to 16. A driving method of a pixel driving circuit configured to drive the pixel driving circuit according to any one of claims 1 to 16, the method comprising: The first control sub-circuit provides a signal to the first node under the control of signals of the first reference signal line, the first light-emitting signal line, the scan signal line, the data signal line, the control signal line, the first power supply line and the fourth node; The second control sub-circuit provides a signal of the first power supply line or the second reference signal line to the fifth node and a signal of the first initial signal line to the fourth node under the control of signals of the first light-emitting signal line, the first reset signal line and the second reset signal line; The driving sub-circuit provides a driving signal to the fourth node under the control of signals of the first node and the fifth node; The light-emitting control sub-circuit provides a signal of the fourth node or the second initial signal line to the first electrode of the at least two light-emitting devices under the control of signals of the first reset signal line and the at least two light-emitting signal lines.

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