Pixel circuit, pixel driving method, and display device

Abstract

The present application provides a pixel circuit, a pixel driving method, and a display device. The pixel circuit comprises a light-emitting element, a driving circuit, a data writing circuit, and a control circuit; a display cycle comprises a data writing phase, a conduction phase, and a turn-off phase; the control circuit, in the conduction phase, controls a first node to be connected to a fourth node, and in the turn-off phase, controls the fourth node to be disconnected from the third node; alternatively, the control circuit, in the conduction phase, controls the third node to be connected to the fourth node, and in the turn-off phase, controls the first node to be disconnected from the fourth node; the start time of the turn-off phase is set after the end of the data writing phase, the start time of the turn-off phase is set before the end time of the conduction phase, and the end time of the turn-off phase is set after the end time of the conduction phase. The present application can reduce the voltage difference of the first node under different threshold voltage characteristics of compensation transistors.

Description

Pixel circuits, pixel driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] In related technologies, to save power, existing partial refresh (HRD) technology is applied to OLED (organic light-emitting diode) products. This technology generally uses HRD GOA (Gate On Array, a gate driving circuit located on the array substrate) units to control the number of times data is written to the first node (the first node is electrically connected to the gate of the driving transistor) in different rows of pixel circuits in the AA area (effective display area), thereby achieving the goal of reducing power consumption.

[0003] Under HRD functionality, the waveforms of the compensation control signals output by the HRD unit differ between the high-frequency and low-frequency regions. This results in variations in the stress duration experienced by the compensation transistors used for compensation control in the high-frequency and low-frequency regions, leading to different degrees of characteristic deviation in the compensation transistors. The compensation transistors are oxide transistors, and their threshold voltage becomes positively biased when their gates are forward-biased. Because the high-frequency region has more refresh cycles, the positive potential of the compensation control signal is applied more frequently and for a longer duration, resulting in a larger positive bias of the compensation transistor's threshold voltage. Conversely, the low-frequency region has fewer refresh cycles, resulting in fewer positive potential applications of the compensation control signal and a shorter duration, leading to a smaller positive bias of the compensation transistor's threshold voltage. Therefore, the threshold voltages of the oxide transistors used for compensation control will differ between the high-frequency and low-frequency regions. When the threshold voltage of the compensation transistor is positively biased, the potential of the first node will increase, reducing the brightness of the light-emitting element. Because the threshold voltage of the compensation transistor is more forward biased in the high-frequency region than in the low-frequency region, the threshold voltage of the compensation transistor is more forward biased, resulting in a brightness difference between the high-frequency and low-frequency regions. This leads to low brightness in the high-frequency region and high brightness in the low-frequency region, affecting image quality.

[0004] Summary of the Invention

[0005] In one aspect, embodiments of this disclosure provide a pixel circuit, including a light-emitting element, a driving circuit, a data writing circuit, and a control circuit; the display cycle includes a data writing phase, a connectivity phase, and a shutdown phase; the connectivity phase includes the data writing phase;

[0006] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0007] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line to the second node under the control of the write control signal provided by the write control terminal during the data writing stage.

[0008] The control circuit is electrically connected to the compensation control terminal, the on / off control terminal, the first node, the third node, and the fourth node, respectively.

[0009] The control circuit is used to control the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal during the connection phase, and to control the disconnection between the fourth node and the third node under the control of the on / off control signal provided by the on / off control terminal during the shutdown phase; or, the control circuit is used to control the connection between the third node and the fourth node under the control of the compensation control signal during the connection phase, and to control the disconnection between the first node and the fourth node under the control of the on / off control signal during the shutdown phase.

[0010] The start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase.

[0011] In at least one embodiment of this disclosure, the control circuit includes a compensation control circuit and an on / off control circuit;

[0012] The compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the compensation control signal during the connection phase.

[0013] The on / off control circuit is electrically connected to the on / off control terminal, the fourth node, and the third node, respectively, and is used to control the fourth node and the third node to disconnect during the off phase under the control of the on / off control signal.

[0014] In at least one embodiment of this disclosure, the control circuit includes a compensation control circuit and an on / off control circuit;

[0015] The compensation control circuit is electrically connected to the compensation control terminal, the third node, and the fourth node respectively, and is used to control the connection between the third node and the fourth node under the control of the compensation control signal during the connection phase.

[0016] The on / off control circuit is electrically connected to the on / off control terminal, the first node, and the fourth node, respectively, and is used to control the first node and the fourth node to disconnect during the off phase under the control of the on / off control signal.

[0017] The pixel circuit described in at least one embodiment of this disclosure includes a first initialization circuit; the display cycle further includes a first setting phase; the connectivity phase includes the first setting phase; the first setting phase is set before the data writing phase;

[0018] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the second node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first reset control signal provided by the first reset control terminal during the first setting phase.

[0019] In at least one embodiment of this disclosure, the display cycle further includes a first setting phase; the connectivity phase includes the first setting phase; the first setting phase is set before the data writing phase;

[0020] The on / off control circuit is used to control the fourth node to disconnect from the third node under the control of the on / off control signal during the first set phase; or, the on / off control circuit is used to control the first node to disconnect from the fourth node under the control of the on / off control signal during the first set phase.

[0021] The pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit; the display cycle further includes a reset phase, and the connection phase includes the reset phase;

[0022] The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the third node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second reset control signal provided by the second reset control terminal during the reset phase.

[0023] The on / off control circuit is used during the reset phase, under the control of the on / off control signal, to control the connection between the fourth node and the third node; or, the on / off control circuit is used during the reset phase, under the control of the on / off control signal, to control the connection between the first node and the fourth node.

[0024] The pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit; the display cycle further includes a second setting phase; the connection phase includes the second setting phase, the second setting phase is set after the first setting phase, and the second setting phase is set before the data writing phase;

[0025] The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage into the third node under the control of the second reset control signal provided by the second reset control terminal during the second setting phase;

[0026] The on / off control circuit is used to control the connection between the fourth node and the third node under the control of the on / off control signal during the second set phase; or, the on / off control circuit is used to control the connection between the first node and the fourth node under the control of the on / off control signal during the second set phase.

[0027] In at least one embodiment of this disclosure, the display cycle further includes a third setting phase; the third setting phase is disposed after the data writing phase; the third setting phase is disposed before the light emission phase;

[0028] The first initialization circuit is used to write the first initial voltage into the second node under the control of the first reset control signal during the third setting phase.

[0029] The compensation control circuit is used, during the third set phase, under the control of the compensation control signal, to control the first node and the fourth node to disconnect; and / or, the on / off control circuit is used, during the third set phase, under the control of the on / off control signal, to control the fourth node and the third node to disconnect; or...

[0030] The compensation control circuit is used to control the third node and the fourth node to disconnect during the third setting phase, under the control of the compensation control signal; and / or, the on / off control circuit is used to control the first node and the fourth node to disconnect during the third setting phase, under the control of the on / off control signal.

[0031] In at least one embodiment of this disclosure, the first reset control terminal is the nth level first reset control terminal, and the on / off control terminal is the nxth level first reset control terminal;

[0032] The nth-level first reset control signal provided by the nth-level first reset control terminal and the nx-level first reset control signal provided by the nx-level first reset control terminal are provided by the same drive module;

[0033] n and x are positive integers.

[0034] In at least one embodiment of this disclosure, the second reset control terminal is the nth level second reset control terminal, and the on / off control terminal is the n+yth level second reset control terminal;

[0035] The nth-level second reset control signal provided by the nth-level second reset control terminal and the n+y-level second reset control signal provided by the n+y-level second reset control terminal are provided by the same drive module;

[0036] n and y are positive integers.

[0037] In at least one embodiment of this disclosure, the transistor included in the on / off control circuit is a p-type transistor.

[0038] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit, and an energy storage circuit; the display cycle includes a light-emitting phase; the light-emitting phase is disposed after the connection phase and the light-emitting phase is disposed after the shutdown phase;

[0039] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting stage.

[0040] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal during the light-emitting stage;

[0041] The second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0042] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0043] The pixel circuit described in at least one embodiment of this disclosure further includes a third initialization circuit;

[0044] The third initialization circuit is electrically connected to the third reset control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal during the first set phase and the third set phase.

[0045] In at least one embodiment of this disclosure, the first reset control terminal and the third reset control terminal are the same control terminal.

[0046] In at least one embodiment of this disclosure, the driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the data writing circuit includes a second transistor, and the on / off control circuit includes a third transistor.

[0047] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0048] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0049] The gate of the second transistor is electrically connected to the write control terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the second node.

[0050] The gate of the third transistor is electrically connected to the on / off control terminal, the first terminal of the third transistor is electrically connected to the fourth node, and the second terminal of the third transistor is electrically connected to the third node.

[0051] In at least one embodiment of this disclosure, the driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the data writing circuit includes a second transistor, and the on / off control circuit includes a third transistor.

[0052] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0053] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node.

[0054] The gate of the second transistor is electrically connected to the write control terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the second node.

[0055] The gate of the third transistor is electrically connected to the on / off control terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the fourth node.

[0056] In at least one embodiment of this disclosure, the first initialization circuit includes a fourth transistor;

[0057] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.

[0058] In at least one embodiment of this disclosure, the second initialization circuit includes a fifth transistor;

[0059] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

[0060] In at least one embodiment of this disclosure, the first light-emitting control circuit includes a sixth transistor; the second light-emitting control circuit includes a seventh transistor; and the energy storage circuit includes a storage capacitor.

[0061] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0062] The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the third node, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0063] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the power supply voltage terminal.

[0064] In at least one embodiment of this disclosure, the third initialization circuit includes an eighth transistor;

[0065] The gate of the eighth transistor is electrically connected to the third reset control terminal, the first terminal of the eighth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0066] In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, wherein the display cycle includes a data writing phase, a connectivity phase, and a shutdown phase; the connectivity phase includes the data writing phase; the start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase; the pixel driving method includes:

[0067] During the data writing phase, the data writing circuit, under the control of the write control signal, writes the data voltage to the second node;

[0068] The pixel driving method further includes: during the connection phase, the control circuit, under the control of a compensation control signal, controls the connection between the first node and the fourth node; during the shutdown phase, the control circuit, under the control of an on / off control signal, controls the disconnection between the fourth node and the third node; or...

[0069] The pixel driving method further includes: in the connection phase, the control circuit controls the connection between the third node and the third node under the control of the compensation control signal; in the shutdown phase, the control circuit controls the disconnection between the first node and the fourth node under the control of the on / off control signal.

[0070] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0071] Figure 1A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] Figure 1B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0073] Figure 1C is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] Figure 2A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] Figure 2B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] Figure 3A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] Figure 3B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] Figure 4A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] Figure 4B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] Figure 5A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] Figure 5B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] Figure 6A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] Figure 6B is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] Figure 7A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 6A;

[0085] Figure 7B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 6A;

[0086] Figure 8 is a waveform diagram of the potential of the first node when at least one embodiment of the pixel circuit shown in Figure 6A is operating in the low-frequency region and the high-frequency region.

[0087] Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] Figure 10 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9;

[0089] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11;

[0091] Figure 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0092] Figure 14 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 13. Detailed Implementation

[0093] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0094] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0095] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0096] The pixel circuit described in this embodiment includes a light-emitting element, a driving circuit, a data writing circuit, and a control circuit; the display cycle includes a data writing phase, a connectivity phase, and a shutdown phase; the connectivity phase includes the data writing phase;

[0097] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0098] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line to the second node under the control of the write control signal provided by the write control terminal during the data writing stage.

[0099] The control circuit is electrically connected to the compensation control terminal, the on / off control terminal, the first node, the third node, and the fourth node, respectively.

[0100] The control circuit is used to control the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal during the connection phase, and to control the disconnection between the fourth node and the third node under the control of the on / off control signal provided by the on / off control terminal during the shutdown phase; or, the control circuit is used to control the connection between the third node and the fourth node under the control of the compensation control signal during the connection phase, and to control the disconnection between the first node and the fourth node under the control of the on / off control signal during the shutdown phase.

[0101] The start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase.

[0102] In related technologies, to save power, existing partial refresh (HRD) technology is applied to OLED (organic light-emitting diode) products. This technology generally uses HRD GOA (Gate On Array, a gate driving circuit located on the array substrate) units to control the number of times data is written to the first node (the first node is electrically connected to the gate of the driving transistor) in different rows of pixel circuits in the AA area (effective display area), thereby achieving the goal of reducing power consumption.

[0103] Under HRD functionality, the waveforms of the compensation control signals output by the HRD unit differ between the high-frequency and low-frequency regions. This results in variations in the stress duration experienced by the compensation transistors used for compensation control in the high-frequency and low-frequency regions, leading to different degrees of characteristic deviation in the compensation transistors. The compensation transistors are oxide transistors, and their threshold voltage becomes positively biased when their gates are forward-biased. Because the high-frequency region has more refresh cycles, the positive potential of the compensation control signal is applied more frequently and for a longer duration, resulting in a larger positive bias of the compensation transistor's threshold voltage. Conversely, the low-frequency region has fewer refresh cycles, resulting in fewer positive potential applications of the compensation control signal and a shorter duration, leading to a smaller positive bias of the compensation transistor's threshold voltage. Therefore, the threshold voltages of the oxide transistors used for compensation control will differ between the high-frequency and low-frequency regions. When the threshold voltage of the compensation transistor is positively biased, the potential of the first node will increase, reducing the brightness of the light-emitting element. Because the threshold voltage of the compensation transistor is more forward biased in the high-frequency region than in the low-frequency region, the threshold voltage of the compensation transistor is more forward biased, resulting in a brightness difference between the high-frequency and low-frequency regions. This leads to low brightness in the high-frequency region and high brightness in the low-frequency region, affecting image quality.

[0104] Based on this, a control circuit is provided between the first node and the third node in the pixel circuit of the present disclosure embodiment. The control circuit operates under the control of the compensation control signal and the on / off control signal.

[0105] During the shutdown phase, under the control of the on / off control signal, the control circuit controls the fourth node to disconnect from the third node. The start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connection phase, and the end time of the shutdown phase is set after the end time of the connection phase. This is so that when the control circuit controls the first node to disconnect from the fourth node under the control of the compensation control signal, the current path between the first node and the third node is blocked, and the circuit path between the first node and the second node is blocked, reducing the voltage difference of the first node under the threshold voltage characteristics of different compensation transistors (the compensation transistors are the transistors included in the compensation control circuit); or...

[0106] During the shutdown phase, the control circuit, under the control of the on / off control signal, controls the disconnection between the first node and the fourth node. The start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connection phase, and the end time of the shutdown phase is set after the end time of the connection phase. This is so that when the control circuit, under the control of the compensation control signal, controls the disconnection between the third node and the fourth node, it blocks the current path between the first node and the third node, blocks the circuit path between the first node and the second node, and reduces the voltage difference of the first node under the threshold voltage characteristics of different compensation transistors (the compensation transistors are the transistors included in the compensation control circuit).

[0107] As shown in Figure 1A, the pixel circuit of this embodiment includes a light-emitting element E1, a driving circuit 10, a data writing circuit 12, and a control circuit 20; the display cycle includes a data writing phase, a connection phase, and a shutdown phase; the connection phase includes the data writing phase;

[0108] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0109] The data writing circuit 12 is electrically connected to the write control terminal GSTV, the data line DL and the second node N2 respectively, and is used to write the data voltage provided by the data line DL to the second node N2 under the control of the write control signal provided by the write control terminal GSTV during the data writing stage.

[0110] The control circuit 20 is electrically connected to the compensation control terminal NSTV, the on / off control terminal ST, the first node N1, the third node N3, and the fourth node N4, respectively. During the connection phase, under the control of the compensation control signal provided by the compensation control terminal NSTV, the control circuit 20 controls the connection between the first node N1 and the fourth node N4; during the off phase, under the control of the on / off control signal provided by the on / off control terminal ST, the control circuit 20 controls the disconnection between the fourth node N4 and the third node N3. Alternatively, during the connection phase, the control circuit 20 controls the connection between the third node N3 and the fourth node N4 under the control of the compensation control signal; during the off phase, under the control of the on / off control signal, the control circuit 20 controls the disconnection between the first node N4 and the fourth node N4.

[0111] The start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase.

[0112] In at least one embodiment of this disclosure, the control circuit includes a compensation control circuit and an on / off control circuit;

[0113] The compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the compensation control signal during the connection phase.

[0114] The on / off control circuit is electrically connected to the on / off control terminal, the fourth node, and the third node, respectively, and is used to control the fourth node and the third node to disconnect during the off phase under the control of the on / off control signal.

[0115] As shown in Figure 1B, based on at least one embodiment of the pixel circuit shown in Figure 1A, the control circuit includes a compensation control circuit 11 and an on / off control circuit 13.

[0116] The compensation control circuit 11 is electrically connected to the compensation control terminal NSTV, the first node N1 and the fourth node N4 respectively, and is used to control the connection between the first node N1 and the fourth node N4 under the control of the compensation control signal provided by the compensation control terminal NSTV during the connection phase.

[0117] The on / off control circuit 13 is electrically connected to the on / off control terminal ST, the fourth node N4, and the third node N3, respectively, and is used to control the fourth node N4 and the third node N3 to disconnect during the off phase under the control of the on / off control signal provided by the on / off control terminal ST.

[0118] The pixel circuit embodiment shown in Figure 1B of this disclosure, when in operation, displays a cycle including a data writing phase, a connectivity phase, and a shutdown phase; the connectivity phase includes the data writing phase; the start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase.

[0119] During the connection phase, the compensation control circuit 11 controls the connection between the first node N1 and the fourth node N4 under the control of the compensation control signal;

[0120] During the data writing phase, the data writing circuit 12 writes the data voltage to the second node N2 under the control of the writing control signal;

[0121] During the shutdown phase, the on / off control circuit 13 controls the fourth node N4 and the third node N3 to disconnect under the control of the on / off control signal.

[0122] The pixel circuit described in this embodiment includes an on / off control circuit between the first node and the third node, in addition to the compensation control circuit. During the off phase, the on / off control circuit, under the control of the on / off control signal, controls the fourth node to disconnect from the third node. The start time of the off phase is set after the end of the data writing phase, the start time of the off phase is set before the end time of the connection phase, and the end time of the off phase is set after the end time of the connection phase. This is to ensure that when the compensation control circuit controls the disconnection between the first node and the fourth node, the current path between the first node and the third node is blocked, and the circuit path between the first node and the second node is blocked, reducing the voltage difference of the first node under the threshold voltage characteristics of different compensation transistors (the compensation transistors are the transistors included in the compensation control circuit).

[0123] Since the transistors included in the on / off control circuit are not transistors controlled by the HRD unit, the on / off control signals provided by the on / off control terminal have the same frequency in both the high-frequency and low-frequency regions. Therefore, there is no difference in the threshold voltage of the transistors included in the on / off control circuit between the high-frequency and low-frequency regions.

[0124] In at least one embodiment of this disclosure, the control circuit includes a compensation control circuit and an on / off control circuit;

[0125] The compensation control circuit is electrically connected to the compensation control terminal, the third node, and the fourth node respectively, and is used to control the connection between the third node and the fourth node under the control of the compensation control signal during the connection phase.

[0126] The on / off control circuit is electrically connected to the on / off control terminal, the first node, and the fourth node, respectively, and is used to control the first node and the fourth node to disconnect during the off phase under the control of the on / off control signal.

[0127] As shown in FIG1C, based on at least one embodiment of the pixel circuit shown in FIG1A, the control circuit includes a compensation control circuit 11 and an on / off control circuit 13.

[0128] The compensation control circuit 11 is electrically connected to the compensation control terminal NSTV, the fourth node N4 and the third node N3 respectively, and is used to control the connection between the fourth node N4 and the third node N3 under the control of the compensation control signal provided by the compensation control terminal NSTV during the connection phase.

[0129] The on / off control circuit 13 is electrically connected to the on / off control terminal ST, the first node N1 and the fourth node N4 respectively, and is used to control the first node N1 and the fourth node N4 to disconnect during the off phase under the control of the on / off control signal provided by the on / off control terminal ST.

[0130] The pixel circuit embodiment shown in FIG1C of this disclosure, when in operation, displays a cycle including a data writing phase, a connectivity phase, and a shutdown phase; the connectivity phase includes the data writing phase; the start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase.

[0131] During the connection phase, the compensation control circuit 11 controls the connection between the third node N3 and the fourth node N4 under the control of the compensation control signal;

[0132] During the data writing phase, the data writing circuit 12 writes the data voltage to the second node N2 under the control of the writing control signal;

[0133] During the shutdown phase, the on / off control circuit 13 controls the fourth node N4 to disconnect from the first node N1 under the control of the on / off control signal.

[0134] The pixel circuit described in this embodiment includes an on / off control circuit between the first node and the third node, in addition to the compensation control circuit. During the off phase, the on / off control circuit, under the control of the on / off control signal, controls the fourth node to disconnect from the first node. The start time of the off phase is set after the end of the data writing phase, the start time of the off phase is set before the end time of the connection phase, and the end time of the off phase is set after the end time of the connection phase. This is to ensure that when the compensation control circuit controls the disconnection between the third node and the fourth node, the current path between the first node and the third node is blocked, and the circuit path between the first node and the second node is blocked, reducing the voltage difference of the first node under the threshold voltage characteristics of different compensation transistors (the compensation transistors are the transistors included in the compensation control circuit).

[0135] Since the transistors included in the on / off control circuit are not transistors controlled by the HRD unit, the on / off control signals provided by the on / off control terminal have the same frequency in both the high-frequency and low-frequency regions. Therefore, there is no difference in the threshold voltage of the transistors included in the on / off control circuit between the high-frequency and low-frequency regions.

[0136] The pixel circuit described in at least one embodiment of this disclosure includes a first initialization circuit; the display cycle further includes a first setting phase; the connectivity phase includes the first setting phase; the first setting phase is set before the data writing phase;

[0137] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the second node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first reset control signal provided by the first reset control terminal during the first setting phase.

[0138] In a specific implementation, the pixel circuit may further include a first initialization circuit. In the first setting phase, under the control of the first reset control signal, the first initialization circuit writes the first initial voltage to the second node so that the driving transistor included in the driving circuit is in a negative bias state, thereby improving FFR (first frame brightness difference) and afterimage phenomenon. The first setting phase may be included in the connection phase and may be set before the data writing phase.

[0139] As shown in Figure 2A, based on at least one embodiment of the pixel circuit shown in Figure 1B, the pixel circuit of at least one embodiment of this disclosure includes a first initialization circuit 21; the display cycle further includes a first setting phase; the connection phase includes the first setting phase; the first setting phase is set before the data writing phase;

[0140] The first initialization circuit 21 is electrically connected to the first reset control terminal RSTH, the first initial voltage terminal I1 and the second node N2 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first reset control signal provided by the first reset control terminal RSTH during the first setting phase.

[0141] As shown in Figure 2B, based on at least one embodiment of the pixel circuit shown in Figure 1C, the pixel circuit of at least one embodiment of this disclosure includes a first initialization circuit 21; the display cycle further includes a first setting phase; the connection phase includes the first setting phase; the first setting phase is set before the data writing phase;

[0142] The first initialization circuit 21 is electrically connected to the first reset control terminal RSTH, the first initial voltage terminal I1 and the second node N2 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first reset control signal provided by the first reset control terminal RSTH during the first setting phase.

[0143] In at least one embodiment of this disclosure, the display cycle further includes a first setting phase; the connectivity phase includes the first setting phase; the first setting phase is set before the data writing phase;

[0144] The on / off control circuit is used to control the fourth node to disconnect from the third node under the control of the on / off control signal during the first set phase; or, the on / off control circuit is used to control the first node to disconnect from the fourth node under the control of the on / off control signal during the first set phase.

[0145] In specific implementation, during the first setting phase, the on / off control circuit, under the control of the on / off control signal, controls the fourth node to disconnect from the third node, thereby controlling the first node to disconnect from the third node; or,

[0146] During the first setting phase, the on / off control circuit, under the control of the on / off control signal, controls the fourth node to disconnect from the first node, thereby controlling the first node to disconnect from the third node.

[0147] The pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit; the display cycle further includes a reset phase, and the connection phase includes the reset phase;

[0148] The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the third node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second reset control signal provided by the second reset control terminal during the reset phase.

[0149] The on / off control circuit is used during the reset phase, under the control of the on / off control signal, to control the connection between the fourth node and the third node; or, the on / off control circuit is used during the reset phase, under the control of the on / off control signal, to control the connection between the first node and the fourth node.

[0150] In a specific implementation, the pixel circuit may further include a second initialization circuit.

[0151] During the reset phase, the second initialization circuit, under the control of the second reset control signal, writes the second initial voltage to the third node; the on / off control circuit controls the connection between the fourth node and the third node; and the compensation control circuit, under the control of the compensation control signal, controls the connection between the first node and the fourth node, so as to write the second initial voltage to the first node, thereby initializing the potential of the first node and the potential of the third node; or...

[0152] During the reset phase, the second initialization circuit, under the control of the second reset control signal, writes the second initial voltage into the third node. The on / off control circuit controls the connection between the fourth node and the first node. The compensation control circuit, under the control of the compensation control signal, controls the connection between the third node and the fourth node to write the second initial voltage into the first node, thereby initializing the potential of the first node and the potential of the third node.

[0153] The pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit; the display cycle further includes a second setting phase; the connection phase includes the second setting phase, the second setting phase is set after the first setting phase, and the second setting phase is set before the data writing phase;

[0154] The second initialization circuit is used to write the second initial voltage into the third node under the control of the second reset control signal during the second set phase.

[0155] The on / off control circuit is used to control the connection between the fourth node and the third node under the control of the on / off control signal during the second set phase; or, the on / off control circuit is used to control the connection between the first node and the fourth node under the control of the on / off control signal during the second set phase.

[0156] In a specific implementation, the pixel circuit may further include a second initialization circuit.

[0157] In the second setting phase, under the control of the second reset control signal, the second initialization circuit writes the second initial voltage to the third node; under the control of the on / off control signal, the on / off control circuit controls the connection between the fourth node and the third node; and under the control of the compensation control signal, the compensation control circuit controls the connection between the first node and the fourth node, so as to write the second initial voltage to the first node and initialize the potential of the first node and the potential of the third node; or...

[0158] In the second setting phase, the second initialization circuit, under the control of the second reset control signal, writes the second initial voltage into the third node. The on / off control circuit, under the control of the on / off control signal, controls the fourth node to connect with the first node. The compensation control circuit, under the control of the compensation control signal, controls the third node to connect with the fourth node, so as to write the second initial voltage into the first node and initialize the potential of the first node and the potential of the third node.

[0159] In at least one embodiment of this disclosure, the display cycle further includes a third setting phase; the third setting phase is disposed after the data writing phase; the third setting phase is disposed before the light emission phase;

[0160] The first initialization circuit is used to write the first initial voltage into the second node under the control of the first reset control signal during the third setting phase.

[0161] The compensation control circuit is used, during the third set phase, under the control of the compensation control signal, to control the first node and the fourth node to disconnect; and / or, the on / off control circuit is used, during the third set phase, under the control of the on / off control signal, to control the fourth node and the third node to disconnect; or...

[0162] The compensation control circuit is used to control the third node and the fourth node to disconnect during the third setting phase, under the control of the compensation control signal; and / or, the on / off control circuit is used to control the first node and the fourth node to disconnect during the third setting phase, under the control of the on / off control signal.

[0163] In specific implementation, after the data writing stage and before the light emission stage, the display cycle may also include a third setting stage. In the third setting stage, under the control of the first reset control signal, the first initialization circuit writes the first initial voltage to the second node, and the compensation control circuit and / or on / off control circuit control the first node to disconnect from the third node, so that the driving transistor included in the driving circuit is in a negative bias state, thereby improving FFR and image retention.

[0164] As shown in FIG3A, based on at least one embodiment of the pixel circuit shown in FIG2A, the pixel circuit described in at least one embodiment of the present disclosure may further include a second initialization circuit 22;

[0165] The second initialization circuit 22 is electrically connected to the second reset control terminal RSTP, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second reset control signal provided by the second reset control terminal RSTP.

[0166] As shown in FIG3B, based on at least one embodiment of the pixel circuit shown in FIG2B, the pixel circuit described in at least one embodiment of the present disclosure may further include a second initialization circuit 22.

[0167] The second initialization circuit 22 is electrically connected to the second reset control terminal RSTP, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second reset control signal provided by the second reset control terminal RSTP.

[0168] Optionally, the first reset control terminal is the nth level first reset control terminal, and the on / off control terminal is the nxth level first reset control terminal;

[0169] The nth-level first reset control signal provided by the nth-level first reset control terminal and the nx-level first reset control signal provided by the nx-level first reset control terminal are provided by the same drive module;

[0170] n and x are positive integers.

[0171] In practical implementation, the same GOA module can be used to provide the first reset control signal and the on / off control signal, thereby reducing the number of GOA modules used.

[0172] In at least one embodiment of this disclosure, the second reset control terminal is the nth level second reset control terminal, and the on / off control terminal is the n+yth level second reset control terminal;

[0173] The nth-level second reset control signal provided by the nth-level second reset control terminal and the n+y-level second reset control signal provided by the n+y-level second reset control terminal are provided by the same drive module;

[0174] n and y are positive integers.

[0175] In practical implementation, the same GOA module can be used to provide the second reset control signal and the on / off control signal, thereby reducing the number of GOA modules used.

[0176] In at least one embodiment of this disclosure, the transistor included in the on / off control circuit is a p-type transistor.

[0177] In practical implementation, the transistors included in the on / off control circuit can be set as p-type transistors, and a separate GOA module can be added to control the transistors included in the on / off control circuit. This allows the on / off control terminal to provide a low voltage signal except during the time period from the on to the off of the compensation control circuit. Under this scheme, in the high-frequency and low-frequency regions, the gate of the transistors included in the on / off control circuit is under the action of a low potential gate voltage for a long time, and the threshold voltage of the transistors included in the on / off control circuit remains basically unchanged, resulting in better overall brightness stability of the screen.

[0178] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit, and an energy storage circuit; the display cycle includes a light-emitting phase; the light-emitting phase is disposed after the connection phase and the light-emitting phase is disposed after the shutdown phase;

[0179] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting stage.

[0180] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal during the light-emitting stage;

[0181] The second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0182] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0183] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, a second light-emitting control circuit, and an energy storage circuit. After the connection phase and the turn-off phase, a light-emitting phase is provided. In the light-emitting phase, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first pole of the light-emitting element; and the driving circuit generates a driving current to drive the light-emitting element.

[0184] As shown in FIG4A, based on at least one embodiment of the pixel circuit shown in FIG3A, the pixel circuit of at least one embodiment of the present disclosure further includes a first light-emitting control circuit 41, a second light-emitting control circuit 42, and an energy storage circuit 40.

[0185] The first light-emitting control circuit 41 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM during the light-emitting stage.

[0186] The second light-emitting control circuit 42 is electrically connected to the light-emitting control terminal EM, the third node N3 and the first pole of the light-emitting element E1, respectively, and is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal during the light-emitting stage.

[0187] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1;

[0188] The energy storage circuit 40 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0189] As shown in FIG4B, based on at least one embodiment of the pixel circuit shown in FIG3B, the pixel circuit described in at least one embodiment of the present disclosure further includes a first light-emitting control circuit 41, a second light-emitting control circuit 42, and an energy storage circuit 40.

[0190] The first light-emitting control circuit 41 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM during the light-emitting stage.

[0191] The second light-emitting control circuit 42 is electrically connected to the light-emitting control terminal EM, the third node N3 and the first pole of the light-emitting element E1, respectively, and is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal during the light-emitting stage.

[0192] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1;

[0193] The energy storage circuit 40 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0194] The pixel circuit described in at least one embodiment of this disclosure further includes a third initialization circuit;

[0195] The third initialization circuit is electrically connected to the third reset control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal during the first set phase and the third set phase.

[0196] In a specific implementation, the pixel circuit may further include a third initialization circuit. During the first and third setting phases, the third initialization circuit, under the control of a third reset control signal, writes a third initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0197] In at least one embodiment of this disclosure, the first reset control terminal and the third reset control terminal are the same control terminal, so as to reduce the number of reset control terminals used.

[0198] As shown in FIG5A, based on at least one embodiment of the pixel circuit shown in FIG4A, the pixel circuit of at least one embodiment of the present disclosure further includes a third initialization circuit 43;

[0199] The third initialization circuit 43 is electrically connected to the third reset control terminal RST, the third initial voltage terminal I3, and the first pole of the light-emitting element E1, respectively. It is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the light-emitting element E1 under the control of the third reset control signal provided by the third reset control terminal RST during the first set phase and the third set phase.

[0200] As shown in FIG5B, based on at least one embodiment of the pixel circuit shown in FIG4B, the pixel circuit of at least one embodiment of the present disclosure further includes a third initialization circuit 43;

[0201] The third initialization circuit 43 is electrically connected to the third reset control terminal RST, the third initial voltage terminal I3, and the first pole of the light-emitting element E1, respectively. It is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the light-emitting element E1 under the control of the third reset control signal provided by the third reset control terminal RST during the first set phase and the third set phase.

[0202] Optionally, the driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the data writing circuit includes a second transistor, and the on / off control circuit includes a third transistor.

[0203] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0204] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0205] The gate of the second transistor is electrically connected to the write control terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the second node.

[0206] The gate of the third transistor is electrically connected to the on / off control terminal, the first terminal of the third transistor is electrically connected to the fourth node, and the second terminal of the third transistor is electrically connected to the third node.

[0207] Optionally, the driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the data writing circuit includes a second transistor, and the on / off control circuit includes a third transistor.

[0208] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0209] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node.

[0210] The gate of the second transistor is electrically connected to the write control terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the second node.

[0211] The gate of the third transistor is electrically connected to the on / off control terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the fourth node.

[0212] Optionally, the first initialization circuit includes a fourth transistor;

[0213] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.

[0214] Optionally, the second initialization circuit includes a fifth transistor;

[0215] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

[0216] Optionally, the first light-emitting control circuit includes a sixth transistor; the second light-emitting control circuit includes a seventh transistor; and the energy storage circuit includes a storage capacitor.

[0217] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0218] The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the third node, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0219] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the power supply voltage terminal.

[0220] Optionally, the third initialization circuit includes an eighth transistor;

[0221] The gate of the eighth transistor is electrically connected to the third reset control terminal, the first terminal of the eighth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0222] As shown in Figure 6A, based on at least one embodiment of the pixel circuit shown in Figure 5A, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the data writing circuit includes a second transistor T2, and the on / off control circuit includes a third transistor T3; the light-emitting element is an organic light-emitting diode O1.

[0223] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0224] The gate of the first transistor T1 is electrically connected to the compensation control terminal NSTV, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0225] The gate of the second transistor T2 is electrically connected to the write control terminal GSTV, the source of the second transistor T2 is electrically connected to the data line DL, and the drain of the second transistor T2 is electrically connected to the second node N2.

[0226] The gate of the third transistor T3 is electrically connected to the first reset control terminal RSTH(nx) of the nxth stage, the source of the third transistor T3 is electrically connected to the fourth node N4, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0227] The first initialization circuit includes a fourth transistor T4;

[0228] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal RSTH, the source of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the second node N2; the first initial voltage terminal I1 is used to pass the first initial voltage Vinit1.

[0229] The second initialization circuit includes a fifth transistor T5;

[0230] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal RSTP, the source of the fifth transistor T5 is electrically connected to the second initial voltage terminal I2, and the drain of the fifth transistor T5 is electrically connected to the third node N3; the second initial voltage terminal I2 is used to pass the second initial voltage Vinit2.

[0231] The first light-emitting control circuit includes a sixth transistor T6; the second light-emitting control circuit includes a seventh transistor T7; and the energy storage circuit includes a storage capacitor Cst.

[0232] The gate of the sixth transistor T6 is electrically connected to the light-emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2.

[0233] The gate of the seventh transistor T7 is electrically connected to the light-emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the anode of O1.

[0234] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD.

[0235] The third initialization circuit includes an eighth transistor T8;

[0236] The gate of the eighth transistor T8 is electrically connected to the first reset control terminal RSTH, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of O1; the third initial voltage terminal I3 is used to pass the third initial voltage Vinit3.

[0237] The cathode of O1 is electrically connected to the low-voltage terminal VSS.

[0238] In at least one embodiment of the pixel circuit shown in Figure 6A, T1 and T3 are n-type transistors, the other transistors are p-type transistors, and T1 and T3 are oxide transistors.

[0239] The on / off control terminal is the first reset control terminal of the nx-th stage, and the first reset control terminal RSTH is the first reset control terminal of the n-th stage, where n and x are both positive integers.

[0240] In at least one embodiment shown in Figure 6A, the third reset control terminal is the first reset control terminal RSTH.

[0241] In at least one embodiment shown in Figure 6A, the voltage value of Vinit1 can be greater than or equal to -5V and less than or equal to 0V, the voltage value of Vinit3 can be greater than or equal to -5V and less than or equal to 0V, and the voltage value of Vinit3 can be greater than or equal to 5V and less than or equal to 8V.

[0242] As shown in Figure 7A, at least one embodiment of the pixel circuit shown in Figure 6A of this disclosure, when in operation, includes a display cycle consisting of a first set phase SZ1, a second set phase SZ2, a third set phase SZ3, and a light emission phase SE, which are set sequentially; the display cycle includes a connection phase SL, a shutdown phase SG, and a data writing phase SW.

[0243] The connectivity phase SL includes a first set phase SZ1, a second set phase SZ2, and a data write phase SW; the data write phase SW is set between the second set phase SZ2 and the third set phase SZ3.

[0244] During the connection phase SL, NSTV provides a high-voltage signal;

[0245] The start time of the shutdown phase SG is set after the end of the data writing phase SW, the start time of the shutdown phase SG is set before the end time of the connection phase SL, and the end time of the shutdown phase SG is set after the end time of the connection phase SL, so that when T1 is disconnected, the current path between the first node N1 and the third node N3 is blocked, the circuit path between the first node N1 and the second node N2 is blocked, and the voltage difference of the first node N1 under different threshold voltage characteristics of T1 is reduced.

[0246] As shown in Figure 7A, at least one embodiment of the pixel circuit shown in Figure 6A of this disclosure operates as follows:

[0247] In the first set phase SZ1, RSTH provides a low voltage signal, EM provides a high voltage signal, GSTV provides a high voltage signal, RSTP provides a high voltage signal, NSTV provides a high voltage signal, RSTH(nx) provides a low voltage signal, T8 is turned on, T4 is turned on, T1 is turned on, T3 is turned off, I1 provides a first initial voltage Vinit1 to N2 to initialize the potential of the second node N2, and I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0248] During the second set phase SZ2, EM provides a high voltage signal, RSTH provides a high voltage signal, GSTV provides a high voltage signal, RSTP provides a low voltage signal, NSTV provides a high voltage signal, RSTH(nx) provides a high voltage signal, T5 is turned on, I2 provides the second initial voltage Vinit2 to N3, T1 and T3 are turned on, and Vinit2 is written to N1 to initialize the potential of the first node N1 and the potential of the third node N3;

[0249] During the data writing phase, SW and EM provide high voltage signals, RSTH provides high voltage signals, GSTV provides low voltage signals, RSTP provides high voltage signals, NSTV provides high voltage signals, RSTH(nx) provides high voltage signals, T2 is turned on, DL provides data voltage Vdata to N2, T1 and T3 are turned on, and N1 and N3 are connected.

[0250] When the data writing phase SW begins, T0 is turned on, and Vdata charges Cst through T2, T0, T3 and T1 until the potential of N1 becomes Vdata+Vth0, T0 is turned off, and Vth0 is the threshold voltage of T0.

[0251] During the turn-off phase, SG and EM provide high voltage signals, GSTV provides high voltage signals, RSTP provides high voltage signals, RSTH(nx) provides low voltage signals, and T3 turns off.

[0252] During the turn-off phase, the compensation control signal provided by SG and NSTV changes from high voltage to low voltage, and T1 changes from the on state to the off state. At this time, T3 turns off, blocking the current path between N1 and N3, blocking the current path between N1 and N2, and reducing the voltage difference of the first node under different threshold voltage characteristics of T1.

[0253] In the third set phase SZ3, RSTH provides a low voltage signal, T4 is turned on, RSTH(nx) provides a low voltage signal, T8 is turned on, I1 provides the first initial voltage Vinit1 to N2 to initialize the potential of the second node N2 so that T0 is in a negative bias state, and I3 provides the third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0254] During the light-emitting phase, SE and EM provide a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0255] In at least one embodiment of the pixel circuit shown in Figure 6A, the gate of T3 is electrically connected to RSTH(nx). In the high-frequency region and the low-frequency region, the frequency of the signal provided by RSTH(nx) is the same. Therefore, there is no difference in the threshold voltage of T3 in the high-frequency region and the low-frequency region.

[0256] In practical operation, when at least one embodiment of the pixel circuit shown in Figure 6A is working, taking the example that the threshold voltage difference of T1 is 0.5V in the high-frequency region and the low-frequency region caused by HRD, and the threshold voltage difference of T3 is not different, under the same data voltage, when T1 generates a threshold voltage difference of 0.5V in the high-frequency region and the low-frequency region, the potential difference of N1 is 0.015V; while in the related pixel circuit, the potential difference of N1 is 0.03V; as can be seen from the above, at least one embodiment of this disclosure can reduce the potential difference of N1 caused by the threshold voltage shift of T1 by about 50%, which can significantly optimize image quality.

[0257] As shown in Figure 8, L1 is a waveform diagram of the potential of N1 when at least one embodiment of the pixel circuit shown in Figure 6A is operating in the low-frequency region, and L2 is a waveform diagram of the potential of N1 when at least one embodiment of the pixel circuit shown in Figure 6A is operating in the high-frequency region.

[0258] As shown in Figure 7B, at least one embodiment of the pixel circuit shown in Figure 6A of this disclosure, when in operation, displays a cycle including a reset phase SR, a first set phase SZ1, a second set phase SZ2, a data writing phase SW, a third set phase SZ3, and a light emission phase SE, which are set sequentially.

[0259] The display cycle includes a connection phase SL, and the display cycle includes a shutdown phase SG;

[0260] The connection phase SL includes a reset phase SR, a first set phase SZ1, a second set phase SZ2, and a data write phase SW.

[0261] During the connection phase SL, NSTV provides a high-voltage signal;

[0262] During the reset phase, SR, EM provide high voltage signals, RSTH provides high voltage signals, GSTV provides high voltage signals, RSTP provides low voltage signals, NSTV provides high voltage signals, RSTH(nx) provides high voltage signals, T4 is turned off, T1 and T3 are turned on, N1 and N3 are connected, T5 is turned on, and I2 provides a second initial voltage Vinit2 to N3 and N1; Vinit2 is a negative voltage, and the voltage value of Vinit2 can be -3V;

[0263] In the first set phase SZ1, EM provides a high voltage signal, RSTH provides a low voltage signal, GSTV provides a high voltage signal, RSTP provides a high voltage signal, NSTV provides a high voltage signal, and RSTH(nx) provides a low voltage signal. T3 is turned off, and the potential of N1 is maintained at Vinit2. T4 is turned on, and I1 provides the first initial voltage Vinit1 to N2, so the potential of N2 is Vinit1. T0 is turned on, and the potential of N3 is Vinit1. The voltage value of Vinit1 is positive and can be 7V. That is, before the data voltage is written, the potential of N1 is negative, and the gate-source voltage Vgs of T0 is relatively large, which has a strong negative bias effect on T0, which can improve FFR and image retention. T8 is turned on, and I3 provides the third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0264] In the second set phase SZ2, EM provides a high voltage signal, RSTH provides a high voltage signal, GSTV provides a high voltage signal, RSTP provides a low voltage signal, NSTV provides a high voltage signal, RSTH(nx) provides a high voltage signal, T5 is turned on, I2 provides the second initial voltage Vinit2 to N3, T1 and T3 are both turned on, Vinit2 is written to N1, so that the potential of N1 and the potential of N3 are both Vinit2;

[0265] During the data writing phase, SW and EM provide high voltage signals, RSTH provides high voltage signals, GSTV provides low voltage signals, RSTP provides high voltage signals, NSTV provides high voltage signals, RSTH(nx) provides high voltage signals, T2 is turned on, DL provides data voltage Vdata to N2, and T1 and T3 are turned on.

[0266] When the data writing phase SW begins, T0 is turned on, and Vdata charges Cst through T2, T0, T1 and T3, changing the potential of N1 until T0 is turned off, at which point the potential of N1 becomes Vdata + Vth.

[0267] In the third set phase SZ3, EM provides a high voltage signal, RSTH provides a low voltage signal, GSTV provides a high voltage signal, RSTP provides a high voltage signal, NSTV provides a low voltage signal, RSTH(nx) provides a low voltage signal, T1 is turned off, T8 is turned on, and I3 provides the third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0268] During the turn-off phase, SG and RSTH(nx) provide a low voltage signal, and T3 turns off;

[0269] During the light-emitting phase, SE and EM provide a low-voltage signal, and T0 drives O1 to emit light.

[0270] As shown in Figure 6B, based on at least one embodiment of the pixel circuit shown in Figure 5B, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the data writing circuit includes a second transistor T2, and the on / off control circuit includes a third transistor T3; the light-emitting element is an organic light-emitting diode O1.

[0271] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0272] The gate of the first transistor T1 is electrically connected to the compensation control terminal NSTV, the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the third node N3.

[0273] The gate of the second transistor T2 is electrically connected to the write control terminal GSTV, the source of the second transistor T2 is electrically connected to the data line DL, and the drain of the second transistor T2 is electrically connected to the second node N2.

[0274] The gate of the third transistor T3 is electrically connected to the first reset control terminal RSTH(nx) of the nxth stage, the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the fourth node N4.

[0275] The first initialization circuit includes a fourth transistor T4;

[0276] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal RSTH, the source of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the second node N2; the first initial voltage terminal I1 is used to pass the first initial voltage Vinit1.

[0277] The second initialization circuit includes a fifth transistor T5;

[0278] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal RSTP, the source of the fifth transistor T5 is electrically connected to the second initial voltage terminal I2, and the drain of the fifth transistor T5 is electrically connected to the third node N3; the second initial voltage terminal I2 is used to pass the second initial voltage Vinit2;

[0279] The first light-emitting control circuit includes a sixth transistor T6; the second light-emitting control circuit includes a seventh transistor T7; and the energy storage circuit includes a storage capacitor Cst.

[0280] The gate of the sixth transistor T6 is electrically connected to the light-emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2.

[0281] The gate of the seventh transistor T7 is electrically connected to the light-emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the anode of O1.

[0282] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD.

[0283] The third initialization circuit includes an eighth transistor T8;

[0284] The gate of the eighth transistor T8 is electrically connected to the first reset control terminal RSTH, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of O1; the third initial voltage terminal I3 is used to pass the third initial voltage Vinit3.

[0285] The cathode of O1 is electrically connected to the low-voltage terminal VSS.

[0286] In at least one embodiment of the pixel circuit shown in Figure 6B, T1 and T3 are n-type transistors, the other transistors are p-type transistors, and T1 and T3 are oxide transistors.

[0287] The on / off control terminal is the first reset control terminal of the nx-th stage, and the first reset control terminal RSTH is the first reset control terminal of the n-th stage, where n and x are both positive integers.

[0288] In at least one embodiment shown in Figure 6B, the third reset control terminal is the first reset control terminal RSTH.

[0289] In at least one embodiment shown in Figure 6B, the voltage value of Vinit1 can be greater than or equal to -5V and less than or equal to 0V, the voltage value of Vinit3 can be greater than or equal to -5V and less than or equal to 0V, and the voltage value of Vinit3 can be greater than or equal to 5V and less than or equal to 8V.

[0290] As shown in Figure 7A, at least one embodiment of the pixel circuit shown in Figure 6B of this disclosure operates as follows:

[0291] In the first set phase SZ1, RSTH provides a low voltage signal, EM provides a high voltage signal, GSTV provides a high voltage signal, RSTP provides a high voltage signal, NSTV provides a high voltage signal, RSTH(nx) provides a low voltage signal, T8 is turned on, T4 is turned on, T1 is turned on, T3 is turned off, I1 provides a first initial voltage Vinit1 to N2 to initialize the potential of the second node N2, and I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0292] During the second set phase SZ2, EM provides a high voltage signal, RSTH provides a high voltage signal, GSTV provides a high voltage signal, RSTP provides a low voltage signal, NSTV provides a high voltage signal, RSTH(nx) provides a high voltage signal, T5 is turned on, I2 provides the second initial voltage Vinit2 to N3, T1 and T3 are turned on, and Vinit2 is written to N1 to initialize the potential of the first node N1 and the potential of the third node N3;

[0293] During the data writing phase, SW and EM provide high voltage signals, RSTH provides high voltage signals, GSTV provides low voltage signals, RSTP provides high voltage signals, NSTV provides high voltage signals, RSTH(nx) provides high voltage signals, T2 is turned on, DL provides data voltage Vdata to N2, T1 and T3 are turned on, and N1 and N3 are connected.

[0294] When the data writing phase SW begins, T0 is turned on, and Vdata charges Cst through T2, T0, T3 and T1 until the potential of N1 becomes Vdata+Vth0, T0 is turned off, and Vth0 is the threshold voltage of T0.

[0295] During the turn-off phase, SG and EM provide high voltage signals, GSTV provides high voltage signals, RSTP provides high voltage signals, RSTH(nx) provides low voltage signals, and T3 turns off.

[0296] During the turn-off phase, the compensation control signal provided by SG and NSTV changes from high voltage to low voltage, and T1 changes from the on state to the off state. At this time, T3 turns off, blocking the current path between N1 and N3, blocking the current path between N1 and N2, and reducing the voltage difference of the first node under different threshold voltage characteristics of T1.

[0297] In the third set phase SZ3, RSTH provides a low voltage signal, T4 is turned on, RSTH(nx) provides a low voltage signal, T8 is turned on, I1 provides the first initial voltage Vinit1 to N2 to initialize the potential of the second node N2 so that T0 is in a negative bias state, and I3 provides the third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0298] During the light-emitting phase, SE and EM provide a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0299] In at least one embodiment of the pixel circuit shown in Figure 6B, the gate of T3 is electrically connected to RSTH(nx). In the high-frequency region and the low-frequency region, the frequency of the signal provided by RSTH(nx) is the same. Therefore, there is no difference in the threshold voltage of T3 in the high-frequency region and the low-frequency region.

[0300] In practical operation, when at least one embodiment of the pixel circuit shown in Figure 6B is working, taking the example that the threshold voltage difference of T1 is 0.5V in the high-frequency region and the low-frequency region caused by HRD, and the threshold voltage difference of T3 is not different, under the same data voltage, when T1 generates a threshold voltage difference of 0.5V in the high-frequency region and the low-frequency region, the potential difference of N1 is 0.015V; while in the related pixel circuit, the potential difference of N1 is 0.03V; as can be seen from the above, at least one embodiment of this disclosure can reduce the potential difference of N1 caused by the threshold voltage shift of T1 by about 50%, which can significantly optimize image quality.

[0301] As shown in Figure 7B, at least one embodiment of the pixel circuit shown in Figure 6B of this disclosure, when in operation, displays a cycle including a reset phase SR, a first set phase SZ1, a second set phase SZ2, a data writing phase SW, a third set phase SZ3, and a light emission phase SE, which are set sequentially.

[0302] The display cycle includes a connection phase SL, and the display cycle includes a shutdown phase SG;

[0303] The connection phase SL includes a reset phase SR, a first set phase SZ1, a second set phase SZ2, and a data write phase SW.

[0304] During the connection phase SL, NSTV provides a high-voltage signal;

[0305] During the reset phase, SR, EM provide high voltage signals, RSTH provides high voltage signals, GSTV provides high voltage signals, RSTP provides low voltage signals, NSTV provides high voltage signals, RSTH(nx) provides high voltage signals, T4 is turned off, T1 and T3 are turned on, N1 and N3 are connected, T5 is turned on, and I2 provides a second initial voltage Vinit2 to N3 and N1; Vinit2 is a negative voltage, and the voltage value of Vinit2 can be -3V;

[0306] In the first set phase SZ1, EM provides a high voltage signal, RSTH provides a low voltage signal, GSTV provides a high voltage signal, RSTP provides a high voltage signal, NSTV provides a high voltage signal, and RSTH(nx) provides a low voltage signal. T3 is turned off, and the potential of N1 is maintained at Vinit2. T4 is turned on, and I1 provides the first initial voltage Vinit1 to N2, so the potential of N2 is Vinit1. T0 is turned on, and the potential of N3 is Vinit1. The voltage value of Vinit1 is positive and can be 7V. That is, before the data voltage is written, the potential of N1 is negative, and the gate-source voltage Vgs of T0 is relatively large, which has a strong negative bias effect on T0, which can improve FFR and image retention. T8 is turned on, and I3 provides the third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0307] In the second set phase SZ2, EM provides a high voltage signal, RSTH provides a high voltage signal, GSTV provides a high voltage signal, RSTP provides a low voltage signal, NSTV provides a high voltage signal, RSTH(nx) provides a high voltage signal, T5 is turned on, I2 provides the second initial voltage Vinit2 to N3, T1 and T3 are both turned on, Vinit2 is written to N1, so that the potential of N1 and the potential of N3 are both Vinit2;

[0308] During the data writing phase, SW and EM provide high voltage signals, RSTH provides high voltage signals, GSTV provides low voltage signals, RSTP provides high voltage signals, NSTV provides high voltage signals, RSTH(nx) provides high voltage signals, T2 is turned on, DL provides data voltage Vdata to N2, and T1 and T3 are turned on.

[0309] When the data writing phase SW begins, T0 is turned on, and Vdata charges Cst through T2, T0, T1 and T3, changing the potential of N1 until T0 is turned off, at which point the potential of N1 becomes Vdata + Vth.

[0310] In the third set phase SZ3, EM provides a high voltage signal, RSTH provides a low voltage signal, GSTV provides a high voltage signal, RSTP provides a high voltage signal, NSTV provides a low voltage signal, RSTH(nx) provides a low voltage signal, T1 is turned off, T8 is turned on, and I3 provides the third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1.

[0311] During the turn-off phase, SG and RSTH(nx) provide a low voltage signal, and T3 turns off;

[0312] During the light-emitting phase, SE and EM provide a low-voltage signal, and T0 drives O1 to emit light.

[0313] The differences between at least one embodiment of the pixel circuit shown in FIG. 9 of this disclosure and at least one embodiment of the pixel circuit shown in FIG. 6A of this disclosure are as follows:

[0314] The gate of T3 is electrically connected to the second reset control terminal RSTP(n+x) of the n+x stage.

[0315] In at least one embodiment of the pixel circuit shown in Figure 9, the second reset control terminal RSTP is the nth stage second reset control terminal, where n and x are positive integers. For example, x can be equal to 3.

[0316] Figure 10 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure.

[0317] In at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure, when in operation, RSTP(n+x) needs to ensure that T3 is already in the off state when NSTV controls T1 to turn off, and T3 only starts to conduct after T1 is turned off. The purpose is to block the current path between N1 and N3 and the current path between N1 and N2 during the T1 turn-off process, thereby reducing the potential difference of N1 under different threshold voltage characteristics of T1.

[0318] The difference between at least one embodiment of the pixel circuit shown in FIG11 of this disclosure and at least one embodiment of the pixel circuit shown in FIG9 of this disclosure is that:

[0319] The gate of T3 is electrically connected to the on / off control terminal ST, and the on / off control signal provided by the on / off control terminal ST is provided by a separate GOA module.

[0320] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure.

[0321] As shown in Figure 12, T3 is turned off except during the turn-off phase SG.

[0322] The differences between at least one embodiment of the pixel circuit shown in FIG13 of this disclosure and at least one embodiment of the pixel circuit shown in FIG11 of this disclosure are as follows:

[0323] T3 is a p-type transistor.

[0324] Figure 14 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 13 of this disclosure.

[0325] As shown in FIG14, in at least one embodiment of the pixel circuit shown in FIG13 of this disclosure, T3 is turned off except during the turn-off phase SG.

[0326] Except during the turn-off phase, ST provides a low-voltage signal;

[0327] Under this scheme, in both the high-frequency and low-frequency regions, the gate of T3 is under the long-term effect of a low gate voltage, and the threshold voltage of T3 remains basically unchanged, resulting in better overall brightness stability of the screen.

[0328] The pixel driving method described in this embodiment is applied to the pixel circuit described above, and the display cycle includes a data writing phase, a connectivity phase, and a shutdown phase; the connectivity phase includes the data writing phase; the start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase; the pixel driving method includes:

[0329] During the data writing phase, the data writing circuit, under the control of the write control signal, writes the data voltage to the second node;

[0330] The pixel driving method further includes: during the connection phase, the control circuit, under the control of a compensation control signal, controls the connection between the first node and the fourth node; during the shutdown phase, the control circuit, under the control of an on / off control signal, controls the disconnection between the fourth node and the third node; or...

[0331] The pixel driving method further includes: in the connection phase, the control circuit controls the connection between the third node and the third node under the control of the compensation control signal; in the shutdown phase, the control circuit controls the disconnection between the first node and the fourth node under the control of the on / off control signal.

[0332] The display device described in this disclosure includes the pixel circuit described above.

[0333] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element, a driving circuit, a data writing circuit, and a control circuit; the display cycle includes a data writing phase, a connection phase, and a shutdown phase; the connection phase includes the data writing phase; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node. The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line to the second node under the control of the write control signal provided by the write control terminal during the data writing stage. The control circuit is electrically connected to the compensation control terminal, the on / off control terminal, the first node, the third node, and the fourth node, respectively. The control circuit is used to control the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal during the connection phase, and to control the disconnection between the fourth node and the third node under the control of the on / off control signal provided by the on / off control terminal during the shutdown phase; or, the control circuit is used to control the connection between the third node and the fourth node under the control of the compensation control signal during the connection phase, and to control the disconnection between the first node and the fourth node under the control of the on / off control signal during the shutdown phase. The start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase.

2. The pixel circuit as described in claim 1, wherein, The control circuit includes a compensation control circuit and an on / off control circuit; The compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the compensation control signal during the connection phase. The on / off control circuit is electrically connected to the on / off control terminal, the fourth node, and the third node, respectively, and is used to control the fourth node and the third node to disconnect during the off phase under the control of the on / off control signal.

3. The pixel circuit as described in claim 1, wherein, The control circuit includes a compensation control circuit and an on / off control circuit; The compensation control circuit is electrically connected to the compensation control terminal, the third node, and the fourth node respectively, and is used to control the connection between the third node and the fourth node under the control of the compensation control signal during the connection phase. The on / off control circuit is electrically connected to the on / off control terminal, the first node, and the fourth node, respectively, and is used for... During the shutdown phase, under the control of the on / off control signal, the first node and the fourth node are disconnected.

4. The pixel circuit as described in claim 2 or 3, wherein, The system includes a first initialization circuit; the display cycle further includes a first setting phase; the connection phase includes the first setting phase; the first setting phase is set before the data writing phase; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the second node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first reset control signal provided by the first reset control terminal during the first setting phase.

5. The pixel circuit as described in claim 2 or 3, wherein, The display cycle further includes a first setting phase; the connection phase includes the first setting phase; the first setting phase is set before the data writing phase; The on / off control circuit is used to control the fourth node to disconnect from the third node under the control of the on / off control signal during the first set phase; or, the on / off control circuit is used to control the first node to disconnect from the fourth node under the control of the on / off control signal during the first set phase.

6. The pixel circuit as described in claim 2 or 3, wherein, It also includes a second initialization circuit; the display cycle further includes a reset phase, and the connection phase includes the reset phase; The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the third node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second reset control signal provided by the second reset control terminal during the reset phase. The on / off control circuit is used during the reset phase, under the control of the on / off control signal, to control the connection between the fourth node and the third node; or, the on / off control circuit is used during the reset phase, under the control of the on / off control signal, to control the connection between the first node and the fourth node.

7. The pixel circuit as described in claim 4, wherein, It also includes a second initialization circuit; the display cycle further includes a second setting phase; the connection phase includes the second setting phase, which is set after the first setting phase and before the data writing phase; The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage into the third node under the control of the second reset control signal provided by the second reset control terminal during the second setting phase; The on / off control circuit is used to control the connection between the fourth node and the third node under the control of the on / off control signal during the second set phase; or, the on / off control circuit is used to control the connection between the first node and the fourth node under the control of the on / off control signal during the second set phase.

8. The pixel circuit as described in claim 4, wherein, The display cycle further includes a third setting phase; the third setting phase is set after the data writing phase; the third setting phase is set before the light emission phase; The first initialization circuit is used to write the first initial voltage into the second node under the control of the first reset control signal during the third setting phase. The compensation control circuit is used, during the third setting phase, to control the [unclear - possibly a specific function or signal] under the control of the compensation control signal. The first node is disconnected from the fourth node; and / or, the on / off control circuit is used, during the third set phase, under the control of the on / off control signal, to control the fourth node to disconnect from the third node; or... The compensation control circuit is used to control the third node and the fourth node to disconnect during the third setting phase, under the control of the compensation control signal; and / or, the on / off control circuit is used to control the first node and the fourth node to disconnect during the third setting phase, under the control of the on / off control signal.

9. The pixel circuit as described in claim 4, wherein, The first reset control terminal is the nth level first reset control terminal, and the on / off control terminal is the nxth level first reset control terminal; The nth-level first reset control signal provided by the nth-level first reset control terminal and the nx-level first reset control signal provided by the nx-level first reset control terminal are provided by the same drive module; n and x are positive integers.

10. The pixel circuit as claimed in claim 7, wherein, The second reset control terminal is the nth level second reset control terminal, and the on / off control terminal is the n+yth level second reset control terminal; The nth-level second reset control signal provided by the nth-level second reset control terminal and the n+y-level second reset control signal provided by the n+y-level second reset control terminal are provided by the same drive module; n and y are positive integers.

11. The pixel circuit as described in claim 2 or 3, wherein, The on / off control circuit includes p-type transistors.

12. The pixel circuit according to any one of claims 1 to 3, wherein, It also includes a first light-emitting control circuit, a second light-emitting control circuit, and an energy storage circuit; the display cycle includes a light-emitting phase; the light-emitting phase is set after the connection phase and the light-emitting phase is set after the shutdown phase; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting stage. The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal during the light-emitting stage; The second electrode of the light-emitting element is electrically connected to the first voltage terminal; The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

13. The pixel circuit as claimed in claim 8, wherein, It also includes a third initialization circuit; The third initialization circuit is electrically connected to the third reset control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal during the first set phase and the third set phase.

14. The pixel circuit as claimed in claim 13, wherein, The first reset control terminal and the third reset control terminal are the same control terminal.

15. The pixel circuit as claimed in claim 2, wherein, The driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the data writing circuit includes a second transistor, and the on / off control circuit includes a third transistor. The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node. The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node. The gate of the second transistor is electrically connected to the write control terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the second node. The gate of the third transistor is electrically connected to the on / off control terminal, the first terminal of the third transistor is electrically connected to the fourth node, and the second terminal of the third transistor is electrically connected to the third node.

16. The pixel circuit as claimed in claim 3, wherein, The driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the data writing circuit includes a second transistor, and the on / off control circuit includes a third transistor. The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node. The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node. The gate of the second transistor is electrically connected to the write control terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the second node. The gate of the third transistor is electrically connected to the on / off control terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the fourth node.

17. The pixel circuit as claimed in claim 4, wherein, The first initialization circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.

18. The pixel circuit as claimed in claim 6, wherein, The second initialization circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

19. The pixel circuit as claimed in claim 12, wherein, The first light-emitting control circuit includes a sixth transistor; the second light-emitting control circuit includes a seventh transistor; and the energy storage circuit includes a storage capacitor. The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second node. The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the third node, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element. The first terminal of the storage capacitor is electrically connected to the first node, and the second terminal of the storage capacitor is connected to the power supply voltage. Terminal electrical connection.

20. The pixel circuit of claim 13, wherein, The third initialization circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the third reset control terminal, the first terminal of the eighth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

21. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 20, wherein the display cycle includes a data writing phase, a connectivity phase, and a shutdown phase; the connectivity phase includes the data writing phase; the start time of the shutdown phase is set after the end of the data writing phase, the start time of the shutdown phase is set before the end time of the connectivity phase, and the end time of the shutdown phase is set after the end time of the connectivity phase. The pixel driving method includes: During the data writing phase, the data writing circuit, under the control of the write control signal, writes the data voltage to the second node; The pixel driving method further includes: during the connection phase, the control circuit, under the control of a compensation control signal, controls the connection between the first node and the fourth node; during the shutdown phase, the control circuit, under the control of an on / off control signal, controls the disconnection between the fourth node and the third node; or... The pixel driving method further includes: in the connection phase, the control circuit controls the connection between the third node and the third node under the control of the compensation control signal; in the shutdown phase, the control circuit controls the disconnection between the first node and the fourth node under the control of the on / off control signal.

22. A display device comprising the pixel circuitry as claimed in any one of claims 20.

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