Pixel driving circuit, display panel, and display device

Abstract

A pixel driving circuit, a display panel, and a display device. The display panel comprises a plurality of pixel units, and each pixel unit comprises a plurality of sub-pixel units. The sub-pixel units comprise an electrode layer and a pixel definition layer which are on a base substrate: the electrode layer is provided with first electrode portions (D1) and second electrode portions (D2) which are spaced apart from each other and are respectively used as first electrodes of light-emitting units of the same color; and the pixel definition layer is located above the electrode layer and is provided with pixel openings (Ph) corresponding to the electrode portions, and the orthographic projection of each opening on the base substrate is within the orthographic projection of the corresponding electrode portion. Within a same sub-pixel, the number of openings corresponding to the first electrode portion is greater than the number of openings corresponding to the second electrode portion, but the area of a single opening is smaller. The display panel implements a privacy display mode and a normal display mode.

Description

Pixel driving circuit, display panel, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Technology

[0002] In related technologies, the anti-peeping function of display panels is generally achieved through external anti-peeping films. However, anti-peeping films can seriously affect the display effect of display panels.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes a plurality of pixel units, the pixel units including a plurality of sub-pixel units, and the display panel further includes:

[0006] Substrate;

[0007] An electrode layer is located on one side of the substrate. The sub-pixel unit includes at least two electrode portions located on the electrode layer. The two electrode portions respectively form a first electrode portion and a second electrode portion. In the same sub-pixel unit, the first electrode portion and the second electrode portion are spaced apart, and the first electrode portion and the second electrode portion are respectively used to form the first electrode of the same color light-emitting unit.

[0008] A pixel definition layer is located on the side of the electrode layer opposite to the substrate. A plurality of pixel openings are formed on the pixel definition layer. The electrode portion and the pixel opening are correspondingly disposed. The orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the corresponding electrode portion on the substrate.

[0009] In the same sub-pixel unit, the number of pixel openings corresponding to the first electrode portion is greater than the number of pixel openings corresponding to the second electrode portion, and the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion on the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion on the substrate.

[0010] In one exemplary embodiment of this disclosure, in the same sub-pixel unit, the ratio of the number of individual pixel openings corresponding to the first electrode portion to the number of individual pixel openings corresponding to the second electrode portion is greater than or equal to 2 and less than or equal to 20.

[0011] In one exemplary embodiment of this disclosure, the display panel further includes:

[0012] Pixel driving circuit;

[0013] A data line, the data line being used to provide data signals to the pixel driving circuit, the data line extending along a second direction in its orthogonal projection on the substrate.

[0014] In the same sub-pixel unit, the size of the orthogonal projection of the single pixel opening corresponding to the first electrode portion onto the substrate in the first direction is smaller than the size of the orthogonal projection of the single pixel opening corresponding to the second electrode portion onto the substrate in the first direction, and the first direction and the second direction intersect.

[0015] In one exemplary embodiment of this disclosure, the orthographic projection of a single pixel opening corresponding to the first electrode portion onto the substrate is circular.

[0016] In one exemplary embodiment of this disclosure, the pixel opening corresponding to the second electrode portion forms a second pixel opening, the orthographic projection of the second pixel opening on the substrate has an arc-shaped chamfer, and the arc-shaped chamfer on the second pixel opening is located on the side facing the adjacent second pixel opening.

[0017] In one exemplary embodiment of this disclosure, in the same pixel unit, the orthographic projections of a plurality of first electrode portions on the substrate and the orthographic projections of a plurality of second electrode portions on the substrate are located in different regions.

[0018] In one exemplary embodiment of this disclosure, the sub-pixel unit includes at least two pixel driving circuits, which are used to provide driving current to the first electrode portion and the second electrode portion, respectively.

[0019] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a sixth transistor, a seventh transistor, and a ninth transistor;

[0020] The first terminal of the sixth transistor is connected to the second terminal of the driving transistor, and the second terminal is connected to the electrode portion;

[0021] The first terminal of the seventh transistor is connected to the second initial signal line, and the second terminal is connected to the electrode portion;

[0022] The first electrode of the ninth transistor is connected to the gate of the driving transistor, the gate is connected to the enable signal line, and the second electrode is floating.

[0023] The display panel also includes:

[0024] A first gate layer is located between the substrate and the electrode layer. The first gate layer includes a first conductive portion and a plurality of gate lines. The orthogonal projection of the gate lines on the substrate extends along a first direction. The plurality of gate lines include a first reset signal line and an enable signal line. The first conductive portion is used to form the gate of the driving transistor. A portion of the structure of the first reset signal line is used to form the gate of the seventh transistor. A portion of the structure of the enable signal line is used to form the gates of the ninth transistor and the sixth transistor, respectively.

[0025] In the same pixel driving circuit, the orthogonal projection of the enable signal line on the substrate is located between the orthogonal projection of the first conductive part on the substrate and the orthogonal projection of the first reset signal line on the substrate.

[0026] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, an eighth transistor, and a capacitor;

[0027] The first electrode of the capacitor is connected to the gate of the driving transistor;

[0028] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor;

[0029] The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor;

[0030] The first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the second electrode of the capacitor.

[0031] The first terminal of the fifth transistor is connected to the reference voltage line, and the second terminal is connected to the second electrode of the capacitor.

[0032] The first terminal of the eighth transistor is connected to the reference voltage line, and the second terminal is connected to the second electrode of the capacitor.

[0033] The plurality of gate lines also includes a first gate line, a portion of the structure of the first gate line being used to form the gates of the second transistor and the fourth transistor, a portion of the structure of the enable signal line being used to form the gate of the eighth transistor, the first conductive portion being multiplexed as the first electrode of the capacitor, and a portion of the structure of the first reset signal line being used to form the gates of the first transistor and the fifth transistor.

[0034] In the same pixel driving circuit, the orthographic projection of the first gate line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is far from the orthographic projection of the enable signal line on the substrate.

[0035] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, the driving transistor providing a driving current to the electrode portion according to its gate voltage, and the display panel further includes:

[0036] A first source / drain layer is located between the substrate and the electrode layer. The first source / drain layer includes a second bridging portion and a third bridging portion. The second bridging portion is connected to the electrode portion through a via, and the third bridging portion is connected to the gate of the driving transistor through a via.

[0037] A data line, the data line extending along a second direction by its orthogonal projection on the substrate, the data line being used to provide data signals to the pixel driving circuit;

[0038] Wherein, the second direction is the column direction, and the orthographic projection of the second bridging part in the column pixel driving circuit on the substrate is located between the orthographic projection of the third bridging part in the column pixel driving circuit on the substrate and the orthographic projection of the data line connected to the adjacent column pixel driving circuit on the substrate.

[0039] Furthermore, in the same pixel driving circuit, the orthographic projection of the second bridging portion on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite each other in a first direction, and the first direction and the second direction intersect.

[0040] In one exemplary embodiment of this disclosure, the second bridging portion includes a first via connection portion, a second via connection portion, and an extension portion connected to one end of the second via connection portion away from the first via connection portion;

[0041] The first via connection portion is connected to the pixel driving circuit through a via, and the second via connection portion is connected to the electrode portion through a via. In the same pixel driving circuit, the orthographic projection of the extension portion on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite to each other in the first direction.

[0042] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a driving transistor, a fourth transistor, an eighth transistor, and a capacitor;

[0043] The first electrode of the capacitor is connected to the gate of the driving transistor;

[0044] The first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the second electrode of the capacitor.

[0045] The first terminal of the eighth transistor is connected to the reference voltage line, and the second terminal is connected to the second electrode of the capacitor.

[0046] The display panel also includes:

[0047] A first source / drain layer is located between the substrate and the electrode layer. The first source / drain layer includes a third bridging portion and a fourth bridging portion. The third bridging portion is connected to the gate of the driving transistor through a via. The fourth bridging portion is connected to the second electrode of the capacitor, the second electrode of the fourth transistor, and the second electrode of the eighth transistor through vias, respectively.

[0048] A data line, the data line extending along the second direction by its orthogonal projection on the substrate, the data line being used to provide data signals to the pixel driving circuit;

[0049] Wherein, the second direction is the column direction, and the orthographic projection of the fourth bridging part in the column pixel driving circuit on the substrate is located between the orthographic projection of the third bridging part in the column pixel driving circuit and the orthographic projection of the data line connected to the column pixel driving circuit on the substrate.

[0050] Furthermore, in the same pixel driving circuit, the orthographic projection of the fourth bridging portion on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite each other in a first direction, and the first direction intersects with the second direction.

[0051] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, the driving transistor providing a driving current to the electrode portion according to its gate voltage, and the display panel further includes:

[0052] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a third bridging portion, which is connected to the gate of the driving transistor through a via.

[0053] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a data line, a second power line, and a first power connection line.

[0054] The data line extends along a second direction in the orthogonal projection on the substrate, and the data line is used to provide data signals to the pixel driving circuit.

[0055] The second power line extends along the second direction in the orthogonal projection on the substrate, and the second power line is used to connect the second electrode of the light-emitting unit;

[0056] The first power connection line extends along the second direction in the orthogonal projection on the substrate, and the first power connection line is used to provide a high-level power signal to the pixel driving circuit.

[0057] Wherein, the orthogonal projection of the first power connection line on the substrate is located between the data line connected to the same pixel driving circuit and the orthogonal projection of the third bridging part on the substrate.

[0058] And / or, the orthographic projection of the second power line on the substrate is located between the orthographic projection of the third bridging portion in the pixel driving circuit of this column on the substrate and the orthographic projection of the data line connected to the pixel driving circuit of the adjacent column on the substrate.

[0059] In one exemplary embodiment of this disclosure, the sub-pixel unit includes at least one pixel driving circuit, which is used to provide driving current to the first electrode portion and the second electrode portion in a time-division manner.

[0060] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a sixth transistor, an eighth transistor, and a ninth transistor;

[0061] The driving transistor is used to provide a driving current to the electrode portion according to its gate voltage, and the first terminal of the sixth transistor is connected to the second terminal of the driving transistor;

[0062] The first terminal of the eighth transistor is connected to the second terminal of the sixth transistor, and the second terminal is connected to the second electrode portion;

[0063] The first electrode of the ninth transistor is connected to the second electrode of the sixth transistor, and the second electrode is connected to the first electrode portion;

[0064] The display panel also includes:

[0065] A first gate layer is located between the substrate and the electrode layer. The first gate layer includes a first conductive portion and a plurality of gate lines. The orthogonal projection of the gate lines on the substrate extends along a first direction. The plurality of gate lines include a first enable signal line, a second enable signal line, and a third enable signal line. A portion of the structure of the first enable signal line is used to form the gate of the sixth transistor. A portion of the structure of the third enable signal line is used to form the gate of the ninth transistor. A portion of the structure of the second enable signal line is used to form the gate of the eighth transistor. The first conductive portion is used to form the gate of the driving transistor.

[0066] In the same pixel driving circuit, the orthographic projection of the third enable signal line on the substrate is located between the orthographic projection of the second enable signal line on the substrate and the orthographic projection of the first enable signal line on the substrate, and the orthographic projection of the first enable signal line on the substrate is located between the orthographic projection of the third enable signal line on the substrate and the orthographic projection of the first conductive portion on the substrate.

[0067] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor;

[0068] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor;

[0069] The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor;

[0070] The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the first terminal of the driving transistor.

[0071] The first terminal of the fifth transistor is connected to the first power supply line, and the second terminal is connected to the first terminal of the driving transistor.

[0072] The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the second electrode portion;

[0073] The plurality of gate lines further include: a first gate line, a first reset signal line, and a second reset signal line, wherein a portion of the structure of the first gate line is used to form the gate of the second transistor and the fourth transistor, a portion of the structure of the first reset signal line is used to form the gate of the first transistor, and a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor.

[0074] In the same pixel driving circuit, the orthographic projection of the first gate line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is away from the orthographic projection of the first enable signal line on the substrate; the orthographic projection of the first reset signal line on the substrate is located on the side where the orthographic projection of the first gate line on the substrate is away from the orthographic projection of the first conductive part on the substrate; and the orthographic projection of the second reset signal line on the substrate is located on the side where the orthographic projection of the second enable signal line on the substrate is away from the orthographic projection of the third enable signal line on the substrate.

[0075] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, the driving transistor being configured to provide a driving current to an electrode portion according to its gate voltage, and the display panel further includes:

[0076] A first source / drain layer is located between the substrate and the electrode layer. The first source / drain layer includes a third bridging portion, which is connected to the gate of the driving transistor through a via.

[0077] The second source / drain layer is located between the first source / drain layer and the electrode layer. The second source / drain layer includes a data line and a ninth bridging portion. The data line extends along a second direction in the orthogonal projection on the substrate. The data line is used to provide data signals to the pixel driving circuit. The ninth bridging portion is connected to the pixel driving circuit and the first electrode portion through vias.

[0078] Wherein, the second direction is the column direction, and the orthographic projection of the ninth bridging part in the column pixel driving circuit on the substrate is located between the orthographic projection of the data line connected to the adjacent column pixel driving circuit on the substrate and the orthographic projection of the third bridging part in the column pixel driving circuit on the substrate.

[0079] Furthermore, in the same pixel driving circuit, the orthographic projection of the ninth bridging portion on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite each other in a first direction, and the first direction intersects with the second direction.

[0080] In one exemplary embodiment of this disclosure, the ninth bridging portion includes a first via connection portion, a second via connection portion, and an extension portion connected to one end of the second via connection portion away from the first via connection portion;

[0081] The first via connection portion is connected to the pixel driving circuit through a via, and the second via connection portion is connected to the first electrode portion through a via;

[0082] In the same pixel driving circuit, the orthographic projection of the extension on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite to each other in the first direction.

[0083] In one exemplary embodiment of this disclosure, at least a portion of the multiple gate lines include multiple gate line segments, and the orthographic projections of the multiple gate line segments on the substrate extend along a first direction and are spaced apart along the first direction;

[0084] The display panel also includes:

[0085] A first source / drain layer is located between the first gate layer and the electrode layer. The first source / drain layer includes a gate connection line. The orthogonal projection of the gate connection line on the substrate extends along a first direction, and the gate connection line connects multiple gate segments in the same gate line through vias.

[0086] In one exemplary embodiment of this disclosure, the display panel further includes:

[0087] The second planarization layer is located between the substrate and the electrode layer;

[0088] The second passivation layer is located between the second planarization layer and the electrode layer;

[0089] The second passivation layer has a first slot formed thereon, and the orthographic projection of the first slot on the substrate is located between the orthographic projections of two adjacent electrode portions on the substrate.

[0090] A second slot is formed on the second planarization layer. The orthographic projection of the second slot on the substrate and the orthographic projection of the first slot on the substrate at least partially overlap. The second slot includes first sidewalls disposed opposite to each other in the distribution direction of the two adjacent electrodes. At least one of the first sidewalls forms a lateral recess. The orthographic projection of the second passivation layer on the substrate covers the orthographic projection of the recess on the substrate.

[0091] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0092] According to one aspect of this disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit is used to form a pixel driving circuit in the above-mentioned display panel, the pixel driving circuit comprising:

[0093] The driving circuit connects a first node, a first power line, and a third node. The driving circuit is used to input driving current to the third node using the first power line according to the voltage of the first node.

[0094] The first light-emitting control circuit is connected to the third node, the first electrode of the light-emitting unit, and the enable signal line. The first light-emitting control circuit is used to respond to the signal of the enable signal line to connect the third node and the first electrode of the light-emitting unit.

[0095] A voltage regulator circuit, connected to the first node and the enable signal line, is used to stabilize the voltage of the first node according to the signal on the enable signal line.

[0096] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0097] The second light-emitting control circuit is connected to the reference voltage line and the fourth node. The second light-emitting control circuit is used to respond to a control signal to transmit the signal of the reference voltage line to the fourth node.

[0098] A first reset circuit is connected to a first initial signal line and a first node. The first reset circuit is used to respond to a control signal to transmit the signal of the first initial signal line to the first node.

[0099] The second reset circuit is connected to the first electrode of the light-emitting unit and the second initial signal line. The second reset circuit is used to respond to a control signal to transmit the signal of the second initial signal line to the first electrode of the light-emitting unit.

[0100] A third reset circuit is connected to a reference voltage line and a fourth node. The third reset circuit is used to respond to a control signal to transmit the signal of the reference voltage line to the fourth node.

[0101] A data writing circuit is connected to a data line and a fourth node. The data writing circuit is used to respond to a control signal to transmit the signal of the data line to the fourth node.

[0102] A compensation circuit is provided to connect the first node and the third node, and the compensation circuit is used to respond to a control signal to connect the first node and the third node.

[0103] A coupling circuit is connected between the first node and the fourth node, the coupling circuit being used to couple voltage changes of the fourth node to the first node.

[0104] In one exemplary embodiment of this disclosure, the driving circuit includes:

[0105] The driving transistor has its first terminal connected to the first power supply line, its second terminal connected to the third node, and its gate connected to the first node.

[0106] The first light-emitting control circuit includes:

[0107] The sixth transistor has its first electrode connected to the third node, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the enable signal line.

[0108] The voltage regulator circuit includes:

[0109] The ninth transistor has its first electrode connected to the first node, its gate connected to the enable signal line, and its second electrode floating.

[0110] The second light-emitting control circuit is also connected to the enable signal line. The second light-emitting control circuit is used to respond to the signal from the enable signal line to transmit the signal from the reference voltage line to the fourth node. The second light-emitting control circuit includes:

[0111] The eighth transistor has its first terminal connected to the reference voltage line, its second terminal connected to the fourth node, and its gate connected to the enable signal line.

[0112] The first reset circuit is also connected to a first reset signal line. The first reset circuit is used to respond to the signal of the first reset signal line to transmit the signal of the first initial signal line to the fourth node. The first reset circuit includes:

[0113] The first transistor has a first terminal connected to the first initial signal line, a second terminal connected to the fourth node, and a gate connected to the first reset signal line.

[0114] The second reset circuit is also connected to the first reset signal line. The second reset circuit is used to respond to the signal of the first reset signal line to transmit the signal of the second initial signal line to the first electrode of the light-emitting unit. The second reset circuit includes:

[0115] The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the first reset signal line.

[0116] The third reset circuit is also connected to the first reset signal line. The third reset circuit is used to respond to the signal of the first reset signal line to transmit the signal of the reference voltage line to the fourth node. The third reset circuit includes:

[0117] The fifth transistor has its first terminal connected to the reference voltage line, its second terminal connected to the fourth node, and its gate connected to the first reset signal line.

[0118] The data writing circuit is also connected to the first gate line, and the data writing circuit is used to respond to the signal of the first gate line to transmit the signal of the data line to the fourth node. The data writing circuit includes:

[0119] The fourth transistor has its first terminal connected to the data line, its second terminal connected to the fourth node, and its gate connected to the first gate line.

[0120] The compensation circuit is also connected to the first gate line, and the compensation circuit is used to connect the first node and the third node in response to a signal from the first gate line. The compensation circuit includes:

[0121] The second transistor has its first terminal connected to the first node, its second terminal connected to the third node, and its gate connected to the first gate line.

[0122] The coupling circuit includes:

[0123] The capacitor has its first electrode connected to the first node and its second electrode connected to the fourth node.

[0124] According to one aspect of this disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit is used to form a pixel driving circuit in the above-mentioned display panel, the pixel driving circuit comprising:

[0125] A driving circuit is connected to a first node, a second node, and a third node. The driving circuit is used to provide a driving current to the third node through the second node based on the voltage of the first node.

[0126] A first light-emitting control circuit is connected to the third node, the fourth node, and the first enable signal line. The first light-emitting control circuit is used to respond to the signal of the first enable signal line to connect the third node and the fourth node.

[0127] The second light-emitting control circuit is connected to the fourth node, the second electrode part, and the second enable signal line. The second light-emitting control circuit is used to respond to the signal of the second enable signal line to connect the second electrode part and the fourth node.

[0128] The third light-emitting control circuit is connected to the fourth node, the third enable signal line, and the first electrode. The third light-emitting control circuit is used to respond to the signal of the third enable signal line to connect the fourth node and the first electrode.

[0129] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0130] A compensation circuit is provided to connect the first node and the third node, and the compensation circuit is used to respond to a control signal to connect the first node and the third node.

[0131] A data writing circuit is connected to the second node and the data line. The data writing circuit is used to respond to a control signal to transmit the data signal on the data line to the second node.

[0132] A first reset circuit is connected to the first node and a first initial signal line. The first reset circuit is used to respond to a control signal to transmit a signal on the first initial signal line to the first node.

[0133] The second reset circuit is connected to the second electrode section and the second initial signal line. The second reset circuit is used to respond to a control signal to transmit the signal of the second initial signal line to the second electrode section.

[0134] A storage circuit is connected to the first node, and the storage circuit is used to store the voltage of the first node;

[0135] The first light-emitting control circuit is also connected to the second node and the first power line. The first light-emitting control circuit is also used to respond to a control signal to connect the first power line and the second node.

[0136] In one exemplary embodiment of this disclosure, the driving circuit includes:

[0137] A driving transistor is configured such that its gate is connected to the first node, its first electrode is connected to the second node, and its second electrode is connected to the third node.

[0138] The first light-emitting control circuit is also connected to a first enable signal line. The first light-emitting control circuit is used to respond to a signal from the first enable signal line to connect the third node and the fourth node, and to respond to a signal from the first enable signal line to connect the first power line and the second node. The first light-emitting control circuit includes:

[0139] The fifth transistor has its first terminal connected to the first power supply line, its second terminal connected to the second node, and its gate connected to the first enable signal line.

[0140] The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the first enable signal line.

[0141] The second light-emitting control circuit includes:

[0142] The eighth transistor has its first electrode connected to the fourth node, its second electrode connected to the second electrode portion, and its gate connected to the second enable signal line.

[0143] The third light-emitting control circuit includes:

[0144] The ninth transistor has its first electrode connected to the fourth node, its second electrode connected to the first electrode portion, and its gate connected to the third enable signal line.

[0145] The compensation circuit is also connected to a first gate line, and the compensation circuit is used to connect the first node and the third node in response to a signal from the first gate line. The compensation circuit includes:

[0146] The second transistor has a first terminal connected to the first node, a second terminal connected to the third node, and a gate connected to the first gate line.

[0147] The data writing circuit is also connected to a first gate line, and the data writing circuit is used to respond to a signal from the first gate line to transmit a data signal on the data line to the second node. The data writing circuit includes:

[0148] The fourth transistor has its first terminal connected to the data line, its second terminal connected to the second node, and its gate connected to the first gate line.

[0149] The first reset circuit is also connected to a first reset signal line. The first reset circuit is used to transmit the signal on the first initial signal line to the first node in response to the signal on the first reset signal line. The first reset circuit includes:

[0150] The first transistor has a first terminal connected to the first initial signal line, a second terminal connected to the first node, and a gate connected to the first reset signal line.

[0151] The second reset circuit is also connected to a second reset signal line. The second reset circuit is used to respond to the signal of the second reset signal line to transmit the signal of the second initial signal line to the second electrode portion. The second reset circuit includes:

[0152] The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the second electrode portion, and its gate connected to the second reset signal line.

[0153] The storage circuit includes:

[0154] The capacitor has its first electrode connected to the first node and its second electrode connected to the first power line.

[0155] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0156] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0157] Figure 1 is a partial structural schematic diagram of a display panel in an exemplary embodiment of the present disclosure;

[0158] Figure 2 is a partial cross-sectional view of the display panel of this disclosure along the location of the dashed line AA in Figure 1;

[0159] Figure 3 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0160] Figure 4 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 3;

[0161] Figure 5 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0162] Figure 6 is a structural layout of the active layer in the display panel shown in Figure 5;

[0163] Figure 7 is a structural layout of the first gate layer in the display panel shown in Figure 5;

[0164] Figure 8 is a structural layout of the second gate layer in the display panel shown in Figure 5;

[0165] Figure 9 is a structural layout of the first source / drain layer in the display panel shown in Figure 5;

[0166] Figure 10 is a structural layout of the second source / drain layer in the display panel shown in Figure 5;

[0167] Figure 11 is a structural layout of the electrode layer and pixel definition layer in the display panel shown in Figure 5;

[0168] Figure 12 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 5;

[0169] Figure 13 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 5.

[0170] Figure 14 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 5.

[0171] Figure 15 is a structural layout of the active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 5.

[0172] Figure 16 is a partial cross-sectional view of the display panel shown in Figure 5, cut along the dashed line BB.

[0173] Figure 17 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0174] Figure 18 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 17;

[0175] Figure 19 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 17;

[0176] Figure 20 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0177] Figure 21 is a structural layout of the active layer in the display panel shown in Figure 20;

[0178] Figure 22 is a structural layout of the first gate layer in the display panel shown in Figure 20;

[0179] Figure 23 is a structural layout of the second gate layer in the display panel shown in Figure 20;

[0180] Figure 24 is a structural layout of the first source / drain layer in the display panel shown in Figure 20;

[0181] Figure 25 is a structural layout of the second source / drain layer in the display panel shown in Figure 20;

[0182] Figure 26 is a structural layout of the electrode layer and pixel definition layer in the display panel shown in Figure 20;

[0183] Figure 27 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 20;

[0184] Figure 28 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 20;

[0185] Figure 29 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 20;

[0186] Figure 30 is a structural layout of the active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 20.

[0187] Figure 31 is a partial cross-sectional view of the display panel shown in Figure 20, cut along the dashed line CC.

[0188] Figure 32 is a partial cross-sectional view of another exemplary embodiment of the display panel of this disclosure. Detailed Implementation

[0189] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0190] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0191] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0192] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0193] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0194] This exemplary embodiment first provides a display panel, as shown in FIG1, which is a partial structural schematic diagram of an exemplary embodiment of the display panel disclosed herein. The display panel includes a plurality of pixel units, and each pixel unit includes a plurality of sub-pixel units. FIG1 shows a structural layout of the electrode layer and pixel definition layer in a pixel unit of the display panel. The pixel unit may include three sub-pixel units: an R sub-pixel unit, a G sub-pixel unit, and a B sub-pixel unit. As shown in FIG1, the display panel further includes: a substrate; an electrode layer; and a pixel definition layer. The electrode layer is located on one side of the substrate. The sub-pixel unit includes at least two electrode portions located on the electrode layer. The two electrode portions respectively form a first electrode portion D1 and a second electrode portion D2. For example, as shown in FIG1, the R sub-pixel unit includes a first electrode portion R1 and a second electrode portion R2; the G sub-pixel unit includes a first electrode portion G1 and a second electrode portion G2; and the B sub-pixel unit includes a first electrode portion B1 and a second electrode portion B2. The first electrode portion and the second electrode portion in the same sub-pixel unit are spaced apart, and the first electrode portion and the second electrode portion in the same sub-pixel unit are respectively used to form the first electrode of a light-emitting unit of the same color. For example, first electrode portion R1 and second electrode portion R2 are spaced apart, first electrode portion G1 and second electrode portion G2 are spaced apart, first electrode portion B1 and second electrode portion B2 are spaced apart, first electrode portion R1 and second electrode portion R2 are respectively used to form the first electrode of the red light-emitting unit, first electrode portion G1 and second electrode portion G2 are respectively used to form the first electrode of the green light-emitting unit, and first electrode portion B1 and second electrode portion B2 are respectively used to form the first electrode of the blue light-emitting unit. A pixel definition layer is located on the side of the electrode layer opposite to the substrate. Multiple pixel openings Ph are formed on the pixel definition layer. The electrode portions and pixel openings are correspondingly arranged, and the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of its corresponding electrode portion on the substrate. In the same sub-pixel unit, the number of pixel openings corresponding to the first electrode portion is greater than the number of pixel openings corresponding to the second electrode portion, and the area of ​​the orthographic projection of a single pixel opening Ph corresponding to the first electrode portion on the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening Ph corresponding to the second electrode portion on the substrate.For example, the number of pixel openings corresponding to the first electrode portion R1 is greater than the number of pixel openings corresponding to the second electrode portion R2, and the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion R1 on the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion R2 on the substrate; the number of pixel openings corresponding to the first electrode portion G1 is greater than the number of pixel openings corresponding to the second electrode portion G2, and the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion G1 on the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion G2 on the substrate; the number of pixel openings corresponding to the first electrode portion B1 is greater than the number of pixel openings corresponding to the second electrode portion B2, and the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion B1 on the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion B2 on the substrate.

[0195] In this exemplary embodiment, since the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion D1 onto the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion D2 onto the substrate, the light-emitting angle of the light-emitting unit formed by the first electrode portion D1 is smaller than the light-emitting angle of the light-emitting unit formed by the second electrode portion D2. The first electrode portion D1 can form the first electrode of the anti-peeping light-emitting unit, and the second electrode portion D2 can form the first electrode of the shared light-emitting unit. The display panel can switch between anti-peeping display and normal display modes by controlling the anti-peeping light-emitting unit and the shared light-emitting unit to emit light in a time-division manner.

[0196] In this exemplary embodiment, as shown in FIG1, in the same sub-pixel unit, the ratio of the number of individual pixel openings corresponding to the first electrode portion D1 to the number of individual pixel openings corresponding to the second electrode portion D2 is greater than or equal to 2 and less than or equal to 20. For example, the ratio of the number of individual pixel openings corresponding to the first electrode portion D1 to the number of individual pixel openings corresponding to the second electrode portion D2 can be equal to 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, etc.

[0197] In this exemplary embodiment, as shown in FIG1, in the same sub-pixel unit, the size of the orthogonal projection of the single pixel opening corresponding to the first electrode portion D1 onto the substrate in the first direction X is smaller than the size of the orthogonal projection of the single pixel opening corresponding to the second electrode portion D2 onto the substrate in the first direction X, where the first direction X is the row direction. This arrangement allows the anti-peeping light-emitting unit to have a smaller light-emitting angle in the row direction than the shared light-emitting unit in the row direction, thereby enabling the anti-peeping light-emitting unit to achieve an anti-peeping effect at least in the horizontal direction.

[0198] In this exemplary embodiment, as shown in FIG1, the orthographic projection of the single pixel opening Ph corresponding to the first electrode portion D1 on the substrate can be a circle. It should be understood that in other exemplary embodiments, the orthographic projection of the pixel opening Ph corresponding to the first electrode portion D1 on the substrate can also be other shapes. For example, the orthographic projection of the single pixel opening Ph corresponding to the first electrode portion D1 on the substrate can also be an ellipse, a rectangle, an irregular shape, etc.

[0199] In this exemplary embodiment, as shown in FIG1, the second electrode portion D2 is provided with one pixel opening Ph. It should be understood that in other exemplary embodiments, the second electrode portion D2 may also be provided with multiple pixel openings Ph.

[0200] In this exemplary embodiment, as shown in FIG1, the pixel opening Ph corresponding to the second electrode portion D2 forms a second pixel opening Ph2. The orthographic projection of the second pixel opening Ph2 on the substrate has an arc-shaped chamfer Hd, and the arc-shaped chamfer Hd on the second pixel opening Ph2 is located on its side facing the adjacent second pixel opening Ph2. In this exemplary embodiment, since two sets of light-emitting units are provided in a sub-pixel unit, the design gap between the light-emitting units is small. At the same time, since there is a gap between the mask and the pixel definition layer when depositing the light-emitting layer in the pixel opening, the light-emitting layer will be deposited outside the pixel opening, which can easily lead to the light-emitting layer being deposited inside the pixel opening corresponding to other color light-emitting layers, thereby causing color shift in the pixel unit. This exemplary embodiment provides an arc-shaped chamfer on the side of the second pixel opening Ph2 facing other adjacent second pixel openings Ph2. This arc-shaped chamfer can reduce the distance between adjacent second pixel openings Ph2, thereby reducing the risk of the light-emitting layer being deposited inside the pixel opening corresponding to other color light-emitting layers.

[0201] In this exemplary embodiment, as shown in FIG1, in the same pixel unit, the orthographic projections of multiple first electrode portions D1 on the substrate and the orthographic projections of multiple second electrode portions D2 on the substrate are located in different regions. This arrangement allows both the anti-peeping light-emitting unit and the shared light-emitting unit in the same pixel unit to have a better color mixing effect.

[0202] Figure 2 shows a partial cross-sectional view of the display panel of this disclosure along the location of the dashed line AA in Figure 1. The display panel may further include a light-emitting layer Lx and a common electrode layer Cah. The light-emitting layer Lx is located within the pixel opening formed by the pixel definition layer PDL, and the light-emitting layer Lx emits light under the voltage of the first electrode portion R1 and the common electrode layer Cah. As shown in Figure 2, the display panel may further include an encapsulation layer Fz, a light-shielding layer BM, and a light-concentrating structure Ln. The orthographic projection of the light-shielding layer BM on the substrate surrounds the orthographic projection of the pixel opening on the substrate. The light-concentrating structure Ln is located on the side of the anti-peeping light-emitting unit facing away from the substrate. Both the light-shielding layer BM and the light-concentrating structure Ln can reduce the light-emitting angle of the anti-peeping light-emitting unit.

[0203] In this exemplary embodiment, a light-shielding layer BM may or may not be provided around the shared light-emitting unit. A light-focusing structure Ln may or may not be provided on the side of the shared light-emitting unit away from the substrate. When the light-focusing structure Ln is provided on the side of the shared light-emitting unit away from the substrate, the light-focusing structure Ln located above the shared light-emitting unit can focus the light emitted by the shared light-emitting unit only in the second direction Y, where the second direction Y is the column direction.

[0204] In this exemplary embodiment, the sub-pixel unit may include two pixel driving circuits, which can be used to provide driving current to the first electrode portion D1 and the second electrode portion D2, respectively.

[0205] Figure 3 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit includes: a driving circuit 1, a first light-emitting control circuit 21, and a voltage regulator circuit 9. The driving circuit 1 is connected to a first node N1, a first power line VDD, and a third node N3. The driving circuit 1 is used to input a driving current to the third node N3 via the first power line VDD according to the voltage of the first node N1. The first light-emitting control circuit 21 is connected to the third node N3, the first electrode of the light-emitting unit L, and an enable signal line EM. The first light-emitting control circuit 21 is used to connect the third node N3 and the first electrode of the light-emitting unit L in response to the signal of the enable signal line EM. The voltage regulator circuit 9 is connected to the first node N1 and the enable signal line EM and is used to stabilize the voltage of the first node N1 according to the signal on the enable signal line EM.

[0206] In this exemplary embodiment, as shown in FIG3, the pixel driving circuit further includes: a second light-emitting control circuit 202, a first reset circuit 4, a second reset circuit 3, a third reset circuit 5, a data writing circuit 6, a compensation circuit 7, and a coupling circuit 8. The second light-emitting control circuit 202 is connected to a reference voltage line Vref and a fourth node N4, and is used to respond to a control signal to transmit the signal of the reference voltage line Vref to the fourth node N4; the first reset circuit 4 is connected to a first initial signal line Vinit1 and a first node N1, and is used to respond to a control signal to transmit the signal of the first initial signal line Vinit1 to the first node N1; the second reset circuit 3 is connected to the first electrode of the light-emitting unit L and a second initial signal line Vinit2, and is used to respond to a control signal to transmit the signal of the second initial signal line Vinit2 to the first electrode of the light-emitting unit L; the third reset circuit 5, the second reset circuit 6, the third reset circuit 7, the fourth reset circuit 8, the fifth reset circuit 9, the sixth reset circuit 102, the seventh reset circuit 102, the eighth reset circuit 102, the ninth reset circuit 102, the eleventh ... Bit circuit 5 is connected to reference voltage line Vref and fourth node N4. The third reset circuit 5 is used to respond to a control signal to transmit the signal of reference voltage line Vref to fourth node N4. Data writing circuit 6 is connected to data line Da and fourth node. The data writing circuit 6 is used to respond to a control signal to transmit the signal of data line Da to fourth node. Compensation circuit 7 is connected to first node N1 and third node N3. The compensation circuit 7 is used to respond to a control signal to connect first node N1 and third node N3. Coupling circuit 8 is connected between first node N1 and fourth node. The coupling circuit 8 is used to couple the voltage change of fourth node to first node N1.

[0207] In this exemplary embodiment, as shown in FIG3, the driving circuit includes: a driving transistor T3, the first electrode of the driving transistor T3 is connected to the first power supply line VDD, the second electrode is connected to the third node N3, and the gate is connected to the first node N1; the first light-emitting control circuit 21 includes: a sixth transistor T6, the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal line EM; the voltage regulator circuit 9 includes: a ninth transistor T9, the first electrode of the ninth transistor T9 is connected to the first node N1, the gate is connected to the enable signal line EM, and the second electrode of the ninth transistor T9 is floating, which can be understood as the second electrode of the ninth transistor T9 not being connected to other structures.

[0208] In this exemplary embodiment, as shown in FIG3, the second light-emitting control circuit 202 is also connected to the enable signal line EM. The second light-emitting control circuit 202 is used to transmit the signal of the reference voltage line Vref to the fourth node N4 in response to the signal of the enable signal line EM. The second light-emitting control circuit 202 includes: an eighth transistor T8, the first terminal of the eighth transistor T8 is connected to the reference voltage line Vref, the second terminal is connected to the fourth node N4, and the gate is connected to the enable signal line EM; the first reset circuit 4 is also connected to the first reset signal line Re1. The first reset circuit 4 is used to transmit the signal of the first initial signal line Vini in response to the signal of the first reset signal line Re1. The signal t1 is transmitted to the fourth node N4. The first reset circuit 4 includes: a first transistor T1, the first terminal of which is connected to the first initial signal line Vinit1, the second terminal of which is connected to the fourth node, and the gate of which is connected to the first reset signal line Re1; the second reset circuit 3 is also connected to the first reset signal line Re1, and the second reset circuit 3 is used to respond to the signal of the first reset signal line Re1 to transmit the signal of the second initial signal line Vinit2 to the first electrode of the light-emitting unit L. The second reset circuit 3 includes: a seventh transistor T7, the first terminal of which is connected to the second initial signal line Vinit2, and the second terminal of which is connected to the first electrode of the light-emitting unit L. The first electrode of the optical unit L has its gate connected to the first reset signal line Re1; the third reset circuit 5 is also connected to the first reset signal line Re1, and is used to respond to the signal of the first reset signal line Re1 to transmit the signal of the reference voltage line Vref to the fourth node N4. The third reset circuit 5 includes: a fifth transistor T5, the first electrode of the fifth transistor T5 is connected to the reference voltage line Vref, the second electrode is connected to the fourth node N4, and the gate is connected to the first reset signal line Re1; the data writing circuit 6 is also connected to the first gate line Ga1, and is used to respond to the signal of the first gate line Ga1 to transmit the signal of the data line Da to the fourth node N4. The fourth node N4, the data writing circuit 6 includes: a fourth transistor T4, the first electrode of the fourth transistor T4 is connected to the data line Da, the second electrode is connected to the fourth node, and the gate is connected to the first gate line Ga1; the compensation circuit 7 is also connected to the first gate line Ga1, the compensation circuit 7 is used to respond to the signal of the first gate line Ga1 to connect the first node N1 and the third node N3, the compensation circuit 7 includes: a second transistor T2, the first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate is connected to the first gate line Ga1; the coupling circuit 8 includes: a capacitor C, the first electrode of the capacitor C is connected to the first node N1, and the second electrode is connected to the fourth node. The second electrode of the light-emitting unit is connected to the second power line VSS.

[0209] In this exemplary embodiment, as shown in FIG3, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors.

[0210] Figure 4 shows the timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 3. Ga1 represents the timing diagram of the signal on the first gate line, EM represents the timing diagram of the signal on the enable signal line, and Re1 represents the timing diagram of the signal on the first reset signal line. This pixel driving circuit driving method may include a reset stage t1, a data writing stage t2, and a light emission stage t3.

[0211] During the reset phase t1, the first reset signal line Re1 outputs a low-level signal, the first transistor T1, the fifth transistor T5, and the seventh transistor T7 are turned on, the first initial signal line Vinit1 inputs the first initial signal to the first node N1, the second initial signal line Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit, and the reference voltage line Vref inputs the reference voltage Vf to the fourth node N4.

[0212] During the data writing phase t2, the first gate line Ga1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the first power supply line VDD inputs a compensation voltage Vdd+Vth to the first node N1, where Vdd is the voltage of the first power supply line VDD and Vth is the threshold voltage of the driving transistor T3. Simultaneously, the data line Da inputs a data signal to the fourth node N4, with a voltage of Vdata.

[0213] During the light-emitting stage t3: The enable signal line EM outputs a low-level signal, turning on the sixth transistor T6 and the eighth transistor T8. The reference voltage line Vref inputs a reference voltage Vf to the fourth node N4, changing the voltage at the fourth node N4 from Vdata to Vf. Under the coupling effect of capacitor C, the voltage at the first node N1 changes from Vdd + Vth to Vf - Vdata + Vdd + Vth. The output current of the driving transistor is I = (μWCox / 2L)(Vgs - Vth). 2 =(μWCox / 2L)(Vf-Vdata+Vdd+Vth-Vdd-Vth) 2This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Here, I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage. A parasitic capacitance is formed between the gate and the first electrode of the ninth transistor T9. Under the action of this parasitic capacitance, the DC signal of the enable signal line EM during the light-emitting phase can stabilize the voltage of the first node N1, thereby avoiding changes in the brightness of the light-emitting unit due to voltage fluctuations at the first node N1.

[0214] This exemplary embodiment allows the display panel to switch between privacy-protected display and normal display by using two pixel driving circuits in the sub-pixel unit to drive the first electrode and the second electrode in a time-division manner. For example, this exemplary embodiment can control the privacy-protected light-emitting unit and the shared light-emitting unit to be driven in a time-division manner by controlling the signals on the enable signal lines corresponding to the two pixel driving circuits in the sub-pixel unit. Specifically, when the privacy-protected light-emitting unit is controlled to emit light, the enable signal line corresponding to the pixel driving circuit connected to the second electrode continuously outputs a high level; when the shared light-emitting unit is controlled to emit light, the enable signal line corresponding to the pixel driving circuit connected to the first electrode continuously outputs a high level. Furthermore, the display panel can also control the privacy-protected light-emitting unit and the shared light-emitting unit to emit light simultaneously.

[0215] This exemplary embodiment also provides another display panel, which may include a substrate, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, an electrode layer, and a pixel definition layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 5-15, Figure 5 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 6 is a structural layout diagram of the active layer in the display panel shown in Figure 5, Figure 7 is a structural layout diagram of the first gate layer in the display panel shown in Figure 5, Figure 8 is a structural layout diagram of the second gate layer in the display panel shown in Figure 5, Figure 9 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 5, Figure 10 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 5, Figure 11 is a structural layout diagram of the electrode layer and pixel definition layer in the display panel shown in Figure 5, Figure 12 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 5, Figure 13 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 5, Figure 14 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 5, and Figure 15 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 5.

[0216] As shown in Figure 15, the display panel may include multiple pixel driving circuits Pix arrayed in a first direction X and a second direction Y. As shown in Figure 5, in this exemplary embodiment, the sub-pixel unit includes two pixel driving circuits as shown in Figure 3, which are respectively connected to the first electrode portion D1 and the second electrode portion D2. The two pixel driving circuits in the sub-pixel unit can be arranged adjacent to each other in the second direction Y. Specifically, the first gate line Ga1 corresponding to two adjacent rows of pixel driving circuits in the same row of sub-pixel units can be connected to the same output terminal of the gate driving circuit, and the first reset signal line Re1 corresponding to two adjacent rows of pixel driving circuits in the same row of sub-pixel units can be connected to the same output terminal of the gate driving circuit. That is, two adjacent rows of pixel driving circuits in the same row of sub-pixel units can scan simultaneously, and two adjacent rows of pixel driving circuits in the same row of sub-pixel units can achieve time-division emissivity by receiving different signals on different enable signal lines.

[0217] As shown in Figures 5, 6, and 12, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, a nineteenth active section 719, a twentieth active section 720, and a first initial signal line Vinit1. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 731 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form a driving transistor T3. The channel region of the fourth active part 74 can be used to form the channel region of the fourth transistor T4; the fifth active part 75 can be used to form the channel region of the fifth transistor T5; the sixth active part 76 can be used to form the channel region of the sixth transistor T6; the seventh active part 77 can be used to form the channel region of the seventh transistor T7; the eighth active part 78 can be used to form the channel region of the eighth transistor T8; the ninth active part 79 can be used to form the channel region of the ninth transistor T9; the tenth active part 710 is connected to the end of the seventh active part 77 away from the sixth active part 76; the eleventh active part 711 is connected between the sixth active part 76 and the seventh active part 77; the twelfth active part 712 is connected between the third sub-active part 723 and the fourth sub-active part 724; the thirteenth active part 713 and the fourteenth active part 714 are respectively connected to the two ends of the fourth active part 74; the fifteenth active part... Part 715 is connected to the end of the third active part 73 away from the sixth active part 76; the sixteenth active part 716 is connected between the fifth active part 75 and the eighth active part 78; the seventeenth active part 717 is connected between the fifth active part 75 and the eighth active part 78, and the seventeenth active part 717 is connected to the end of the eighth active part 78 away from the sixteenth active part 716, and the seventeenth active part 717 is connected to the end of the fifth active part 75 away from the sixteenth active part 716; the eighteenth active part 718 is connected to the end of the second active part 72 away from the third active part 73; the nineteenth active part 719 is connected between the ninth active part 79 and the first active part 71; the twentieth active part 720 is connected between the first initial signal line Vinit1 and the first active part 71; the first initial signal line Vinit1 is connected to the end of the first active part 71 away from the ninth active part 79.

[0218] As shown in Figures 5, 6, and 12, the active layer can be formed of polycrystalline silicon. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type low-temperature polycrystalline silicon thin-film transistors. In this exemplary embodiment, the first transistor T1 and the second transistor T2 are both dual-gate structures. The dual-gate transistor has two spaced-apart channel regions, resulting in a smaller turn-off leakage current. This configuration can reduce the leakage current through the first and second transistors at the gate of the driving transistor, thereby improving the voltage stability of the gate of the driving transistor T3.

[0219] As shown in Figures 5, 7, and 12, the first gate layer may include: a first conductive portion 11 and multiple gate lines, among which a first reset signal line Re1, a first gate line Ga1, and an enable signal line EM. The orthographic projections of the first gate line Ga1, the enable signal line EM, and the first reset signal line Re1 on the substrate can all extend along a first direction X. The orthographic projection of the first gate line Ga1 on the substrate covers the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line Ga1 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line Ga1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projections of the sixth active portion 76, the eighth active portion 78, and the ninth active portion 79 on the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9, respectively. The first reset signal line Re1 may include multiple first reset signal segments Re11. The orthographic projections of the multiple first reset signal segments Re11 on the substrate can extend along the first direction X and be spaced apart along the first direction X. The orthographic projections of the first reset signal segments Re11 on the substrate cover the orthographic projections of the first active portion 71, the fifth active portion 75, and the seventh active portion 77 on the substrate. Partial structures of the first reset signal segments Re11 can be used to form the gates of the first transistor T1, the fifth transistor T5, and the seventh transistor T7, respectively. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform conductive processing on the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductive structure.

[0220] As shown in Figures 5, 8, and 13, the second gate layer may include: a second conductive portion 22, a second initial signal line Vinit2, and a reference voltage line Vref. The orthographic projection of the second conductive portion 22 onto the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 onto the substrate. The second conductive portion 22 is used to form the second electrode of the capacitor C. The orthographic projections of the second initial signal line Vinit2 and the reference voltage line Vref onto the substrate both extend along the first direction X.

[0221] As shown in Figures 5, 9, and 14, the first source / drain layer may include a first bridging section 31, a second bridging section 32, a third bridging section 33, a fourth bridging section 34, a fifth bridging section 35, a sixth bridging section 36, a seventh bridging section 37, an eighth bridging section 38, a first power supply line VDD, and multiple gate connection lines, including a first reset connection line 3Re1 and a first gate connection line 3G1. The first bridging section 31 connects to the tenth active section 710 and the second initial signal line Vinit2 via vias, thereby connecting the second initial signal line Vinit2 and the first terminal of the seventh transistor. The second bridging section 32 connects to the eleventh active section 711 via vias, thereby connecting the second terminal of the sixth transistor and the second terminal of the seventh transistor. The third bridging portion 33 can be connected to the nineteenth active portion 719, the first conductive portion 11, and the eighteenth active portion 718 via vias, to connect the second electrode of the first transistor T1, the gate of the driving transistor T3, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9. An opening 221 is formed on the second conductive portion 22, and a via connecting the first conductive portion 11 and the third bridging portion 33 is disposed through the opening 221. The fourth bridging portion 34 can be connected to the seventeenth active portion 717, the second conductive portion 22, and the fourteenth active portion 714 via vias, to connect the second electrode of the fourth transistor, the second electrode of the fifth transistor T5, the second electrode of the eighth transistor T8, and the second electrode of the capacitor C. The fifth bridging portion 35 can be connected to the fifteenth active portion 715 via a via, to connect the first electrode of the driving transistor T3. The sixth bridging portion 36 can be connected to the thirteenth active portion 713 via a via, to connect the first electrode of the fourth transistor T4. The seventh bridging section 37 can connect the reference voltage line Vref and the sixteenth active section 716 via vias, respectively, to connect the reference voltage line Vref and the first terminal of the fifth transistor T5 and the first terminal of the eighth transistor T8. The eighth bridging section 38 connects to the twentieth active section 720 via vias. The orthographic projections of the first reset connection line 3Re1, the first power line VDD, and the first gate connection line 3G1 on the substrate extend along the first direction X. The first reset connection line 3Re1 connects to multiple first reset signal line segments Re11 located in the same first reset signal line via vias. The sheet resistance of the first source / drain layer is less than the sheet resistance of the first gate layer. In this exemplary embodiment, by connecting multiple first reset signal line segments Re11 through the first reset connection line 3Re1 located in the first source / drain layer, the resistance of the first reset signal line can be reduced, thereby reducing the voltage difference of the first reset signal line at different positions on the display panel and improving display uniformity. The first gate connection line 3G1 connects to the first gate line Ga1 via one or more vias. This setting can reduce the resistance of the first gate line, thereby reducing the voltage difference of the first gate line at different locations on the display panel.

[0222] It should be understood that, in other exemplary embodiments, other gate lines may also include multiple gate line segments spaced apart, wherein the orthographic projections of the multiple gate line segments on the substrate extend along the first direction X and are spaced apart along the first direction. Accordingly, multiple gate line segments in the same gate line can be connected by gate interconnects located in the first source / drain layer. Furthermore, in other exemplary embodiments, the first reset signal line may also be continuously arranged.

[0223] As shown in Figures 5, 10, and 15, the second source / drain layer may include a data line Da, a first power connection line 4VDD, a first initial connection line 4Vinit1, a second initial connection line 4Vinit2, a reference voltage connection line 4Vref, a second power line VSS, and a ninth bridge portion 49. The orthogonal projections of the data line Da, the first power connection line 4VDD, the first initial connection line 4Vinit1, the second initial connection line 4Vinit2, the reference voltage connection line 4Vref, and the second power line VSS onto the substrate all extend along the second direction Y. The data line Da can be connected to the sixth bridge portion 36 via a via to connect the data line Da and the first terminal of the fourth transistor T4. The first power connection line 4VDD can be connected to the fifth bridge portion 35 via a via to connect the first terminal of the driving transistor T3. Simultaneously, the first power connection line 4VDD can be connected to the intersecting first power line VDD via a via. The first power connection line 4VDD and the first power line VDD can form a mesh structure. The mesh structure of the first power lines has lower resistance, thereby reducing the voltage difference of the first power lines at different locations on the display panel. The first initial connection line 4Vinit1 can be connected to the eighth bridging portion 38 through a via, so that the first initial connection line 4Vinit1 and the intersecting first initial signal line Vinit1 can be connected. The first initial connection line 4Vinit1 and the first initial signal line Vinit can form a mesh structure. The first initial signal line Vinit in the mesh structure has a small resistance, thereby reducing the voltage difference of the first initial signal line Vinit at different positions on the display panel. The second initial connection line 4Vinit2 can be connected to the first bridging portion 31 through a via, so that the second initial connection line 4Vinit2 and the intersecting second initial signal line Vinit1 can be connected. The second initial connection line 4Vinit2 and the second initial signal line Vinit1 can form a mesh structure. The second initial signal line Vinit1 in the mesh structure has a small resistance, thereby reducing the voltage difference of the second initial signal line Vinit1 at different positions on the display panel. The reference voltage connection line 4Vref is connected to the seventh bridging portion 37 via a via, connecting the reference voltage connection line 4Vref and the intersecting reference voltage line Vref. The reference voltage connection line 4Vref and the reference voltage line Vref can form a grid structure. The grid structure of the reference voltage line Vref has lower resistance, thereby reducing the voltage difference of the reference voltage line Vref at different locations on the display panel. The signal lines with the aforementioned grid structure can all improve the display uniformity of the display panel. The second power line VSS can be connected to the common electrode layer via a via to reduce the voltage difference of the common electrode layer at different locations on the display panel. The ninth bridging portion 49 can be connected to the second bridging portion 32 via a via to connect to the second electrode of the sixth transistor.

[0224] As shown in Figures 5 and 11, the electrode layer may include multiple electrode portions. The red sub-pixel unit includes a first electrode portion R1 and a second electrode portion R2, the green sub-pixel unit includes a first electrode portion G1 and a second electrode portion G2, and the blue sub-pixel unit includes a first electrode portion B1 and a second electrode portion B2. Multiple pixel openings Ph are formed on the pixel definition layer. The electrode portions and pixel openings are correspondingly arranged, and the orthographic projection of each pixel opening onto the substrate lies within the orthographic projection of its corresponding electrode portion onto the substrate. Within the same sub-pixel unit, the number of pixel openings corresponding to the first electrode portion is greater than the number of pixel openings corresponding to the second electrode portion, and the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion onto the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion onto the substrate.

[0225] In this exemplary embodiment, as shown in FIG5-15, in the same pixel driving circuit, the orthogonal projection of the enable signal line EM on the substrate can be located between the orthogonal projection of the first conductive part 11 on the substrate and the orthogonal projection of the first reset signal line Re1 on the substrate.

[0226] In this exemplary embodiment, as shown in FIG5-15, in the same pixel driving circuit, the orthographic projection of the first gate line Ga1 on the substrate is located on the side of the orthographic projection of the first conductive part 11 on the substrate that is away from the orthographic projection of the enable signal line EM on the substrate.

[0227] In this exemplary embodiment, as shown in FIG5-15, the orthographic projection of the second bridging portion 32 in the pixel driving circuit of this column onto the substrate is located between the orthographic projection of the third bridging portion 33 in the pixel driving circuit of this column onto the substrate and the orthographic projection of the data line Da connected to the adjacent pixel driving circuit onto the substrate; and in the same pixel driving circuit, the orthographic projections of the second bridging portion 32 and the third bridging portion 33 onto the substrate are arranged opposite to each other in the first direction X. The second bridging portion 32 can shield the signal interference of the data line Da to the third bridging portion 33, thereby improving the voltage stability of the gate of the driving transistor T3.

[0228] In this exemplary embodiment, as shown in FIG5-15, the second bridging portion 32 includes a first via connection portion 321, a second via connection portion 322, and an extension portion 323 connected to one end of the second via connection portion 322 away from the first via connection portion 321. The first via connection portion 321 is connected to the pixel driving circuit through a via, and the second via connection portion 322 is connected to the electrode portion through a via. In the same pixel driving circuit, the orthographic projection of the extension portion 323 on the substrate and the orthographic projection of the third bridging portion 33 on the substrate are disposed opposite to each other in the first direction. This exemplary embodiment uses the extended portion 323 to shield the signal interference of the data line Da to the third bridging portion 33.

[0229] It should be noted that the relative arrangement of structures A and B in the first direction X can be understood as the area covered by structure A extending infinitely along the first direction X and the area covered by structure B extending infinitely along the first direction X at least partially overlap.

[0230] In this exemplary embodiment, as shown in FIG5-15, the orthographic projection of the fourth bridging portion 34 in the pixel driving circuit of this column onto the substrate is located between the orthographic projections of the third bridging portion 33 in the pixel driving circuit of this column and the data line Da connected to the pixel driving circuit of this column onto the substrate; and in the same pixel driving circuit, the orthographic projections of the fourth bridging portion 34 and the third bridging portion 33 onto the substrate are arranged opposite to each other in the first direction X. This arrangement can shield the signal interference of the data line Da to the third bridging portion 33 by the fourth bridging portion 34.

[0231] In this exemplary embodiment, as shown in Figures 5-15, the orthographic projection of the first power connection line 4VDD on the substrate is located between the orthographic projection of the data line Da connected to the same pixel driving circuit and the orthographic projection of the third bridging portion 33 on the substrate. The first power connection line 4VDD can shield the data line Da from signal interference to the third bridging portion 33. The orthographic projection of the second power line VSS on the substrate is located between the orthographic projection of the third bridging portion 33 in the same column of pixel driving circuits and the orthographic projection of the data line Da connected to the adjacent column of pixel driving circuits on the substrate. The second power line VSS can shield the data line Da from signal interference to the third bridging portion 33.

[0232] Figure 16 shows a partial cross-sectional view of the display panel shown in Figure 5, taken along the dashed line BB. The display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a dielectric layer 104, a first passivation layer 105, a first planarization layer 106, a second planarization layer 107, a second passivation layer 108, and a pixel definition layer (PDL). The substrate 100, buffer layer 101, active layer, first insulating layer 102, first gate layer, second insulating layer 103, second gate layer, dielectric layer 104, first source / drain layer, first passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, second passivation layer 108, electrode layer, and pixel definition layer (PDL) are sequentially stacked. The buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The first passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0233] In other exemplary embodiments, the sub-pixel unit may include a pixel driving circuit, which can be used to provide driving current to the first electrode portion D1 and the second electrode portion D2 in a time-division manner.

[0234] Figure 17 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit includes: a driving circuit 1, a first light-emitting control circuit 21, a second light-emitting control circuit 202, and a third light-emitting control circuit 203. The driving circuit is connected to a first node N1, a second node N2, and a third node N3. The driving circuit is used to provide a driving current to the third node N3 using the second node N2 based on the voltage of the first node N1. A first light-emitting control circuit 21 is connected to the third node N3, a fourth node N4, and a first enable signal line EM1. The first light-emitting control circuit 21 is used to connect the third node N3 and the fourth node N4 in response to the signal of the first enable signal line EM1. A second light-emitting control circuit 202 is connected to the fourth node N4, a second electrode, and a second enable signal line EM2. The second light-emitting control circuit 202 is used to connect the second electrode and the fourth node N4 in response to the signal of the second enable signal line EM2. A third light-emitting control circuit 203 is connected to the fourth node N4, a third enable signal line EM3, and a first electrode. The third light-emitting control circuit 203 is used to connect the fourth node N4 and the first electrode in response to the signal of the third enable signal line EM3. As shown in Figure 17, the first electrode portion is used to form the first electrode of the anti-peeping light-emitting unit L1, and the second electrode portion is used to form the first electrode of the shared light-emitting unit L2.

[0235] This exemplary embodiment can utilize a first light-emitting control circuit 21, a second light-emitting control circuit 202, and a third light-emitting control circuit 203 to drive the anti-peeping light-emitting unit L1 and the shared light-emitting unit L2 in a time-division manner. For example, when the first light-emitting control circuit 21 turns on the third node N3 and the fourth node N4, the second light-emitting control circuit 202 turns on the fourth node N4 and the second electrode, and the third light-emitting control circuit 230 turns off the fourth node N4 and the anti-peeping light-emitting unit L1, the driving circuit 1 drives the shared light-emitting unit L2 to emit light; when the first light-emitting control circuit 21 turns on the third node N3 and the fourth node N4, the third light-emitting control circuit 230 turns on the fourth node N4 and the anti-peeping light-emitting unit L1, and the second light-emitting control circuit 202 turns off the fourth node N4 and the second electrode, the driving circuit 1 drives the anti-peeping light-emitting unit L1 to emit light. Of course, in other exemplary embodiments, the first light-emitting control circuit 21, the second light-emitting control circuit 202, and the third light-emitting control circuit 203 can also be turned on simultaneously to achieve simultaneous emission of the anti-peeping light-emitting unit L1 and the shared light-emitting unit L2.

[0236] As shown in Figure 17, the pixel driving circuit may further include: a compensation circuit 7, a data writing circuit 6, a first reset circuit 4, a second reset circuit 3, and a storage circuit 8. Compensation circuit 7 is connected to the first node N1 and the third node N3, and is used to respond to a control signal to connect the first node N1 and the third node N3; data writing circuit 6 is connected to the second node N2 and data line Da, and is used to respond to a control signal to transmit the data signal on the data line Da to the second node N2; first reset circuit 4 is connected to the first node N1 and the first initial signal line Vinit1, and is used to respond to a control signal to transmit the signal on the first initial signal line Vinit1 to the first node N1; second reset circuit 3 is connected to the second electrode and the second initial signal line Vinit2, and is used to respond to a control signal to transmit the signal on the second initial signal line Vinit2 to the second electrode; storage circuit 8 is connected to the first node N1, and is used to store the voltage of the first node N1; the first light-emitting control circuit 21 is also connected to the second node N2 and the first power line VDD, and is also used to respond to a control signal to connect the first power line VDD and the second node N2.

[0237] As shown in Figure 17, the driving circuit includes: a driving transistor T3, the gate of which is connected to the first node N1, the first terminal of which is connected to the second node N2, and the second terminal of which is connected to the third node N3; the first light-emitting control circuit 21 is also connected to a first enable signal line EM1, the first light-emitting control circuit 21 being used to respond to the signal of the first enable signal line EM1 to connect the third node N3 and the fourth node N4, and to respond to the signal of the first enable signal line EM1 to connect the first power line VDD and the second node N2, the first light-emitting control circuit 21 including: a fifth transistor T5, a sixth transistor T6, and a fifth transistor T7. The first electrode of transistor T5 is connected to the first power supply line VDD, the second electrode is connected to the second node N2, and the gate is connected to the first enable signal line EM1; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the fourth node N4, and the gate is connected to the first enable signal line EM1; the second light-emitting control circuit 202 includes: an eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the fourth node N4, the second electrode is connected to the second electrode portion, and the gate is connected to the second enable signal line EM2; the third light-emitting control circuit 203 includes: a ninth transistor T9, the first electrode of the ninth transistor T9 is connected to the fourth node N4, the second electrode is connected to... The first electrode portion is connected to the third enable signal line EM3; the compensation circuit 7 is also connected to the first gate line Ga1, and the compensation circuit 7 is used to respond to the signal of the first gate line Ga1 to connect the first node N1 and the third node N3. The compensation circuit 7 includes: a second transistor T2, the first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate is connected to the first gate line Ga1; the data writing circuit is also connected to the first gate line Ga1, and the data writing circuit is used to respond to the signal of the first gate line Ga1 to transmit the data signal on the data line Da to the second node N2. The data writing circuit includes: a fourth transistor T4, the first terminal of the fourth transistor T4 is connected to the data line Da, the second terminal is connected to the second node N2, and the gate is connected to the first gate line Ga1; the first reset circuit 4 is also connected to the first reset signal line Re1, and the first reset circuit 4 is used to transmit the signal on the first initial signal line Vinit1 to the first node N1 in response to the signal of the first reset signal line Re1. The first reset circuit 4 includes: a first transistor T1, the first terminal of the first transistor T1 is connected to the first initial signal line Vinit1, the second terminal is connected to the first node N1, and the gate is connected to the first reset signal line Re1;The second reset circuit 3 is also connected to the second reset signal line Re2. The second reset circuit 3 is used to respond to the signal of the second reset signal line Re2 to transmit the signal of the second initial signal line Vinit2 to the second electrode portion. The second reset circuit 3 includes: a seventh transistor T7, the first electrode of which is connected to the second initial signal line Vinit2, the second electrode of which is connected to the second electrode portion, and the gate of which is connected to the second reset signal line Re2; the storage circuit 8 includes: a capacitor C, the first electrode of which is connected to the first node N1, and the second electrode of which is connected to the first power supply line VDD.

[0238] In this exemplary embodiment, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type transistors.

[0239] Figure 18 shows the timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 17. Here, EM1 represents the timing diagram of the signals on the first enable signal line, Re1 represents the timing diagram of the signals on the first reset signal line, Re2 represents the timing diagram of the signals on the second reset signal line, Ga1 represents the timing diagram of the signals on the first gate line, EM2 represents the timing diagram of the signals on the second enable signal line, and EM3 represents the timing diagram of the signals on the third enable signal line. This pixel driving circuit driving method may include a reset stage t1, a data writing stage t2, and a light emission stage t3.

[0240] During the reset phase t1, the first reset signal line Re1, the second enable signal line EM2, and the third enable signal line EM3 output low-level signals, and the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on. The first initial signal line Vinit1 inputs the first initial signal to the first node N1, and the second initial signal line Vinit2 inputs the second initial signal to the first electrode and the second electrode.

[0241] During the data writing phase t2, the first gate line Ga1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data line Da inputs a compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal on the data line and Vth is the threshold voltage of the driving transistor T3.

[0242] During the light-emitting stage t3: the first enable signal line EM1 and the third enable signal line EM3 output low-level signals, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, and the driving transistor T3 provides driving current to the first electrode, causing the anti-peeping light-emitting unit L1 to emit light. The output current of the driving transistor I = (μWCox / 2L)(Vgs-Vth)2 =(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; Vth is the driving transistor threshold voltage; and Vdd is the voltage on the first power supply line.

[0243] Figure 19 shows the timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 17. EM1 represents the timing diagram of the signals on the first enable signal line, Re1 represents the timing diagram of the signals on the first reset signal line, Re2 represents the timing diagram of the signals on the second reset signal line, Ga1 represents the timing diagram of the signals on the first gate line, EM2 represents the timing diagram of the signals on the second enable signal line, and EM3 represents the timing diagram of the signals on the third enable signal line. This pixel driving circuit driving method may include a reset stage t1, a data writing stage t2, and a light emission stage t3.

[0244] During the reset phase t1, the first reset signal line Re1, the second enable signal line EM2, and the third enable signal line EM3 output low-level signals, and the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on. The first initial signal line Vinit1 inputs the first initial signal to the first node N1, and the second initial signal line Vinit2 inputs the second initial signal to the first electrode and the second electrode.

[0245] During the data writing phase t2, the first gate line Ga1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data line Da inputs a compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal on the data line and Vth is the threshold voltage of the driving transistor T3.

[0246] During the light-emitting stage t3: the first enable signal line EM1 and the second enable signal line EM2 output low-level signals, turning on the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8. This drives the transistor T3 to provide driving current to the second electrode, enabling the light-emitting unit L2 to emit light. The output current of the driving transistor is I = (μWCox / 2L)(Vgs-Vth). 2 =(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; Vth is the driving transistor threshold voltage; and Vdd is the voltage on the first power supply line.

[0247] In other exemplary embodiments, the first reset signal line Re1 and the second reset signal line Re2 may also output low-level signals in a time-division manner.

[0248] This exemplary embodiment also provides another display panel, which may include a substrate, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, an electrode layer, and a pixel definition layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 20-30, Figure 20 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 21 is a structural layout diagram of the active layer in the display panel shown in Figure 20, Figure 22 is a structural layout diagram of the first gate layer in the display panel shown in Figure 20, Figure 23 is a structural layout diagram of the second gate layer in the display panel shown in Figure 20, Figure 24 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 20, Figure 25 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 20, Figure 26 is a structural layout diagram of the electrode layer and pixel definition layer in the display panel shown in Figure 20, Figure 27 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 20, Figure 28 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 20, Figure 29 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 20, and Figure 30 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 20.

[0249] As shown in FIG30, the display panel may include a plurality of pixel driving circuits Pix arrayed in the first direction X and the second direction Y. As shown in FIG20, in this exemplary embodiment, the sub-pixel unit includes a pixel driving circuit as shown in FIG17, and the pixel driving circuit is capable of driving the first electrode portion and the second electrode portion in a time-division manner.

[0250] As shown in Figures 20, 21, and 27, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, a nineteenth active section 719, and a twentieth active section 720. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 731 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 can be used to form the channel region of the ninth transistor T9; the tenth active portion 710 is connected to the end of the first active portion 71 away from the second active portion 72; the... Eleventh active unit 711 is connected to the end of fifth active unit 75 away from third active unit 73; twelfth active unit 712 is connected to the end of eighth active unit 78 away from seventh active unit 77; thirteenth active unit 713 is connected to the end of fourth active unit 74 away from third active unit 73; fourteenth active unit 714 is connected between eighth active unit 78 and seventh active unit 77; fifteenth active unit 715 is connected to the end of seventh active unit 77 away from eighth active unit 78; The sixteenth active part 716 is connected to the end of the ninth active part 79 that is away from the sixth active part 76; the seventeenth active part 717 is connected between the sixth active part 76 and the ninth active part 79; the eighteenth active part 718 is connected between the second active part 72 and the first active part 71; the nineteenth active part 719 is connected between the first sub-active part 731 and the second sub-active part 732; and the twentieth active part 720 is connected between the third sub-active part 723 and the fourth sub-active part 724.

[0251] As shown in Figures 20, 21, and 27, the active layer can be formed of polycrystalline silicon. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type low-temperature polycrystalline silicon thin-film transistors. In this exemplary embodiment, the first transistor T1 and the second transistor T2 are both dual-gate structures. The dual-gate transistor has two spaced-apart channel regions, resulting in a smaller turn-off leakage current. This configuration can reduce the leakage current through the first and second transistors at the gate of the driving transistor, thereby improving the voltage stability of the gate of the driving transistor T3.

[0252] As shown in Figures 20, 22, and 27, the first gate layer may include: a first conductive portion 11 and multiple gate lines, among which are a first reset signal line Re1, a first gate line Ga1, a first enable signal line EM1, a third enable signal line EM3, a second enable signal line EM2, and a second reset signal line Re2. The orthographic projections of the first reset signal line Re1, the first gate line Ga1, the first enable signal line EM1, the third enable signal line EM3, the second enable signal line EM2, and the second reset signal line Re2 onto the substrate can all extend along a first direction X. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The orthographic projection of the first enable signal line EM1 onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the first enable signal line EM1 is used to form the channel regions of the fifth transistor T5 and the sixth transistor T6, respectively. The first gate line Ga1 includes multiple first gate line segments G11. The orthographic projections of the multiple first gate line segments G11 on the substrate extend along the first direction X and are spaced apart along the first direction X. The orthographic projections of the first gate line segments G11 on the substrate cover the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line segment G11 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line segment G11 is used to form the gate of the second transistor T2. The first reset signal line Re1 includes multiple first reset signal line segments Re11. The orthographic projections of the multiple first reset signal line segments Re11 on the substrate extend along the first direction X and are spaced apart along the first direction X. The orthographic projections of the first reset signal line segments Re11 on the substrate cover the orthographic projection of the first active portion 71 on the substrate. A portion of the structure of the first reset signal line segment Re11 is used to form the gate of the first transistor. The third enable signal line EM3 includes multiple third enable signal segments EM31. The orthographic projections of the multiple third enable signal segments EM31 on the substrate extend along the first direction X and are spaced apart along the first direction X. The orthographic projections of the third enable signal segments EM31 on the substrate cover the orthographic projection of the ninth active portion 79 on the substrate. A portion of the structure of the third enable signal segments EM31 is used to form the gate of the ninth transistor. The second enable signal line EM2 includes multiple second enable signal segments EM21. The orthographic projections of the multiple second enable signal segments EM21 on the substrate extend along the first direction X and are spaced apart along the first direction X. The orthographic projections of the second enable signal segments EM21 on the substrate cover the orthographic projection of the eighth active portion 78 on the substrate. A portion of the structure of the second enable signal segments EM21 is used to form the gate of the eighth transistor.The second reset signal line Re2 includes multiple second reset signal segments Re21. The orthographic projections of the multiple second reset signal segments Re21 on the substrate extend along the first direction X and are spaced apart along the first direction X. The orthographic projections of the second reset signal segments Re21 on the substrate cover the orthographic projections of the seventh active portion 77 on the substrate. A portion of the structure of the second reset signal segments Re21 is used to form the gate of the seventh transistor. This display panel can use the first gate layer as a mask to perform conductor processing on the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0253] In this exemplary embodiment, the first reset signal line Re1 and the second reset signal line Re2 can be connected in the bezel area of ​​the display panel.

[0254] As shown in Figures 20, 23, and 28, the second gate layer may include: a second conductive portion 22, a fourth conductive portion 24, a third conductive portion 23, a first initial signal line Vinit1, and a second initial signal line Vinit2. The orthographic projection of the second conductive portion 22 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 is used to form the second electrode of the capacitor C. The third conductive portion 23 is connected to the second conductive portion 22. The orthographic projection of the third conductive portion 23 on the substrate may at least partially overlap with the orthographic projection of the twentieth active portion 720 on the substrate. The third conductive portion 23 can stabilize the voltage of the twentieth active portion 720, thereby reducing the leakage current to the source and drain of the second transistor T2 caused by voltage fluctuations in the twentieth active portion 720. The orthographic projection of the first initial signal line Vinit1 on the substrate and the orthographic projection of the nineteenth active part 719 on the substrate at least partially overlap. The first initial signal line Vinit1 can stabilize the voltage of the nineteenth active part 719, thereby reducing the leakage current to the source and drain of the first transistor T1 caused by voltage fluctuations in the nineteenth active part 719.

[0255] As shown in Figures 20, 24, and 29, the first source / drain layer may include a first bridging section 31, a second bridging section 32, a third bridging section 33, a fourth bridging section 34, a fifth bridging section 35, a sixth bridging section 36, a seventh bridging section 37, an eighth bridging section 38, a first power supply line VDD, and multiple gate connection lines. These multiple gate connection lines include: a first reset connection line 3Re1, a first gate connection line 3G1, a second enable connection line 3EM2, a third enable connection line 3EM3, a second reset connection line 3Re2, and a first enable connection line 3EM1. The first bridging section 31 connects to the fifteenth active section 715 and the second initial signal line Vinit2 via vias, thereby connecting the first electrode of the seventh transistor T7 and the second initial signal line Vinit2. The second bridging section 32 connects to the sixteenth active section 716 via vias, thereby connecting the second electrode of the ninth transistor T9. The third bridging portion 33 can be connected to the eighteenth active portion 718 and the first conductive portion 11 via vias, to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2 and the second electrode of the first transistor T1. An opening 221 is formed on the second conductive portion 22, and the via connecting the third bridging portion 33 and the first conductive portion 11 is disposed through the opening 221. The fourth bridging portion 34 is connected to the fourteenth active portion 714 via vias, to connect the second electrode of the seventh transistor T7 and the second electrode of the eighth transistor T8. The fifth bridging portion 35 can be connected to the seventeenth active portion 717 and the fourth conductive portion 24 via vias, and the seventh bridging portion 37 can be connected to the twelfth active portion 712 and the fourth conductive portion 24 via vias, to connect the first electrode of the ninth transistor T9 and the first electrode of the eighth transistor T8. The sixth bridging portion 36 can be connected to the thirteenth active portion 713 via vias, to connect the first electrode of the fourth transistor T4. The eighth bridging section 38 connects the first initial signal line Vinit1 and the tenth active section 710 through vias to connect the first initial signal line Vinit1 and the first electrode of the first transistor T1.

[0256] As shown in Figures 20, 24, and 29, the orthographic projections of the first reset connection line 3Re1, the first gate connection line 3G1, the first power supply line VDD, the second enable connection line 3EM2, the third enable connection line 3EM3, the second reset connection line 3Re2, and the first enable connection line 3EM1 on the substrate extend along the first direction X. The first reset connection line 3Re1 can be connected via vias to multiple first reset signal line segments Re11 located in the same first reset signal line Re1, thereby connecting the first reset signal line Re1 and the gate of the first transistor T1. The first gate connection line 3G1 can be connected via vias to multiple first gate line segments G11 located in the same first gate line Ga1, thereby connecting the first gate line Ga1, the gate of the second transistor T2, and the gate of the fourth transistor T4. The first power supply line VDD is connected via vias to the eleventh active part 711 and the second conductive part 22, thereby connecting the first power supply line VDD and the first terminal of the fifth transistor and the second terminal of the capacitor C. The second enable connection line 3EM2 can be connected via vias to multiple second enable signal segments EM21 located within the same second enable signal line EM2, thereby connecting the second enable signal line EM2 to the gate of the eighth transistor T8. The third enable connection line 3EM3 can be connected via vias to multiple third enable signal segments EM31 located within the same third enable signal line EM3, thereby connecting the third enable signal line EM3 to the gate of the ninth transistor T9. The second reset connection line 3Re2 can be connected via vias to multiple second reset signal segments Re21 located within the same second reset signal line Re2, thereby connecting the second reset signal line Re2 to the gate of the seventh transistor T7. The first enable connection line 3EM1 can be connected to the first enable signal line EM1 via one or more vias. This configuration reduces the resistance of the first enable signal line EM1, thereby reducing the voltage difference of the first enable signal line EM1 at different locations on the display panel.

[0257] In this exemplary embodiment, the sheet resistance of the first source / drain layer is less than the sheet resistance of the first gate layer. In this exemplary embodiment, the gate lines corresponding to the first source / drain layer are connected through the gate connection vias located in the first source / drain layer, thereby reducing the resistance of each gate line and improving the display uniformity of the display panel.

[0258] As shown in Figures 20, 25, and 30, the second source / drain layer may include a data line Da, a first power connection line 4VDD, a first initial connection line 4Vinit1, a second initial connection line 4Vinit2, a second power line VSS, a ninth bridge portion 49, and a tenth bridge portion 410. The orthographic projections of the data line Da, the first power connection line 4VDD, the first initial connection line 4Vinit1, the second initial connection line 4Vinit2, and the second power line VSS on the substrate all extend along the second direction Y. The data line Da can be connected to the sixth bridge portion 36 via a via to connect the data line and the first terminal of the fourth transistor T4. The first power connection line 4VDD can be connected to the intersecting first power line VDD via a via. The first initial connection line 4Vinit1 can be connected to the eighth bridge portion 38 via a via to connect the first initial connection line 4Vinit1 and the intersecting first initial signal line Vinit1. The second initial connection line 4Vinit2 can be connected to the first bridging portion 31 via a via, so that the second initial connection line 4Vinit2 and the intersecting second initial signal line Vinit1 are connected. In this exemplary embodiment, the first power connection line 4VDD, the first initial connection line 4Vinit1, the second initial connection line 4Vinit2, and the signal lines connected thereto form a grid structure. The signal lines in the grid structure have lower resistance, which can reduce the voltage difference of the same signal lines at different locations on the display panel. The second power line VSS can be connected to the common electrode layer via a via, so as to reduce the voltage difference of the common electrode layer at different locations on the display panel. The ninth bridging portion 49 can be connected to the second bridging portion 32 via a via, so as to connect the second electrode of the ninth transistor T9. The tenth bridging portion 410 can be connected to the fourth bridging portion 34 via a via, so as to connect the second electrode of the eighth transistor T8 and the second electrode of the seventh transistor T7.

[0259] In this exemplary embodiment, as shown in FIG30, a second power line VSS can be correspondingly provided for every three columns of pixel driving circuits. Furthermore, in an adjacent set of six columns of pixel driving circuits, a first initial connection line 4Vinit1 is correspondingly provided for every three adjacent columns of pixel driving circuits, and a second initial connection line 4Vinit2 is correspondingly provided for every three adjacent columns of pixel driving circuits.

[0260] As shown in Figures 20 and 26, the electrode layer may include multiple electrode portions. The red sub-pixel unit includes a first electrode portion R1 and a second electrode portion R2, the green sub-pixel unit includes a first electrode portion G1 and a second electrode portion G2, and the blue sub-pixel unit includes a first electrode portion B1 and a second electrode portion B2. Multiple pixel openings Ph are formed on the pixel definition layer. The electrode portions and pixel openings are correspondingly arranged, and the orthographic projection of each pixel opening onto the substrate lies within the orthographic projection of its corresponding electrode portion onto the substrate. Within the same sub-pixel unit, the number of pixel openings corresponding to the first electrode portion is greater than the number of pixel openings corresponding to the second electrode portion, and the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion onto the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion onto the substrate.

[0261] In this exemplary embodiment, as shown in FIG20-30, in the same pixel driving circuit, the orthographic projection of the third enable signal line EM3 on the substrate is located between the orthographic projection of the second enable signal line EM2 on the substrate and the orthographic projection of the first enable signal line EM1 on the substrate, and the orthographic projection of the first enable signal line EM1 on the substrate is located between the orthographic projection of the third enable signal line EM3 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate.

[0262] In this exemplary embodiment, as shown in FIG20-30, in the same pixel driving circuit, the orthographic projection of the first gate line Ga1 on the substrate is located on the side where the orthographic projection of the first conductive part 11 on the substrate is away from the orthographic projection of the first enable signal line EM1 on the substrate; the orthographic projection of the first reset signal line Re1 on the substrate is located on the side where the orthographic projection of the first gate line Ga1 on the substrate is away from the orthographic projection of the first conductive part 11 on the substrate; and the orthographic projection of the second reset signal line Re2 on the substrate is located on the side where the orthographic projection of the second enable signal line EM2 on the substrate is away from the orthographic projection of the third enable signal line EM3 on the substrate.

[0263] In this exemplary embodiment, as shown in Figures 20-30, the orthographic projection of the ninth bridging portion 49 in this column of pixel driving circuit onto the substrate is located between the orthographic projection of the data line Da connected to the adjacent column of pixel driving circuit onto the substrate and the orthographic projection of the third bridging portion 33 in this column of pixel driving circuit onto the substrate; and within the same pixel driving circuit, the orthographic projections of the ninth bridging portion 49 and the third bridging portion 33 onto the substrate are arranged opposite to each other in the first direction X. The ninth bridging portion 49 can shield the data line Da from signal interference to the third bridging portion 33.

[0264] In this exemplary embodiment, as shown in Figures 20-30, the ninth bridging portion 49 includes a first via connection portion 491, a second via connection portion 492, and an extension portion 493 connected to one end of the second via connection portion 492 away from the first via connection portion 491. The first via connection portion 491 is connected to the pixel driving circuit through a via, and the second via connection portion 492 is connected to the first electrode portion through a via. In the same pixel driving circuit, the orthographic projection of the extension portion 493 on the substrate and the orthographic projection of the third bridging portion 33 on the substrate are disposed opposite each other in the first direction X. This exemplary embodiment uses the extended portion 493 to shield the signal interference of the data line Da to the third bridging portion 33.

[0265] In this exemplary embodiment, as shown in Figures 20-30, the orthographic projection of the first power connection line 4VDD1 on the substrate covers the orthographic projection of the third bridging portion 33 on the substrate, and the first power connection line 4VDD1 can shield the noise interference of other signals to the third bridging portion 33.

[0266] Figure 31 shows a partial cross-sectional view of the display panel shown in Figure 20, cut along the dashed line CC. The display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a dielectric layer 104, a first passivation layer 105, a first planarization layer 106, a second planarization layer 107, a second passivation layer 108, and a pixel definition layer (PDL). The substrate 100, buffer layer 101, active layer, first insulating layer 102, first gate layer, second insulating layer 103, second gate layer, dielectric layer 104, first source / drain layer, first passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, second passivation layer 108, electrode layer, and pixel definition layer (PDL) are sequentially stacked. The buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The first passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0267] Figure 32 shows a partial cross-sectional view of another exemplary embodiment of the display panel of this disclosure. The display panel further includes: a second planarization layer 107 and a second passivation layer 108. The second planarization layer 107 is located between the substrate 100 and the electrode layer; the second passivation layer 108 is located between the second planarization layer 107 and the electrode layer. A first slot K1 is formed on the second passivation layer 108, and the orthographic projection of the first slot K1 on the substrate is located between the orthographic projections of two adjacent electrode portions on the substrate 100. A second slot K2 is formed on the second planarization layer 107, and the orthographic projection of the second slot K2 on the substrate and the orthographic projection of the first slot K1 on the substrate at least partially overlap. The second slot K2 includes first sidewalls K21 disposed opposite to each other in the distribution direction of the two adjacent electrode portions. At least one of the first sidewalls K21 forms a lateral recess 1071. The orthographic projection of the second passivation layer 108 on the substrate covers the orthographic projection of the recess 1071 on the substrate. This setting allows the light-emitting layer to be disconnected in the recess 1071 when the light-emitting layer is formed on the side of the pixel definition layer PDL away from the substrate 100, thereby preventing the light-emitting layers on different electrode sections from connecting.

[0268] It should be noted that, as shown in Figure 2-30, the chamfered black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the chamfered black squares drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the chamfered black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different locations can penetrate different insulating layers.

[0269] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0270] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, vehicle-mounted display device, or the like.

[0271] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0272] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes multiple pixel units, each pixel unit includes multiple sub-pixel units, and the display panel further includes: Substrate; An electrode layer is located on one side of the substrate. The sub-pixel unit includes at least two electrode portions located on the electrode layer. The two electrode portions respectively form a first electrode portion and a second electrode portion. In the same sub-pixel unit, the first electrode portion and the second electrode portion are spaced apart, and the first electrode portion and the second electrode portion are respectively used to form the first electrode of the same color light-emitting unit. A pixel definition layer is located on the side of the electrode layer opposite to the substrate. A plurality of pixel openings are formed on the pixel definition layer. The electrode portion and the pixel opening are correspondingly disposed. The orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the corresponding electrode portion on the substrate. In the same sub-pixel unit, the number of pixel openings corresponding to the first electrode portion is greater than the number of pixel openings corresponding to the second electrode portion, and the area of ​​the orthographic projection of a single pixel opening corresponding to the first electrode portion on the substrate is smaller than the area of ​​the orthographic projection of a single pixel opening corresponding to the second electrode portion on the substrate.

2. The display panel according to claim 1, wherein, In the same sub-pixel unit, the ratio of the number of individual pixel openings corresponding to the first electrode portion to the number of individual pixel openings corresponding to the second electrode portion is greater than or equal to 2 and less than or equal to 20.

3. The display panel according to claim 1, wherein, The display panel also includes: Pixel driving circuit; A data line, the data line being used to provide data signals to the pixel driving circuit, the data line extending along a second direction in its orthogonal projection on the substrate. In the same sub-pixel unit, the size of the orthogonal projection of the single pixel opening corresponding to the first electrode portion onto the substrate in the first direction is smaller than the size of the orthogonal projection of the single pixel opening corresponding to the second electrode portion onto the substrate in the first direction, and the first direction and the second direction intersect.

4. The display panel according to claim 1, wherein, The orthographic projection of the single pixel opening corresponding to the first electrode portion onto the substrate is a circle.

5. The display panel according to claim 1, wherein, The pixel opening corresponding to the second electrode portion forms a second pixel opening. The orthographic projection of the second pixel opening on the substrate has an arc-shaped chamfer, and the arc-shaped chamfer on the second pixel opening is located on the side facing the adjacent second pixel opening.

6. The display panel according to claim 1, wherein, In the same pixel unit, the orthographic projections of multiple first electrode portions on the substrate and the orthographic projections of multiple second electrode portions on the substrate are located in different regions.

7. The display panel according to any one of claims 1-6, wherein, The sub-pixel unit includes at least two pixel driving circuits, which are used to provide driving current to the first electrode portion and the second electrode portion, respectively.

8. The display panel according to claim 7, wherein, The pixel driving circuit includes a driving transistor, a sixth transistor, a seventh transistor, and a ninth transistor; The first terminal of the sixth transistor is connected to the second terminal of the driving transistor, and the second terminal is connected to the electrode portion; The first terminal of the seventh transistor is connected to the second initial signal line, and the second terminal is connected to the electrode portion; The first electrode of the ninth transistor is connected to the gate of the driving transistor, the gate is connected to the enable signal line, and the second electrode is floating. The display panel also includes: A first gate layer is located between the substrate and the electrode layer. The first gate layer includes a first conductive portion and a plurality of gate lines. The orthogonal projection of the gate lines on the substrate extends along a first direction. The plurality of gate lines include a first reset signal line and an enable signal line. The first conductive portion is used to form the gate of the driving transistor. A portion of the structure of the first reset signal line is used to form the gate of the seventh transistor. A portion of the structure of the enable signal line is used to form the gates of the ninth transistor and the sixth transistor, respectively. In the same pixel driving circuit, the orthogonal projection of the enable signal line on the substrate is located between the orthogonal projection of the first conductive part on the substrate and the orthogonal projection of the first reset signal line on the substrate.

9. The display panel according to claim 8, wherein, The pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, an eighth transistor, and a capacitor; The first electrode of the capacitor is connected to the gate of the driving transistor; The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor; The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the second electrode of the capacitor. The first terminal of the fifth transistor is connected to the reference voltage line, and the second terminal is connected to the second electrode of the capacitor. The first terminal of the eighth transistor is connected to the reference voltage line, and the second terminal is connected to the second electrode of the capacitor. The plurality of gate lines also includes a first gate line, a portion of the structure of the first gate line being used to form the gates of the second transistor and the fourth transistor, a portion of the structure of the enable signal line being used to form the gate of the eighth transistor, the first conductive portion being multiplexed as the first electrode of the capacitor, and a portion of the structure of the first reset signal line being used to form the gates of the first transistor and the fifth transistor. In the same pixel driving circuit, the orthographic projection of the first gate line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is far from the orthographic projection of the enable signal line on the substrate.

10. The display panel according to claim 7, wherein, The pixel driving circuit includes a driving transistor, which provides a driving current to the electrode portion according to its gate voltage. The display panel further includes: A first source / drain layer is located between the substrate and the electrode layer. The first source / drain layer includes a second bridging portion and a third bridging portion. The second bridging portion is connected to the electrode portion through a via, and the third bridging portion is connected to the gate of the driving transistor through a via. A data line, the data line extending along a second direction by its orthogonal projection on the substrate, the data line being used to provide data signals to the pixel driving circuit; Wherein, the second direction is the column direction, and the orthographic projection of the second bridging portion in the column pixel driving circuit onto the substrate is located at the position of the third bridging portion in the column pixel driving circuit. The orthographic projection on the substrate and the data lines connected to the adjacent column pixel driving circuits are between the orthographic projections on the substrate. Furthermore, in the same pixel driving circuit, the orthographic projection of the second bridging portion on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite each other in a first direction, and the first direction and the second direction intersect.

11. The display panel according to claim 10, wherein, The second bridging portion includes a first via connection portion, a second via connection portion, and an extension portion connected to the end of the second via connection portion away from the first via connection portion; The first via connection portion is connected to the pixel driving circuit through a via, and the second via connection portion is connected to the electrode portion through a via. In the same pixel driving circuit, the orthographic projection of the extension portion on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite to each other in the first direction.

12. The display panel according to claim 7, wherein, The pixel driving circuit also includes a driving transistor, a fourth transistor, an eighth transistor, and a capacitor; The first electrode of the capacitor is connected to the gate of the driving transistor; The first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the second electrode of the capacitor. The first terminal of the eighth transistor is connected to the reference voltage line, and the second terminal is connected to the second electrode of the capacitor. The display panel also includes: A first source / drain layer is located between the substrate and the electrode layer. The first source / drain layer includes a third bridging portion and a fourth bridging portion. The third bridging portion is connected to the gate of the driving transistor through a via. The fourth bridging portion is connected to the second electrode of the capacitor, the second electrode of the fourth transistor, and the second electrode of the eighth transistor through vias, respectively. A data line, the data line extending along a second direction by its orthogonal projection on the substrate, the data line being used to provide data signals to the pixel driving circuit; Wherein, the second direction is the column direction, and the orthographic projection of the fourth bridging part in the column pixel driving circuit on the substrate is located between the orthographic projection of the third bridging part in the column pixel driving circuit and the orthographic projection of the data line connected to the column pixel driving circuit on the substrate. Furthermore, in the same pixel driving circuit, the fourth bridging portion is located on the substrate. The projection and the orthographic projection of the third bridging portion on the substrate are arranged opposite each other in a first direction, and the first direction intersects with the second direction.

13. The display panel according to claim 7, wherein, The pixel driving circuit includes a driving transistor, which provides a driving current to the electrode portion according to its gate voltage. The display panel further includes: A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a third bridging portion, which is connected to the gate of the driving transistor through a via. The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a data line, a second power line, and a first power connection line. The data line extends along a second direction in the orthogonal projection on the substrate, and the data line is used to provide data signals to the pixel driving circuit. The second power line extends along the second direction in the orthogonal projection on the substrate, and the second power line is used to connect the second electrode of the light-emitting unit; The first power connection line extends along the second direction in the orthogonal projection on the substrate, and the first power connection line is used to provide a high-level power signal to the pixel driving circuit. Wherein, the orthogonal projection of the first power connection line on the substrate is located between the data line connected to the same pixel driving circuit and the orthogonal projection of the third bridging part on the substrate. And / or, the orthographic projection of the second power line on the substrate is located between the orthographic projection of the third bridging portion in the pixel driving circuit of this column on the substrate and the orthographic projection of the data line connected to the pixel driving circuit of the adjacent column on the substrate.

14. The display panel according to any one of claims 1-6, wherein, The sub-pixel unit includes at least one pixel driving circuit, which is used to provide driving current to the first electrode portion and the second electrode portion in a time-division manner.

15. The display panel according to claim 14, wherein, The pixel driving circuit includes a driving transistor, a sixth transistor, an eighth transistor, and a ninth transistor; The driving transistor is used to provide a driving current to the electrode portion according to its gate voltage, and the first terminal of the sixth transistor is connected to the second terminal of the driving transistor; The first terminal of the eighth transistor is connected to the second terminal of the sixth transistor, and the second terminal is connected to the second electrode portion; The first electrode of the ninth transistor is connected to the second electrode of the sixth transistor, and the second electrode is connected to the first electrode portion; The display panel also includes: A first gate layer is located between the substrate and the electrode layer. The first gate layer includes a first conductive portion and a plurality of gate lines. The orthogonal projection of the gate lines on the substrate extends along a first direction. The plurality of gate lines include a first enable signal line, a second enable signal line, and a third enable signal line. A portion of the structure of the first enable signal line is used to form the gate of the sixth transistor. A portion of the structure of the third enable signal line is used to form the gate of the ninth transistor. A portion of the structure of the second enable signal line is used to form the gate of the eighth transistor. The first conductive portion is used to form the gate of the driving transistor. In the same pixel driving circuit, the orthographic projection of the third enable signal line on the substrate is located between the orthographic projection of the second enable signal line on the substrate and the orthographic projection of the first enable signal line on the substrate, and the orthographic projection of the first enable signal line on the substrate is located between the orthographic projection of the third enable signal line on the substrate and the orthographic projection of the first conductive portion on the substrate.

16. The display panel according to claim 15, wherein, The pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor; The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor; The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the first terminal of the driving transistor. The first terminal of the fifth transistor is connected to the first power supply line, and the second terminal is connected to the first terminal of the driving transistor. The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the second electrode portion; The plurality of gate lines further include: a first gate line, a first reset signal line, and a second reset signal line, wherein a portion of the structure of the first gate line is used to form the second transistor and the fourth transistor, respectively. The gate of the first transistor is formed by a portion of the structure of the first reset signal line, and the gate of the seventh transistor is formed by a portion of the structure of the second reset signal line. In the same pixel driving circuit, the orthographic projection of the first gate line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is away from the orthographic projection of the first enable signal line on the substrate; the orthographic projection of the first reset signal line on the substrate is located on the side where the orthographic projection of the first gate line on the substrate is away from the orthographic projection of the first conductive part on the substrate; and the orthographic projection of the second reset signal line on the substrate is located on the side where the orthographic projection of the second enable signal line on the substrate is away from the orthographic projection of the third enable signal line on the substrate.

17. The display panel according to claim 14, wherein, The pixel driving circuit includes a driving transistor, which is used to provide a driving current to the electrode portion according to its gate voltage. The display panel further includes: A first source / drain layer is located between the substrate and the electrode layer. The first source / drain layer includes a third bridging portion, which is connected to the gate of the driving transistor through a via. The second source / drain layer is located between the first source / drain layer and the electrode layer. The second source / drain layer includes a data line and a ninth bridging portion. The data line extends along a second direction in the orthogonal projection on the substrate. The data line is used to provide data signals to the pixel driving circuit. The ninth bridging portion is connected to the pixel driving circuit and the first electrode portion through vias. Wherein, the second direction is the column direction, and the orthographic projection of the ninth bridging part in the column pixel driving circuit on the substrate is located between the orthographic projection of the data line connected to the adjacent column pixel driving circuit on the substrate and the orthographic projection of the third bridging part in the column pixel driving circuit on the substrate. Furthermore, in the same pixel driving circuit, the orthographic projection of the ninth bridging portion on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite each other in a first direction, and the first direction intersects with the second direction.

18. The display panel according to claim 17, wherein, The ninth bridging portion includes a first via connection portion, a second via connection portion, and an extension portion connected to the end of the second via connection portion away from the first via connection portion. The first via connection portion is connected to the pixel driving circuit through a via, and the second via connection portion is connected to the first electrode portion through a via; In the same pixel driving circuit, the orthographic projection of the extension on the substrate and the orthographic projection of the third bridging portion on the substrate are arranged opposite to each other in the first direction.

19. The display panel according to any one of claims 8, 9, 15, and 16, wherein, At least a portion of the multiple gate lines include multiple gate line segments, and the orthographic projections of the multiple gate line segments on the substrate extend along a first direction and are spaced apart along the first direction; The display panel also includes: A first source / drain layer is located between the first gate layer and the electrode layer. The first source / drain layer includes a gate connection line. The orthogonal projection of the gate connection line on the substrate extends along a first direction, and the gate connection line connects multiple gate segments in the same gate line through vias.

20. The display panel according to any one of claims 1-19, wherein, The display panel also includes: The second planarization layer is located between the substrate and the electrode layer; The second passivation layer is located between the second planarization layer and the electrode layer; The second passivation layer has a first slot formed thereon, and the orthographic projection of the first slot on the substrate is located between the orthographic projections of two adjacent electrode portions on the substrate. A second slot is formed on the second planarization layer. The orthographic projection of the second slot on the substrate and the orthographic projection of the first slot on the substrate at least partially overlap. The second slot includes first sidewalls disposed opposite to each other in the distribution direction of the two adjacent electrodes. At least one of the first sidewalls forms a lateral recess. The orthographic projection of the second passivation layer on the substrate covers the orthographic projection of the recess on the substrate.

21. A display device, wherein, The display device includes the display panel as described in any one of claims 1-20.

22. A pixel driving circuit, wherein, The pixel driving circuit is used to form the pixel driving circuit in the display panel of claim 7, and the pixel driving circuit includes: The driving circuit connects a first node, a first power line, and a third node. The driving circuit is used to input driving current to the third node using the first power line according to the voltage of the first node. The first light-emitting control circuit is connected to the third node, the first electrode of the light-emitting unit, and the enable signal line. The first light-emitting control circuit is used to respond to the signal of the enable signal line to connect the third node and the first electrode of the light-emitting unit. A voltage regulator circuit, connected to the first node and the enable signal line, is used to stabilize the voltage of the first node according to the signal on the enable signal line.

23. The pixel driving circuit according to claim 22, wherein, The pixel driving circuit also includes: The second light-emitting control circuit is connected to the reference voltage line and the fourth node. The second light-emitting control circuit is used to respond to a control signal to transmit the signal of the reference voltage line to the fourth node. A first reset circuit is connected to a first initial signal line and a first node. The first reset circuit is used to respond to a control signal to transmit the signal of the first initial signal line to the first node. The second reset circuit is connected to the first electrode of the light-emitting unit and the second initial signal line. The second reset circuit is used to respond to a control signal to transmit the signal of the second initial signal line to the first electrode of the light-emitting unit. A third reset circuit is connected to a reference voltage line and a fourth node. The third reset circuit is used to respond to a control signal to transmit the signal of the reference voltage line to the fourth node. A data writing circuit is connected to a data line and a fourth node. The data writing circuit is used to respond to a control signal to transmit the signal of the data line to the fourth node. A compensation circuit is provided to connect the first node and the third node, and the compensation circuit is used to respond to a control signal to connect the first node and the third node. A coupling circuit is connected between the first node and the fourth node, the coupling circuit being used to couple voltage changes of the fourth node to the first node.

24. The pixel driving circuit according to claim 23, wherein, The driving circuit includes: The driving transistor has its first terminal connected to the first power supply line, its second terminal connected to the third node, and its gate connected to the first node. The first light-emitting control circuit includes: The sixth transistor has its first electrode connected to the third node, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the enable signal line. The voltage regulator circuit includes: The ninth transistor has its first electrode connected to the first node, its gate connected to the enable signal line, and its second electrode floating. The second light-emitting control circuit is also connected to the enable signal line. The second light-emitting control circuit is used to respond to the signal from the enable signal line to transmit the signal from the reference voltage line to the fourth node. The second light-emitting control circuit includes: The eighth transistor has its first terminal connected to the reference voltage line, its second terminal connected to the fourth node, and its gate connected to the enable signal line. The first reset circuit is also connected to a first reset signal line. The first reset circuit is used to respond to the signal of the first reset signal line to transmit the signal of the first initial signal line to the fourth node. The first reset circuit includes: The first transistor has a first terminal connected to the first initial signal line, a second terminal connected to the fourth node, and a gate connected to the first reset signal line. The second reset circuit is also connected to the first reset signal line. The second reset circuit is used to respond to the signal of the first reset signal line to transmit the signal of the second initial signal line to the first electrode of the light-emitting unit. The second reset circuit includes: The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the first reset signal line. The third reset circuit is also connected to the first reset signal line. The third reset circuit is used to respond to the signal of the first reset signal line to transmit the signal of the reference voltage line to the fourth node. The third reset circuit includes: The fifth transistor has its first terminal connected to the reference voltage line, its second terminal connected to the fourth node, and its gate connected to the first reset signal line. The data writing circuit is also connected to the first gate line, and the data writing circuit is used to respond to the signal of the first gate line to transmit the signal of the data line to the fourth node. The data writing circuit includes: The fourth transistor has its first terminal connected to the data line, its second terminal connected to the fourth node, and its gate connected to the first gate line. The compensation circuit is also connected to the first gate line, and the compensation circuit is used to connect the first node and the third node in response to a signal from the first gate line. The compensation circuit includes: The second transistor has its first terminal connected to the first node, its second terminal connected to the third node, and its gate connected to... Connect to the first gate line; The coupling circuit includes: The capacitor has its first electrode connected to the first node and its second electrode connected to the fourth node.

25. A pixel driving circuit, wherein, The pixel driving circuit is used to form the pixel driving circuit in the display panel of claim 14, the pixel driving circuit comprising: A driving circuit is connected to a first node, a second node, and a third node. The driving circuit is used to provide a driving current to the third node through the second node based on the voltage of the first node. A first light-emitting control circuit is connected to the third node, the fourth node, and the first enable signal line. The first light-emitting control circuit is used to respond to the signal of the first enable signal line to connect the third node and the fourth node. The second light-emitting control circuit is connected to the fourth node, the second electrode part, and the second enable signal line. The second light-emitting control circuit is used to respond to the signal of the second enable signal line to connect the second electrode part and the fourth node. The third light-emitting control circuit is connected to the fourth node, the third enable signal line, and the first electrode. The third light-emitting control circuit is used to respond to the signal of the third enable signal line to connect the fourth node and the first electrode.

26. The pixel driving circuit according to claim 25, wherein, The pixel driving circuit also includes: A compensation circuit is provided to connect the first node and the third node, and the compensation circuit is used to respond to a control signal to connect the first node and the third node. A data writing circuit is connected to the second node and the data line. The data writing circuit is used to respond to a control signal to transmit the data signal on the data line to the second node. A first reset circuit is connected to the first node and a first initial signal line. The first reset circuit is used to respond to a control signal to transmit a signal on the first initial signal line to the first node. The second reset circuit is connected to the second electrode section and the second initial signal line. The second reset circuit is used to respond to a control signal to transmit the signal of the second initial signal line to the second electrode section. A storage circuit is connected to the first node, and the storage circuit is used to store the voltage of the first node; The first light-emitting control circuit is also connected to the second node and the first power line. The first light-emitting control circuit is also used to respond to a control signal to connect the first power line and the second node.

27. The pixel driving circuit according to claim 26, wherein, The driving circuit includes: A driving transistor is configured such that its gate is connected to the first node, its first electrode is connected to the second node, and its second electrode is connected to the third node. The first light-emitting control circuit is also connected to a first enable signal line. The first light-emitting control circuit is used to respond to a signal from the first enable signal line to connect the third node and the fourth node, and to respond to a signal from the first enable signal line to connect the first power line and the second node. The first light-emitting control circuit includes: The fifth transistor has its first terminal connected to the first power supply line, its second terminal connected to the second node, and its gate connected to the first enable signal line. The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the first enable signal line. The second light-emitting control circuit includes: The eighth transistor has its first electrode connected to the fourth node, its second electrode connected to the second electrode portion, and its gate connected to the second enable signal line. The third light-emitting control circuit includes: The ninth transistor has its first electrode connected to the fourth node, its second electrode connected to the first electrode portion, and its gate connected to the third enable signal line. The compensation circuit is also connected to a first gate line, and the compensation circuit is used to connect the first node and the third node in response to a signal from the first gate line. The compensation circuit includes: The second transistor has a first terminal connected to the first node, a second terminal connected to the third node, and a gate connected to the first gate line. The data writing circuit is also connected to a first gate line, and the data writing circuit is used to respond to a signal from the first gate line to transmit a data signal on the data line to the second node. The data writing circuit includes: The fourth transistor has its first terminal connected to the data line, its second terminal connected to the second node, and its gate connected to the first gate line. The first reset circuit is also connected to a first reset signal line. The first reset circuit is used to transmit the signal on the first initial signal line to the first node in response to the signal on the first reset signal line. The first reset circuit includes: The first transistor has a first terminal connected to the first initial signal line, a second terminal connected to the first node, and a gate connected to the first reset signal line. The second reset circuit is also connected to a second reset signal line. The second reset circuit is used to respond to the signal of the second reset signal line to transmit the signal of the second initial signal line to the second electrode portion. The second reset circuit includes: The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the second electrode portion, and its gate connected to the second reset signal line. The storage circuit includes: The capacitor has its first electrode connected to the first node and its second electrode connected to the first power line.

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