Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display device. The display panel comprises: a base substrate, a plurality of light-emitting units, a plurality of pixel drive circuits, an electrode layer, and a pixel definition layer. The pixel drive circuits are used for driving the light-emitting units, and the plurality of pixel drive circuits are distributed in an array in a first direction and a second direction, wherein the first direction intersects with the second direction. The plurality of pixel drive circuits form a plurality of pixel drive circuit row groups distributed in the second direction, wherein each pixel drive circuit row group comprises two adjacent pixel drive circuit rows, each of which comprises a plurality of pixel drive circuits distributed in the first direction, and orthographic projections, on the base substrate, of two adjacent pixel drive circuit rows in the pixel drive circuit row group are at least partially arranged in mirror symmetry along a first symmetry axis, the first symmetry axis being parallel to the first direction. The electrode layer comprises a plurality of electrode portions, each of which comprises a main body portion and a connection portion, wherein the main body portions are at least partially used for forming first electrodes of the light-emitting units, and the connection portions are connected between the main body portions and the pixel drive circuits. The pixel definition layer is located on the side of the electrode layer that faces away from the base substrate, and a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings are arranged corresponding to the electrode portions, and orthographic projections of the pixel openings on the base substrate are located within orthographic projections, on the base substrate, of the main body portions in the electrode portions, which correspond to the pixel openings. The plurality of electrode portions comprise a plurality of first electrode portions, which are used for respectively forming first electrodes of the light-emitting units of the same color. In the same pixel drive circuit row group, the pixel drive circuits in one pixel drive circuit row form first pixel drive circuits, and the pixel drive circuits in the other pixel drive circuit row form second pixel drive circuits. The extension length of an orthographic projection, on the base substrate, of the connection portion of each first electrode portion connected to a first pixel driving circuit is greater than the extension length of an orthographic projection, on the base substrate, of the connection portion of the first electrode portion connected to the second pixel driving circuit, and the area of the orthographic projection, on the base substrate, of the main body portion of each first electrode portion connected to the first pixel driving circuit is smaller than the area of the orthographic projection, on the base substrate, of the main body portion of the first electrode portion connected to the second pixel driving circuit. The display panel has a good display effect.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, the area of ​​the electrode portion in the display panel varies, which can cause horizontal stripes to appear on the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0006] Substrate;

[0007] Multiple light-emitting units;

[0008] Multiple pixel driving circuits are provided to drive the light-emitting unit. The multiple pixel driving circuits are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

[0009] The plurality of pixel driving circuits form a plurality of pixel driving circuit row groups distributed in the second direction, the pixel driving circuit row group includes two adjacent pixel driving circuit rows, and the pixel driving circuit row includes a plurality of pixel driving circuits distributed in the first direction.

[0010] In the pixel driving circuit row group, the orthogonal projections of two adjacent pixel driving circuit rows on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry, and the first axis of symmetry is parallel to the first direction.

[0011] An electrode layer includes multiple electrode portions, each electrode portion including a main body portion and a connecting portion. The main body portion is at least partially used to form the first electrode of the light-emitting unit, and the connecting portion is connected between the main body portion and the pixel driving circuit.

[0012] A pixel defining layer is located on the side of the electrode layer opposite to the substrate. A plurality of pixel openings are formed on the pixel defining layer. The pixel openings are correspondingly disposed with the electrode portions. The orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the main body of the corresponding electrode portion on the substrate.

[0013] Among them, the plurality of electrode portions include a plurality of first electrode portions, and the plurality of first electrode portions are used to form the first electrode of the same color light-emitting unit respectively;

[0014] In the same pixel driving circuit row group, the pixel driving circuit in one pixel driving circuit row forms the first pixel driving circuit, and the pixel driving circuit in another pixel driving circuit row forms the second pixel driving circuit.

[0015] The extension length of the orthographic projection of the connection portion of the first electrode portion connected to the first pixel driving circuit on the substrate is greater than the extension length of the orthographic projection of the connection portion of the first electrode portion connected to the second pixel driving circuit on the substrate, and the area of ​​the orthographic projection of the main body portion of the first electrode portion connected to the first pixel driving circuit on the substrate is smaller than the area of ​​the orthographic projection of the main body portion of the first electrode portion connected to the second pixel driving circuit on the substrate.

[0016] In one exemplary embodiment of this disclosure, the main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate.

[0017] The main body portion of the first electrode portion connected to the second pixel driving circuit also includes a first protrusion portion, which is connected to the outer extension portion.

[0018] In one exemplary embodiment of this disclosure, the main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate.

[0019] A first missing portion is formed on the epitaxial portion of the first electrode portion connected to the first pixel driving circuit.

[0020] In one exemplary embodiment of this disclosure, the display panel includes a green light-emitting unit, a red light-emitting unit, and a blue light-emitting unit;

[0021] The first electrode portion is used to form the first electrode of the green light-emitting unit;

[0022] Alternatively, the first electrode portion is used to form the first electrode of the red light-emitting unit;

[0023] Alternatively, the first electrode portion is used to form the first electrode of the blue light-emitting unit.

[0024] In one exemplary embodiment of this disclosure, the display panel further includes:

[0025] A second source / drain layer is located between the substrate and the electrode layer, and the second source / drain layer includes at least a data line;

[0026] Wherein, the orthographic projection of the first protrusion on the substrate and the orthographic projection of the second source / drain layer on the substrate at least partially overlap.

[0027] In one exemplary embodiment of this disclosure, the pixel driving circuit includes one or more transistors, wherein the orthographic projection of the first protrusion on the substrate and the orthographic projection of at least a portion of the channel region of the transistor on the substrate overlap.

[0028] In an exemplary embodiment of this disclosure, the length of the orthographic projection of the outer edge of the epitaxial portion on the substrate is L1, and the extension length of the orthographic projection of the boundary line between the first protrusion and the epitaxial portion on the substrate is L2, where L2 / L1 is greater than or equal to 20% and less than or equal to 1.

[0029] In one exemplary embodiment of this disclosure, the first missing portion is disposed around the outer periphery of the extension portion.

[0030] In one exemplary embodiment of this disclosure, the first missing portion is a notch or through hole formed on the epitaxial portion.

[0031] In one exemplary embodiment of this disclosure, the display panel includes a green light-emitting unit, a red light-emitting unit, and a blue light-emitting unit;

[0032] The plurality of electrode portions include: a plurality of R electrode portions, a plurality of G electrode portions, and a plurality of B electrode portions, wherein the R electrode portions are used to form the first electrode of the red light-emitting unit, the G electrode portions are used to form the first electrode of the green light-emitting unit, and the B electrode portions are used to form the first electrode of the blue light-emitting unit;

[0033] The first direction is the row direction, and the second direction is the column direction. Among the multiple electrode portions connected to the same row pixel driving circuit, the orthogonal projections of the R electrode portion, G electrode portion, B electrode portion, and G electrode portion on the substrate are alternately distributed in the row direction.

[0034] In two adjacent pixel driving circuits, a plurality of R electrode portions and a plurality of B electrode portions are connected to the same column of pixel driving circuits, and the orthogonal projections of the R electrode portions and B electrode portions connected to the same column of pixel driving circuits on the substrate are alternately distributed in the column direction, and a plurality of G electrode portions are connected to another column of pixel driving circuits.

[0035] In one exemplary embodiment of this disclosure, the pixel driving circuit row group includes a plurality of repeating units distributed in a first direction, the repeating unit including two rows and four columns of the pixel driving circuit, and the first electrode portion is a G electrode portion;

[0036] In the same repeating unit, the two G electrode portions connected to the first pixel driving circuit respectively form a first G electrode portion and a second G electrode portion. The extension length of the orthographic projection of the connecting portion in the first G electrode portion on the substrate is greater than the extension length of the orthographic projection of the connecting portion in the second G electrode portion on the substrate, and the area of ​​the orthographic projection of the main body portion in the first G electrode portion on the substrate is smaller than the area of ​​the orthographic projection of the main body portion in the second G electrode portion on the substrate.

[0037] In one exemplary embodiment of this disclosure, the main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate.

[0038] The main body of the second G electrode portion further includes a second protrusion, which is connected to the extension portion;

[0039] Alternatively, a second missing portion may be formed on the epitaxial portion of the first G electrode portion.

[0040] In an exemplary embodiment of this disclosure, the difference between the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate and the area of ​​the orthographic projection of the first electrode portion connected to the second pixel driving circuit on the substrate is S1, and the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate is S2, and S1 / S2 is greater than or equal to 0 and less than or equal to 5%.

[0041] In one exemplary embodiment of this disclosure, the second direction is a column direction, and the pixel driving circuit includes a plurality of transistors. In two pixel driving circuits located in the same row group and in the same column, the channel regions of the same type of transistor are mirror-symmetrically arranged along the first axis of symmetry when projected onto the substrate.

[0042] In an exemplary embodiment of this disclosure, the second direction is a column direction, the pixel driving circuit includes a seventh transistor, the first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit;

[0043] The display panel also includes:

[0044] An active layer is located between the substrate and the electrode layer. The active layer includes a seventh active portion and a twelfth active portion. The seventh active portion is used to form the channel region of the seventh transistor. In two pixel driving circuits located in the same row group and in the same column, the two seventh active portions are connected through the twelfth active portion.

[0045] The second initial signal line extends along the first direction by its orthogonal projection on the substrate, and the second initial signal line is connected to the twelfth active part through a via.

[0046] In one exemplary embodiment of this disclosure, the second direction is a column direction, the pixel driving circuit includes a driving transistor and an eighth transistor, the first terminal of the eighth transistor is connected to a third initial signal line, and the second terminal of the eighth transistor is connected to the first terminal of the driving transistor;

[0047] The display panel also includes:

[0048] An active layer is located on one side of the substrate. The active layer includes an eighth active portion and a tenth active portion. The eighth active portion is used to form the channel region of the eighth transistor. In two pixel driving circuits located in the same row group and in the same column, the two eighth active portions are connected through the tenth active portion.

[0049] The third initial signal line, the orthogonal projection of the third initial signal line on the substrate extends along the first direction, and the third initial signal line is connected to the tenth active part through a via.

[0050] In one exemplary embodiment of this disclosure, the orthographic projections of two adjacent pixel driving circuits in the first direction onto the substrate are at least partially mirror-symmetrically arranged along a second axis of symmetry, which extends along the column direction.

[0051] In one exemplary embodiment of this disclosure, the display panel further includes:

[0052] A data line, which provides data signals to a pixel driving circuit, extends along a column direction.

[0053] In one exemplary embodiment of this disclosure, the main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate.

[0054] The epitaxial portion is projected onto the substrate to form a ring structure of equal width.

[0055] In an exemplary embodiment of this disclosure, the plurality of electrode portions include: a plurality of R electrode portions, a plurality of G electrode portions, and a plurality of B electrode portions. The R electrode portions are used to form the first electrode of the red light-emitting unit, the G electrode portions are used to form the first electrode of the green light-emitting unit, and the B electrode portions are used to form the first electrode of the blue light-emitting unit.

[0056] The widths of the equal-width annular structures formed by the epitaxial portion in the R electrode section, the G electrode section, and the B electrode section are all equal.

[0057] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0058] Drive transistors;

[0059] The first transistor has a first terminal connected to a first initial signal line and a second terminal connected to the gate of the driving transistor.

[0060] The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor;

[0061] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0062] The fifth transistor has its first terminal connected to the power supply line and its second terminal connected to the first terminal of the driving transistor.

[0063] The sixth transistor has its first electrode connected to the second electrode of the driving transistor, and the second electrode connected to the first electrode of the light-emitting unit.

[0064] The seventh transistor has its first electrode connected to the second initial signal line and its second electrode connected to the first electrode of the light-emitting unit.

[0065] The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor.

[0066] The capacitor has its first electrode connected to the gate of the driving transistor and its second electrode connected to the power supply line.

[0067] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0068] Substrate;

[0069] Multiple light-emitting units;

[0070] Multiple pixel driving circuits are provided to drive the light-emitting unit. The multiple pixel driving circuits are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

[0071] The plurality of pixel driving circuits form a plurality of pixel driving circuit row groups distributed in the second direction, the pixel driving circuit row group includes two adjacent pixel driving circuit rows, and the pixel driving circuit row includes a plurality of pixel driving circuits distributed in the first direction.

[0072] In the pixel driving circuit row group, the orthogonal projections of two adjacent pixel driving circuit rows on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry, and the first axis of symmetry is parallel to the first direction.

[0073] An electrode layer includes multiple electrode portions, each electrode portion including a main body portion and a connecting portion. The main body portion is at least partially used to form the first electrode of the light-emitting unit, and the connecting portion is connected between the main body portion and the pixel driving circuit.

[0074] Among them, the plurality of electrode portions include a plurality of first electrode portions, and the plurality of first electrode portions are used to form the first electrode of the same color light-emitting unit respectively;

[0075] In the same pixel driving circuit row group, the pixel driving circuit in one pixel driving circuit row forms the first pixel driving circuit, and the pixel driving circuit in another pixel driving circuit row forms the second pixel driving circuit.

[0076] The difference between the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate and the area of ​​the orthographic projection of the first electrode portion connected to the second pixel driving circuit on the substrate is S1, and the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate is S2, where S1 / S2 is greater than or equal to 0 and less than or equal to 5%.

[0077] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0078] Substrate;

[0079] Multiple light-emitting units;

[0080] Multiple pixel driving circuits are provided to drive the light-emitting unit. The multiple pixel driving circuits are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

[0081] The plurality of pixel driving circuits form a plurality of pixel driving circuit row groups distributed in the second direction, the pixel driving circuit row group includes two adjacent pixel driving circuit rows, and the pixel driving circuit row includes a plurality of pixel driving circuits distributed in the first direction.

[0082] In the pixel driving circuit row group, the orthogonal projections of two adjacent pixel driving circuit rows on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry, and the first axis of symmetry is parallel to the first direction.

[0083] An electrode layer includes multiple electrode portions, each electrode portion including a main body portion and a connecting portion. The main body portion is at least partially used to form the first electrode of the light-emitting unit, and the connecting portion is connected between the main body portion and the pixel driving circuit.

[0084] Among them, the plurality of electrode portions include a plurality of first electrode portions, and the plurality of first electrode portions are used to form the first electrode of the same color light-emitting unit respectively;

[0085] In the same pixel driving circuit row group, the pixel driving circuit in one pixel driving circuit row forms the first pixel driving circuit, and the pixel driving circuit in another pixel driving circuit row forms the second pixel driving circuit.

[0086] The capacitance formed by the first electrode portion connected to the first pixel driving circuit and the equipotential portion electrically connected thereto is C1, and the capacitance formed by the first electrode portion connected to the second pixel driving circuit and the equipotential portion electrically connected thereto is C2, and |C1-C2| / C1 is less than or equal to 2%.

[0087] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0088] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0089] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0090] Figure 1 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0091] Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0092] Figure 3 is a structural layout of the shielding layer in the display panel shown in Figure 2;

[0093] Figure 4 is a structural layout of the active layer in the display panel shown in Figure 2;

[0094] Figure 5 is a structural layout of the first gate layer in the display panel shown in Figure 2;

[0095] Figure 6 is a structural layout of the second gate layer in the display panel shown in Figure 2;

[0096] Figure 7 is a structural layout of the first source / drain layer in the display panel shown in Figure 2;

[0097] Figure 8 is a structural layout of the second source / drain layer in the display panel shown in Figure 2;

[0098] Figure 9 is a structural layout of the electrode layer in the display panel shown in Figure 2;

[0099] Figure 10 is a structural layout of the shielding layer and active layer in the display panel shown in Figure 2;

[0100] Figure 11 is a structural layout of the shielding layer, active layer, and first gate layer in the display panel shown in Figure 2;

[0101] Figure 12 is a structural layout of the shielding layer, active layer, first gate layer and second gate layer in the display panel shown in Figure 2;

[0102] Figure 13 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, and first source / drain layer in the display panel shown in Figure 2;

[0103] Figure 14 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 2.

[0104] Figure 15 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0105] Figure 16 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0106] Figure 17 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0107] Figure 18 is a partial cross-sectional view of the display panel shown in Figure 2, cut along the dashed line CC.

[0108] Figure 19 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0109] Figure 20 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0110] Figure 21 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0111] Figure 22 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0112] Figure 23 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0113] Figure 24 is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0114] Figure 25 is a structural layout of the second source / drain layer and electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0115] Figure 26 is a structural layout of the second source / drain layer and electrode layer in another exemplary embodiment of the display panel of this disclosure. Detailed Implementation

[0116] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0117] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0118] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0119] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0120] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0121] Figure 1 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. In this configuration, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to node N; the first electrode of the second transistor T2 is connected to node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode is connected to the first power supply terminal VDD; the first electrode of the eighth transistor T8 is connected to the third initial signal line Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal terminal Re2. The pixel driving circuit can be connected to an OLED light-emitting unit. The pixel driving circuit is used to drive the OLED to emit light. The OLED can be connected between the second terminal and the second power supply terminal VSS of the sixth transistor T6. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors.

[0122] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light-emitting stage. In the reset stage, the first reset signal terminal Re1 outputs a low-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to node N, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the data writing stage, the first gate driving signal terminal G1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and simultaneously the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting stage: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. In this pixel driving circuit, the output current of the driving transistor is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth). 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage.

[0123] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 2-14, Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 3 is a structural layout diagram of the shielding layer in the display panel shown in Figure 2; Figure 4 is a structural layout diagram of the active layer in the display panel shown in Figure 2; Figure 5 is a structural layout diagram of the first gate layer in the display panel shown in Figure 2; Figure 6 is a structural layout diagram of the second gate layer in the display panel shown in Figure 2; Figure 7 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 2; Figure 8 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 2; and Figure 9 is a structural layout diagram of the electrode layer in the display panel shown in Figure 2. Figure 10 is a structural layout of the shielding layer and active layer in the display panel shown in Figure 2. Figure 11 is a structural layout of the shielding layer, active layer, and first gate layer in the display panel shown in Figure 2. Figure 12 is a structural layout of the shielding layer, active layer, first gate layer, and second gate layer in the display panel shown in Figure 2. Figure 13 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, and first source / drain layer in the display panel shown in Figure 2. Figure 14 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 2.

[0124] As shown in Figure 14, the display panel may include multiple pixel driving circuits Pix arrayed in a first direction X and a second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X is a row direction and the second direction Y is a column direction. The pixel driving circuits can be as shown in Figure 1. These multiple pixel driving circuits form multiple pixel driving circuit row groups Phz distributed in the second direction. Each pixel driving circuit row group Phz includes two adjacent pixel driving circuit rows Ph, and each pixel driving circuit row Ph includes multiple pixel driving circuits Pix distributed in the first direction X. In this configuration, the orthographic projections of two adjacent pixel driving circuit rows Phz on the substrate are at least partially mirror-symmetrical along the first axis of symmetry AA. The first axis of symmetry AA is parallel to the first direction X. For example, as shown in FIG14, the orthographic projections of the channel regions of the same type of transistors in two pixel driving circuits located in the same column of the pixel driving circuit row Phz on the substrate are mirror-symmetrical along the first axis of symmetry AA. For example, the orthographic projections of the channel regions of the driving transistors in two pixel driving circuits located in the same column of the pixel driving circuit row Phz on the substrate are mirror-symmetrical along the first axis of symmetry AA, and the orthographic projections of the channel regions of the first transistors in two pixel driving circuits located in the same column of the pixel driving circuit row Phz on the substrate are mirror-symmetrical along the first axis of symmetry AA.

[0125] As shown in Figure 14, the orthographic projections of two adjacent pixel driving circuits located in the same row on the substrate are at least partially mirror-symmetrically arranged along the second axis of symmetry BB. Specifically, the orthographic projections of the channel regions of the same type of transistors in the two adjacent pixel driving circuits in the same row on the substrate are mirror-symmetrically arranged along the second axis of symmetry BB. For example, the orthographic projection of the channel region of the first transistor in the two adjacent pixel driving circuits in the same row on the substrate is mirror-symmetrically arranged along the second axis of symmetry BB, which extends in the second direction Y. It should be understood that in other exemplary embodiments, the orthographic projections of two adjacent pixel driving circuits in the same row on the substrate may also be asymmetrically arranged.

[0126] As shown in Figures 2, 3, and 10, the shielding layer includes multiple shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are interconnected.

[0127] As shown in Figures 2, 4, and 11, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, and a first initial signal line Vinit1. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 731 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected to the first active portion. The first active part 71 is connected to the second active part 72; the tenth active part 710 and the eleventh active part 711 are connected to the two ends of the eighth active part 78; the twelfth active part 712 is connected to the end of the seventh active part 77 away from the sixth active part 76; the thirteenth active part 713 is connected between the seventh active part 77 and the sixth active part 76; the fourteenth active part 714 is connected to the end of the fifth active part 75 away from the third active part 73; the fifteenth active part 715 is connected between the fifth active part 75 and the third active part 73; the sixteenth active part 716 is connected to the end of the fourth active part 74 away from the third active part 73; the seventeenth active part 717 is connected between the third sub-active part 723 and the fourth sub-active part 724; the first initial signal line Vinit1 is connected to the end of the first active part 71 away from the second active part 72. The active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon thin-film transistors. In this exemplary embodiment, both the first transistor T1 and the second transistor T2 have two spaced-apart channel regions. Correspondingly, both the first transistor and the second transistor have two gates, i.e., the first transistor and the second transistor are dual-gate structures. The dual-gate structure transistor has a smaller turn-off leakage current. This configuration can reduce the leakage current through the first transistor and the second transistor to the gate of the driving transistor, thereby improving the voltage stability of the gate of the driving transistor.

[0128] As shown in Figures 2 and 10, the orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can block light from the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source. The shielding layer can shield the pixel driving circuit from signals, and the shielding layer can be connected to stable voltage sources such as the first initial signal terminal, the second initial signal terminal, the third initial signal terminal, the first power supply terminal, and the second power supply terminal in Figure 1.

[0129] As shown in Figures 2, 5, and 11, the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projections of the first gate line G1, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to conduct the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0130] As shown in Figures 2, 6, and 12, the second gate layer may include a second conductive portion 22, a third conductive portion 23, and a second initial signal line Vinit2. The orthographic projection of the second conductive portion 22 onto the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 onto the substrate. The second conductive portion 22 is used to form the second electrode of capacitor C. The orthographic projection of the third conductive portion 23 onto the substrate may at least partially overlap with the orthographic projection of the seventeenth active portion 717 onto the substrate. The third conductive portion 23 may be connected to a stable power supply terminal, and the third conductive portion 23 may regulate the voltage of the seventeenth active portion 717 to improve the problem of leakage to the source / drain of the second transistor T2 caused by voltage fluctuations in the seventeenth active portion 717. The third conductive portion 23 may be connected to stable voltage sources such as the first initial signal terminal, the second initial signal terminal, the third initial signal terminal, the first power supply terminal, and the second power supply terminal in Figure 1. The orthographic projection of the second initial signal line Vinit2 onto the substrate extends along the first direction X. The second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 1. In the same pixel driving circuit row group, the orthographic projection of the second initial signal line Vinit2 on the substrate is located between the orthographic projections of the two second reset signal lines Re2 on the substrate.

[0131] As shown in Figures 2, 7, and 13, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, a third initial signal line Vinit3, and a first fan-out line FIPH. The first bridging portion 41 is connected to the third conductive portion 23 via a via. The second bridging portion 42 can be connected to the first conductive portion 11 and the ninth active portion 79 via vias to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2. A through-hole 221 is formed on the second conductive portion 22, and the through-hole connecting the first conductive portion 11 and the second bridging portion 42 can be disposed through the through-hole 221. The third bridging portion 43 is connected to the second conductive portion 22 and the fourteenth active portion 714 via vias to connect the second electrode of the capacitor C and the first electrode of the fifth transistor. The fourth bridging section 44 can be connected to the thirteenth active section 713 via vias to connect the second terminals of the sixth and seventh transistors. The fifth bridging section 45 can be connected to the twelfth active section 712 and the second initial signal line Vinit2 via vias to connect the first terminal and the second initial signal terminal of the seventh transistor T7. The sixth bridging section 46 can be connected to the sixteenth active section 716 via vias to connect the first terminal of the fourth transistor T4. The eighth bridging section 48 can be connected to the fifteenth active section 715 and the eleventh active section 711 via vias to connect the second terminal of the eighth transistor T8 and the first terminal of the driving transistor T3. The ninth bridging section 49 can be connected to the first initial signal line Vinit1 via vias. The orthographic projection of the third initial signal line Vinit3 on the substrate can extend along the first direction X, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in FIG1. In the same pixel driving circuit row group, the orthographic projection of the third initial signal line Vinit3 on the substrate is located between the orthographic projections of the two second reset signal lines Re2 on the substrate. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the first direction X, and the first fan-out line FIPH can serve as a row direction fan-out line connecting data lines in the FIP (Fanout In Pixel).

[0132] As shown in Figures 2, 8, and 14, the second source / drain layer may include a data line Da, a power line VDD, a second fan-out line FIPV, a first initial signal connection line 5Vinit1, a second initial signal connection line 5Vinit2, a third initial signal connection line 5Vinit3, and a tenth bridge section 510. The orthogonal projections of the data line Da, power line VDD, second fan-out line FIPV, first initial signal connection line 5Vinit1, second initial signal connection line 5Vinit2, and third initial signal connection line 5Vinit3 onto the substrate all extend along the second direction Y. The data line Da provides the data signal terminal shown in Figure 1. The data line Da can be connected to the sixth bridge section 46 via vias to connect the data signal terminal and the first terminal of the fourth transistor T4. The power line VDD provides the first power terminal shown in Figure 1. The power line VDD can be connected to the third bridge section 43 and the first bridge section 41 via vias to connect the first power terminal and the first terminal of the fifth transistor T5 and the second terminal of the capacitor C. The first initial signal connection line 5Vinit1 can be connected via a via to the ninth bridging part 49 to connect to the intersecting first initial signal line Vinit1. The first initial signal connection line 5Vinit1 and the first initial signal line Vinit1 can form a grid structure. The second initial signal connection line 5Vinit2 can be connected via a via to the fifth bridging part 45 to connect to the intersecting second initial signal line Vinit2. The second initial signal connection line 5Vinit2 and the second initial signal line Vinit2 can form a grid structure. The third initial signal connection line 5Vinit3 can be connected via a via to the intersecting third initial signal line Vinit3. The third initial signal connection line 5Vinit3 and the third initial signal line Vinit3 can form a grid structure. The grid structure of the initial signal lines can reduce the voltage difference on the initial signal lines at different positions on the display panel, thereby improving the display uniformity of the display panel. Specifically, one initial signal connection line is set for every two columns of pixel driving, and three initial signal connection lines can be set for every six adjacent columns of pixel driving circuits: the first initial signal connection line 5Vinit1, the second initial signal connection line 5Vinit2, and the third initial signal connection line 5Vinit3. The second fan-out line FIPV can serve as a column-direction fan-out line connecting data lines within a FIP (Fanout In Pixel). The second fan-out line FIPV can include multiple fan-out line segments spaced apart in the column direction, and adjacent fan-out line segments can be bridged via the seventh bridging part 47. The tenth bridging part 510 can be connected to the fourth bridging part 44 via a via.

[0133] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, any one of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in any one of the active layer, the second gate layer, the first source / drain layer, and the second source / drain layer.

[0134] In this exemplary embodiment, as shown in FIG2, in two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA, the two seventh active units 77 are connected through the twelfth active unit 712. The two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA can share the same second initial signal line Vinit2. The second initial signal line Vinit2 is connected to the twelfth active unit 712 through a via, thereby simultaneously connecting the seventh transistors in the two mirror-symmetrical pixel driving circuits. This arrangement can improve the integration density of the pixel driving circuits in the display panel.

[0135] In this exemplary embodiment, as shown in FIG2, in two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA, the two eighth active portions 78 are connected through the tenth active portion 710. The two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA can share the same third initial signal line Vinit3. The third initial signal line Vinit3 is connected to the tenth active portion 710 through a via, thereby simultaneously connecting the eighth transistors in the two mirror-symmetrical pixel driving circuits. This arrangement can also improve the integration density of the pixel driving circuits in the display panel.

[0136] As shown in Figures 2 and 9, the plurality of electrode portions include: a plurality of R electrode portions R, a plurality of G electrode portions G, and a plurality of B electrode portions B. The R electrode portions are used to form the first electrode of the red light-emitting unit, the G electrode portions are used to form the first electrode of the green light-emitting unit, and the B electrode portions are used to form the first electrode of the blue light-emitting unit. In the plurality of electrode portions connected to the same row of pixel driving circuits, the orthogonal projections of the R electrode portions, G electrode portions, B electrode portions and G electrode portions on the substrate are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, the plurality of R electrode portions and the plurality of B electrode portions are connected to the same column of pixel driving circuits, and the orthogonal projections of the R electrode portions and B electrode portions connected to the same column of pixel driving circuits on the substrate are alternately distributed in the column direction. The plurality of G electrode portions are connected to another column of pixel driving circuits.

[0137] As shown in Figures 2 and 9, each electrode part includes a main body part 91 and a connecting part 92. The main body part 91 is at least partially used to form the first electrode of the light-emitting unit, and the connecting part 92 is connected between the main body part 91 and the pixel driving circuit Pix.

[0138] In this exemplary embodiment, the plurality of electrode portions may include a plurality of first electrode portions, which are used to form the first electrode of the same color light-emitting unit, as shown in FIG2 and 9. The first electrode portion may be a G electrode portion.

[0139] As shown in Figure 2-14, in the same pixel driving circuit row group Phz, the pixel driving circuit in one pixel driving circuit row Ph forms a first pixel driving circuit P1, and the pixel driving circuit in another pixel driving circuit row Ph forms a second pixel driving circuit P2. The extension length of the orthographic projection of the connecting portion 92 of the first electrode portion (G electrode portion) connected to the first pixel driving circuit P1 onto the substrate is greater than the extension length of the orthographic projection of the connecting portion 92 of the first electrode portion (G electrode portion) connected to the second pixel driving circuit P2 onto the substrate, and the area of ​​the orthographic projection of the main body portion 91 of the first electrode portion (G electrode portion) connected to the first pixel driving circuit P1 onto the substrate is smaller than the area of ​​the orthographic projection of the main body portion 91 of the first electrode portion (G electrode portion) connected to the second pixel driving circuit P2 onto the substrate.

[0140] In this exemplary embodiment, since the orthographic projections of two pixel driving circuit rows in the same pixel driving circuit row group Phz onto the substrate are mirror-symmetrically arranged along the first axis of symmetry AA, in the same-color light-emitting units respectively connected to the two pixel driving circuit rows in the same pixel driving circuit row group, at least one color light-emitting unit has a length difference in the connection portion of the electrode portion. This results in different capacitances being formed between the first electrode and other conductive structures of the light-emitting units of the same color but different rows, leading to horizontal lines appearing on the display panel. This exemplary embodiment compensates for the difference in capacitance of the electrode portions by controlling the area of ​​the main body portion 91, thereby improving the above-mentioned horizontal line problem.

[0141] In this exemplary embodiment, the display panel may further include a pixel defining layer located on the side of the electrode layer opposite to the substrate. A plurality of pixel openings are formed on the pixel defining layer, and the pixel openings are correspondingly disposed with the electrode portions. The orthographic projection of each pixel opening onto the substrate is located within the orthographic projection of the corresponding main body portion 91 onto the substrate. As shown in Figures 2 and 9, the main body portion 91 includes a body portion 911 and an epitaxial portion 912. The epitaxial portion 912 is disposed around the body portion 911, and the orthographic projection of each pixel opening onto the substrate coincides with the orthographic projection of the corresponding body portion 911 onto the substrate.

[0142] As shown in Figure 2-14, the main body 91 of the first electrode portion (G electrode portion) connected to the second pixel driving circuit P2 further includes a first protrusion 913, which is connected to the extension portion 912. This exemplary embodiment compensates for the area of ​​the corresponding first electrode portion (G electrode portion) by using the first protrusion 913, so that the area of ​​the orthographic projection of the first electrode portion (G electrode portion) connected to the first pixel driving circuit P1 onto the substrate is equal to or approximately the same as the area of ​​the orthographic projection of the first electrode portion (G electrode portion) connected to the second pixel driving circuit P2 onto the substrate. This makes the capacitance formed by the first electrode portion (G electrode portion) connected to the first pixel driving circuit P1 equal to or approximately the same as the capacitance formed by the first electrode portion (G electrode portion) connected to the second pixel driving circuit P2, thereby improving the problem of horizontal lines on the display panel.

[0143] As shown in Figure 2-14, the pixel driving circuit row group Phz includes multiple repeating units Pc distributed in the first direction X. Figure 2-14 shows a repeating unit in the display panel. The repeating unit Pc includes two rows and four columns of the pixel driving circuit Pix. In the same repeating unit Pc, the two G electrode portions connecting the first pixel driving circuit P1 respectively form a first G electrode portion G1 and a second G electrode portion G2. The extension length of the orthographic projection of the connecting portion 92 in the first G electrode portion G1 onto the substrate is greater than the extension length of the orthographic projection of the connecting portion 92 in the second G electrode portion G2 onto the substrate, and the area of ​​the orthographic projection of the main body portion 91 in the first G electrode portion G1 onto the substrate is smaller than the area of ​​the orthographic projection of the main body portion 91 in the second G electrode portion G2 onto the substrate. This arrangement also allows the capacitance formed by the first G electrode portion G1 and the capacitance formed by the second G electrode portion G2 to be the same or approximately the same, thereby improving the uniformity of the display panel.

[0144] As shown in Figure 2-14, in the same repeating unit Pc, the two G electrode portions connected to the second pixel driving circuit P2 respectively form a third G electrode portion G3 and a fourth G electrode portion G4. The extension length of the orthographic projection of the connecting portion 92 in the third G electrode portion G3 onto the substrate is greater than the extension length of the orthographic projection of the connecting portion 92 in the fourth G electrode portion G4 onto the substrate, and the area of ​​the orthographic projection of the main body portion 91 in the third G electrode portion G3 onto the substrate is smaller than the area of ​​the orthographic projection of the main body portion 91 in the fourth G electrode portion G4 onto the substrate. For example, as shown in Figure 9, the area of ​​the orthographic projection of the first protrusion 913 in the third G electrode portion G3 onto the substrate is smaller than the area of ​​the orthographic projection of the first protrusion 913 in the fourth G electrode portion G4 onto the substrate. This arrangement can also improve the uniformity of the display panel.

[0145] As shown in Figure 2-14, the main body 91 of the second G electrode portion G2 also includes a second protrusion 914. The second protrusion 914 is connected to the extension portion 912. In this exemplary embodiment, the area of ​​the second G electrode portion G2 is compensated by the second protrusion 914, so that the area of ​​the orthographic projection of the first G electrode portion G1 on the substrate and the area of ​​the orthographic projection of the second G electrode portion G2 on the substrate are the same or result in the same area. This arrangement can improve the uniformity of the display panel display.

[0146] It should be understood that in other exemplary embodiments, the area of ​​the first G electrode portion G1 projected onto the substrate can be reduced to make the area of ​​the first G electrode portion G1 projected onto the substrate the same as or result in the same area of ​​the second G electrode portion G2 projected onto the substrate. For example, as shown in FIG15, which is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure, a second missing portion 922 can be formed on the epitaxial portion 912 of the first G electrode portion G2. The second missing portion 922 can be disposed around the epitaxial portion 912, that is, the area of ​​the first G electrode portion G1 is reduced by reducing the width of the epitaxial portion 912. Furthermore, in other exemplary embodiments, the second missing portion can also be a notch or a through hole formed on the epitaxial portion 912.

[0147] Figure 16 shows a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure. A first missing portion 921 is formed on the extension portion 912 of the first electrode portion (first G electrode portion G1, second G electrode portion G2) connected to the first pixel driving circuit P1. This exemplary embodiment can reduce the area of ​​the first electrode portion connected to the first pixel driving circuit P1 so that the area of ​​the orthographic projection of the first electrode portion (first G electrode portion G1, second G electrode portion G2) connected to the first pixel driving circuit P1 on the substrate is equal to or approximately the same as the area of ​​the orthographic projection of the first electrode portion (third G electrode portion G3, fourth G electrode portion G4) connected to the second pixel driving circuit P2 on the substrate. This makes the capacitance formed by the first electrode portion connected to the first pixel driving circuit P1 equal to or approximately the same as the capacitance formed by the first electrode portion connected to the second pixel driving circuit P2. This arrangement can also improve the problem of horizontal lines in the display panel.

[0148] As shown in Figure 16, in the same repeating unit Pc, the extension length of the orthographic projection of the connecting portion 92 in the first G electrode portion G1 onto the substrate is greater than the extension length of the orthographic projection of the connecting portion 92 in the second G electrode portion G2 onto the substrate. Correspondingly, the area of ​​the first missing portion 921 on the substrate of the first G electrode portion G1 is greater than the area of ​​the first missing portion 921 on the substrate of the second G electrode portion G2. That is, the width of the epitaxial portion 912 on the substrate of the first G electrode portion G1 is less than the width of the epitaxial portion 912 on the substrate of the second G electrode portion G2.

[0149] As shown in FIG16, the first missing portion 921 may be disposed around the epitaxial portion 912. It should be understood that in other exemplary embodiments, the first missing portion 921 may also have other arrangements. For example, as shown in FIG17, which is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure, the first missing portion 921 may also be a notch or a through hole formed on the epitaxial portion 912.

[0150] Figure 18 shows a partial cross-sectional view of the display panel shown in Figure 2, taken along the dashed line CC. This display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, a second planarization layer 107, and a pixel defining layer 108. The substrate 100, shielding layer, buffer layer 101, active layer, first insulating layer 102, first gate layer, second insulating layer 103, second gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, electrode layer, and pixel defining layer 108 are sequentially stacked. A pixel opening H is formed on the pixel defining layer 108, and a light-emitting unit can be formed within the pixel opening H. The buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0151] Figure 19 shows a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure. The first electrode portion can be a B electrode portion. The extension length of the orthographic projection of the connection portion 92 of the first electrode portion (B electrode portion in the first row electrode portion) connected to the first pixel driving circuit on the substrate is greater than the extension length of the orthographic projection of the connection portion 92 of the first electrode portion (B electrode portion in the second row electrode portion) connected to the second pixel driving circuit P2 on the substrate, and the area of ​​the orthographic projection of the main body portion 91 of the first electrode portion (B electrode portion) connected to the first pixel driving circuit P1 on the substrate is smaller than the area of ​​the orthographic projection of the main body portion 91 of the first electrode portion (B electrode portion) connected to the second pixel driving circuit P2 on the substrate.

[0152] This exemplary embodiment can also improve the horizontal stripe problem of the display panel by controlling the area of ​​the main body 91 to compensate for the difference in capacitance of the electrode part.

[0153] As shown in FIG19, the main body 91 of the first electrode portion (B electrode portion) connected to the second pixel driving circuit P2 further includes a first protrusion 913, which is connected to the extension portion 912. This exemplary embodiment compensates for the area of ​​the corresponding first electrode portion (B electrode portion) by using the first protrusion 913, so that the area of ​​the orthographic projection of the first electrode portion (B electrode portion) connected to the first pixel driving circuit P1 onto the substrate is equal to or approximately the same as the area of ​​the orthographic projection of the first electrode portion (B electrode portion) connected to the second pixel driving circuit P2 onto the substrate. This makes the capacitance formed by the first electrode portion (B electrode portion) connected to the first pixel driving circuit P1 equal to or approximately the same as the capacitance formed by the first electrode portion (B electrode portion) connected to the second pixel driving circuit P2. This arrangement can improve the problem of horizontal lines on the display panel.

[0154] Figure 20 shows a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure. A first missing portion 921 is formed on the extension portion 912 of the first electrode portion (the B electrode portion in the first row of electrodes) connected to the first pixel driving circuit P1. This exemplary embodiment can reduce the area of ​​the first electrode portion connected to the first pixel driving circuit P1 so that the area of ​​the orthographic projection of the first electrode portion (B electrode portion) connected to the first pixel driving circuit P1 on the substrate is equal to or approximately the same as the area of ​​the orthographic projection of the first electrode portion (B electrode portion) connected to the second pixel driving circuit P2 on the substrate. This makes the capacitance formed by the first electrode portion connected to the first pixel driving circuit P1 equal to or approximately the same as the capacitance formed by the first electrode portion connected to the second pixel driving circuit P2. This arrangement can also improve the problem of horizontal lines in the display panel.

[0155] As shown in FIG20, the first missing portion 921 may be disposed around the epitaxial portion 912. It should be understood that in other exemplary embodiments, the first missing portion 921 may also have other arrangements. For example, as shown in FIG21, which is a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure, the first missing portion 921 may also be a notch or a through hole formed on the epitaxial portion 912.

[0156] Figure 22 shows a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure. The first electrode portion can be an R electrode portion. The extension length of the orthographic projection of the connection portion 92 of the first electrode portion (R electrode portion in the first row electrode portion) connected to the first pixel driving circuit on the substrate is greater than the extension length of the orthographic projection of the connection portion 92 of the first electrode portion (R electrode portion in the second row electrode portion) connected to the second pixel driving circuit P2 on the substrate, and the area of ​​the orthographic projection of the main body portion 91 of the first electrode portion (R electrode portion) connected to the first pixel driving circuit P1 on the substrate is smaller than the area of ​​the orthographic projection of the main body portion 91 of the first electrode portion (R electrode portion) connected to the second pixel driving circuit P2 on the substrate.

[0157] This exemplary embodiment can also improve the horizontal stripe problem of the display panel by controlling the area of ​​the main body 91 to compensate for the difference in capacitance of the electrode part.

[0158] As shown in FIG22, the main body 91 of the first electrode portion (R electrode portion) connected to the second pixel driving circuit P2 further includes a first protrusion 913, which is connected to the epitaxial portion 912. This exemplary embodiment compensates for the area of ​​the corresponding first electrode portion (R electrode portion) by using the first protrusion 913, so that the area of ​​the orthographic projection of the first electrode portion (R electrode portion) connected to the first pixel driving circuit P1 onto the substrate is equal to or approximately the same as the area of ​​the orthographic projection of the first electrode portion (R electrode portion) connected to the second pixel driving circuit P2 onto the substrate. This makes the capacitance formed by the first electrode portion (R electrode portion) connected to the first pixel driving circuit P1 equal to or approximately the same as the capacitance formed by the first electrode portion (R electrode portion) connected to the second pixel driving circuit P2, thereby improving the problem of horizontal lines on the display panel.

[0159] Figure 23 shows a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure. A first missing portion 921 is formed on the extension portion 912 of the first electrode portion (R electrode portion in the first row electrode portion) connected to the first pixel driving circuit P1. This exemplary embodiment can reduce the area of ​​the first electrode portion connected to the first pixel driving circuit P1 so that the area of ​​the orthographic projection of the first electrode portion (R electrode portion) connected to the first pixel driving circuit P1 on the substrate is equal to or approximately the same as the area of ​​the orthographic projection of the first electrode portion (R electrode portion) connected to the second pixel driving circuit P2 on the substrate. This makes the capacitance formed by the first electrode portion connected to the first pixel driving circuit P1 equal to or approximately the same as the capacitance formed by the first electrode portion connected to the second pixel driving circuit P2. This arrangement can also improve the problem of horizontal lines in the display panel.

[0160] As shown in FIG23, the first missing portion 921 may be disposed around the epitaxial portion 912. It should be understood that in other exemplary embodiments, the first missing portion 921 may also have other arrangements. For example, FIG24 shows a structural layout of the electrode layer in another exemplary embodiment of the display panel of this disclosure. The first missing portion 921 may also be a notch or a through hole formed on the epitaxial portion 912.

[0161] In this exemplary embodiment, the first missing portion 921 may also be located on the body portion 911. The orthographic projection of the first missing portion 921 on the substrate may at least partially overlap with the orthographic projection of the data line Da on the substrate. For example, as shown in FIG25, it is a structural layout of the second source / drain layer and electrode layer in another exemplary embodiment of the display panel of this disclosure. The orthographic projection of the first missing portion 921 on the first G electrode portion G1 and the second G electrode portion G2 on the substrate may at least partially overlap with the orthographic projection of the data line Da on the substrate. This arrangement can not only greatly reduce the parasitic capacitance of the first G electrode portion G1 and the second G electrode portion G2, but also reduce the parasitic capacitance between the data line Da and the first G electrode portion G1 and the second G electrode portion G2, thereby reducing the signal interference between the data line Da and the first G electrode portion G1 and the second G electrode portion G2. It should be understood that, in other exemplary embodiments, the first missing portion 921 on the R electrode portion and the B electrode portion may also be located on the body portion 911, and the orthogonal projection of the first missing portion 921 on the R electrode portion and the B electrode portion on the substrate may at least partially overlap with the orthogonal projection of the data line Da on the substrate.

[0162] In this exemplary embodiment, the first missing portion 921 may also be located on the body portion 911, and the orthographic projection of the first missing portion 921 on the substrate and the orthographic projection of the voltage regulation signal line in the display panel on the substrate do not overlap at least partially or completely. The voltage regulation signal line may include any one or more of the following: power line VDD, first initial signal connection line 5Vinit1, second initial signal connection line 5Vinit2, and third initial signal connection line 5Vinit3. For example, as shown in FIG26, it is a structural layout of the second source / drain layer and electrode layer in another exemplary embodiment of the display panel of this disclosure. The first electrode portion (electrode B in the first row electrode portion) connected to the first pixel driving circuit P1, and the power line VDD, the first initial signal connection line 5Vinit1, the second initial signal connection line 5Vinit2, and the third initial signal connection line 5Vinit3, do not overlap on the substrate. This setting can not only adjust the parasitic capacitance of the B electrode portion, but also increase the parasitic capacitance between the power line VDD, the first initial signal connection line 5Vinit1, the second initial signal connection line 5Vinit2, the third initial signal connection line 5Vinit3, and the B electrode portion. Thus, the voltage of the electrode portion B can be regulated by the power line VDD, the first initial signal connection line 5Vinit1, the second initial signal connection line 5Vinit2, the third initial signal connection line 5Vinit3, and other voltage-regulated signal lines. As shown in Figure 26, the orthographic projection of the body portion 911 on the substrate of the first electrode portion (B electrode portion in the first row electrode portion) connected to the first pixel driving circuit P1 overlaps with the orthographic projection of the power line VDD on the substrate. It should be understood that the orthographic projection of the body portion 911 on the substrate of the first electrode portion (B electrode portion in the first row electrode portion) connected to the first pixel driving circuit P1 can also overlap with the orthographic projection of any one or more of the voltage regulation signal lines such as the first initial signal connection line 5Vinit1, the second initial signal connection line 5Vinit2, the third initial signal connection line 5Vinit3, and the power line VDD on the substrate.

[0163] In this exemplary embodiment, the pixel driving circuit in the display panel shown in Figures 15-24 can be as shown in Figure 1, and the layout structure of the pixel driving circuit in the display panel shown in Figures 15-24 can be as shown in Figure 14. As shown in Figures 15-24, the via positions connecting the electrode layer and the second source / drain layer are different in different display panels. Accordingly, display panels with different electrode layers can bridge the electrode portion and the pixel driving circuit by adjusting the shape and position of the fourth bridging portion and / or the tenth bridging portion in Figure 14. It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel can also have other structures.

[0164] As shown in Figure 2-24, the orthographic projection of the epitaxial portion 912 onto the substrate forms a ring structure of equal width. This equal-width ring structure means that the width is equal at all locations. It should be understood that during the manufacturing process of the display panel, slight differences in the width of the equal-width ring structure at different locations may occur due to manufacturing errors.

[0165] As shown in Figure 2-24, the widths of the equal-width annular structures formed by the epitaxial portion in the R electrode section, the G electrode section, and the B electrode section are all equal.

[0166] In this exemplary embodiment, as shown in FIG2-24, the orthographic projection of the first protrusion on the substrate can at least partially overlap with the orthographic projection of the second source / drain layer on the substrate. The electrode layer and the second source / drain layer are close together, which can greatly increase the capacitance formed by the first protrusion. Similarly, the orthographic projection of the second protrusion on the substrate can also at least partially overlap with the orthographic projection of the second source / drain layer on the substrate.

[0167] In this exemplary embodiment, the orthographic projection of the first protrusion on the substrate may overlap with the orthographic projection of at least a portion of the channel region of the transistor on the substrate. The first protrusion can provide light shielding for the transistor. Similarly, the orthographic projection of the second protrusion on the substrate may overlap with the orthographic projection of at least a portion of the channel region of the transistor on the substrate.

[0168] In this exemplary embodiment, as shown in FIG2-24, the length of the orthographic projection of the outer edge of the epitaxial portion 912 on the substrate is L1, and the extension length of the orthographic projection of the boundary line between the first protrusion 913 and the epitaxial portion 912 on the substrate is L2. L2 / L1 is greater than or equal to 20% and less than or equal to 1. For example, L2 / L1 can be equal to 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 1. When L2 / L1 equals 1, the first protrusion is provided around the epitaxial portion. At the same time, setting L2 / L1 to a value greater than or equal to 20% can reduce the resistance of the electrode portion, improve the charging efficiency of the electrode portion, and reduce the power consumption of the electrode portion.

[0169] This exemplary embodiment also provides a display panel, wherein the display panel includes: a substrate, a plurality of light-emitting units, a plurality of pixel driving circuits, and an electrode layer. The pixel driving circuits drive the light-emitting units, and the plurality of pixel driving circuits are arrayed along a first direction and a second direction, the first direction and the second direction intersecting; the plurality of pixel driving circuits form a plurality of pixel driving circuit rows distributed in the second direction, each pixel driving circuit row group including two adjacent pixel driving circuit rows, each pixel driving circuit row including a plurality of pixel driving circuits distributed in the first direction; wherein, the orthographic projections of two adjacent pixel driving circuit rows in the pixel driving circuit row group on the substrate are at least partially mirror-symmetrically arranged along a first axis of symmetry, the first axis of symmetry being parallel to the first direction; the electrode layer includes a plurality of electrode portions, each electrode portion including a main body portion and a connecting portion, the main body portion being at least partially used to form a first electrode of the light-emitting unit, the... A connecting portion is connected between the main body portion and the pixel driving circuit; wherein, among the plurality of electrode portions, there are a plurality of first electrode portions, and the plurality of first electrode portions are used to respectively form the first electrode of the same color light-emitting unit; in the same pixel driving circuit row group, the pixel driving circuit in one pixel driving circuit row forms a first pixel driving circuit, and the pixel driving circuit in another pixel driving circuit row forms a second pixel driving circuit; the difference between the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate and the area of ​​the orthographic projection of the first electrode portion connected to the second pixel driving circuit on the substrate is S1, and the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate is S2, and S1 / S2 is greater than or equal to 0 and less than or equal to 5%.

[0170] In this exemplary embodiment, S1 / S2 can be equal to 0, 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, etc.

[0171] In this exemplary embodiment, the areas of the same-color electrode portions are set to be equal or approximately the same, so that the capacitance formed by the first electrode portion connected to the first pixel driving circuit P1 and the capacitance formed by the first electrode portion connected to the second pixel driving circuit P2 are equal or approximately the same. This setting can also improve the problem of horizontal stripes on the display panel.

[0172] This exemplary embodiment also provides a display panel, the display panel comprising: a substrate, a plurality of light-emitting units, a plurality of pixel driving circuits, and an electrode layer. The pixel driving circuits are used to drive the light-emitting units. The plurality of pixel driving circuits are arrayed along a first direction and a second direction, the first direction and the second direction intersecting each other. The plurality of pixel driving circuits form a plurality of pixel driving circuit rows distributed in the second direction. Each pixel driving circuit row includes two adjacent pixel driving circuit rows. Each pixel driving circuit row includes a plurality of pixel driving circuits distributed in the first direction. In the pixel driving circuit row group, the orthographic projections of two adjacent pixel driving circuit rows on the substrate are at least partially mirror-symmetrically arranged along a first axis of symmetry, the first axis of symmetry being parallel to the first direction. The electrode layer includes a plurality of electrode portions. The electrode portion includes a main body portion and a connecting portion. The main body portion is at least partially used to form the first electrode of the light-emitting unit, and the connecting portion connects the main body portion and the pixel driving circuit. The plurality of electrode portions include a plurality of first electrode portions, which are used to respectively form the first electrode of the same color light-emitting unit. In the same pixel driving circuit row group, the pixel driving circuit in one pixel driving circuit row forms a first pixel driving circuit, and the pixel driving circuit in another pixel driving circuit row forms a second pixel driving circuit. The capacitance formed by the first electrode portion connected to the first pixel driving circuit and the equipotential portion electrically connected thereto is C1, and the capacitance formed by the first electrode portion connected to the second pixel driving circuit and the equipotential portion electrically connected thereto is C2. |C1-C2| / C1 is less than or equal to 2%. For example, |C1-C2| / C1 can be equal to 0, 0.5%, 1%, 1.5%, or 2%.

[0173] In this exemplary embodiment, the equipotential bonding section electrically connected to the first electrode section may include structures such as a fourth bridging section 44 and a tenth bridging section 510. This exemplary embodiment sets the capacitance formed by the same-color electrode section and its equipotential bonding section to be equal or substantially the same; this setting can also improve the problem of horizontal stripes on the display panel.

[0174] In this exemplary embodiment, the capacitance formed by the first electrode portion and its equipotential portion can be adjusted by adjusting the area of ​​their orthogonal projections onto the substrate. Furthermore, this exemplary embodiment can also adjust the capacitance formed by the first electrode portion and its equipotential portion by adjusting the overlapping area of ​​the orthogonal projections of other conductive portions and the first electrode portion, and the equipotential portion of the first electrode portion, onto the substrate. For example, this exemplary embodiment can adjust the overlapping area of ​​the orthogonal projections of the data line, power line, and the first electrode portion, and the equipotential portion of the first electrode portion, onto the substrate by providing missing portions or adding portions on the data line or power line.

[0175] It should be noted that, as shown in Figures 2, 13, and 14, the black squares with chamfers drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black circles drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different locations can penetrate different insulating layers.

[0176] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0177] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0178] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0179] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Substrate; Multiple light-emitting units; Multiple pixel driving circuits are provided to drive the light-emitting unit. The multiple pixel driving circuits are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect. The plurality of pixel driving circuits form a plurality of pixel driving circuit row groups distributed in the second direction, the pixel driving circuit row group includes two adjacent pixel driving circuit rows, and the pixel driving circuit row includes a plurality of pixel driving circuits distributed in the first direction. In the pixel driving circuit row group, the orthogonal projections of two adjacent pixel driving circuit rows on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry, and the first axis of symmetry is parallel to the first direction. An electrode layer includes multiple electrode portions, each electrode portion including a main body portion and a connecting portion. The main body portion is at least partially used to form the first electrode of the light-emitting unit, and the connecting portion is connected between the main body portion and the pixel driving circuit. A pixel defining layer is located on the side of the electrode layer opposite to the substrate. A plurality of pixel openings are formed on the pixel defining layer. The pixel openings are correspondingly disposed with the electrode portions. The orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the main body of the corresponding electrode portion on the substrate. Among them, the plurality of electrode portions include a plurality of first electrode portions, and the plurality of first electrode portions are used to form the first electrode of the same color light-emitting unit respectively; In the same pixel driving circuit row group, the pixel driving circuit in one pixel driving circuit row forms the first pixel driving circuit, and the pixel driving circuit in another pixel driving circuit row forms the second pixel driving circuit. The orthographic projection length of the connecting portion of the first electrode portion connecting the first pixel driving circuit on the substrate is greater than the orthographic projection length of the connecting portion of the first electrode portion connecting the second pixel driving circuit on the substrate, and the orthographic projection area of ​​the main body portion of the first electrode portion connecting the first pixel driving circuit on the substrate is smaller than the orthographic projection area of ​​the main body portion of the first electrode portion connecting the second pixel driving circuit on the substrate. The area of ​​the projection.

2. The display panel according to claim 1, wherein, The main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate. The main body portion of the first electrode portion connected to the second pixel driving circuit also includes a first protrusion portion, which is connected to the outer extension portion.

3. The display panel according to claim 1, wherein, The main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate. A first missing portion is formed on the epitaxial portion of the first electrode portion connected to the first pixel driving circuit.

4. The display panel according to any one of claims 1-3, wherein, The display panel includes green light-emitting units, red light-emitting units, and blue light-emitting units; The first electrode portion is used to form the first electrode of the green light-emitting unit; Alternatively, the first electrode portion is used to form the first electrode of the red light-emitting unit; Alternatively, the first electrode portion is used to form the first electrode of the blue light-emitting unit.

5. The display panel according to claim 2, wherein, The display panel also includes: A second source / drain layer is located between the substrate and the electrode layer, and the second source / drain layer includes at least a data line; Wherein, the orthographic projection of the first protrusion on the substrate and the orthographic projection of the second source / drain layer on the substrate at least partially overlap.

6. The display panel according to claim 2, wherein, The pixel driving circuit includes one or more transistors, wherein the orthographic projection of the first protrusion on the substrate and the orthographic projection of at least a portion of the channel region of the transistor on the substrate overlap.

7. The display panel according to claim 2, wherein, The length of the orthographic projection of the outer edge of the epitaxial portion onto the substrate is L1, and the extension length of the orthographic projection of the boundary line between the first protrusion and the epitaxial portion onto the substrate is L2, where L2 / L1 is greater than or equal to 20% and less than or equal to 1.

8. The display panel according to claim 3, wherein, The first missing portion is disposed around the outer periphery of the extension portion.

9. The display panel according to claim 3, wherein, The first missing portion is a notch or through hole formed on the epitaxial portion.

10. The display panel according to any one of claims 1-9, wherein, The display panel includes green light-emitting units, red light-emitting units, and blue light-emitting units; The plurality of electrode portions include: a plurality of R electrode portions, a plurality of G electrode portions, and a plurality of B electrode portions, wherein the R electrode portions are used to form the first electrode of the red light-emitting unit, the G electrode portions are used to form the first electrode of the green light-emitting unit, and the B electrode portions are used to form the first electrode of the blue light-emitting unit; The first direction is the row direction, and the second direction is the column direction. Among the multiple electrode portions connected to the same row pixel driving circuit, the orthogonal projections of the R electrode portion, G electrode portion, B electrode portion, and G electrode portion on the substrate are alternately distributed in the row direction. In two adjacent pixel driving circuits, a plurality of R electrode portions and a plurality of B electrode portions are connected to the same column of pixel driving circuits, and the orthogonal projections of the R electrode portions and B electrode portions connected to the same column of pixel driving circuits on the substrate are alternately distributed in the column direction, and a plurality of G electrode portions are connected to another column of pixel driving circuits.

11. The display panel according to claim 10, wherein, The pixel driving circuit row group includes a plurality of repeating units distributed in a first direction, and the repeating unit includes two rows and four columns of the pixel driving circuit, wherein the first electrode part is a G electrode part. In the same repeating unit, the two G electrode portions connected to the first pixel driving circuit respectively form a first G electrode portion and a second G electrode portion. The extension length of the orthographic projection of the connecting portion in the first G electrode portion on the substrate is greater than the extension length of the orthographic projection of the connecting portion in the second G electrode portion on the substrate, and the area of ​​the orthographic projection of the main body portion in the first G electrode portion on the substrate is smaller than the area of ​​the orthographic projection of the main body portion in the second G electrode portion on the substrate.

12. The display panel according to claim 11, wherein, The main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate. The main body of the second G electrode also includes a second protrusion, the second protrusion being connected to... Connected to the extended portion; Alternatively, a second missing portion may be formed on the epitaxial portion of the first G electrode portion.

13. The display panel according to any one of claims 1-12, wherein, The difference between the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate and the area of ​​the orthographic projection of the first electrode portion connected to the second pixel driving circuit on the substrate is S1, and the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate is S2, where S1 / S2 is greater than or equal to 0 and less than or equal to 5%.

14. The display panel according to any one of claims 1-12, wherein, The second direction is the column direction. The pixel driving circuit includes multiple transistors. In two pixel driving circuits located in the same row group and in the same column, the channel regions of the same type of transistor are mirror-symmetrically arranged along the first axis of symmetry when projected onto the substrate.

15. The display panel according to any one of claims 1-12, wherein, The second direction is the column direction, and the pixel driving circuit includes a seventh transistor. The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel also includes: An active layer is located between the substrate and the electrode layer. The active layer includes a seventh active portion and a twelfth active portion. The seventh active portion is used to form the channel region of the seventh transistor. In two pixel driving circuits located in the same row group and in the same column, the two seventh active portions are connected through the twelfth active portion. The second initial signal line extends along the first direction by its orthogonal projection on the substrate, and the second initial signal line is connected to the twelfth active part through a via.

16. The display panel according to any one of claims 1-12, wherein, The second direction is the column direction. The pixel driving circuit includes a driving transistor and an eighth transistor. The first terminal of the eighth transistor is connected to the third initial signal line, and the second terminal of the eighth transistor is connected to the first terminal of the driving transistor. The display panel also includes: An active layer, located on one side of the substrate, includes an eighth active portion and a tenth active portion. The eighth active portion is used to form the channel region of the eighth transistor. In two pixel driving circuits located in the same row and column of the same pixel driving circuit group, the two eighth active portions... The eighth active unit is connected through the tenth active unit; The third initial signal line, the orthogonal projection of the third initial signal line on the substrate extends along the first direction, and the third initial signal line is connected to the tenth active part through a via.

17. The display panel according to any one of claims 1-12, wherein, The orthographic projections of two adjacent pixel driving circuits in the first direction onto the substrate are at least partially mirror-symmetrical along a second axis of symmetry, which extends along the column direction.

18. The display panel according to any one of claims 1-17, wherein, The display panel also includes: A data line, which provides data signals to a pixel driving circuit, extends along a column direction.

19. The display panel according to any one of claims 1-18, wherein, The main body includes a body portion and an epitaxial portion, the epitaxial portion is disposed around the body portion, and the orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding body portion on the substrate. The epitaxial portion is projected onto the substrate to form a ring structure of equal width.

20. The display panel according to claim 19, wherein, The plurality of electrode portions include: a plurality of R electrode portions, a plurality of G electrode portions, and a plurality of B electrode portions, wherein the R electrode portions are used to form the first electrode of the red light-emitting unit, the G electrode portions are used to form the first electrode of the green light-emitting unit, and the B electrode portions are used to form the first electrode of the blue light-emitting unit; The widths of the equal-width annular structures formed by the epitaxial portion in the R electrode section, the G electrode section, and the B electrode section are all equal.

21. The display panel according to any one of claims 1-20, wherein, The pixel driving circuit includes: Drive transistors; The first transistor has a first terminal connected to a first initial signal line and a second terminal connected to the gate of the driving transistor. The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor; The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor. The fifth transistor has its first terminal connected to the power supply line and its second terminal connected to the first terminal of the driving transistor. The sixth transistor has its first electrode connected to the second electrode of the driving transistor, and the second electrode connected to the first electrode of the light-emitting unit. The seventh transistor has its first electrode connected to the second initial signal line and its second electrode connected to the first electrode of the light-emitting unit. The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor. The capacitor has its first electrode connected to the gate of the driving transistor and its second electrode connected to the power supply line.

22. A display panel, wherein, The display panel includes: Substrate; Multiple light-emitting units; Multiple pixel driving circuits are provided to drive the light-emitting unit. The multiple pixel driving circuits are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect. The plurality of pixel driving circuits form a plurality of pixel driving circuit row groups distributed in the second direction, the pixel driving circuit row group includes two adjacent pixel driving circuit rows, and the pixel driving circuit row includes a plurality of pixel driving circuits distributed in the first direction. In the pixel driving circuit row group, the orthogonal projections of two adjacent pixel driving circuit rows on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry, and the first axis of symmetry is parallel to the first direction. An electrode layer includes multiple electrode portions, each electrode portion including a main body portion and a connecting portion. The main body portion is at least partially used to form the first electrode of the light-emitting unit, and the connecting portion is connected between the main body portion and the pixel driving circuit. Among them, the plurality of electrode portions include a plurality of first electrode portions, and the plurality of first electrode portions are used to form the first electrode of the same color light-emitting unit respectively; In the same pixel driving circuit row group, the pixel driving circuits in one pixel driving circuit row form the first pixel driving circuit, and the pixel driving circuits in another pixel driving circuit row form... Form the second pixel driving circuit; The difference between the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate and the area of ​​the orthographic projection of the first electrode portion connected to the second pixel driving circuit on the substrate is S1, and the area of ​​the orthographic projection of the first electrode portion connected to the first pixel driving circuit on the substrate is S2, where S1 / S2 is greater than or equal to 0 and less than or equal to 5%.

23. A display panel, wherein, The display panel includes: Substrate; Multiple light-emitting units; Multiple pixel driving circuits are provided to drive the light-emitting unit. The multiple pixel driving circuits are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect. The plurality of pixel driving circuits form a plurality of pixel driving circuit row groups distributed in the second direction, the pixel driving circuit row group includes two adjacent pixel driving circuit rows, and the pixel driving circuit row includes a plurality of pixel driving circuits distributed in the first direction. In the pixel driving circuit row group, the orthogonal projections of two adjacent pixel driving circuit rows on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry, and the first axis of symmetry is parallel to the first direction. An electrode layer includes multiple electrode portions, each electrode portion including a main body portion and a connecting portion. The main body portion is at least partially used to form the first electrode of the light-emitting unit, and the connecting portion is connected between the main body portion and the pixel driving circuit. Among them, the plurality of electrode portions include a plurality of first electrode portions, and the plurality of first electrode portions are used to form the first electrode of the same color light-emitting unit respectively; In the same pixel driving circuit row group, the pixel driving circuit in one pixel driving circuit row forms the first pixel driving circuit, and the pixel driving circuit in another pixel driving circuit row forms the second pixel driving circuit. The capacitance formed by the first electrode portion connected to the first pixel driving circuit and the equipotential portion electrically connected thereto is C1, and the capacitance formed by the first electrode portion connected to the second pixel driving circuit and the equipotential portion electrically connected thereto is C2, and |C1-C2| / C1 is less than or equal to 2%.

24. A display device, wherein, The display device includes the display panel as described in any one of claims 1-23.

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