Display panel and display device

Abstract

Disclosed in the embodiments of the present application are a display panel and a display device. The display panel comprises a substrate and a light-emitting device layer located on one side of the substrate. The light-emitting device layer comprises an anode layer, a first light-emitting unit, a charge generation layer, a second light-emitting unit and a cathode layer that are sequentially stacked. The first light-emitting unit comprises a first electron blocking layer and a first light-emitting layer, and the second light-emitting unit comprises a second electron blocking layer and a second light-emitting layer, wherein the thickness of any subunit in the first electron blocking layer is 0, or the thickness of any subunit in the second electron blocking layer is 0.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202411170528.3, filed on August 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0003] With the development of flat panel display technology, customers' requirements for display stability are gradually increasing. In recent years, organic light-emitting diode (OLED) displays have developed rapidly worldwide, and OLED display technology has become increasingly sophisticated. Currently, the mainstream multilayer OLED devices have complex film layer structures. The light-emitting unit generally includes an electron blocking layer and a light-emitting layer. There are often leakage current problems between different blocking units within the electron blocking layer. Invention Overview

[0004] Embodiments of this application provide a display panel and display device to at least solve the technical problem of leakage current between different blocking units within the electron blocking layer of currently mainstream stacked OLED devices.

[0005] In a first aspect, embodiments of this application provide a display panel, including a substrate and a light-emitting device layer located on one side of the substrate. The light-emitting device layer includes: an anode layer located on one side of the substrate; a first light-emitting unit including a first electron blocking layer and a first light-emitting layer, wherein the first electron blocking layer is located on the side of the anode layer facing away from the substrate and includes a first electron blocking unit, a second electron blocking unit, and a third electron blocking unit; the first light-emitting layer is located on the side of the first electron blocking layer facing away from the anode layer and includes a first light-emitting sub-unit, a second light-emitting sub-unit, and a third light-emitting sub-unit, wherein the first light-emitting sub-unit overlaps with the orthographic projection of the first electron blocking unit on the substrate, the second light-emitting sub-unit overlaps with the orthographic projection of the second electron blocking unit on the substrate, and the third light-emitting sub-unit overlaps with the orthographic projection of the third electron blocking unit on the substrate; wherein the thickness of any one of the first electron blocking unit, the second electron blocking unit, and the third electron blocking unit is 0; a charge-generating layer located on the side of the first light-emitting unit facing away from the anode layer; and a second light-emitting unit located on the side of the charge-generating layer facing away from the first light-emitting unit, wherein the second light-emitting unit includes: a second electron blocking layer. The system comprises a second light-emitting layer, wherein the second electron blocking layer is located on the side of the charge-generating layer opposite to the first light-emitting unit, and includes a fourth electron blocking unit, a fifth electron blocking unit, and a sixth electron blocking unit; the second light-emitting layer is located on the side of the second electron blocking layer opposite to the charge-generating layer, and includes a fourth light-emitting sub-unit, a fifth light-emitting sub-unit, and a sixth light-emitting sub-unit; the fourth light-emitting sub-unit overlaps with the orthographic projection of the fourth electron blocking unit on the substrate; the fifth light-emitting sub-unit overlaps with the orthographic projection of the fifth electron blocking unit on the substrate; and the sixth light-emitting sub-unit overlaps with the orthographic projection of the sixth electron blocking unit on the substrate; and a cathode layer located on the side of the second light-emitting unit opposite to the charge-generating layer; wherein the thickness of any one of the first electron blocking unit, the second electron blocking unit, and the third electron blocking unit is 0; or the thickness of any one of the fourth electron blocking unit, the fifth electron blocking unit, and the sixth electron blocking unit is 0; the light-emitting materials in the first light-emitting layer and the second light-emitting layer include: a host material, a sensitizer, and a fluorescent guest material; the sensitizer includes at least one of a phosphorescent material utilizing triplet excitons and a thermally activated delayed fluorescence material.

[0006] Secondly, embodiments of this application also provide a display device, including a driver chip and a display panel. The display panel includes a substrate and a light-emitting device layer located on one side of the substrate. The light-emitting device layer includes: an anode layer located on one side of the substrate; a first light-emitting unit including a first electron blocking layer and a first light-emitting layer, wherein the first electron blocking layer is located on the side of the anode layer away from the substrate and includes a first electron blocking unit, a second electron blocking unit, and a third electron blocking unit; the first light-emitting layer is located on the side of the first electron blocking layer away from the anode layer and includes a first light-emitting sub-unit, a second light-emitting sub-unit, and a third light-emitting sub-unit, wherein the first light-emitting sub-unit overlaps with the orthographic projection of the first electron blocking unit on the substrate, the second light-emitting sub-unit overlaps with the orthographic projection of the second electron blocking unit on the substrate, and the third light-emitting sub-unit overlaps with the orthographic projection of the third electron blocking unit on the substrate; wherein the thickness of any one of the first electron blocking unit, the second electron blocking unit, and the third electron blocking unit is 0; a charge-generating layer located on the side of the first light-emitting unit away from the anode layer; and a second light-emitting unit located on the side of the charge-generating layer away from the first light-emitting unit. The system includes: a second electron blocking layer and a second light-emitting layer. The second electron blocking layer is located on the side of the charge generating layer opposite to the first light-emitting unit and includes a fourth electron blocking unit, a fifth electron blocking unit, and a sixth electron blocking unit. The second light-emitting layer is located on the side of the second electron blocking layer opposite to the charge generating layer and includes a fourth light-emitting sub-unit, a fifth light-emitting sub-unit, and a sixth light-emitting sub-unit. The fourth light-emitting sub-unit overlaps with the orthographic projection of the fourth electron blocking unit on the substrate, the fifth light-emitting sub-unit overlaps with the orthographic projection of the fifth electron blocking unit on the substrate, and the sixth light-emitting sub-unit overlaps with the orthographic projection of the first electron blocking unit on the substrate. The six electron blocking units overlap in orthographic projection on the substrate; and a cathode layer is located on the side of the second light-emitting unit opposite to the charge generation layer; wherein the thickness of any one of the first electron blocking unit, the second electron blocking unit, and the third electron blocking unit is 0; or the thickness of any one of the fourth electron blocking unit, the fifth electron blocking unit, and the sixth electron blocking unit is 0; the light-emitting materials in the first light-emitting layer and the second light-emitting layer include: a host material, a sensitizer, and a fluorescent guest material, wherein the sensitizer includes at least one of a phosphorescent material utilizing triplet excitons and a thermally activated delayed fluorescence material. Attached Figure Description

[0007] Figure 1 is a schematic diagram of the structure of a display panel provided in an optional embodiment of this application;

[0008] Figure 2 is a schematic diagram of the structure of another display panel provided in an optional embodiment of this application;

[0009] Figure 3 is a schematic diagram of the structure of another display panel provided in an optional embodiment of this application;

[0010] Figure 4 is a schematic diagram of a leakage current path provided in an optional embodiment of this application;

[0011] Figure 5 is a schematic diagram of another leakage current path provided in an optional embodiment of this application;

[0012] Figure 6 is a schematic diagram of another leakage current path provided in an optional embodiment of this application;

[0013] Figure 7 is a schematic diagram of the structure of a display device provided in an optional embodiment of this application.

[0014] Explanation of reference numerals in the attached figures:

[0015] 10. Substrate;

[0016] 20, Light-emitting device layer; 21, Anode layer; 22, First light-emitting unit; 221, First electron blocking layer; 2211, First electron blocking unit; 2212, Second electron blocking unit; 2213, Third electron blocking unit; 222, First light-emitting layer; 2221, First light-emitting sub-unit; 2222, Second light-emitting sub-unit; 2223, Third light-emitting sub-unit; 223, Hole injection layer; 224, First hole transport layer; 225, First hole blocking layer; 226, First electron transport layer; 23, Charge generation layer; 24, Second light-emitting unit; 241, Second electron blocking layer; 2411, Fourth electron blocking unit; 2412, Fifth electron blocking unit; 2413, Sixth electron blocking unit; 242, Second light-emitting layer; 2421, Fourth light-emitting sub-unit; 2422, Fifth light-emitting sub-unit; 2423, Sixth light-emitting sub-unit; 25, Cathode layer;

[0017] 30, Display device; 31, Driver chip; 32, Display panel. Embodiments of the present invention

[0018] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0019] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.

[0020] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0021] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0022] Referring to FIG1, an embodiment of this application provides a display panel 32, including a substrate 10 and a light-emitting device layer 20 located on one side of the substrate. The light-emitting device layer 20 includes an anode layer 21, a first light-emitting unit 22, a charge-generating layer 23, a second light-emitting unit 24 and a cathode layer 25 stacked sequentially.

[0023] It's important to note that there are two main types of light emission in OLED displays: top-emission and bottom-emission. In top-emission OLEDs, the light-emitting layer is located above the electrodes, and light is emitted from top to bottom. This design reduces light reflection and scattering within the device, thus improving screen brightness and contrast. Top-emission OLEDs are typically used in applications requiring high brightness and contrast, such as outdoor displays or devices with high brightness requirements. In bottom-emission OLEDs, the light-emitting layer is located below the electrodes, and light is emitted from bottom to top. This design makes the light easier for the user's eye to capture, providing a more comfortable viewing experience. Bottom-emission OLEDs are widely used in mobile phones, televisions, and other portable devices, generally those with lower brightness requirements. Bottom-emission OLEDs prioritize color accuracy and display consistency over pure brightness in their design.

[0024] According to an optional embodiment of this application, taking a top-emitting structure as an example, as shown in FIG2, the light-emitting device layer 20 includes:

[0025] Anode layer 21 is located on one side of substrate 10;

[0026] The first light-emitting unit 22 includes a first electron blocking layer 221 and a first light-emitting layer 222. The first electron blocking layer 221 is located on the side of the anode layer 21 away from the substrate 10, and includes a first electron blocking unit 2211 (which can be abbreviated as FLB1), a second electron blocking unit 2212 (which can be abbreviated as FLG1), and a third electron blocking unit 2213. The ratio R1 of the thickness of the third electron blocking unit 2213 to the thickness of the first electron blocking unit 2211 satisfies: 0 < R1 < 4. The first light-emitting layer 222 is located on the side of the first electron blocking layer 2211 away from the anode layer 21, and includes a first light-emitting sub-unit 2221 (which can be abbreviated as B EML), a second light-emitting sub-unit 2222 (which can be abbreviated as G EML), and a third light-emitting sub-unit 2223 (which can be abbreviated as R EML). EML), the orthographic projections of the first light-emitting subunit 2221 and the first electron blocking unit 2211 on the substrate 10 overlap, the orthographic projections of the second light-emitting subunit 2222 and the second electron blocking unit 2212 on the substrate 10 overlap, and the orthographic projections of the third light-emitting subunit 2223 and the third electron blocking unit 2213 on the substrate 10 overlap.

[0027] The charge generation layer 23 is located on the side of the first light-emitting unit 22 away from the anode layer 21;

[0028] The second light-emitting unit 24 is located on the side of the charge generation layer opposite to the first light-emitting unit 22; and

[0029] The cathode layer 25 is located on the side of the second light-emitting unit 24 away from the charge generation layer 23.

[0030] It should be noted that the light-emitting units in the light-emitting layer can emit monochromatic light, trichromatic light, or quadrichromatic light, and this application does not limit this. The accompanying drawings of this application illustrate the application by showing the first light-emitting subunit corresponding to blue light, the second light-emitting subunit corresponding to green light, and the third light-emitting subunit corresponding to red light.

[0031] It should be noted that in existing vapor deposition processes, FLR1 uses a Fine Metal Mask (FMM), and REML also uses an FMM. Currently, the mainstream vapor deposition machine is a three-source vapor deposition machine, containing three materials. When vapor deposition of one material, a baffle is needed to close the gate for the other two materials to prevent them from being deposited onto the panel. Even when the gate is closed, the vapor deposition process does not stop, and the deposited material accumulates on the baffle. If the FLR1 thickness is too large (meaning the FLR1 material deposition rate is high), when FLR1 is not being deposited on the panel, the baffle needs to be used to block it, resulting in excessive FLR1 material accumulating on the baffle. When this accumulation reaches a certain level, the baffle will fail. Therefore, in terms of process, excessively thick FLR1 cannot be placed in the same vapor deposition chamber as REML.

[0032] When FLR1 is designed to be thinner (which can be understood as the rate of FLR1 material evaporation is smaller), when FLR1 is not evaporated on the panel, a baffle is needed to block it. Compared with the thicker FLR1, the failure time of the baffle is much longer, enough to extend to the next mass production. Therefore, in terms of process, FLR1 and REML can be placed in the same evaporation chamber and share a single FMM.

[0033] The display panel provided in this application embodiment includes a substrate and a light-emitting device layer located on one side of the substrate. The light-emitting device layer includes an anode layer, a first light-emitting unit, a charge-generating layer, a second light-emitting unit, and a cathode layer stacked sequentially. The first light-emitting unit includes a first electron blocking layer and a first light-emitting layer. The first electron blocking layer is located on the side of the anode layer away from the substrate and includes a first electron blocking unit, a second electron blocking unit, and a third electron blocking unit. The ratio R1 of the thickness of the third electron blocking unit to the thickness of the first electron blocking unit satisfies: 0 < R1 < 4. The first light-emitting layer is located on the side of the first electron blocking layer away from the anode layer and includes a first light-emitting sub-unit, a second light-emitting sub-unit, and a third light-emitting sub-unit. The orthographic projections of the first light-emitting sub-unit and the first electron blocking unit on the substrate overlap. The orthographic projections of the second light-emitting sub-unit and the second electron blocking unit on the substrate overlap. The orthographic projections of the third light-emitting sub-unit and the third electron blocking unit on the substrate overlap. In existing technologies, the ratio R1 of the thickness of the third electron blocking unit to the thickness of the first electron blocking unit is generally set to be greater than or equal to 4. This results in a relatively large thickness of the third electron blocking unit, making it impossible for it to share a fine metal mask for vapor deposition with the corresponding third light-emitting unit. In this application, the thickness of the third electron blocking unit is reduced to be close to that of the first electron blocking unit, thereby enabling the third electron blocking unit and the third light-emitting unit to share a fine metal mask for vapor deposition. This solves, to some extent, the technical problem of high manufacturing costs caused by the complex structure of current mainstream stacked OLED devices, effectively reducing production costs and simplifying the production process.

[0034] In related technologies, because the optimal microcavity position of the first light-emitting unit varies, the thicknesses of the first electron blocking unit 2211, the second electron blocking unit 2212, and the third electron blocking unit 2213 need to be adjusted to achieve the optimal microcavity position of the first light-emitting unit. Since the wavelength of red light (~610nm) is longer than that of green light (~530nm) and blue light (~450nm), the red pixel requires the longest cavity length; that is, the thickness of FLR1 is greater than the thicknesses of FLG1 and FLB1.

[0035] In this embodiment of the application, the thickness of FLB1 is taken as the benchmark. It can be understood that the thickness of FLB1 is the thinnest electron blocking layer film thickness that can be monitored on the mass production line in the current process, which can be combined with the actual application effect and process level.

[0036] Referring to the table below, in an optional embodiment, the ratio R1 of FLR1 and FLB1 can be set between 0 and 4. Experiments have shown that when the thickness of FLR1 is within this range, the voltage, efficiency, and lifespan of the R device can achieve optimal results, as shown in Table 1 below. FLR1 and R EML can be placed in the same vapor deposition chamber and share a single FMM.

[0037] Table 1

[0038] R1 multiples of R, device voltage, device efficiency, and device lifetime. (Ref (4~5 times)) 100% 100% 100% 0~0.7 100% 99% 113% 0.8~1.5 100% 102% 110% 1.6~2.3 100% 101% 108% 2.4~3.1 100% 100% 105% 3.2~3.9 100% 100% 103%

[0039] To achieve better vapor deposition results, R1 can be set between 0.8 and 1.5. In an optional embodiment, the ratio R3 of the thickness of the second electron blocking unit 2212 to the thickness of the first electron blocking unit 2211 satisfies: 2 ≤ R3 ≤ 4. The thickness of the third electron blocking unit 2213 is equal to the thickness of the first electron blocking unit 2211.

[0040] The ideal state is that the thickness of FLR1 is equal to the thickness of FLB1, that is, both FLR1 and FLB1 are made as thin as possible, or the thickness of FLR1 and FLB1 are infinitely close, which is also included in the scope of the embodiments described in this application.

[0041] Referring to FIG3, in an optional embodiment, the first light-emitting unit 22 further includes: a hole injection layer 223 (HIL) located on the side of the anode layer 21 away from the substrate 10; a first hole transport layer 224 (HTL1) located between the hole injection layer 223 and the first electron blocking layer 221; a first hole blocking layer 225 (EICL1) located on the side of the first light-emitting layer 222 away from the first electron blocking layer 221; and a first electron transport layer 226 (ETL1) located between the first hole blocking layer 225 and the charge generation layer 23.

[0042] Referring to FIG2, in an optional embodiment, the second light-emitting unit 24 includes: a second electron blocking layer 241 located on the side of the charge generating layer 23 away from the first light-emitting unit 22, and including a fourth electron blocking unit 2411 (which can be simply referred to as FLB2), a fifth electron blocking unit 2412 (which can be simply referred to as FLG2), and a sixth electron blocking unit 2413 (which can be simply referred to as FLR2), wherein the ratio R2 of the thickness of the sixth electron blocking unit 2413 to the thickness of the fourth electron blocking unit 2411 satisfies: 15≤R2≤17; and a second light-emitting layer 242 located on the side of the second electron blocking layer 241 away from the charge generating layer 23, and including a fourth light-emitting sub-unit 2421 (which can be simply referred to as B EML), a fifth light-emitting sub-unit 2422 (which can be simply referred to as G EML), and a sixth light-emitting sub-unit 2423 (which can be simply referred to as R EML). (EML), the orthographic projections of the fourth light-emitting subunit 2421 and the fourth electron blocking unit 2411 on the substrate 10 overlap, the orthographic projections of the fifth light-emitting subunit 2422 and the fifth electron blocking unit 2412 on the substrate 10 overlap, and the orthographic projections of the sixth light-emitting subunit 2423 and the sixth electron blocking unit 2413 on the substrate 10 overlap.

[0043] It should be noted that the light-emitting units in the light-emitting layer can emit monochromatic light, trichromatic light, or quadrichromatic light, and this application does not limit this. The accompanying drawings of this application illustrate the application by showing the fourth light-emitting subunit corresponding to blue light, the fifth light-emitting subunit corresponding to green light, and the sixth light-emitting subunit corresponding to red light.

[0044] To compensate for the reduced thickness of FLR1 in the above embodiments, in an optional embodiment, the thickness of FLR2 can be increased. For example, if the thickness of FLR2 before the improvement is 10 to 12 times that of FLB2, the thickness of FLR2 after the improvement can be set to 15 to 17 times that of FLB2.

[0045] In the embodiments of this application, the thickness of FLB1 and the thickness of FLB2 can be set to be equal or infinitely similar, or a certain proportional relationship can be set according to actual needs. This application does not limit this.

[0046] Referring to FIG3, in an optional embodiment, the second light-emitting unit 24 further includes: a second hole transport layer 243 (HTL2) located between the charge generation layer 23 and the second electron blocking layer 241; a second hole blocking layer 244 (EICL2) located on the side of the second light-emitting layer 242 opposite to the second electron blocking layer 241; a second electron transport layer 245 (ETL2) located on the side of the second hole blocking layer 244 opposite to the second light-emitting layer 242; and an electron injection layer 246 (EIL) located between the second electron transport layer 245 and the cathode layer 25.

[0047] Referring again to FIG3, in an optional embodiment, the charge generation layer 23 includes:

[0048] An N-type semiconductor layer (N-CGL) 231 is in contact with the first light-emitting unit 22 and is configured to provide electrons to the first light-emitting unit 22;

[0049] The P-type semiconductor layer (P-CGL) 232 is in contact with the second light-emitting unit 24 and is configured to provide holes to the second light-emitting unit 24.

[0050] It's important to note that the Charge Generation Layer (CGL) is a unique structure distinct from single-layer devices. This structure consists of two layers: NCGL (N-type semiconductor) and PCGL (P-type semiconductor). It possesses charge generation capabilities, providing holes and electrons for multilayer light-emitting devices. NCGL (N-type semiconductor) is made by doping organic electron transport materials with metals (typically Yb, Li, Cs, Mg, etc.). The organic electron transport material in NCGL requires an electron mobility μe ≥ 10⁻³ cm² / Vs. PCGL (P-type semiconductor) is typically composed of metal oxides (such as ITO, WO₃, MoO₃, V₂O₅, etc.) or hole transport materials doped with Lewis acids (such as FeCl₃:NPB, F₄-TCNQ:NPB). The organic hole transport material requires a hole mobility μh ≥ 10⁻² cm² / Vs.

[0051] Referring to Figure 4, the OLED film structure provided in this application embodiment has multiple leakage paths. This application uses the main leakage path L1 and the secondary leakage path L2 as examples in the embodiments. Through lateral leakage experiments, it is verified that the main leakage path L1 is implemented through the CGL film layer. For example, when only pixel G is lit, pixel R will also be lit. This phenomenon is more obvious at low brightness because a portion of the charge that lights pixel G flows to pixel R through the CGL film layer, causing the R pixel circuit to conduct and thus lighting up pixel R. Most of the charge flows from the CGL film layer to adjacent pixels, while a small portion flows to adjacent pixels through the FLG2-FLR2 path. Similarly, leakage current also exists between FLG1-FLR1, FLG1-FLB1, and FLG2-FLB2.

[0052] To address the aforementioned leakage current issue, in one optional embodiment, the thickness of any one of the first electron blocking unit FLB1, the second electron blocking unit FLG1, and the third electron blocking unit FLR1 can be set to 0; or the thickness of any one of the fourth electron blocking unit FLB2, the fifth electron blocking unit FLG2, and the sixth electron blocking unit FLR2 can be set to 0. This is equivalent to deleting any electron blocking unit. Deleting an electron blocking unit in one layer corresponds to compensating for the thickness of the electron blocking unit in another layer. For example, deleting FLR1 will compensate for the thickness in FLR2, and deleting FLR2 will compensate for the thickness in FLR1.

[0053] The beneficial effects provided by the embodiments of this application include at least the following:

[0054] This application provides a display panel including a substrate and a light-emitting device layer located on one side of the substrate. The light-emitting device layer includes an anode layer, a first light-emitting unit, a charge-generating layer, a second light-emitting unit, and a cathode layer stacked sequentially. The first light-emitting unit includes a first electron blocking layer and a first light-emitting layer. The first electron blocking layer is located on the side of the anode layer facing away from the substrate and includes a first electron blocking unit, a second electron blocking unit, and a third electron blocking unit. The first light-emitting layer is located on the side of the first electron blocking layer facing away from the anode layer. The second light-emitting unit includes a second electron blocking layer and a second light-emitting layer. Either the thickness of any sub-unit in the first electron blocking layer or the thickness of any sub-unit in the second electron blocking layer is 0. By removing any sub-unit in the electron blocking layer, leakage current between adjacent sub-units can be effectively reduced.

[0055] In one example of this application, the thickness of the second electron blocking unit FLG1 or the thickness of the fifth electron blocking unit FLG2 can be set to 0. In this case, the ratio R1 of the thickness of the third electron blocking unit FLR1 to the thickness of the first electron blocking unit FLB1 satisfies: 0 < R1 < 4; the ratio R2 of the thickness of the sixth electron blocking unit FLR2 to the thickness of the fourth electron blocking unit FLB1 satisfies: 15 ≤ R2 ≤ 17. This allows FLR1 and REML to be placed in the same vapor deposition chamber and share a single FMM. The specific data has been described in the foregoing embodiments and will not be repeated here.

[0056] In this embodiment, the thickness of FLG2 is set to 0 for illustrative purposes. Referring to FIG5, the thickness of FLG2 can be set to 0, and the ratio R3 of the thickness of FLG1 to the thickness of FLB1 satisfies: 5≤R3≤6. This can be understood as removing the fifth electron blocking unit in the second light-emitting unit 24 and compensating its thickness to the second electron blocking unit in the first light-emitting unit 22. In this way, the FLG2-FLR2 path is directly disconnected, thereby effectively improving the problem of lateral leakage current between film layers in the OLED device and improving the light extraction efficiency.

[0057] In an optional embodiment of this application, the film thicknesses of FLR1 and FLR2 may not be adjusted, that is, the ratio of the film thickness of FLR1 to the film thickness of FLB1 remains greater than or equal to 4. Only FLG2 is removed and the thickness of FLG1 is compensated. Other film structures are as described in the above embodiment.

[0058] It should be noted that in OLED devices, to fully utilize the device's light emission, optical microcavities are used for interference enhancement. Only when the emissive layer is in a specific position will the light directly incident on the emission window from the emissive layer interfere with the light reflected from the bottom layer of the microcavity to the window, thus enhancing the light emission. This position of the emissive layer is the optimal light emission position. In a single-layer device, the optimal light emission position is the position of interference enhancement at 1 / 4 wavelength of the target color in the emissive layer (EML). The stacked device involved in this application has two emissive layers, meaning there are two optimal light emission positions: one emissive layer (the second emissive unit) has the optimal light emission position at 1 / 4 wavelength of the target color, and the other emissive layer (the first emissive unit) has the optimal light emission position at 3 / 4 wavelength of the target color.

[0059] If a certain light-emitting sub-unit is removed and the thickness is compensated in another layer, the optimal light-emitting position is deviated. In order to ensure the full and effective transfer of energy in the light-emitting region and improve the luminous efficiency of the device, the energy levels of the light-emitting host material and the doped guest material need to be matched.

[0060] For example, when FLG2 is removed and its thickness is compensated to that of FLG1, the first emitting unit is no longer at the 3 / 4 wavelength position, i.e., it deviates from the optimal emitting position. To ensure sufficient and effective energy transfer in the emitting region and improve the device's luminous efficiency, the energy levels of the G emitting host material and the doped guest material need to be matched.

[0061] In an optional embodiment, both the first and second light-emitting layers contain a host material and a guest material as a dopant. The S1 energy level of the host material of the second and fifth light-emitting subunits is greater than that of the guest material, and the T1 energy level of the host material of the second and fifth light-emitting subunits is greater than that of the guest material. The host material includes phosphorescently doped electron-type host material and phosphorescently doped hole-type host material. The guest material includes a first dopant (e.g., PGD) and a second dopant (e.g., FGD).

[0062] In one optional embodiment, the FLB of the first and second light-emitting units is an aromatic amine compound, belonging to hole transport materials, with a HOMO level 0-0.5 eV deeper than the HTL layer, a wide bandgap, and serving as an auxiliary hole transport material, with a film thickness requirement of 0 Å-200 Å for both. The FLG of the second light-emitting unit is an aromatic amine compound, serving as a hole transport material, with a HOMO level 0-0.5 eV deeper than the HTL layer, a wide bandgap, and serving as an auxiliary hole transport material, with a film thickness requirement of 4-5 times that of the FLB. The FLR of the second light-emitting unit is an aromatic amine compound, serving as a hole transport material, with a HOMO level 0-0.5 eV deeper than the HTL layer, a wide bandgap, and serving as an auxiliary hole transport material, with a film thickness requirement of 10-15 times that of the FLB. The HOMO level of the FLB is 0-0.1 eV deeper than the FLG, and the LUMO level is 0-0.1 eV shallower than the FLG. The HOMO level of the FLB is 0-0.2 eV deeper than the FLR, and the LUMO level is 0-0.2 eV shallower than the FLR. The HUMO level of FLB is 0~0.1 eV higher than that of HTL. The HUMO level of FLB is 0.1~0.2 eV lower than that of G EML. The HUMO level of FLB is 0~0.2 eV lower than that of R EML.

[0063] In an optional embodiment, the luminescent materials in the first luminescent layer and the second luminescent layer include: a host material, a sensitizer, and a fluorescent guest material. The sensitizer includes at least one of a phosphorescent material utilizing triplet excitons and a thermally activated delayed fluorescence material. The S1 energy level of the host material is greater than that of the fluorescent guest material, and the T1 energy level of the host material is greater than that of the fluorescent guest material.

[0064] The sensitizer is uniformly distributed in the luminescent layer 105. The host material acts as a dispersant, separating the sensitizer from the fluorescent guest material. Furthermore, the carrier transport performance can be balanced by adjusting the types of the host material and the sensitizer. Of course, both the host material and the sensitizer can be electron transport materials or hole transport materials, or they can be different charge transport materials. For example, the host material can be an electron transport material and the sensitizer a hole transport material, or vice versa.

[0065] In some embodiments, the body material includes one or both of N-type body material and P-type body material.

[0066] In some embodiments, the main body material is selected from N-type main body materials, including but not limited to the following structures:

[0067] .

[0068] In some embodiments, the main body material is selected as a P-type main body material, including but not limited to the following structures:

[0069] .

[0070] In some embodiments, the main body material is a combination of the above-mentioned N-type main body material and P-type main body material.

[0071] In the above technical solution, the sensitizer includes at least one of phosphorescent materials utilizing triplet excitons and thermally activated delayed fluorescence materials.

[0072] In some embodiments, the sensitizer includes, but is not limited to, the following structures:

[0073] .

[0074] In the above technical solution, the emission spectrum peak of the fluorescent guest material is located in the range of 400-700 nm, and the full width at half maximum (FWHM) of the spectrum is less than 60 nm.

[0075] In some embodiments, the fluorescent guest material includes, but is not limited to, the following structures:

[0076] .

[0077] Referring to FIG6, in an optional embodiment of this application, the thickness of FLG1 can be set to be equal to or infinitely close to that of FLB1 to reduce one FMM, simplify the production process, and reduce production costs.

[0078] When FLG1 is designed to be thinner (which can be understood as the rate of FLG1 material vapor deposition is smaller), when FLG1 is not vapor deposited on the panel, a baffle is needed to block it. Compared with the thicker FLG1, the failure time of the baffle is much longer, enough to extend to the next mass production. Therefore, in terms of process, FLG1 and G EML can be placed in the same vapor deposition chamber and share a single FMM.

[0079] In an optional embodiment of this application, leakage current can also be reduced by removing FLR2 and compensating its thickness to that of FLR1; or by removing FLR1 and compensating its thickness to that of FLR2. To improve light extraction efficiency, the red luminescent material can be sensitized using the aforementioned sensitizing materials.

[0080] In an optional embodiment of this application, leakage current can also be reduced by removing FLB2 and compensating its thickness to that of FLB1; or by removing FLB1 and compensating its thickness to that of FLB2. To improve light extraction efficiency, the blue luminescent material can be sensitized using the aforementioned sensitizing materials.

[0081] On the other hand, referring to FIG7, an embodiment of this application also provides a display device 30, including a driver chip 31 and a display panel 32 as described in any of the above embodiments. The main function of the driver chip is to control the OLED display panel, drive the display panel through electrical signals, and transmit video data.

[0082] The principle behind OLED display devices emitting light is briefly described below:

[0083] 1. Current injection: When the OLED device is powered on, the anode (usually a metal electrode) injects holes into the hole injection layer, and the cathode (usually a low work function metal or a transparent conductive layer) injects electrons into the electron injection layer.

[0084] 2. Hole and electron transport: Holes are transported from the anode to the light-emitting layer through the hole injection layer and the hole transport layer, while electrons are transported from the cathode to the light-emitting layer through the electron injection layer and the electron transport layer.

[0085] 3. Recombination luminescence: In the luminescent layer, holes and electrons meet and recombine. This recombination process usually occurs in the excited state of the luminescent molecule. When an electron transitions from a higher energy level to a lower energy level, it releases energy, which is emitted in the form of light.

[0086] The organic materials used in the light-emitting layer can be small molecules, polymers, or quantum dots. These materials are carefully designed to possess specific luminescent properties, such as color, brightness, and efficiency. The selection and arrangement of the luminescent materials have a significant impact on the luminescent performance of OLEDs.

[0087] In some OLED designs, energy transfer mechanisms may be used to improve luminous efficiency. For example, a combination of fluorescent and phosphorescent materials may be used, in which the fluorescent material absorbs excited-state energy and transfers it to the phosphorescent material, which then emits light through a phosphorescence process.

[0088] The material of the light-emitting layer can be designed to emit light of specific wavelengths, thereby producing different colors. By adjusting the chemical structure of the material or using different dopants, the emitted color of an OLED can be changed.

[0089] To protect OLED devices from environmental factors such as oxygen and moisture, they are typically encapsulated. The encapsulation materials and methods also affect the lifespan and performance of the OLED.

[0090] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0091] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0092] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0093] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, comprising a substrate and a light-emitting device layer located on one side of the substrate, the light-emitting device layer comprising: An anode layer is located on one side of the substrate; A first light-emitting unit includes a first electron blocking layer and a first light-emitting layer. The first electron blocking layer is located on the side of the anode layer away from the substrate and includes a first electron blocking unit, a second electron blocking unit, and a third electron blocking unit. The first light-emitting layer is located on the side of the first electron blocking layer away from the anode layer and includes a first light-emitting sub-unit, a second light-emitting sub-unit, and a third light-emitting sub-unit. The first light-emitting sub-unit overlaps with the orthographic projection of the first electron blocking unit on the substrate, the second light-emitting sub-unit overlaps with the orthographic projection of the second electron blocking unit on the substrate, and the third light-emitting sub-unit overlaps with the orthographic projection of the third electron blocking unit on the substrate. A charge generation layer is located on the side of the first light-emitting unit away from the anode layer; A second light-emitting unit is located on the side of the charge-generating layer opposite to the first light-emitting unit. The second light-emitting unit includes a second electron-blocking layer and a second light-emitting layer. The second electron-blocking layer is located on the side of the charge-generating layer opposite to the first light-emitting unit and includes a fourth electron-blocking unit, a fifth electron-blocking unit, and a sixth electron-blocking unit. The second light-emitting layer is located on the side of the second electron-blocking layer opposite to the charge-generating layer and includes a fourth light-emitting sub-unit, a fifth light-emitting sub-unit, and a sixth light-emitting sub-unit. The fourth light-emitting sub-unit overlaps with the orthographic projection of the fourth electron-blocking unit on the substrate; the fifth light-emitting sub-unit overlaps with the orthographic projection of the fifth electron-blocking unit on the substrate; and the sixth light-emitting sub-unit overlaps with the orthographic projection of the sixth electron-blocking unit on the substrate. The cathode layer is located on the side of the second light-emitting unit away from the charge generation layer; Wherein, the thickness of any one of the first electron blocking unit, the second electron blocking unit, and the third electron blocking unit is 0; or the thickness of any one of the fourth electron blocking unit, the fifth electron blocking unit, and the sixth electron blocking unit is 0. The luminescent materials in the first luminescent layer and the second luminescent layer include: a host material, a sensitizer, and a fluorescent guest material, wherein the sensitizer includes at least one of phosphorescent materials utilizing triplet excitons and thermally activated delayed fluorescence materials.

2. The display panel according to claim 1, wherein, The main material includes one or both of N-type and P-type main materials.

3. The display panel according to claim 1, wherein, Both the host material and the sensitizer are either electron transport materials or hole transport materials.

4. The display panel according to claim 1, wherein, The main material is an electron transport material, and the sensitizer is a hole transport material; or The main material is a hole-transporting material, and the sensitizer is an electron-transporting material.

5. The display panel according to claim 1, wherein, The S1 energy level of the host material is greater than that of the fluorescent guest material, and the T1 energy level of the host material is greater than that of the fluorescent guest material.

6. The display panel according to claim 1, wherein, When the thickness of the second electron blocking unit is 0 or the thickness of the fifth electron blocking unit is 0, the ratio R1 of the thickness of the third electron blocking unit to the thickness of the first electron blocking unit satisfies: 0 < R1 < 4; the ratio R2 of the thickness of the sixth electron blocking unit to the thickness of the fourth electron blocking unit satisfies: 15 ≤ R2 ≤ 17.

7. The display panel according to claim 1, wherein, The thickness of the fifth electron blocking layer is 0, and the ratio R3 of the thickness of the second electron blocking unit to the thickness of the first electron blocking unit satisfies: 5≤R3≤6.

8. The display panel according to claim 1, wherein, The first light-emitting unit further includes: A hole injection layer is located on the side of the anode layer opposite to the substrate; The first hole transport layer is located between the hole injection layer and the first electron blocking layer; A first hole-blocking layer is located on the side of the first light-emitting layer opposite to the first electron-blocking layer; and The first electron transport layer is located between the first hole blocking layer and the charge generation layer.

9. The display panel according to claim 1, wherein, The second light-emitting unit further includes: The second hole transport layer is located between the charge generation layer and the second electron blocking layer; The second hole blocking layer is located on the side of the second light-emitting layer that is away from the second electron blocking layer; A second electron transport layer is located on the side of the second hole blocking layer opposite to the second light-emitting layer; and An electron injection layer is located between the second electron transport layer and the cathode layer.

10. The display panel according to claim 1, wherein, The charge generation layer includes: An N-type semiconductor layer is in contact with the first light-emitting unit and is configured to provide electrons to the first light-emitting unit; A P-type semiconductor layer is in contact with the second light-emitting unit and is configured to provide holes to the second light-emitting unit.

11. A display device, characterized in that, Includes a driver chip and a display panel, wherein the display panel includes: A substrate and a light-emitting device layer located on one side of the substrate, the light-emitting device layer comprising: An anode layer is located on one side of the substrate; A first light-emitting unit includes a first electron blocking layer and a first light-emitting layer. The first electron blocking layer is located on the side of the anode layer away from the substrate and includes a first electron blocking unit, a second electron blocking unit, and a third electron blocking unit. The first light-emitting layer is located on the side of the first electron blocking layer away from the anode layer and includes a first light-emitting sub-unit, a second light-emitting sub-unit, and a third light-emitting sub-unit. The first light-emitting sub-unit overlaps with the orthographic projection of the first electron blocking unit on the substrate, the second light-emitting sub-unit overlaps with the orthographic projection of the second electron blocking unit on the substrate, and the third light-emitting sub-unit overlaps with the orthographic projection of the third electron blocking unit on the substrate. A charge generation layer is located on the side of the first light-emitting unit away from the anode layer; A second light-emitting unit is located on the side of the charge-generating layer opposite to the first light-emitting unit. The second light-emitting unit includes a second electron-blocking layer and a second light-emitting layer. The second electron-blocking layer is located on the side of the charge-generating layer opposite to the first light-emitting unit and includes a fourth electron-blocking unit, a fifth electron-blocking unit, and a sixth electron-blocking unit. The second light-emitting layer is located on the side of the second electron-blocking layer opposite to the charge-generating layer and includes a fourth light-emitting sub-unit, a fifth light-emitting sub-unit, and a sixth light-emitting sub-unit. The fourth light-emitting sub-unit overlaps with the orthographic projection of the fourth electron-blocking unit on the substrate; the fifth light-emitting sub-unit overlaps with the orthographic projection of the fifth electron-blocking unit on the substrate; and the sixth light-emitting sub-unit overlaps with the orthographic projection of the sixth electron-blocking unit on the substrate. The cathode layer is located on the side of the second light-emitting unit away from the charge generation layer; Wherein, the thickness of any one of the first electron blocking unit, the second electron blocking unit, and the third electron blocking unit is 0; or the thickness of any one of the fourth electron blocking unit, the fifth electron blocking unit, and the sixth electron blocking unit is 0. The luminescent materials in the first luminescent layer and the second luminescent layer include: a host material, a sensitizer, and a fluorescent guest material, wherein the sensitizer includes at least one of phosphorescent materials utilizing triplet excitons and thermally activated delayed fluorescence materials.

12. The display device according to claim 11, wherein, The main material includes one or both of N-type and P-type main materials.

13. The display device according to claim 11, wherein, Both the host material and the sensitizer are either electron transport materials or hole transport materials.

14. The display device according to claim 11, wherein, The main material is an electron transport material, and the sensitizer is a hole transport material; or The main material is a hole-transporting material, and the sensitizer is an electron-transporting material.

15. The display device according to claim 11, wherein, The S1 energy level of the host material is greater than that of the fluorescent guest material, and the T1 energy level of the host material is greater than that of the fluorescent guest material.

16. The display device according to claim 11, wherein, When the thickness of the second electron blocking unit is 0 or the thickness of the fifth electron blocking unit is 0, the ratio R1 of the thickness of the third electron blocking unit to the thickness of the first electron blocking unit satisfies: 0 < R1 < 4; the ratio R2 of the thickness of the sixth electron blocking unit to the thickness of the fourth electron blocking unit satisfies: 15 ≤ R2 ≤ 17.

17. The display device according to claim 11, wherein, The thickness of the fifth electron blocking layer is 0, and the ratio R3 of the thickness of the second electron blocking unit to the thickness of the first electron blocking unit satisfies: 5≤R3≤6.

18. The display device according to claim 11, wherein, The first light-emitting unit further includes: A hole injection layer is located on the side of the anode layer opposite to the substrate; The first hole transport layer is located between the hole injection layer and the first electron blocking layer; A first hole-blocking layer is located on the side of the first light-emitting layer opposite to the first electron-blocking layer; and The first electron transport layer is located between the first hole blocking layer and the charge generation layer.

19. The display panel according to claim 11, wherein, The second light-emitting unit further includes: The second hole transport layer is located between the charge generation layer and the second electron blocking layer; The second hole blocking layer is located on the side of the second light-emitting layer that is away from the second electron blocking layer; A second electron transport layer is located on the side of the second hole blocking layer opposite to the second light-emitting layer; and An electron injection layer is located between the second electron transport layer and the cathode layer.

20. The display device according to claim 11, wherein, The charge generation layer includes: An N-type semiconductor layer is in contact with the first light-emitting unit and is configured to provide electrons to the first light-emitting unit; A P-type semiconductor layer is in contact with the second light-emitting unit and is configured to provide holes to the second light-emitting unit.

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