Display panel and display device

Abstract

The present application provides a display panel and a display device. A light-shielding layer of the display panel comprises a first light-shielding portion, a second light-shielding portion and a third light-shielding portion, wherein the first light-shielding portion can perform light shielding on a first active portion of a driving transistor, the second light-shielding portion can perform light shielding on a third active portion of a compensation transistor, and the third light-shielding portion can perform light shielding on a fourth active portion of a first initialization transistor, thereby improving the photosensitivity and electrical properties of the compensation transistor and the first initialization transistor.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display devices, the requirements for power consumption and screen-to-body ratio are becoming increasingly stringent. To reduce power consumption and increase screen-to-body ratio, existing display devices employ Low Temperature Polysilicon Oxide (LTPO) technology. LTPO technology utilizes both low-temperature polysilicon thin-film transistors (LTSi) and oxide thin-film transistors (OTFTs), allowing the driving circuit to combine the advantages of both technologies, thereby reducing power consumption and leakage current. However, existing display devices using LTPO technology have a large number of film layers, requiring a correspondingly large number of photomasks, resulting in a more complex manufacturing process and higher costs. To reduce the number of photomasks, existing display devices remove some gate layers and insulating layers, but this leads to the absence of the bottom gate of the OTFT, degrading the photosensitivity and electrical properties of the OTFT.

[0003] Therefore, existing display devices using LTPO technology suffer from technical problems such as deteriorated photosensitivity and electrical properties due to the lack of a bottom gate in oxide thin-film transistors. Invention Overview

[0004] This application provides a display panel and a display device to alleviate the technical problem of degraded photosensitivity and electrical properties caused by the lack of bottom gate of oxide thin film transistors in existing display devices using LTPO technology.

[0005] The technical solution provided in this application is as follows:

[0006] In a first aspect, embodiments of this application provide a display panel, which includes a substrate and a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a driving transistor, a switching transistor, a compensation transistor, and a first initialization transistor. The switching transistor is connected to the driving transistor at a first node. One electrode of the compensation transistor and one electrode of the first initialization transistor are connected to the driving transistor at a second node. The other electrode of the compensation transistor is connected to the driving transistor at a third node. The display panel further includes:

[0007] A light-shielding layer is disposed on one side of the substrate;

[0008] A first semiconductor layer is disposed on the side of the light-shielding layer away from the substrate, and the first semiconductor layer includes a first active portion of the driving transistor and a second active portion of the switching transistor;

[0009] A second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate. The second semiconductor layer includes a third active portion of the compensation transistor and a fourth active portion of the first initialization transistor.

[0010] The light-shielding layer includes a first light-shielding part corresponding to the first active part, a second light-shielding part corresponding to the third active part, and a third light-shielding part corresponding to the fourth active part; the light-shielding layer also includes a first connecting line extending along a first direction and a second connecting line extending along a second direction, the first direction and the second direction being different, the first connecting line connecting two first light-shielding parts arranged adjacent to each other in the first direction, and the second connecting line connecting two first light-shielding parts arranged adjacent to each other in the second direction.

[0011] Secondly, embodiments of this application also provide a display device, the display device including a display panel as described in one of the foregoing embodiments. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 is a schematic diagram of the first type of contrast display device provided in the embodiments of this application.

[0014] Figure 2 is a schematic diagram of a second type of contrast display device provided in an embodiment of this application.

[0015] Figure 3 is a schematic diagram of a third type of comparison display device provided in an embodiment of this application.

[0016] Figure 4 is a schematic diagram of the film layer of the display panel provided in the embodiment of this application.

[0017] Figure 5 is a circuit diagram of the sub-pixels of the display panel provided in an embodiment of this application.

[0018] Figure 6 is a first type of stacking diagram of the film layers of the display panel provided in the embodiment of this application.

[0019] Figure 7 is a second stacking diagram of the film layers of the display panel provided in the embodiment of this application.

[0020] Figure 8 is an exploded view of the light-shielding layer of the display panel in Figure 6.

[0021] Figure 9 is an exploded view of the light-shielding layer of the display panel in Figure 7.

[0022] Figure 10 is an exploded view of the first semiconductor layer of the display panel in Figure 6.

[0023] Figure 11 is an exploded view of the first gate layer of the display panel in Figure 6.

[0024] Figure 12 is an exploded view of the second semiconductor layer of the display panel in Figure 6.

[0025] Figure 13 is an exploded view of the second gate layer of the display panel in Figure 6.

[0026] Figure 14 is an exploded view of the first source-drain layer of the display panel in Figure 6.

[0027] Figure 15 is an exploded view of the second source-drain layer of the display panel in Figure 6.

[0028] Figure 16 is an exploded view of the first via in the display panel of Figure 6.

[0029] Figure 17 is an exploded view of the second via of the display panel in Figure 6.

[0030] Figure 18 is an exploded view of the third via of the display panel in Figure 6.

[0031] Figure 19 is an exploded view of the fourth via of the display panel in Figure 6. Embodiments of the present invention

[0032] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.

[0033] Please refer to Figures 1 to 3 as an introduction to the embodiments of this application, and provide some contrast display devices. Figure 1 is a schematic diagram of the first type of contrast display device provided in the embodiments of this application, Figure 2 is a schematic diagram of the second type of contrast display device provided in the embodiments of this application, and Figure 3 is a schematic diagram of the third type of contrast display device provided in the embodiments of this application. Referring to Figure 1, a contrast display device employing LTPO technology includes a substrate 101, a light-shielding film 102, a blocking film 103, a buffer film 104, a low-temperature polycrystalline silicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarization film 117, a second source-drain film 118, a second planarization film 119, a third source-drain film 121, a third planarization film 122, an anode film 123, a pixel definition film 124, and a support film 125. As can be seen from Figure 1, the contrast display device includes three source-drain films and three gate films, requiring 16 photomasks for its formation, resulting in a complex process and high cost.

[0034] To address the issue of complex manufacturing processes in contrast display devices, another type of contrast display device removes one of the gate film and insulating film layers, as shown in Figure 2. It can be seen that the second gate film 109 and the second gate insulating film 108 are removed in the contrast display device, which can reduce the number of photomasks to 14. However, the problem of a large number of photomasks, complex manufacturing processes, and high costs still exists.

[0035] To address the complexity of the manufacturing process in contrast display devices, another type of contrast display device further removes a source / drain film and an insulating film, as shown in Figure 3. By removing the third source / drain film 121 and the third planarization film 122, the number of photomasks can be reduced to 13. However, as can be seen from Figures 2 and 3, the oxide semiconductor film 112 is unshielded, resulting in the absence of the bottom gate of the oxide thin-film transistor, which degrades the photosensitivity and electrical properties of the thin-film transistor.

[0036] Therefore, this application provides a display panel and a display device. Referring to Figures 1 to 19, Figure 4 is a schematic diagram of the film layers of the display panel provided in an embodiment of this application. Figure 5 is a circuit diagram of the sub-pixels of the display panel provided in an embodiment of this application. Figure 6 is a first stacked diagram of the film layers of the display panel provided in an embodiment of this application. Figure 7 is a second stacked diagram of the display panel provided in an embodiment of this application. Figure 8 is an exploded view of the light-shielding layer of the display panel in Figure 6. Figure 9 is an exploded view of the light-shielding layer of the display panel in Figure 7. Figure 10 is an exploded view of the first semiconductor layer of the display panel in Figure 6. Figure 11 is an exploded view of the first gate layer of the display panel in Figure 6. Figure 12 is an exploded view of the second semiconductor layer of the display panel in Figure 6. Figure 13 is an exploded view of the second gate layer of the display panel in Figure 6. Figure 14 is an exploded view of the first source / drain layer of the display panel in Figure 6. Figure 15 is an exploded view of the second source / drain layer of the display panel in Figure 6. Figure 16 is an exploded view of the first via of the display panel in Figure 6. Figure 17 is an exploded view of the second via of the display panel in Figure 6. Figure 18 is an exploded view of the third via in the display panel of Figure 6. Figure 19 is an exploded view of the fourth via in the display panel of Figure 6.

[0037] It should be noted that the difference between the display panel in Figure 6 and the display panel in Figure 7 in this embodiment lies in the design of the light-shielding layer. The design of other film layers on the display panel can be the same. Therefore, in the exploded view of Figure 6 below, except for the light-shielding layer, the exploded views of other film layers can also be used as the exploded views of the corresponding film layers of the display panel in Figure 7. For example, the exploded view of the light-shielding layer of the display panel in Figure 7 can be shown in Figure 9. Similarly, other film layers can be referred to in other exploded views, which will not be repeated here.

[0038] This application provides a display panel, as shown in Figures 4 to 19. The display panel 2 includes a substrate 201 and a plurality of sub-pixels 31 disposed on the substrate 201. Each sub-pixel 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, and a first initialization transistor T4. The switching transistor T2 and the driving transistor T1 are connected to a first node A. One electrode of the compensation transistor T3 and one electrode of the first initialization transistor T4 are connected to the driving transistor T1 at a second node Q. The other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B.

[0039] The display panel 2 also includes a light-shielding layer 202, a first semiconductor layer 207 and a second semiconductor layer 212 disposed on a substrate 201. The light-shielding layer 202 is disposed between the substrate 201 and the first semiconductor layer 207, and the first semiconductor layer 207 is disposed between the light-shielding layer 202 and the second semiconductor layer 212.

[0040] The first semiconductor layer 207 is disposed on the side of the light-shielding layer 202 away from the substrate 201. The first semiconductor layer 207 includes a first active portion T1A of the driving transistor T1 and a second active portion T2A of the switching transistor T2.

[0041] The second semiconductor layer 212 is disposed on the side of the first semiconductor layer 207 away from the substrate 201. The second semiconductor layer 212 includes the third active portion T3A of the compensation transistor T3 and the fourth active portion T4A of the first initialization transistor T4.

[0042] The light-shielding layer 202 includes a first light-shielding part 202a corresponding to the first active part T1A, a second light-shielding part 202b corresponding to the third active part T3A, and a third light-shielding part 202c corresponding to the fourth active part T4A. The light-shielding layer 202 also includes a first connecting line 202e extending along a first direction X and a second connecting line 202d extending along a second direction Y. The first connecting line 202e connects to two adjacent first light-shielding parts 202a in the first direction X, and the second connecting line 202d connects to two adjacent first light-shielding parts 202a in the second direction Y, thus forming a mesh structure in the light-shielding layer 202. The second light-shielding parts 202b and the third light-shielding parts 202c are both located within the area enclosed by two adjacent first connecting lines 202e, two adjacent second connecting lines 202d, and four first light-shielding parts 202a; that is, the second light-shielding parts 202b and the third light-shielding parts 202c are located within a portion of the mesh of the mesh structure formed by the light-shielding layer 202. In this application, the first direction X and the second direction Y are different. For example, the first direction X is horizontal and the second direction Y is vertical, that is, the first direction X is the row direction and the second direction Y is the column direction. Of course, this application is not limited to this. In this application, the first direction X and the second direction Y can also form other angles.

[0043] This application provides a display panel, which includes a substrate and a light-shielding layer, a first semiconductor layer, and a second semiconductor layer disposed on the substrate. The first semiconductor layer forms a first active portion of a driving transistor, and the second semiconductor layer forms a third active portion of a compensation transistor and a fourth active portion of a first initialization transistor. The light-shielding layer includes a first light-shielding portion disposed corresponding to the first active portion, a second light-shielding portion disposed corresponding to the third active portion, and a third light-shielding portion disposed corresponding to the fourth active portion. The second light-shielding portion can block light from the third active portion, and the third light-shielding portion can block light from the fourth active portion, so as to prevent the third active portion of the compensation transistor and the fourth active portion of the first initialization transistor from being affected by light, thereby improving the photosensitivity and electrical properties of the compensation transistor and the first initialization transistor, so as to improve the problem of deteriorated photosensitivity and electrical properties caused by the lack of bottom gate of oxide thin film transistors in display devices using LTPO technology.

[0044] Specifically, in the embodiments of this application, the light-shielding portion formed by the light-shielding layer being correspondingly disposed to the active portion of the transistor means that the light-shielding portion is at least correspondingly disposed to the channel portion of the active portion of the transistor. The projection of the light-shielding portion on the substrate and the projection of the channel portion of the transistor on the substrate overlap. It is understood that the active portion of each transistor includes a doped portion and a channel portion. The channel portion is easily affected by light, which can cause changes in performance. Therefore, the light-shielding portion can be correspondingly disposed to the channel portion of the transistor. Specifically, for example, the second light-shielding portion being correspondingly disposed to the third active portion of the compensation transistor means that the second light-shielding portion is at least correspondingly disposed to the third channel portion of the compensation transistor.

[0045] In some embodiments, as shown in Figures 6 and 8, the light-shielding layer 202 includes a first light-shielding portion 202a, a second light-shielding portion 202b, and a third light-shielding portion 202c. The first light-shielding portion 202a is correspondingly disposed to the first active portion T1A of the driving transistor T1, the second light-shielding portion 202b is correspondingly disposed to the third active portion T3A of the compensation transistor T3, and the third light-shielding portion 202c is correspondingly disposed to the fourth active portion T4A of the first initialization transistor T4.

[0046] Specifically, the orthographic projection of the first active portion of the driving transistor on the substrate is located within the orthographic projection of the first light-shielding portion on the substrate, the orthographic projection of the third active portion of the compensation transistor on the substrate is located within the orthographic projection of the second light-shielding portion on the substrate, and the orthographic projection of the fourth active portion of the first initialization transistor on the substrate is located within the orthographic projection of the third light-shielding portion on the substrate. This prevents light from shining on the first active portion of the driving transistor, the third active portion of the compensation transistor, and the fourth active portion of the first initialization transistor, thereby improving the electrical and photosensitivity of the driving transistor, the compensation transistor, and the first initialization transistor.

[0047] Specifically, the area of ​​the first light-shielding part can be greater than or equal to the area of ​​the first active part of the driving transistor, the area of ​​the second light-shielding part can be greater than or equal to the area of ​​the third active part of the compensation transistor, and the area of ​​the third light-shielding part can be greater than or equal to the area of ​​the fourth active part of the first initialization transistor.

[0048] In some embodiments, as shown in Figures 4, 6, and 8, the display panel includes a plurality of repeating units 30 arrayed on a substrate. Each repeating unit 30 includes two sub-pixels 31 arranged in a mirror-symmetrical manner. Within each repeating unit 30, a light-shielding layer 202 includes two first light-shielding portions 202a, two second light-shielding portions 202b, two third light-shielding portions 202c, and a first connecting line 202e and a second connecting line 202d connecting adjacent first light-shielding portions 202a, symmetrically arranged in the corresponding regions of the two sub-pixels 31. The second light-shielding portion 202b is located between the third light-shielding portion 202c and the first light-shielding portion 202a. The second light-shielding portion 202b is also arranged corresponding to the gap between adjacent first light-shielding portions 202a. The two first light-shielding portions 202a are mirror-symmetrical about the two second light-shielding portions 202b. Furthermore, the second light-shielding portion 202b partially overlaps with the first light-shielding portion 202a in the first direction X. The third light-shielding part 202c is located between two adjacent second connecting lines 202d. In the second direction Y, the third light-shielding part 202c partially overlaps with the first light-shielding part 202a.

[0049] The first connecting line 202e is disposed along the first direction X, and the second connecting line 202d is disposed along the second direction Y. The first light-shielding part 202a has a notch on the side away from the second light-shielding part 202b, and the first connecting line 202e is disposed at the notch. Two adjacent first connecting lines 202e coincide in the first direction X. The second connecting line 202d is located on the side of the center line of the first light-shielding part 202a in the second direction Y, closer to the second light-shielding part 202b, and two adjacent second connecting lines 202d coincide in the second direction Y. The second light-shielding part 202b has gaps with the first light-shielding part 202a, the first connecting line 202e, and the second connecting line 202d to insulate the second light-shielding part 202b from the first light-shielding part 202a. The third light-shielding part 202c also has gaps with the first light-shielding part 202a, the first connecting line 202e, and the second connecting line 202d to insulate the third light-shielding part 202c from the first light-shielding part 202a. Optionally, there is a gap between adjacent second light-shielding portions 202b, a gap between adjacent third light-shielding portions 202c, and a gap between adjacent second light-shielding portions 202b and third light-shielding portions 202c. The second light-shielding portions 202b and / or the third light-shielding portions 202c are in a floating state, meaning they are not connected to electrical signals and no electrical signals are applied to them. At least one of the first light-shielding portion 202a, the first connecting line 202e, and the second connecting line 202d is connected to a high-potential power line.

[0050] Specifically, it is understood that the display panel will include multiple repeating units arranged in an array, and the sub-pixels within each repeating unit can be referred to the design within a repeating unit in the embodiments of this application.

[0051] Specifically, it is understood that in a display panel, adjacent sub-pixels are symmetrically arranged to increase the aperture ratio. In this embodiment, by symmetrically arranging each light-shielding part and connecting the first light-shielding parts in each row and column by setting the first connecting line and the second connecting line, a mesh structure of the first light-shielding part can be realized. This makes the voltage drop of each part of the first light-shielding part similar or even the same when a signal is input, thereby making the signal uniformity better and improving the display effect.

[0052] Specifically, as shown in Figure 8, the first connecting line 202e connects multiple first light-shielding parts 202a in the first direction X, and the second connecting line 202d connects multiple first light-shielding parts 202a in the second direction Y. The second connecting line 202d connects the first light-shielding part 202a in the current row of sub-pixels 31 with the first light-shielding part 202a in the previous row of sub-pixels 31. Adjacent second connecting lines 202d connect the first light-shielding part 202a in the current row of sub-pixels 31 with the first light-shielding part 202a in the next row of sub-pixels 31. Furthermore, the two first light-shielding parts 202a in the repeating unit 30 are interconnected (not shown in the figure, because the interconnection of two first light-shielding parts 202a in some repeating units can achieve a grid-like design), thereby realizing the connection of the first light-shielding parts 202a in each row and column, so that the light-shielding layer 202 forms a mesh structure, thereby achieving uniformity during signal transmission.

[0053] In some embodiments, as shown in Figures 4, 7, and 9, unlike the embodiment illustrated in Figure 8, the light-shielding layer 202 further includes a third connecting line (202f1 and 202f2 as shown in Figure 9). Within a repeating unit, at least one of the second light-shielding part 202b and the third light-shielding part 202c is connected to at least one of the first light-shielding part 202a, the first connecting line 202e, and the second connecting line 202d via the third connecting line. As shown in Figure 9, the second light-shielding part 202b is connected to the first light-shielding part 202a and the second connecting line 202d via the third connecting line 202f1, and the third light-shielding part 202c is connected to the second connecting line 202d via the third connecting line 202f2. Adjacent second light-shielding portions 202b and / or adjacent third light-shielding portions 202c are connected by a fourth connecting line 202g. Thus, the second light-shielding portions 202b, third light-shielding portions 202c, third connecting lines 202f1, 202f2, and fourth connecting line 202g, together with the first light-shielding portion 202a, first connecting line 202e, and second connecting line 202d, form a grid structure, further achieving uniformity in signal transmission. Furthermore, it can replace the first connecting line 202e connecting two adjacent first light-shielding portions 202a within the repeating unit, thereby reducing the number of first connecting lines 202e. Simultaneously, in the second direction Y, the linewidths of the second light-shielding portions 202b, third light-shielding portions 202c, third connecting lines 202f1, 202f2, and fourth connecting line 202g are all greater than the linewidth of the first connecting line 202e, further reducing the overall impedance of the light-shielding layer 202 and further improving signal uniformity.

[0054] Optionally, at least one of the first light-shielding part 202a, the second light-shielding part 202b, the third light-shielding part 202c, the first connecting line 202e, the second connecting line 202d, and the third connecting lines 202f1 and 202f2 is connected to a high-potential power line.

[0055] In some embodiments, as shown in FIG5, the gate of the switching transistor T2 is connected to the first scan signal line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node B; the sub-pixel 31 further includes:

[0056] The first light-emitting control transistor T5 has its gate connected to the light-emitting control signal line EM, its first electrode connected to the high-potential power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0057] The second light-emitting control transistor T6 has its gate connected to the light-emitting control signal line EM, and its first electrode is connected to the second electrode of the driving transistor T1 at the third node B.

[0058] The second initialization transistor T7 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the second initialization signal line VI-ANO, and its second electrode connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C.

[0059] The third initialization transistor T8 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the third initialization signal line VI3, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0060] Storage capacitor Cst, one plate of storage capacitor Cst is connected to the high potential power line VDD, and the other plate of storage capacitor Cst is connected to the gate of driving transistor T1 at the second node Q;

[0061] The boost capacitor Cboost has one plate connected to the first scan signal line Pscan, and the other plate connected to the second electrode of the first initialization transistor T4.

[0062] Specifically, as shown in Figures 4 and 5, the display panel 2 also includes a light-emitting layer 23, which includes a light-emitting device LED. The positive electrode of the light-emitting device LED is connected to the second electrode of the second initialization transistor T7, and the negative electrode of the light-emitting device LED is connected to the low-potential power line VSS.

[0063] In some embodiments, as shown in FIG4, the display panel 2 further includes a first gate layer 209, a second gate layer 214, a first source-drain layer 216, and a second source-drain layer 218. The first gate layer 209 is disposed between the first semiconductor layer 207 and the second semiconductor layer 212, the second gate layer 214 is disposed between the second semiconductor layer 212 and the first source-drain layer 216, and the first source-drain layer 216 is disposed between the second gate layer 214 and the second source-drain layer 218. By including the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer in the display panel, the number of process steps in the display panel can be reduced, and the number of photomasks required to form the display panel can be reduced.

[0064] In some embodiments, as shown in Figures 4 to 6 and Figure 10, the first semiconductor layer 207 includes a first active portion T1A of a driving transistor T1, a second active portion T2A of a switching transistor T2, a fifth active portion T5A of a first light-emitting control transistor T5, a sixth active portion T6A of a second light-emitting control transistor T6, a seventh active portion T7A of a second initialization transistor T7, and an eighth active portion T8A of a third initialization transistor T8. The first active portion T1A of the driving transistor T1 is disposed along a first direction X, and the first active portion T1A of the driving transistor T1 is connected to the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light-emitting control transistor T5, and the sixth active portion T6A of the second light-emitting control transistor T6. The second active portion T2A of transistor T2 and the fifth active portion T5A of the first light-emitting control transistor T5 are arranged along the second direction Y. The sixth active portion T6A of the second light-emitting control transistor T6 and the seventh active portion T7A of the second initialization transistor T7 are arranged along the second direction Y, and the sixth active portion T6A of the second light-emitting control transistor T6 and the seventh active portion T7A of the second initialization transistor T7 are connected. The eighth active portion T8A of the third initialization transistor T8 is spaced apart from the first active portion T1A of the driving transistor T1, the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light-emitting control transistor T5, the sixth active portion T6A of the second light-emitting control transistor T6, and the seventh active portion T7A of the second initialization transistor T7.

[0065] Specifically, it can be seen that within a repeating unit, the seventh active part T7A of the second initialization transistor T7 of two adjacent sub-pixels 31 is connected.

[0066] In some embodiments, as shown in Figures 4 to 7 and Figure 11, the first gate layer 209 includes a first initialization signal line VI-G, a first scan signal line Pscan, a light emission control signal line EM, a fourth scan signal line Pscan2, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light emission control transistor T5, a gate T6G of a second light emission control transistor T6, a gate T7G of a second initialization transistor T7, a gate T8G of a third initialization transistor T8, and a first plate Cst1 of a storage capacitor Cst. The first initialization signal line VI-G, the first scan signal line Pscan, the first plate Cst1 of the storage capacitor Cst, the light emission control signal line EM, and the fourth scan signal line Pscan2 are arranged sequentially at intervals along the second direction Y.

[0067] Specifically, as shown in Figure 11, the gate T2G of the switching transistor T2 is part of the first scan signal line Pscan. It can be understood that since the gates T2G of all the switching transistors T2 in a row of sub-pixels are connected to the same first scan signal line Pscan, when forming the first scan signal line Pscan, the portion of the channel of the switching transistor T2 corresponding to each sub-pixel on the first scan signal line Pscan serves as the gate of the switching transistor T2 of each pixel unit. Therefore, the same structure is identified by two labels. Similarly, the gate T1G of the driving transistor T1 serves as both the gate and the storage capacitor. The first plate Cst1 of Cst has a light emission control signal line EM corresponding to the channel portion of the first light emission control transistor T5 as the gate T5G of the first light emission control transistor T5. The light emission control signal line EM corresponding to the channel portion of the second light emission control transistor T6 is used as the gate T6G of the second light emission control transistor T6. The fourth scan signal line Pscan2 corresponding to the channel portion of the second initialization transistor T7 is used as the gate T7G of the second initialization transistor T7. The fourth scan signal line Pscan2 corresponding to the channel portion of the third initialization transistor T8 is used as the gate T8G of the third initialization transistor T8.

[0068] In some embodiments, as shown in Figures 4 to 7 and Figure 12, the second semiconductor layer 212 includes a third active portion T3A of a compensation transistor T3, a fourth active portion T4A of a first initialization transistor T4, and a second electrode Cst2 of a storage capacitor Cst. The third active portion T3A of the compensation transistor T3 is connected to the fourth active portion T4A of the first initialization transistor T4. The second electrode Cst2 of the storage capacitor Cst is disposed along a first direction X on one side of the third active portion T3A of the compensation transistor T3, and a through hole 331 is provided on the second electrode Cst of the storage capacitor Cst. By forming the second electrode of the storage capacitor in the second semiconductor layer, a storage capacitor can be disposed in the sub-pixel 31, and the through hole on the second electrode of the storage capacitor allows the first electrode of the compensation transistor to be normally connected to the gate of the driving transistor.

[0069] Specifically, it can be understood that the second semiconductor layer forms the second electrode of the storage capacitor. Therefore, it is necessary to make the second electrode of the storage capacitor have good electrical properties. This can be achieved by doping the second electrode of the storage capacitor to keep the electrical properties of the second electrode of the storage capacitor consistent with or even exceed the electrical properties of the doped part of the active part, so that the electrical properties of the storage capacitor are good.

[0070] Specifically, by providing a through hole on the second plate of the storage capacitor, the first electrode of the compensation transistor can pass through the second plate of the storage capacitor and connect to the gate of the driving transistor, enabling the sub-pixel 31 to work normally.

[0071] Specifically, as shown in Figures 11 and 12, the first gate layer 209 further includes the first plate Cboost1 of the boost capacitor Cboost, and the second semiconductor layer 212 further includes the second plate Cboost2 of the boost capacitor Cboost. The overlapping portion of the first scan signal line Pscan and the fourth active part T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the fourth active part T4A of the first initialization transistor T4 and the first scan signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0072] In some embodiments, as shown in Figures 4 to 7 and Figure 13, the second gate layer 214 includes a second scan signal line Nscan1, a third scan signal line Nscan2, a third initialization signal line VI3, the gate T3G of the compensation transistor T3, and the gate T4G of the first initialization transistor T4. The third scan signal line Nscan2, the second scan signal line Nscan1, and the third initialization signal line VI3 are arranged sequentially along the second direction Y.

[0073] In some embodiments, as shown in Figures 4 to 7 and Figure 14, the first source-drain layer 216 includes a first data connection line L1, a first electrode T2S of a switching transistor T2, a first electrode T3S of a compensation transistor T3, a second electrode T3D of a compensation transistor T3, a first electrode T4S of a first initialization transistor T4, a second electrode T4D of a first initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T5D of a first light-emitting control transistor T5, a first electrode T6S of a second light-emitting control transistor T6, a second electrode T6D of a second light-emitting control transistor T6, a first electrode T7S of a second initialization transistor T7, a second electrode T7D of a second initialization transistor T7, a first electrode T8S of a third initialization transistor T8, a second electrode T8D of a third initialization transistor T8, and a second initialization signal line VI-ANO.

[0074] Specifically, as shown in Figure 14, it can be understood that since the electrodes of each transistor are connected together, in actual design, to improve the aperture ratio, the electrodes of each transistor will share the same structure. Therefore, in Figure 14, the same structure is identified by multiple labels. For example, one structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. As can be seen from Figure 5, this is the location where the second node Q is connected. Similarly, other structures will also serve as multiple electrodes, and the positions of each node can be determined accordingly.

[0075] Specifically, as shown in Figures 11 and 14, the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4 are connected through the first connection terminal K1. Given the small distance between the projections of the first initialization signal line VI-G and the third scan signal line Nscan2 on the substrate, directly forming vias in the corresponding region of the first electrode of the first initialization transistor to connect the first initialization signal line would result in vias being formed on the third scan signal line Nscan2. Therefore, the first connection terminal K1 can be set on the first source-drain layer, connecting the first electrode of the first initialization transistor T4. Simultaneously, vias are formed in the corresponding region of the first connection terminal K1, connecting the first connection terminal K1 to the first initialization signal line VI-G. This achieves the connection between the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4. Furthermore, the first connection terminal K1 is positioned on the axis of symmetry of the two symmetrically arranged sub-pixels 31, allowing the first electrodes of the first initialization transistor T4 in the two symmetrically arranged sub-pixels 31 to be connected to the first initialization signal line through the same first connection terminal K1, reducing the number of vias and improving yield.

[0076] Specifically, as shown in Figures 6, 7, 14, and 15, since the high-potential power line VDD does not overlap with the first electrode T5S of the first light-emitting control transistor T5, and the high-potential power line VDD will connect to one plate of the storage capacitor, a second connection terminal K2 needs to be set to connect to the high-potential power line VDD, so that the signal of the high-potential power line VDD can be transmitted to the first electrode T5S of the first light-emitting control transistor T5. A third connection terminal K3 can also be set to connect to the second plate Cst2 of the storage capacitor Cst, thereby realizing the connection of one plate of the storage capacitor Cst, the first light-emitting control transistor T5, and the high-potential power line VDD.

[0077] Specifically, as shown in Figures 6 to 14, the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a fourth connection terminal K4 can be provided in the first source-drain layer. The fourth connection terminal K4 passes through the via 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0078] In some embodiments, as shown in Figures 4 to 15, within the repeating unit 30, the second source-drain layer 218 includes two data lines DATA, an initialization signal connection line L3, two high-potential power lines VDD, and a second data connection line L2. The two data lines DATA are arranged in a mirror-symmetric configuration, the two high-potential power lines VDD are arranged in a mirror-symmetric configuration, and the initialization signal connection line L3 and the second data connection line L2 are arranged in a mirror-symmetric configuration.

[0079] Specifically, the high-potential power line VDD can be connected to the second connection terminal K2 through a via, and the data line can be connected to the first electrode T2S of the switching transistor T2 through a via.

[0080] Specifically, as shown in Figure 15, the second source-drain layer 218 also includes a fifth connection terminal K5, which connects the second electrode T6D of the second light-emitting control transistor T6 and the first electrode of the light-emitting device.

[0081] Specifically, it is understood that due to the design of the sub-pixel 31 in the display area shown in the embodiments of this application, and the connection points of some traces located in the non-display area, some traces may not be connected together. However, in reality, they will be connected. For example, in order to adopt the technology of setting the fanout line in the display area (Fanout In AA, FIAA), the data line DATA will be provided with a first data connection line L1 set along the first direction and a second data connection line L2 set along the second direction, and will be connected to the data line outside the display area. However, the embodiments of this application show the design of the sub-pixel 31, so its connection point is not shown, but in reality, it will be connected.

[0082] Meanwhile, in order to realize the mesh structure design of the initialization signal line, the embodiments of this application will set an initialization signal connection line L3. The initialization signal connection line L3 can realize the mesh structure design of at least one of the first initialization signal line, the second initialization signal line and the third initialization signal line. Similarly, the initialization signal connection line will be connected to the initialization signal line.

[0083] For example, the first initialization signal line can be connected to the initialization signal connection line outside the display area to achieve a mesh structure design for the first initialization signal line. Similarly, a mesh structure design for the second and third initialization signal lines can be achieved. However, the embodiments of this application are not limited to this. Some initialization signal connection lines can be connected to one of the first, second, and third initialization signal lines, and some initialization signal connection lines can be connected to the other one of the first, second, and third initialization signal lines. Alternatively, some initialization signal connection lines can be connected to the other one of the first, second, and third initialization signal lines to achieve a mesh structure design for each initialization signal line.

[0084] In some embodiments, as shown in FIG16, FIG16 illustrates the location of the first via 341, which refers to a via etched from the first source / drain layer to the first semiconductor layer or the first gate layer.

[0085] In some embodiments, as shown in FIG17, FIG17 illustrates the location of the second via 342, which refers to a via etched from the first source / drain layer to the second semiconductor layer or the second gate layer.

[0086] In some embodiments, as shown in FIG18, FIG18 illustrates the location of the third via 343, which refers to a via etched from the second source-drain layer to the first source-drain layer.

[0087] In some embodiments, as shown in FIG19, FIG19 illustrates the location of the fourth via 344, which refers to the via etched from the anode of the light-emitting layer to the second source-drain layer.

[0088] Specifically, as shown in Figure 4, the display panel 2 also includes a first barrier layer 203, a second barrier layer 205, a buffer layer 206, a first gate insulating layer 208, a first interlayer insulating layer 211, a second gate insulating layer 213, a second interlayer insulating layer 215, a first planarization layer 217, and a second planarization layer 219.

[0089] Specifically, as shown in Figure 4, the display panel 2 also includes a light-emitting layer 23, which includes a pixel electrode layer 221, a pixel definition layer 222, a light-emitting material layer, a common electrode layer, and support pillars 223.

[0090] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0091] Specifically, the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM can be connected to different gate driving circuits. Specifically, five sets of gate driving circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM, respectively. Among them, the gate driving circuit connected to the first scan signal line Pscan can use double-sided driving, while the other gate driving circuits use single-sided driving.

[0092] Specifically, the material of the first semiconductor layer includes silicon semiconductor materials, specifically low-temperature polycrystalline silicon.

[0093] Specifically, the material of the second semiconductor layer includes oxide semiconductor materials, specifically metal oxide semiconductor materials, and more specifically, indium gallium zinc oxide.

[0094] Specifically, the materials used for the light-shielding layer include metallic materials.

[0095] Specifically, the driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor, the second initialization transistor, and the third initialization transistor are P-type transistors, while the first initialization transistor and the compensation transistor are N-type transistors.

[0096] Specifically, the above embodiments have provided a detailed description of the display panel from the aspects of sub-pixel structure, film layer structure, specific structure of each layer, material, and potential. It is understood that when there is no conflict between the embodiments, the embodiments can be combined.

[0097] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0098] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0099] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel comprising a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel comprising a driving transistor, a switching transistor, a compensation transistor and a first initialization transistor, the switching transistor being connected to the driving transistor at a first node; one electrode of the compensation transistor, one electrode of the first initialization transistor and the driving transistor being connected to a second node, and the other electrode of the compensation transistor being connected to the driving transistor at a third node; The display panel also includes: A light-shielding layer is disposed on one side of the substrate; A first semiconductor layer is disposed on the side of the light-shielding layer away from the substrate, and the first semiconductor layer includes a first active portion of the driving transistor and a second active portion of the switching transistor; A second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate. The second semiconductor layer includes a third active portion of the compensation transistor and a fourth active portion of the first initialization transistor. The light-shielding layer includes a first light-shielding part corresponding to the first active part, a second light-shielding part corresponding to the third active part, and a third light-shielding part corresponding to the fourth active part; the light-shielding layer also includes a first connecting line extending along a first direction and a second connecting line extending along a second direction, the first direction and the second direction being different, the first connecting line connecting two first light-shielding parts arranged adjacent to each other in the first direction, and the second connecting line connecting two first light-shielding parts arranged adjacent to each other in the second direction.

2. The display panel according to claim 1, wherein, Both the second light-shielding part and the third light-shielding part are located within the area enclosed by two adjacent first connecting lines, two adjacent second connecting lines, and four first light-shielding parts.

3. The display panel according to claim 2, wherein, The second light-shielding part has gaps with the first light-shielding part, the first connecting line and the second connecting line, and the third light-shielding part has gaps with the first light-shielding part, the first connecting line and the second connecting line, and the second light-shielding part and / or the third light-shielding part are in a floating state.

4. The display panel according to claim 3, wherein, There is a gap between adjacent second light-shielding parts, there is a gap between adjacent third light-shielding parts, and there is also a gap between adjacent second light-shielding parts and third light-shielding parts.

5. The display panel according to claim 2, wherein, The light-shielding layer further includes a third connecting line, and at least one of the second light-shielding part and the third light-shielding part is connected to at least one of the first light-shielding part, the first connecting line, and the second connecting line through the third connecting line.

6. The display panel according to claim 5, wherein, The light-shielding layer also includes a fourth connecting line, through which adjacent second light-shielding portions and / or adjacent third light-shielding portions are connected.

7. The display panel according to claim 5, wherein, At least one of the first light-shielding part, the second light-shielding part, the third light-shielding part, the first connecting line, the second connecting line, and the third connecting line is connected to a high-potential power line.

8. The display panel according to claim 1, wherein, The orthographic projection of the first active part on the substrate is located within the orthographic projection of the first light-shielding part on the substrate, the orthographic projection of the third active part on the substrate is located within the orthographic projection of the second light-shielding part on the substrate, and the orthographic projection of the fourth active part on the substrate is located within the orthographic projection of the third light-shielding part on the substrate.

9. The display panel according to claim 8, wherein, In the first direction, the second light-shielding portion partially overlaps with the first light-shielding portion; the third light-shielding portion is located between two adjacent second connecting lines, and in the second direction, the third light-shielding portion partially overlaps with the first light-shielding portion.

10. The display panel according to any one of claims 1 to 9, wherein, The gate of the switching transistor is connected to the first scan signal line, the first electrode of the switching transistor is connected to the data line, and the second electrode of the switching transistor is connected to the first electrode of the driving transistor at a first node; the gate of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the gate of the driving transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor; the gate of the first initialization transistor is connected to the third scan signal line, the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the driving transistor at a second node; The sub-pixel also includes: The first light-emitting control transistor has its gate connected to the light-emitting control signal line, its first electrode connected to the high-potential power supply line, and its second electrode connected to the first electrode of the driving transistor at the first node. The second light-emitting control transistor has its gate connected to the light-emitting control signal line, and its first electrode is connected to the second electrode of the driving transistor at the third node. The second initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the second initialization signal line, and its second electrode connected to the second light-emitting control transistor at the fourth node. The third initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the third initialization signal line, and its second electrode connected to the first electrode of the driving transistor at the first node. A storage capacitor, one plate of which is connected to the high-potential power line, and the other plate of which is connected to the gate of the driving transistor at a second node; A boost capacitor, one plate of which is connected to the first scan signal line, and the other plate of which is connected to the second electrode of the first initialization transistor.

11. The display panel according to claim 10, wherein, The driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor, the second initialization transistor, and the third initialization transistor are all P-type transistors, while the first initialization transistor and the compensation transistor are both N-type transistors.

12. The display panel according to claim 10, wherein, The material of the first semiconductor layer includes silicon semiconductor material, and the material of the second semiconductor layer includes oxide semiconductor material.

13. The display panel according to claim 10, wherein, The second semiconductor layer further includes a second electrode plate of the storage capacitor. The second electrode plate is disposed corresponding to the first active part and is connected to the high-potential power line. A through hole is provided on the second electrode plate.

14. The display panel according to claim 10, wherein, The first semiconductor layer further includes a fifth active portion of the first light-emitting control transistor, a sixth active portion of the second light-emitting control transistor, a seventh active portion of the second initialization transistor, and an eighth active portion of the third initialization transistor. The first active portion is disposed along a first direction and is connected to the second active portion, the fifth active portion, and the sixth active portion. The second active portion and the fifth active portion are disposed along a second direction. The sixth active portion and the seventh active portion are disposed along the second direction and are connected to each other. The eighth active portion is spaced apart from the first active portion, the third active portion, the fifth active portion, the sixth active portion, and the seventh active portion.

15. The display panel according to claim 10, wherein, The display panel also includes: A first gate layer is disposed between the first semiconductor layer and the second semiconductor layer. The first gate layer includes a first initialization signal line, a first scan signal line, a light emission control signal line, a fourth scan signal line, the gate of the driving transistor, the gate of the switching transistor, the gate of the first light emission control transistor, the gate of the second light emission control transistor, the gate of the second initialization transistor, the gate of the third initialization transistor, and the first plate of the storage capacitor. The first initialization signal line, the first scan signal line, the first plate of the storage capacitor, the light emission control signal line, and the fourth scan signal line are arranged sequentially at intervals along the second direction. The second gate layer is disposed on the side of the second semiconductor layer away from the substrate. The second gate layer includes the second scan signal line, the third scan signal line, the third initialization signal line, the gate of the compensation transistor, and the gate of the first initialization transistor. The third scan signal line, the second scan signal line, and the third initialization signal line are arranged sequentially along the second direction. A first source-drain layer is disposed on the side of the second gate away from the substrate. The first source-drain layer includes a first data connection line, a first electrode of the switching transistor, a first electrode and a second electrode of the compensation transistor, a first electrode and a second electrode of the first initialization transistor, a first electrode and a second electrode of the first light-emitting control transistor, a first electrode and a second electrode of the second light-emitting control transistor, a first electrode and a second electrode of the second initialization transistor, a first electrode and a second electrode of the third initialization transistor, and a second initialization signal line. The second source-drain layer is disposed on the side of the first source-drain layer away from the substrate. The second source-drain layer includes the data line, the high-potential power line, the second data connection line, and the initialization signal connection line extending along the second direction.

16. The display panel according to claim 15, wherein, The display panel further includes a plurality of repeating units arranged in an array on the substrate. Each repeating unit includes two mirror-symmetrical sub-pixels, two mirror-symmetrical data lines, two mirror-symmetrical high-potential power lines, and mirror-symmetrical second data connection lines and initialization signal connection lines. Within the repeating unit, the high-potential power lines are located between the second data connection lines and the initialization signal connection lines, and both the second data connection lines and the initialization signal connection lines are located between the high-potential power lines and the data lines.

17. The display panel according to claim 16, wherein, Within the repeating unit, the light-shielding layer includes two first light-shielding portions, two second light-shielding portions, two third light-shielding portions symmetrically disposed within the corresponding regions of the two sub-pixels, and a first connecting line and a second connecting line connecting the two adjacent first light-shielding portions; the second light-shielding portion is located between the third light-shielding portion and the first light-shielding portion, and the second light-shielding portion is also disposed corresponding to the gap between the two adjacent first light-shielding portions, and the two first light-shielding portions are mirror-symmetrical about the two second light-shielding portions.

18. The display panel according to claim 17, wherein, The first light-shielding part has a notch on the side away from the second light-shielding part, and the first connecting line is disposed at the notch.

19. The display panel according to claim 17, wherein, The second connecting line is located on the side of the center line of the first light-shielding part in the second direction, close to the second light-shielding part, and two adjacent second connecting lines coincide in the second direction.

20. A display device comprising a display panel as claimed in any one of claims 1 to 19.

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