Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a display area and a hole area; the display area is arranged around the hole area; the hole area comprises a first area and a second area which are arranged in sequence in a direction distant from the display area; the first area and the second area are each provided with a plurality of isolation pillars; an insulating filling structure is filled between at least two adjacent isolation pillars located in the first area and the second area; at least one insulating filling structure at least partially covers the sidewalls of two adjacent isolation pillars close to the insulating filling structure; the thickness of at least one first insulating filling structure is less than that of at least one second insulating filling structure; the first insulating filling structure is arranged between adjacent first isolation pillars, and the first isolation pillars are isolation pillars located in the first area; and the second insulating filling structure is arranged between adjacent second isolation pillars, and the second isolation pillars are isolation pillars located in the second area.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411217791.3, filed on August 30, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices, possessing advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs as the light-emitting element and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a display substrate and a display device.

[0006] In a first aspect, this disclosure provides a display substrate, including: a display area and a hole area, the display area being disposed around the hole area, the hole area including: a first area and a second area being disposed sequentially away from the display area; the first area and the second area are provided with a plurality of isolation pillars, and an insulating filling structure is filled between at least two adjacent isolation pillars in the first area and the second area, and at least one insulating filling structure at least partially covers the sidewalls of the two adjacent isolation pillars near the insulating filling structure;

[0007] The thickness of at least one first insulating filler structure is less than the thickness of at least one second insulating filler structure. The first insulating filler structure is disposed between adjacent first isolation pillars, which are isolation pillars located in a first region. The second insulating filler structure is disposed between adjacent second isolation pillars, which are isolation pillars located in a second region.

[0008] In an exemplary embodiment, the ratio of the thickness of the second insulating fill structure to the thickness of the first insulating fill structure is between 1.05 and 3.85.

[0009] In an exemplary embodiment, the second insulating fill structure includes a second sub-fill structure, or includes a first sub-fill structure and a second sub-fill structure. When the second insulating fill structure includes a first sub-fill structure and a second fill structure, the first sub-fill structure is located on the side of the second sub-fill structure closer to the display area.

[0010] The thickness of the first sub-filling structure is less than the thickness of the second sub-filling structure.

[0011] In an exemplary embodiment, the thickness of the first insulating fill structure is less than the thickness of the second sub-fill structure.

[0012] In an exemplary embodiment, the display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate, wherein the light-emitting structure layer includes: an organic light-emitting layer and a cathode layer, wherein the organic light-emitting layer and the cathode layer extend from the display area to the second border area;

[0013] The organic light-emitting layer and the cathode layer located in the first frame region or the second frame region are separated by at least one isolation pillar located in the first frame region or the second frame region;

[0014] The organic light-emitting layer located in the first frame region or the second frame region includes: a first organic structure and a second organic structure arranged at intervals between each other; the cathode layer located in the first frame region or the second frame region includes: a first cathode structure and a second cathode structure arranged at intervals between each other, wherein the first cathode structure corresponds one-to-one with the first organic structure and the second cathode structure corresponds one-to-one with the second organic structure.

[0015] The first organic structure is disposed between at least some adjacent isolation pillars and at least partially covers at least a portion of the sidewalls of the adjacent isolation pillars. The second organic structure is disposed on the surface of at least one isolation pillar away from the substrate. The first cathode structure is disposed between at least some adjacent isolation pillars and at least partially covers the sidewalls of the adjacent isolation pillars. The second cathode structure is disposed on the side of the second organic structure away from the substrate. The maximum distance between the surface of at least one second organic structure away from the substrate and the substrate is greater than the maximum distance between the surface of the first cathode structure away from the substrate and the substrate.

[0016] In an exemplary embodiment, a second organic structure disposed on two isolation pillars filled with an insulating filler structure is interconnected, and its orthographic projection on the substrate covers the orthographic projection of the insulating filler structure on the substrate. A second cathode structure disposed on two isolation pillars filled with an insulating filler structure is interconnected, and its orthographic projection on the substrate covers the orthographic projection of the insulating filler structure on the substrate.

[0017] In an exemplary embodiment, the display substrate includes: a substrate and a circuit structure layer disposed on the substrate, the circuit structure layer including: M source-drain metal layers, the (m+1)th source-drain metal layer being located on the side of the mth source-drain metal layer away from the substrate, M≥2, 1≤m≤M-1;

[0018] At least one of the plurality of isolation pillars includes: a first isolation structure, wherein the first isolation structure of the at least one of the plurality of isolation pillars is located in one of the M source / drain metal layers.

[0019] In an exemplary embodiment, the display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate. The light-emitting structure layer includes: a pixel definition layer. The circuit structure layer includes: N planarization layers sequentially stacked on the substrate, wherein the (n+1)th planarization layer is located on the side of the nth planarization layer away from the substrate, and 1≤N≤M, 1≤n≤N-1.

[0020] The first insulating fill structure is located in the Nth flat layer or pixel definition layer.

[0021] In an exemplary embodiment, the display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate. The light-emitting structure layer includes: a pixel definition layer. The circuit structure layer includes: N planarization layers sequentially stacked on the substrate, wherein the (n+1)th planarization layer is located on the side of the nth planarization layer away from the substrate, and 1≤N≤M, 1≤n≤N-1.

[0022] The first sub-fill structure is located in the Nth flat layer or pixel definition layer.

[0023] In an exemplary embodiment, the display substrate includes: a substrate and a light-emitting structure layer disposed on the substrate, the light-emitting structure layer including: a pixel definition layer and spacers disposed on the pixel definition layer;

[0024] The second sub-filling structure is disposed in the same layer as the spacer.

[0025] In an exemplary embodiment, the circuit structure layer further includes: K gate metal layers stacked sequentially on the substrate, wherein the Kth gate metal layer is located on the side of the first source / drain metal layer closest to the substrate;

[0026] At least one of the plurality of isolation pillars further includes at least one of the second isolation structure to the (K+1)th isolation structure, wherein the orthographic projection of at least one of the second isolation structure to the (K+1)th isolation structure on the substrate overlaps with the orthographic projection of the first isolation structure.

[0027] The (k+1)th isolation structure is located in the kth gate metal layer, where 1 ≤ k ≤ K.

[0028] In an exemplary embodiment, the aperture area further includes a third region and a fourth region, wherein the third region is located between the first region and the second region, and the fourth region is located on the side of the second region away from the display area;

[0029] The third area is provided with at least one isolation dam, and the fourth area is provided with a cutting groove or at least one isolation column.

[0030] In an exemplary embodiment, the display substrate includes: a substrate and a circuit structure layer disposed on the substrate, the circuit structure layer further including: a plurality of inorganic insulating layers and a plurality of organic insulating layers; the border region includes: a composite insulating layer, the composite insulating layer including: a plurality of inorganic insulating layers located on the side of the Mth source / drain metal layer near the substrate, the inorganic insulating layer extending from the display region to the fourth region;

[0031] The cutting groove is disposed within the composite insulation layer.

[0032] In an exemplary embodiment, the first isolation structure of at least one of the plurality of isolation pillars includes: a first isolation portion, a second isolation portion, and a third isolation portion, wherein the first isolation portion is located on the side of the second isolation portion closer to the substrate, and the third isolation portion is located on the side of the second isolation portion away from the substrate;

[0033] The orthographic projection of the surface of the second isolation portion near the substrate onto the substrate is within the range of the orthographic projection of the surface of the first isolation portion away from the substrate onto the substrate, and the orthographic projection of the surface of the second isolation portion away from the substrate onto the substrate is within the range of the orthographic projection of the surface of the third isolation portion near the substrate onto the substrate.

[0034] In an exemplary embodiment, the first insulating filling structure overlaps with the orthographic projection of the third isolation portion of the first isolation post on the substrate, and the second insulating filling structure overlaps with the orthographic projection of the third isolation portion of the second isolation post on the substrate.

[0035] In an exemplary embodiment, the following are included: a substrate, the isolation pillars being disposed on the substrate, and at least one of the isolation pillars comprising: L conductive structures and L insulating structures stacked together, the L conductive structures and L insulating structures being alternately disposed, the l-th insulating structure being located on the side of the l-th conductive structure away from the substrate, and L being a positive integer greater than or equal to 1.

[0036] At least one of the conductive structures has a groove-shaped sidewall.

[0037] In an exemplary embodiment, when L is greater than or equal to 2, the orthographic projection of the surface of the l-th conductive structure near the substrate onto the substrate is within the range of the orthographic projection of the surface of the (l-1)-th insulating structure away from the substrate onto the substrate, and the maximum distance between the sidewall of the l-th conductive structure and the centerline of the isolation post is less than the minimum distance between the sidewall of the (l-1)-th insulating structure and the centerline of the isolation post.

[0038] In an exemplary embodiment, the isolation pillar includes: a first conductive structure and a first insulating structure;

[0039] The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: K gate metal layers and M source / drain metal layers disposed on the substrate. The (k+1)th gate metal layer is located on the side of the kth gate metal layer away from the substrate. The kth gate metal layer is located on the side of the first source / drain metal layer close to the substrate. The (m+1)th source / drain metal layer is located on the side of the mth source / drain metal layer away from the substrate. K≥2, 1≤k≤K-1, M≥2, 1≤m≤M-1.

[0040] The circuit structure layer further includes: multiple inorganic insulating layers and multiple organic insulating layers, and at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer;

[0041] The first conductive structure is located in one of the K gate metal layers and M source / drain metal layers, and the first insulating structure is located in one of the plurality of inorganic insulating layers.

[0042] In an exemplary embodiment, the isolation pillar includes: a first conductive structure, a first insulating structure, a second conductive structure, and a second insulating structure;

[0043] The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: K gate metal layers and M source / drain metal layers disposed on the substrate. The (k+1)th gate metal layer is located on the side of the kth gate metal layer away from the substrate. The kth gate metal layer is located on the side of the first source / drain metal layer close to the substrate. The (m+1)th source / drain metal layer is located on the side of the mth source / drain metal layer away from the substrate. K≥2, 1≤k≤K-1, M≥2, 1≤m≤M-1.

[0044] The circuit structure layer further includes: multiple inorganic insulating layers and multiple organic insulating layers, and at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer;

[0045] At least one of the first conductive structure and the second conductive structure is located in two of the K gate metal layers and M source / drain metal layers, and the first conductive structure and the second conductive structure are located in different layers; the first insulating structure and the second insulating structure are located in two of the multilayer inorganic insulating layers, and the first insulating structure and the second insulating structure are located in different layers.

[0046] In an exemplary embodiment, the isolation pillar includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, and a third insulating structure;

[0047] The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: K gate metal layers and M source / drain metal layers disposed on the substrate. The (k+1)th gate metal layer is located on the side of the kth gate metal layer away from the substrate. The kth gate metal layer is located on the side of the first source / drain metal layer close to the substrate. The (m+1)th source / drain metal layer is located on the side of the mth source / drain metal layer away from the substrate. K≥2, 1≤k≤K-1, M≥2, 1≤m≤M-1.

[0048] The circuit structure layer further includes: multiple inorganic insulating layers and multiple organic insulating layers, and at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer;

[0049] The first conductive structure, the second conductive structure, and the third conductive structure are located in three of the K gate metal layers and M source / drain metal layers, and the first conductive structure, the second conductive structure, and the third conductive structure are located in different layers; the first insulating structure, the second insulating structure, and the third insulating structure are located in three of the multilayer inorganic insulating layers, and the first insulating structure, the second insulating structure, and the third insulating structure are located in different layers.

[0050] In an exemplary embodiment, the display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate. The light-emitting structure layer includes: a pixel definition layer. The circuit structure layer includes: a plurality of planarization layers sequentially stacked on the substrate.

[0051] At least one isolation dam includes: a plurality of dam foundations stacked sequentially in a direction away from the base, at least one of the plurality of dam foundations being located in at least one flat layer, and at least one of the plurality of dam foundations being located in a pixel definition layer.

[0052] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0053] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0054] Overview of the attached figures

[0055] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0056] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0057] Figure 2 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0058] Figure 3 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0059] Figure 4 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0060] Figure 5 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0061] Figure 6 is a schematic diagram of the structure of the display substrate in the hole region provided in an embodiment of this disclosure;

[0062] Figure 7 is a second schematic diagram of the structure of the display substrate in the hole region provided in an embodiment of this disclosure;

[0063] Figure 8 is a schematic diagram of the hole region of a display substrate provided in an exemplary embodiment;

[0064] Figure 9 is a schematic diagram of the film layer in the hole region of a display substrate provided in an exemplary embodiment;

[0065] Figure 10 is a schematic diagram of the film layer in the hole region of a display substrate provided in an exemplary embodiment;

[0066] Figure 11 is a schematic diagram of the film layer in the hole region of a display substrate provided in an exemplary embodiment;

[0067] Figure 12 is a schematic diagram of the film layer in the hole region of a display substrate provided in an exemplary embodiment;

[0068] Figure 13 is a schematic diagram of the film layer in the hole region of a display substrate provided in an exemplary embodiment;

[0069] Figure 14 is a partial structural schematic diagram of the first and second regions provided in an embodiment of this disclosure;

[0070] Figure 15 is a schematic diagram of the membrane layer shown in Figure 14;

[0071] Figure 16 is a second schematic diagram of the membrane layer provided in Figure 14;

[0072] Figure 17 is a schematic diagram of the membrane layer shown in Figure 14 (Part 3);

[0073] Figure 18 is a schematic diagram of the membrane layer shown in Figure 14;

[0074] Figure 19 is a schematic diagram of the membrane layer provided in Figure 14;

[0075] Figure 20 is a schematic diagram of the membrane layer shown in Figure 14;

[0076] Figure 21 is a schematic diagram of the membrane layer shown in Figure 14;

[0077] Figure 22 is a schematic diagram of the membrane layer shown in Figure 14;

[0078] Figure 23 is a schematic diagram of the membrane layer provided in Figure 14 (nine).

[0079] Figure 24 is a schematic diagram of the membrane layer provided in Figure 14;

[0080] Figure 25 is a schematic diagram of the membrane layer provided in Figure 14;

[0081] Figure 26 is a schematic diagram of the membrane layer provided in Figure 14, number 12;

[0082] Figure 27 is a schematic diagram of the membrane layer provided in Figure 14, number thirteen.

[0083] Figure 28 is a schematic diagram of the membrane layer shown in Figure 14;

[0084] Figure 29 is a schematic diagram of the membrane layer provided in Figure 14, number 15;

[0085] Figure 30 is a schematic diagram of the membrane layer provided in Figure 14.

[0086] Figure 31 is a schematic diagram of the membrane layer shown in Figure 14.

[0087] Figure 32 is a schematic diagram of the membrane layer shown in Figure 14, number 18;

[0088] Figure 33 is a schematic diagram of the membrane layer provided in Figure 14.

[0089] Figure 34 is a schematic diagram of the membrane layer provided in Figure 14;

[0090] Figure 35 is a schematic diagram of the membrane layer provided in Figure 14, number twenty-one;

[0091] Figure 36 is a schematic diagram after the composite insulating layer is formed;

[0092] Figure 37 is a schematic diagram after the first isolation structure is formed;

[0093] Figure 38 is a schematic diagram after the insulation filling structure is formed;

[0094] Figure 39 is a schematic diagram after the first insulating layer is formed as shown in Figures 15 to 20;

[0095] Figure 40 is a schematic diagram of the first insulating structure formed in Figures 15 to 20;

[0096] Figure 41 is a schematic diagram of the first conductive structure formed in Figures 15 to 20;

[0097] Figure 42 is a schematic diagram of the insulation filling structure formed in Figures 15 to 20;

[0098] Figure 43 is a schematic diagram of the formation of multiple covering structures as shown in Figures 15 to 20;

[0099] Figure 44 is a schematic diagram of the second insulating layer after it has been formed as shown in Figures 21 to 29;

[0100] Figure 45 is a schematic diagram showing the formation of the first and second insulating structures as shown in Figures 21 to 29;

[0101] Figure 46 is a schematic diagram of the first and second conductive structures formed in Figures 20 to 29;

[0102] Figure 47 is a schematic diagram of the insulation filling structure formed in Figures 21 to 29;

[0103] Figure 48 is a schematic diagram of the multiple covering structures formed in Figures 21 to 29;

[0104] Figure 49 is a schematic diagram of the formation of the third insulating layer as shown in Figures 30 to 34;

[0105] Figure 50 is a schematic diagram showing the formation of the first insulating structure, the second insulating structure, and the third insulating structure as shown in Figures 30 to 34;

[0106] Figure 51 is a schematic diagram showing the formation of the first conductive structure, the second conductive structure and the third conductive structure in Figures 30 to 34;

[0107] Figure 52 is a schematic diagram of the insulation filling structure formed in Figures 30 to 34;

[0108] Figure 53 is a schematic diagram of the formation of multiple covering structures as shown in Figures 30 to 34;

[0109] Figure 54 is a schematic diagram of the fourth insulating layer formed in Figure 35;

[0110] Figure 55 is a schematic diagram showing the formation of the first, second, third, and fourth insulating structures in Figure 35.

[0111] Figure 56 is a schematic diagram of the first conductive structure, the second conductive structure, the third conductive structure and the fourth conductive structure formed in Figure 35;

[0112] Figure 57 is a schematic diagram of the insulating filling structure formed in Figure 35;

[0113] Figure 58 is a schematic diagram of the multiple covering structures formed in Figure 35;

[0114] Figure 59 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0115] Detailed Explanation

[0116] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0117] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0118] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0119] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0120] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. "Joining" can include "electrical connection," which includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components. Those skilled in the art will understand the meaning of the above terms in this disclosure as appropriate.

[0121] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0122] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0123] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0124] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0125] In this specification, "approximately" and "roughly" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0126] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0127] The phrase "A and B are of the same layer" in this specification means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B.

[0128] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0129] In embodiments of this disclosure, the thickness of a component refers to the dimension of the component in a direction perpendicular to the substrate.

[0130] The display substrate includes a display area and a hole area. When the isolation pillars in the hole area are energized, they will undergo electrochemical corrosion, and there will be residual adhesive on the isolation pillars. When the display substrate is opened, moisture will enter the display area along the residual adhesive, which can cause black spots to appear on the display substrate and affect the display effect of the display substrate.

[0131] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 1, the shape of the display substrate can be a closed polygon including linear edges. The display substrate may include: a display area AA, a hole area at least partially surrounded by the display area AA, a bonding area BB located on one side of the display area AA, and a border area CC located on at least one side of the display area AA. For example, the display area AA may include: a first display edge (lower display edge) and a second display edge (upper display edge) disposed opposite to each other in a first direction D1, and a third display edge (left display edge) and a fourth display edge (right display edge) disposed opposite to each other in a second direction D2. The first display edge and the second display edge can be mutually parallel linear edges, and the third display edge and the fourth display edge can be mutually parallel linear edges. Adjacent linear edges can be connected by curved edges (e.g., arcuate edges).

[0132] In an exemplary embodiment, the hole region VV can be circular. The hole region VV can also adopt other suitable shapes, not limited to a circle. Furthermore, the location of the hole region VV is not limited to the center of the display area and can be set as needed.

[0133] In an exemplary embodiment, at least a portion of the structure within the hole region VV is removed. For example, all the structure within the hole region VV of the display substrate is removed. For example, after forming the encapsulation layer, a hole-punching process is performed to remove the portion of the display substrate located in the hole region VV.

[0134] In an exemplary embodiment, the display device may further include a sensor, which may be disposed within or entirely within the aperture region VV. Exemplarily, the sensor may include a camera.

[0135] In an exemplary implementation, as shown in FIG1, the binding region BB can be connected to the first display edge.

[0136] In an exemplary embodiment, as shown in FIG1, the bezel region CC may include: the upper bezel region of the display substrate, the left bezel region of the display substrate, and the right bezel region of the display substrate. However, this embodiment is not limited thereto.

[0137] In an exemplary embodiment, as shown in FIG1, the binding area BB may include: a first sub-area B11, a bent area B12, and a second sub-area B13 arranged sequentially along the side away from the display area AA in a first direction D1. The first sub-area B11 may also be referred to as a first fan-out area. The first sub-area B11 may communicate with the left border area and the right border area and be connected to the display area AA. The bent area B12 may connect the first sub-area B11 and the second sub-area B13. The bent area B12 may be configured to bend the second sub-area B13 to the back side of the display area AA.

[0138] In an exemplary embodiment, the second sub-region B13 of the binding region BB may include: a second fan-out region, a circuit setting region, a third fan-out region, a first signal access region B134, and a second signal access region B135, which are sequentially arranged along the direction away from the bending region B12 in the first direction D1.

[0139] In an exemplary embodiment, as shown in FIG1, the display area AA of the display substrate may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the plurality of data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and light emission control signals, or may include scan signals, reset control signals, and light emission control signals.

[0140] In an exemplary embodiment, the second direction D2 may be the extension direction of the grid line GL within the display area AA (e.g., the row direction); the first direction D1 may be the extension direction of the data line within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 may intersect each other, for example, they may be perpendicular to each other.

[0141] In an exemplary embodiment, a pixel unit of the display area AA may include three sub-pixels, which may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and a third sub-pixel emitting a third color light (e.g., green light). However, this embodiment is not limited thereto. In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For example, a pixel unit may include four sub-pixels, which may include one sub-pixel emitting red light, one sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0142] In an exemplary embodiment, a sub-pixel may include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit may include multiple transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In an exemplary embodiment, the multiple transistors in the pixel driving circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel driving circuit may be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield.

[0143] In an exemplary embodiment, the shape of the light-emitting element of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0144] In an exemplary embodiment, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel driving circuit. The color of the light emitted by the light-emitting element can be determined as needed. In an exemplary embodiment, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited in this respect.

[0145] The display substrate in this example can integrate a touch structure, such as an integrated mutual capacitance touch structure, to form an FMLOC structure.

[0146] In an exemplary embodiment, the display substrate may include a substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate. The circuit structure layer includes a pixel driving circuit located in the display area, and the light-emitting structure layer includes a light-emitting element located in the display area.

[0147] In an exemplary embodiment, the display substrate may further include at least one film layer of the encapsulation structure layer and the touch structure layer, without any limitation thereof.

[0148] Figure 2 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 2 illustrates the structure of a sub-pixel of the display area as an example. In this example, the pixel driving circuit includes a low-temperature polysilicon thin-film transistor as an example for description.

[0149] In an exemplary embodiment, as shown in FIG2, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 (which may be called a buffer layer) may be disposed between the substrate and the semiconductor layer; a second insulating layer 102 (which may be called a first gate insulating layer) may be disposed between the semiconductor layer and the first gate metal layer; a third insulating layer 103 (which may be called a second gate insulating layer) may be disposed between the first gate metal layer and the second gate metal layer; a fifth insulating layer 105 (which may be called an interlayer insulating layer) may be disposed between the second gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (which may also be called a passivation layer) and a seventh insulating layer 107 (which may also be called a first planarization layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer, wherein the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (which may also be called a second planarization layer) may be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, while the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. This disclosure uses a display substrate comprising two gate metal layers and two source / drain metal layers as an example for illustration. However, this embodiment is not limited to this. In other examples, a bottom shielding metal layer (BSM) can be disposed on the side of the first insulating layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors in the pixel driving circuit to prevent external light from affecting the performance of the transistors. In other examples, only the sixth or seventh insulating layer can be disposed between the first and second source / drain metal layers.

[0150] In an exemplary embodiment, as shown in FIG2, the semiconductor layer may include at least a first active layer 210 of the transistor 21 located in the display area. The first active layer 210 of the transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate 213 of the transistor 21 located in the display area and a first electrode 231 of the capacitor 23. The orthographic projection of the first gate 213 of the transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 10. The second gate metal layer may include at least a second electrode 232 of the capacitor 23 located in the display area and a third gate 224 of the second type transistor 22. The orthographic projections of the second electrode 232 and the first electrode 231 of the capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide.

[0151] In an exemplary embodiment, as shown in FIG2, the first source-drain metal layer of the display area may include at least a first source 211 and a first drain 212 of the transistor 21 located in the display area. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via and a second pixel via) in the display area. The fifth insulating layer 105, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The first source 211 of the transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source / drain metal layer may include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain 212 of the transistor 21 of the pixel driving circuit through a fifth pixel via formed by the sixth insulating layer 106 and the seventh insulating layer 107. In this example, the first transition electrode 241 can be used to achieve the electrical connection between the pixel driving circuit and the light-emitting element.

[0152] In an exemplary embodiment, the gate lines of the display area may be located, for example, in the first gate metal layer and the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer; and the first power lines of the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect.

[0153] In an exemplary embodiment, as shown in FIG2, the light-emitting structure layer 13 may include a pixel definition layer 134 and a plurality of light-emitting elements located in the display area. For example, each light-emitting element may include a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 stacked thereon. The first electrode 131 of the light-emitting element may be an anode, and the first electrode 131 may be disposed on an eighth insulating layer 108 and electrically connected to a first transition electrode 241 through a sixth pixel via formed in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may have a plurality of pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0154] In an exemplary embodiment, the light-emitting structure layer may include: an anode layer, an organic material layer, and a cathode layer. The anode layer includes: a first electrode of at least one light-emitting element located in the display area. The organic material layer includes: an organic light-emitting layer of at least one light-emitting element located in the display area. The cathode layer includes: a second electrode of at least one light-emitting element located in the display area.

[0155] In an exemplary embodiment, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be utilized to emit light at the required grayscale.

[0156] In exemplary embodiments, the light-emitting layers of light-emitting elements of different colors can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, and the electron injection layer and electron transport layer on the other side of the light-emitting layer can also be common layers. In exemplary embodiments, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In exemplary embodiments, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0157] In an exemplary embodiment, as shown in FIG2, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0158] In an exemplary embodiment, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be disposed in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be disposed in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0159] In an exemplary embodiment, as shown in FIG2, the touch structure layer 15 of the display area may include, in the direction perpendicular to the display substrate, a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a touch protective layer (TOC) 154 sequentially disposed therefrom. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the touch protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer 153. However, this embodiment is not limited in this respect. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In an exemplary embodiment, the first touch electrode may be a driving (Tx) electrode, and the second touch electrode may be a sensing (Rx) electrode. Alternatively, the first touch electrode may be a sensing (Rx) electrode, and the second touch electrode may be a driving (Tx) electrode. This embodiment is not limited in this respect.

[0160] In an exemplary embodiment, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of the following shapes: triangle, square, trapezoid, parallelogram, pentagon, hexagon, and other polygons, which are not limited to the embodiments disclosed herein.

[0161] In an exemplary embodiment, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by interlacing multiple metal wires. The metal mesh can include multiple mesh patterns, and the mesh patterns can be polygons composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0162] Figure 3 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 3, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A fourth insulating layer 104 (which may be referred to as the third gate insulating layer) may be disposed between the second gate metal layer and the third gate metal layer; a fifth insulating layer 105 (which may be referred to as the interlayer insulating layer) may be disposed between the third gate metal layer and the first source / drain metal layer. The fourth insulating layer 104 may be an inorganic insulating layer. This disclosure is illustrated using a display substrate comprising three gate metal layers and two source / drain metal layers as an example. However, this embodiment is not limited thereto. The remaining structure of the display area of ​​the display substrate of this example can be referred to the description of the embodiment shown in Figure 2, and will not be repeated here.

[0163] In an exemplary embodiment, the third gate metal layer may include a third electrode 233 of a capacitor located in the display area. The third electrode 233 is connected to the first electrode 231, and its orthographic projection on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode 232 on the substrate 10, for example, they may coincide.

[0164] In an exemplary embodiment, the gate lines of the display area may be located in at least one of the first gate metal layer, the second gate metal layer, and the third gate metal layer; the data lines of the display area may be located in the second source-drain metal layer; and the first power lines of the display area may be located in the second source-drain metal layer. This embodiment is not limited in this respect.

[0165] Figure 4 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 4, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. An eighth insulating layer 108 (which may also be referred to as a second planarization layer) may be disposed between the second and third source / drain metal layers, and a ninth insulating layer 109 (which may also be referred to as a third planarization layer) may be disposed on the side of the third source / drain metal layer away from the substrate 10. The present disclosure is illustrated using a display substrate comprising two gate metal layers and three source / drain metal layers as an example. In this example, the electrical connection between the pixel driving circuit and the light-emitting element can be achieved through the first transition electrode 241 and the second transition electrode 242. The remaining structure of the display area of ​​the display substrate in this example can be referred to the description of the embodiment shown in Figure 2, and will not be repeated here.

[0166] In an exemplary embodiment, the gate lines of the display area may be located, for example, in the first gate metal layer and the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the first power line of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer. This embodiment is not limited in this respect.

[0167] Figure 5 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 5, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. A fourth insulating layer 104 (which may be referred to as the third gate insulating layer) may be disposed between the second gate metal layer and the third gate metal layer, an eighth insulating layer 108 (which may also be referred to as the second planarization layer) may be disposed between the second source / drain metal layer and the third source / drain metal layer, and a ninth insulating layer 109 (which may also be referred to as the third planarization layer) may be disposed on the side of the third source / drain metal layer away from the substrate 10. The fourth insulating layer 104 may be an inorganic insulating layer, and the ninth insulating layer 109 may be an organic insulating layer. This disclosure is illustrated using a display substrate comprising three gate metal layers and three source / drain metal layers as an example. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 241 and the second transition electrode 242. The remaining structure of the display area of ​​the display substrate in this example can be referred to the description of the embodiments shown in Figures 2 and 3, and will not be repeated here.

[0168] In an exemplary embodiment, the gate lines of the display area may be located in at least one film layer of the first gate metal layer, the second gate metal layer, and the third gate metal layer; the data lines of the display area may be located in the second source-drain metal layer or the third source-drain metal layer; and the first power line of the display area may be located in the second source-drain metal layer or the third source-drain metal layer. This embodiment is not limited in this respect.

[0169] Figure 6 is a schematic diagram of the structure of the display substrate in the hole region according to an embodiment of the present disclosure, and Figure 7 is a schematic diagram of the structure of the display substrate in the hole region according to an embodiment of the present disclosure. As shown in Figures 6 and 7, the display substrate provided in the embodiment of the present disclosure includes: a display area (not shown in the figure) and a hole region. The hole region includes: a first region R1 and a second region R2 arranged sequentially away from the display area. The first region R1 and the second region R2 are provided with a plurality of isolation pillars 300. An insulating filling structure 400 is filled between at least two adjacent isolation pillars 300 in the first region R1 and the second region R2. At least one insulating filling structure 400 at least partially covers the sidewalls of the two adjacent isolation pillars 300 near the insulating filling structure 400.

[0170] As shown in Figures 6 and 7, the thickness H1 of at least one first insulating filler structure 410 is less than the thickness H2 of at least one second insulating filler structure 420. The first insulating filler structure 410 is disposed between adjacent first isolation pillars 310, which are located in the first region R1. The second insulating filler structure 420 is disposed between adjacent second isolation pillars 320, which are located in the second region R2. Figures 6 and 7 illustrate this using the example where the thickness of any at least one first insulating filler structure 410 is less than the thickness of any second insulating filler structure 420.

[0171] In an exemplary embodiment, the light transmittance of at least one second insulating filler structure 420 may be less than the light transmittance of at least one first insulating filler structure 410.

[0172] In an exemplary embodiment, the display substrate includes a substrate 10 covering the display area and the hole area VV.

[0173] In an exemplary embodiment, as shown in Figures 6 and 7, the distance W1 between the surface of at least one insulating fill structure 400 away from the substrate 10 and the substrate 10 is greater than the distance W2 between the surface of at least one insulating post 300 away from the substrate 10 and the substrate 10.

[0174] This disclosure, by setting the thickness H1 of at least one first insulating fill structure 410 to be less than the thickness H2 of at least one second insulating fill structure 420, not only can the power be cut off in the frame area, but also the residual adhesive in the first isolation pillar can be removed through the thinner first insulating fill structure, which can effectively solve the black spot problem of the display substrate and improve the display effect of the display substrate.

[0175] In an exemplary embodiment, as shown in Figures 6 and 7, the display substrate further includes a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate. The border region includes a composite insulating layer 20, with at least a portion of at least one isolation pillar located on the side of the composite insulating layer 20 away from the substrate.

[0176] In an exemplary embodiment, the thickness H1 of the first insulating fill structure 410 can be from 0.8 micrometers to 2.1 micrometers.

[0177] In an exemplary embodiment, the thickness H2 of the second insulating fill structure 420 can be 2.3 micrometers to 3 micrometers.

[0178] In an exemplary embodiment, the ratio of the thickness H2 of the second insulating fill structure 420 to the thickness H1 of the first insulating fill structure 410 can be between 1.05 and 3.85.

[0179] In this disclosure, the thickness of the structure refers to the vertical distance between the highest point of the surface of the structure away from the substrate and the surface of the composite insulating layer 20 on the substrate away from the substrate.

[0180] In an exemplary embodiment, as shown in Figures 6 and 7, the border area further includes a third region R3 and a fourth region R4, wherein the third region R3 is located between the first region R1 and the second region R2, and the fourth region R4 is located on the side of the second region away from the display area.

[0181] In an exemplary embodiment, the third region R3 may be provided with at least one isolation dam 510.

[0182] In an exemplary embodiment, as shown in FIG6, the fourth region R4 may be provided with at least one third isolation post 330, or as shown in FIG7, the fourth region R4 may be provided with a cutting groove V.

[0183] In an exemplary embodiment, the fourth region R4 can be referred to as the cutting region, where the display substrate is cut. In this exemplary embodiment, the presence of a third isolation pillar or cutting groove in the fourth region R4 can reduce the likelihood of cracks during the cutting of the AAH holes, thereby improving the reliability of the display substrate.

[0184] In an exemplary embodiment, the distance W3 between the surface of the isolation dam 510 away from the substrate 10 and the substrate 10 is greater than the distance W2 between the surface of at least one of the isolation pillars 310, 320 and 330 away from the substrate 10 and the substrate.

[0185] In an exemplary embodiment, the second insulating fill structure may include a second sub-fill structure, or may include a first sub-fill structure and a second sub-fill structure, wherein the thickness of the first sub-fill structure is different from the thickness of the second sub-fill structure.

[0186] In an exemplary embodiment, FIG8 is a schematic diagram of the structure of the hole region of a display substrate provided in an exemplary embodiment. As shown in FIG8, when the second insulating filling structure 420 includes a first sub-filling structure 421 and a second sub-filling structure 422, the first sub-filling structure 421 is located on the side of the second sub-filling structure 422 closer to the display area.

[0187] In an exemplary embodiment, as shown in FIG8, the thickness H21 of the first sub-filling structure 421 is less than the thickness H22 of the second sub-filling structure 422. The thickness of the filling structure refers to the vertical distance between the highest point of the surface of the filling structure away from the substrate and the surface of the composite insulating layer 20 on the substrate away from the substrate.

[0188] In an exemplary embodiment, the transmittance of the first sub-filling structure 421 may be greater than the transmittance of the second sub-filling structure 422.

[0189] In an exemplary embodiment, as shown in FIG8, the thickness H1 of the first insulating filler structure 410 is less than the thickness H22 of the second sub-filler structure 422. The thickness of the first insulating filler structure 410 may be greater than, equal to, or less than the thickness H21 of the first sub-filler structure 421, and this disclosure does not limit it in any way.

[0190] Figure 9 is a schematic diagram of the film layer in the hole region of a display substrate according to an exemplary embodiment (first), Figure 10 is a schematic diagram of the film layer in the hole region of a display substrate according to an exemplary embodiment (second), Figure 11 is a schematic diagram of the film layer in the hole region of a display substrate according to an exemplary embodiment (third), Figure 12 is a schematic diagram of the film layer in the hole region of a display substrate according to an exemplary embodiment (fourth), and Figure 13 is a schematic diagram of the film layer in the hole region of a display substrate according to an exemplary embodiment (fifth). Figures 9, 10, and 12 are illustrated with the example of a circuit structure layer including three gate metal layers, while Figures 11 and 13 are illustrated with the example of a circuit structure layer including two gate metal layers. Figures 9 to 11 are illustrated with the example of all insulating filling structures in the second region R2 having the same thickness. Figures 12 and 13 are illustrated with the example of insulating filling structures in the second region R2 including a first sub-filling structure 421 and a second sub-filling structure 422 with different thicknesses.

[0191] In an exemplary embodiment, the display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate.

[0192] In an exemplary embodiment, as shown in Figures 9 to 13, the circuit structure layer includes M source-drain metal layers, wherein the (m+1)th source-drain metal layer is located on the side of the m-th source-drain metal layer away from the substrate 10, where M ≥ 2 and 1 ≤ m ≤ M-1. Exemplarily, the circuit structure layer may include a first source-drain metal layer and a second source-drain metal layer, or it may include a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer; this disclosure does not limit the scope of the embodiment.

[0193] In an exemplary embodiment, as shown in Figures 9 to 13, at least one of the plurality of isolation pillars located in the first region and the second region includes: a first isolation structure 301, wherein the first isolation structure 301 of the plurality of isolation pillars located in the first region and the second region is located in one of the metal layers of the Mth source / drain metal layers.

[0194] In an exemplary embodiment, as shown in Figures 9 to 13, the circuit structure layer further includes K gate metal layers sequentially stacked on the substrate 10, wherein the Kth gate metal layer is located on the side of the first source / drain metal layer closest to the substrate 10. Exemplarily, the circuit structure layer may include a first gate metal layer and a second gate metal layer, or it may include a first gate metal layer, a second gate metal layer, and a third gate metal layer.

[0195] In an exemplary embodiment, at least one of the first isolation pillar 310, the second isolation pillar 320, and the third isolation pillar further includes at least one of the second isolation structure to the (K+1)th isolation structure; the orthographic projection of at least one of the second isolation structure to the (K+1)th isolation structure on the substrate overlaps with the orthographic projection of the first isolation structure, wherein the (K+1)th isolation structure is located in the kth gate metal layer, and 1≤k≤K.

[0196] In an exemplary embodiment, as shown in Figures 9 to 13, the first isolation structure 301 of at least one of the first isolation pillar 310, the second isolation pillar 320 and the third isolation pillar includes: a first isolation portion 3011, a second isolation portion 3012 and a third isolation portion 3013, wherein the first isolation portion 3011 is located on the side of the second isolation portion 3012 close to the substrate 10, and the third isolation portion 3013 is located on the side of the second isolation portion 3012 away from the substrate 10.

[0197] In an exemplary embodiment, as shown in Figures 9 to 13, the orthographic projection of the surface of the second isolation portion 3012 near the substrate 10 onto the substrate 10 is within the range of the orthographic projection of the surface of the first isolation portion 3011 away from the substrate 10 onto the substrate 10. The orthographic projection of the surface of the second isolation portion 3012 away from the substrate 10 onto the substrate 10 is within the range of the orthographic projection of the surface of the third isolation portion 3013 near the substrate 10 onto the substrate 10. The orthographic projection of the surface of the second isolation portion 3012 away from the substrate 10 onto the substrate 10 is within the range of the orthographic projection of the surface of the second isolation portion 3012 near the substrate 10 onto the substrate 10. Furthermore, the sidewall of the second isolation portion 3012 is set at an acute angle to the surface of the second isolation portion 3012 near the substrate 10. Exemplarily, the longitudinal section of the second isolation portion 3012 can be trapezoidal, and the longitudinal section of the first isolation structure 301 can be I-shaped.

[0198] In an exemplary embodiment, the conductivity of the second isolation portion 3012 is greater than that of at least one of the first isolation portion 3011 and the third isolation portion 3013. In an exemplary embodiment, the material of the second isolation portion 3012 may be aluminum (Al) or copper (Cu), and the materials of the first isolation portion 3011 and the third isolation portion 3013 may be inert metals, such as titanium (Ti) or molybdenum (Mo).

[0199] In an exemplary embodiment, as shown in FIG13, the length L1 of the third isolation portion of at least one first isolation post 310 is in the range of 4 micrometers to 5.5 micrometers.

[0200] In an exemplary embodiment, as shown in FIG13, the length L2 of the third isolation portion of at least one second isolation post 320 is in the range of 4 micrometers to 5.5 micrometers.

[0201] In an exemplary embodiment, as shown in FIG13, the first insulating filling structure 410 and the third isolation portion of the first isolation post 310 overlap on the substrate in their orthogonal projections, and the second insulating filling structure 420 and the third isolation portion of the second isolation post 320 overlap on the substrate in their orthogonal projections.

[0202] In an exemplary embodiment, as shown in FIG13, the portion of the third isolation part of at least one isolation post covered by the first insulating fill structure 410 or the first sub-insulating structure 421 is the first sub-isolation part, and the length L3 of the first sub-isolation part is in the range of 0.2 micrometers to 2.4 micrometers.

[0203] In an exemplary embodiment, as shown in FIG13, the third isolation portion of the second isolation pillar 320 includes a second sub-isolation portion, the orthographic projection of the second sub-isolation portion on the substrate being covered by the orthographic projection of the second sub-filling structure 421 on the substrate, and the length L4 of the second sub-isolation portion being in the range of 0.4 micrometers to 4.1 micrometers.

[0204] In an exemplary embodiment, as shown in FIG13, the ratio of the length L3 of the first sub-isolation section to the length L1 of the third isolation section is in the range of 0.2 to 0.35.

[0205] In an exemplary embodiment, as shown in FIG13, the ratio of the length L4 of the second sub-isolation section to the length L2 of the third isolation section is in the range of 0.4 to 0.55.

[0206] In an exemplary embodiment, as shown in FIG13, the ratio of the distance L5 between the highest point of the surface of the first insulating fill structure 410 and the first sub-fill structure 421 away from the substrate and the surface of the target conductive structure away from the substrate, and the distance L6 between the highest point of the surface of the isolation pillar 300 covered by the first insulating fill structure 410 and the first sub-fill structure 421 away from the substrate and the surface of the target conductive structure away from the substrate, is in the range of 0.55 to 0.8. The target conductive structure is the conductive structure with the greatest distance from the substrate among at least one conductive structure located in the gate metal layer.

[0207] In an exemplary embodiment, as shown in FIG13, the ratio between the distance L7 between the highest point of the surface of the second sub-filling structure 422 away from the substrate and the surface of the target conductive structure away from the substrate, and the distance L8 between the highest point of the surface of the first isolation pillar 320 away from the substrate and the surface of the target conductive structure away from the substrate, is in the range of 0.35 to 0.5. The target conductive structure is the conductive structure furthest from the substrate among at least one conductive structure located in the gate metal layer.

[0208] In an exemplary embodiment, as shown in FIG13, the angle A1 between the surfaces of the first insulating filling structure 410 and the first sub-filling structure 421 away from the substrate 10 and the surface of the first isolation pillar 310 away from the substrate is in the range of 8 degrees to 37 degrees.

[0209] In an exemplary embodiment, as shown in FIG13, the angle A2 between the surface of the second sub-filling structure 422 away from the substrate 10 and the surface of the second isolation pillar 320 away from the substrate 10 is in the range of 30 degrees to 60 degrees.

[0210] In an exemplary embodiment, the circuit structure layer further includes N planarization layers sequentially stacked on the substrate 10, wherein the (n+1)th planarization layer is located on the side of the nth planarization layer away from the substrate 10, 1≤N≤M, 1≤n≤N-1. Exemplarily, the circuit structure layer may include a first planarization layer, or may include a first planarization layer and a second planarization layer, or may include a first planarization layer, a second planarization layer, and a third planarization layer. The number of planarization layers depends on the number of source / drain metal layers. The first planarization layer may be the seventh insulating layer in Figures 2 to 5, the second planarization layer may be the eighth insulating layer in Figures 2 to 5, and the third planarization layer may be the ninth insulating layer in Figures 3 and 5. This disclosure does not limit the scope of the invention in any way.

[0211] In an exemplary embodiment, the first insulating fill structure 410 is located in the Nth planarization layer or pixel definition layer. The fact that the first insulating fill structure 410 is located in the Nth planarization layer or pixel definition layer in this disclosure allows for a lower thickness of the first insulating fill structure 410, thereby making subsequent residual adhesive removal easier.

[0212] In an exemplary embodiment, when the insulating fill structure located in the second region R2 includes a first sub-fill structure 421 and a second sub-fill structure 422, the first sub-fill structure 421 is located in the Nth planarization layer or pixel definition layer. In this disclosure, the first sub-fill structure 421 being located in the Nth planarization layer or pixel definition layer allows for a lower thickness of the first insulating fill structure 410, thereby making subsequent residual adhesive removal easier.

[0213] In an exemplary embodiment, the first sub-fill structure 421 may be located in the Nth planar layer, and the first insulating fill structure 410 may be located in the Nth planar layer; or, the first sub-fill structure 421 may be located in the Nth planar layer, and the first insulating fill structure 410 may be located in the pixel definition layer; or, the first sub-fill structure 421 may be located in the pixel definition layer, and the first insulating fill structure 410 may be located in the Nth planar layer; or, the first sub-fill structure 421 may be located in the pixel definition layer, and the first insulating fill structure 410 may be located in the pixel definition layer. This disclosure does not impose any limitations on these embodiments.

[0214] In an exemplary embodiment, the light-emitting structure layer further includes: a spacer disposed on the pixel definition layer; and a second sub-filling structure 422 disposed on the same layer as the spacer.

[0215] In an exemplary embodiment, the border region includes a composite insulating layer 20, which includes a plurality of inorganic insulating layers located on the side of the Mth source / drain metal layer near the substrate 10. The inorganic insulating layers extend from the display region to the fourth region R4. In the display substrates provided in Figures 9, 10, and 12, the inorganic insulating layer includes a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, and a sixth insulating layer 106. In the display substrates provided in Figures 11 and 13, the composite insulating layer includes a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fifth insulating layer 105, and a sixth insulating layer 106.

[0216] In an exemplary embodiment, as shown in Figures 9, 11 to 13, the cutting groove V is disposed within the composite insulating layer 20.

[0217] In an exemplary embodiment, as shown in Figures 9 to 13, the organic light-emitting layer and the cathode layer extend from the display area to the second area R2. The organic light-emitting layer and the cathode layer located in the first border area R1 or the second border area R2 are separated by at least one isolation pillar located in the first border area R1 or the second border area R2. The organic light-emitting layer located in the first area R1 or the second area R2 includes: a first organic structure 611 and a second organic structure 621 disposed at intervals. The cathode layer located in the first area R1 or the second area R2 includes: a first cathode structure 612 and a second cathode structure 622 disposed at intervals, wherein the first cathode structure 612 corresponds one-to-one with the first organic structure 611, and the second cathode structure 622 corresponds one-to-one with the second organic structure 621.

[0218] In an exemplary embodiment, the orthographic projection of the first cathode structure 612 on the substrate 10 may at least partially overlap with the orthographic projection of the second cathode structure 622 on the substrate 10, and the orthographic projection of the first organic structure 611 on the substrate 10 may at least partially overlap with the orthographic projection of the second organic structure 621 on the substrate 10.

[0219] In an exemplary embodiment, a first organic structure 611 is disposed between at least a portion of adjacent isolation pillars 300 and at least partially covers at least a portion of the sidewall of the second isolation portion 3012 of the adjacent isolation pillars 300. A second organic structure 621 is disposed on the surface of at least one isolation pillar 300 away from the substrate 10. A first cathode structure 612 is disposed between at least a portion of adjacent isolation pillars 300 and at least partially covers the sidewall of the second isolation portion 3012 of the adjacent isolation pillars. A second cathode structure 622 is disposed on the side of the second organic structure 621 away from the substrate 10. The maximum distance between the surface of at least one second organic structure 621 away from the substrate 10 and the substrate 10 is greater than the maximum distance between the surface of the first cathode structure 612 away from the substrate 10 and the substrate 10.

[0220] In an exemplary embodiment, the orthographic projection of the first organic structure 611 on the substrate 10 is within the range of the orthographic projection of the corresponding first cathode structure 612 on the substrate 10, and the orthographic projection of the second cathode structure 622 on the substrate 10 is within the range of the orthographic projection of the corresponding second organic structure 621 on the substrate 10.

[0221] In an exemplary embodiment, as shown in Figures 9 to 13, the second organic structure 621 disposed on the two isolation pillars between which the insulating filling structure 400 is filled is interconnected, and its orthogonal projection on the substrate 10 covers the orthogonal projection of the insulating filling structure 400 on the substrate 10. The second cathode structure 622 disposed on the two isolation pillars between which the insulating filling structure 400 is filled is interconnected, and its orthogonal projection on the substrate 10 covers the orthogonal projection of the insulating filling structure 400 on the substrate 10.

[0222] In an exemplary embodiment, as shown in Figures 9 to 13, the organic light-emitting layer 631 located in the third region R3 extends to a portion of the sidewall of the second isolation portion of the first isolation pillar 310 furthest from the display area AA and a portion of the sidewall of the second isolation portion of the second isolation pillar 320 closest to the display area AA. The orthographic projection of the cathode layer 632 located in the third region R3 onto the substrate 10 covers the orthographic projection of the isolation dam 510 onto the substrate 10, and also covers the orthographic projection of the organic light-emitting layer located in the third region R3 onto the substrate 10. In an exemplary embodiment, the second isolation portions of multiple isolation pillars on the side of the second insulating filling structure in the second region away from the display area are electrically connected to multiple second cathode structures. The second isolation portions of multiple isolation pillars on the side of the second insulating filling structure in the second region close to the display area, the cathode layer in the third region, and the second isolation portions of multiple isolation pillars on the side of the first insulating filling structure in the first region away from the display area are electrically connected to each other. The second isolation portions of multiple isolation pillars on the side of the first insulating filling structure in the first region close to the display area are electrically connected to multiple first cathode structures. The insulating filling structure cuts off the electrical connection between the first region and the second region, achieving power disconnection in the frame area.

[0223] In an exemplary embodiment, as shown in Figures 9 to 13, at least one isolation dam 510 includes: a plurality of dam bases stacked sequentially along a direction away from the substrate 10, at least one dam base being located in at least one flat layer, and at least one dam base being located in a pixel definition layer.

[0224] Figures 9 to 13 illustrate the isolation dam 510, which includes three dam bases 511 to 513. Dam base 513 can be located in the pixel definition layer, dam base 511 can be located in one of the flat layers, and dam base 512 can be located in another flat layer. This disclosure does not impose any limitations on this.

[0225] Figure 14 is a partial structural schematic diagram of the first and second regions provided in an embodiment of this disclosure. Figure 14 only shows two isolation pillars with an insulating filling structure disposed between them. As shown in Figure 14, the isolation pillar 300 is disposed on the side of the composite insulating layer 20 away from the substrate 10. At least one isolation pillar 300 includes: L conductive structures 31 and L insulating structures 32 stacked together, with the L conductive structures 31 and L insulating structures 32 alternately disposed. The l-th insulating structure 32 is located on the side of the l-th conductive structure 31 away from the substrate 10, and L is a positive integer greater than or equal to 1.

[0226] In an exemplary embodiment, at least one of the conductive structures has a groove-shaped sidewall with a smooth curve at its edge. Exemplarily, the longitudinal section of at least one conductive structure may be I-shaped.

[0227] In an exemplary embodiment, when L is greater than or equal to 2, the orthographic projection of the surface of the l-th conductive structure near the substrate onto the substrate is within the range of the orthographic projection of the surface of the (l-1)-th insulating structure away from the substrate onto the substrate, and the maximum distance between the sidewall of the l-th conductive structure and the centerline of the isolation column is less than the minimum distance between the sidewall of the (l-1)-th insulating structure and the centerline of the isolation column. The insulating structure 32 disposed on the side of the conductive structure 31 near the substrate 10 can be in the form of an eaves structure.

[0228] In an exemplary embodiment, the longitudinal cross-section of the insulating structure 32 can be trapezoidal.

[0229] In the following figures, A(B) refers to structure A located in membrane layer B.

[0230] In an exemplary embodiment, the display substrate includes a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes K gate metal layers and M source / drain metal layers disposed on the substrate. The (k+1)th gate metal layer is located on the side of the kth gate metal layer away from the substrate, the kth gate metal layer is located on the side of the first source / drain metal layer close to the substrate, and the (m+1)th source / drain metal layer is located on the side of the mth source / drain metal layer away from the substrate, where K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, 1 ≤ m ≤ M-1. The circuit structure layer further includes a plurality of inorganic insulating layers and a plurality of organic insulating layers. At least one insulating layer is disposed between adjacent gate metal layers, between adjacent source / drain metal layers, and between the kth gate metal layer and the first source / drain metal layer.

[0231] In an exemplary embodiment, the isolation pillar includes a first conductive structure and a first insulating structure, wherein the first conductive structure is located in one of the K gate metal layers and M source / drain metal layers, and the first insulating structure is located in one of the plurality of inorganic insulating layers.

[0232] In an exemplary embodiment, the isolation pillar includes: a first conductive structure, a first insulating structure, a second conductive structure, and a second insulating structure. At least one of the first conductive structure and the second conductive structure is located in two of the K gate metal layers and M source / drain metal layers, and the first conductive structure and the second conductive structure are located in different layers; the first insulating structure and the second insulating structure are located in two of the multilayer inorganic insulating layers, and the first insulating structure and the second insulating structure are located in different layers.

[0233] In an exemplary embodiment, the isolation pillar includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, and a third insulating structure. The first conductive structure, the second conductive structure, and the third conductive structure are located in three of the K gate metal layers and M source / drain metal layers, and are situated in different layers. Similarly, the first insulating structure, the second insulating structure, and the third insulating structure are located in three of the multiple inorganic insulating layers, and are situated in different layers.

[0234] Figure 15 is a schematic diagram of the film layer shown in Figure 14. Figure 15 illustrates the example of the isolation pillars including a first conductive structure 311 and a first insulating structure 312. As shown in Figure 15, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. Alternatively, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 may be located in the first gate metal layer, the first insulating structure 312 may be located in the third insulating layer 103, and the composite insulating layer 20 may include a first insulating layer 101 and a second insulating layer 102.

[0235] Figure 16 is a second schematic diagram of the film layer provided in Figure 14. Figure 16 is illustrated using the example of the isolation pillars including a first conductive structure 311 and a first insulating structure 312. As shown in Figure 16, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located on the second gate metal layer, the first insulating structure 312 is located on the fifth insulating layer 105, and the composite insulating layer includes the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103.

[0236] Figure 17 is a schematic diagram of the film layer shown in Figure 14. Figure 16 illustrates the case where the isolation pillar includes a first conductive structure 311 and a first insulating structure 312. As shown in Figure 16, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 can be located in the second gate metal layer, the first insulating structure 312 can be located in the fourth insulating layer 104, and the composite insulating layer can include the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103.

[0237] Figure 18 is a schematic diagram of the film layer shown in Figure 14. Figure 18 illustrates the case where the isolation pillar includes a first conductive structure 311 and a first insulating structure 312. As shown in Figure 18, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 can be located in the first source / drain metal layer, the first insulating structure 312 can be located in the sixth insulating layer 106, and the composite insulating layer 20 can include the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fifth insulating layer 105.

[0238] Figure 19 is a schematic diagram of the film layer provided in Figure 14. Figure 19 illustrates the case where the isolation pillar includes a first conductive structure 311 and a first insulating structure 312. As shown in Figure 19, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 can be located in the first source / drain metal layer, the first insulating structure 312 can be located in the sixth insulating layer 106, and the composite insulating layer 20 can include the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105.

[0239] Figure 20 is a schematic diagram of the film layer provided in Figure 14. Figure 20 is illustrated using the example of an isolation pillar including a first conductive structure 311 and a first insulating structure 312. As shown in Figure 20, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 may be located in the third gate metal layer, the first insulating structure 312 may be located in the fifth insulating layer 105, and the composite insulating layer 20 may include the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104.

[0240] In an exemplary embodiment, as shown in Figures 15 to 20, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10.

[0241] In an exemplary embodiment, as shown in Figures 15 to 20, the display substrate further includes a first cover structure 611 and a second cover structure 612 disposed at intervals. The first cover structure 611 is disposed on the side of the composite insulating layer 20 away from the substrate 10 and is in direct contact with the composite insulating layer 20. The second cover structure is disposed on the side of the isolation pillar 300 away from the substrate 10. The second cover structures disposed on the two isolation pillars 300 between which an insulating filling structure 400 is filled are interconnected, and their orthogonal projection on the substrate 10 covers the orthogonal projection of the insulating filling structure 400 on the substrate 10.

[0242] Figure 21 is a schematic diagram of the film layer shown in Figure 14. Figure 21 illustrates the example of an isolation pillar comprising a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 21, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 can be located in the first gate metal layer, the first insulating structure 312 can be located in the third insulating layer 103, the second conductive structure 313 can be located in the second gate metal layer, and the second insulating structure 314 can be located in the fifth insulating layer 105. The composite insulating layer includes the first insulating layer 101 and the second insulating layer 102.

[0243] Figure 22 is a schematic diagram of the film layer provided in Figure 14. Figure 22 is illustrated using the example of an isolation pillar comprising a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 22, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 includes a first sub-insulating structure 3121 and a second sub-insulating structure 3122, the first sub-insulating structure 3121 is located in the third insulating layer 103, the second sub-insulating structure 3122 is located in the fifth insulating layer 105, the second conductive structure 313 is located in the first source / drain metal layer, the second insulating structure 314 is located in the sixth insulating layer 106, and the composite insulating layer includes a first insulating layer 101 and a second insulating layer 102.

[0244] Figure 23 is a schematic diagram of the film layer provided in Figure 14. Figure 23 is illustrated using the example of an isolation pillar comprising a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 23, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located in the second gate metal layer, the first insulating structure 312 is located in the fifth insulating layer 105, the second conductive structure 313 is located in the first source / drain metal layer, and the second insulating structure 314 is located in the sixth insulating layer 106. The composite insulating layer includes the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103.

[0245] Figure 24 is a schematic diagram of the film layer provided in Figure 14. Figure 24 is illustrated using the example of an isolation pillar including a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 24, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, and the second insulating structure 314 is located in the fourth insulating layer 104. The composite insulating layer includes a first insulating layer 101 and a second insulating layer 102.

[0246] Figure 25 is a schematic diagram of the membrane layer provided in Figure 14. Figure 25 is illustrated using the example of an isolation column including: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 25, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. The first conductive structure 311 is located on the first gate metal layer, and the first insulating structure 312 includes a first sub-insulating structure 3121 and a second sub-insulating structure 3122. The first sub-insulating structure 3121 is located on the third insulating layer 103, the second sub-insulating structure 3122 is located on the fourth insulating layer 104, the second conductive structure 313 is located on the third gate metal layer, and the second insulating structure 314 is located on the fifth insulating layer 105. The composite insulating layer includes the first insulating layer 101 and the second insulating layer 102.

[0247] Figure 26 is a schematic diagram of the membrane layer provided in Figure 14. Figure 26 is illustrated using the example of an isolation column including: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 26, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. The first conductive structure 311 is located on the first gate metal layer. The first insulating structure 312 includes a first sub-insulating structure 3121, a second sub-insulating structure 3122, and a third sub-insulating structure 3123. The first sub-insulating structure 3121 is located on the third insulating layer 103, the second sub-insulating structure 3122 is located on the fourth insulating layer 104, and the third sub-insulating structure 3123 is located on the fifth insulating layer 105. The second conductive structure 313 is located on the first source / drain metal layer, and the second insulating structure 314 is located on the sixth insulating layer 106. The composite insulating layer includes a first insulating layer 101 and a second insulating layer 102.

[0248] Figure 27 is a schematic diagram of the film layer provided in Figure 14. Figure 27 illustrates the example of an isolation pillar including a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 27, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located in the second gate metal layer, the first insulating structure 312 is located in the fourth insulating layer 104, the second conductive structure 313 is located in the third gate metal layer, and the second insulating structure 314 is located in the fifth insulating layer 105. The composite insulating layer includes the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103.

[0249] Figure 28 is a schematic diagram of the film layer provided in Figure 14. Figure 28 is illustrated using the example of an isolation pillar comprising a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 28, when the display substrate comprises a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located on the second gate metal layer, the first insulating structure 312 comprises a first sub-insulating structure and a second sub-insulating structure, the first sub-insulating structure is located on the fourth insulating layer 104, the second sub-insulating structure is located on the fifth insulating layer 105, the second conductive structure 313 is located on the first source / drain metal layer, the second insulating structure 314 is located on the sixth insulating layer 106, and the composite insulating layer comprises a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103.

[0250] Figure 29 is a schematic diagram of the film layer provided in Figure 14. Figure 29 illustrates the example of an isolation pillar comprising a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, and a second insulating structure 314. As shown in Figure 29, when the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located in the third gate metal layer, the first insulating structure 312 is located in the fifth insulating layer 105, the second conductive structure 313 is located in the first source / drain metal layer, and the second insulating structure 314 is located in the sixth insulating layer 106. The composite insulating layer includes the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104.

[0251] In an exemplary embodiment, as shown in Figures 21 to 29, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10, the orthographic projection of the first insulating structure 312 on the substrate 10 covers the orthographic projection of the second conductive structure 313 on the substrate 10, and the orthographic projection of the second conductive structure 313 on the substrate 10 covers the orthographic projection of the second insulating structure 314 on the substrate 10.

[0252] In an exemplary embodiment, the surface of the first insulating structure 312 away from the substrate 10 includes a first surface, a second surface, and a third surface. The first surface and the third surface are located on opposite sides of the second surface. The orthographic projection of the second surface onto the substrate 10 coincides with the orthographic projection of the second conductive structure 313 onto the substrate 10. For two isolation pillars filled with an insulating filling structure, the first surface is located on the side of the second surface away from the insulating filling structure, and the third surface is located on the side of the second surface close to the insulating filling structure. That is, the second surface is the covered surface of the first insulating structure 312 away from the substrate 10, and the first surface and the third surface are the uncovered surfaces of the first insulating structure 312 away from the substrate 10.

[0253] In an exemplary embodiment, as shown in Figures 21 to 29, the display substrate further includes a first cover structure 621, a second cover structure 622, and a third cover structure 623 disposed at intervals. The first cover structure 621 is disposed on the side of the composite insulating layer 20 away from the substrate 10 and is in direct contact with the composite insulating layer 20.

[0254] In an exemplary embodiment, as shown in Figures 21 to 29, the second covering structure 622 is disposed on the side of the isolation column 300 away from the substrate 10. The second covering structure 622 disposed on the two isolation columns 300 between which the insulating filling structure 400 is filled is interconnected, and the orthogonal projection on the substrate 10 covers the orthogonal projection of the insulating filling structure 400 on the substrate 10.

[0255] In an exemplary embodiment, as shown in Figures 21 to 29, the third covering structure 623 is disposed on the first surface of the first insulating structure 312 between the two insulating pillars 300 filled with the insulating filling structure 400, and on the side of the first and third surfaces of the first insulating structure 312 between the two insulating pillars 300 without the insulating filling structure 400 disposed away from the substrate 10.

[0256] Figure 30 is a schematic diagram of the film layer provided in Figure 14. Figure 30 is illustrated using the example of an isolation pillar comprising: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315, and a third insulating structure 316. As shown in Figure 30, when the display substrate includes: a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10, the first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fifth insulating layer 105, the third conductive structure 315 is located in the first source / drain metal layer, and the third insulating structure 316 is located in the sixth insulating layer 106. The composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0257] Figure 31 is a schematic diagram of the membrane layer provided in Figure 14. Figure 31 is illustrated using the example of an isolation column including: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315, and a third insulating structure 316. As shown in Figure 31, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. When the first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fourth insulating layer 104, the third conductive structure 315 is located in the third gate metal layer, and the third insulating structure 316 is located in the fifth insulating layer 105, the composite insulating layer includes the first insulating layer 101 and the second insulating layer 102.

[0258] Figure 32 is a schematic diagram of the membrane layer provided in Figure 14. Figure 32 is illustrated using the example of the isolation pillar including: first conductive structure 311, first insulating structure 312, second conductive structure 313, second insulating structure 314, third conductive structure 315 and third insulating structure 316. As shown in Figure 32, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. When the first conductive structure 311 is located on the first gate metal layer, the first insulating structure 312 is located on the third insulating layer 103, the second conductive structure 313 is located on the second gate metal layer, the second insulating structure 314 includes a first sub-insulating structure 3141 and a second sub-insulating structure 3142, the first sub-insulating structure is located on the fourth insulating layer 104, the second sub-insulating structure is located on the fifth insulating layer 105, the third conductive structure 315 is located on the first source / drain metal layer, and the third insulating structure 316 is located on the sixth insulating layer 106, the composite insulating layer includes the first insulating layer 101 and the second insulating layer 102.

[0259] Figure 33 is a schematic diagram of the membrane layer provided in Figure 14. Figure 33 is illustrated using the example of an isolation column including: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315, and a third insulating structure 316. As shown in Figure 33, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. The first conductive structure 311 is located on the first gate metal layer. The first insulating structure 312 includes a first sub-insulating structure 3121 and a second sub-insulating structure 3122. The first sub-insulating structure 3121 is located on the third insulating layer 103, the second sub-insulating structure 3122 is located on the fourth insulating layer 104, the second conductive structure 313 is located on the third gate metal layer, the second insulating structure 314 is located on the fifth insulating layer 105, the third conductive structure 315 is located on the first source / drain metal layer, and the third insulating structure 316 is located on the sixth insulating layer 106. The composite insulating layer includes the first insulating layer 101 and the second insulating layer 102.

[0260] Figure 34 is a schematic diagram of the membrane layer provided in Figure 14. Figure 34 is illustrated using the example of an isolation column including: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315, and a third insulating structure 316. As shown in Figure 34, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. When the first conductive structure 311 is located on the second gate metal layer, the first insulating structure 312 is located on the fourth insulating layer 104, the second conductive structure 313 is located on the third gate metal layer, the second insulating structure 314 is located on the fifth insulating layer 105, the third conductive structure 315 is located on the first source / drain metal layer, and the third insulating structure 316 is located on the sixth insulating layer 106, the composite insulating layer includes the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103.

[0261] In an exemplary embodiment, as shown in Figures 30 to 34, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10, the orthographic projection of the first insulating structure 312 on the substrate 10 covers the orthographic projection of the second conductive structure 313 on the substrate 10, the orthographic projection of the second conductive structure 313 on the substrate 10 covers the orthographic projection of the second insulating structure 314 on the substrate 10, the orthographic projection of the second insulating structure 314 on the substrate 10 covers the orthographic projection of the third conductive structure 315 on the substrate 10, and the orthographic projection of the third conductive structure 315 on the substrate 10 covers the orthographic projection of the third insulating structure 316 on the substrate 10.

[0262] In an exemplary embodiment, the surface of the first insulating structure 312 away from the substrate 10 includes a first surface, a second surface, and a third surface. The first surface and the third surface are located on opposite sides of the second surface. The orthographic projection of the second surface onto the substrate 10 coincides with the orthographic projection of the second conductive structure 313 onto the substrate 10. For two isolation pillars filled with an insulating filling structure, the first surface is located on the side of the second surface away from the insulating filling structure, and the third surface is located on the side of the second surface close to the insulating filling structure. That is, the second surface is the surface of the first insulating structure 312 that is covered away from the substrate 10, and the first surface and the third surface are the surfaces of the first insulating structure 312 that are not covered away from the substrate 10.

[0263] In an exemplary embodiment, the surface of the second insulating structure 314 away from the substrate 10 includes a fourth surface, a fifth surface, and a sixth surface. The fourth surface and the sixth surface are located on opposite sides of the fifth surface. The orthographic projection of the fifth surface onto the substrate 10 coincides with the orthographic projection of the third conductive structure 315 onto the substrate 10. For the two isolation pillars filled with an insulating filling structure, the fourth surface is located on the side of the fifth surface away from the insulating filling structure, and the sixth surface is located on the side of the fifth surface close to the insulating filling structure. That is, the fourth surface is the surface of the second insulating structure 314 that is covered away from the substrate 10, and the fifth and sixth surfaces are the surfaces of the second insulating structure 314 that are not covered away from the substrate 10.

[0264] In an exemplary embodiment, as shown in Figures 30 to 34, the display substrate further includes a first cover structure 631, a second cover structure 632, a third cover structure 633, and a fourth cover structure 634 disposed at intervals.

[0265] In an exemplary embodiment, as shown in Figures 30 to 34, the first covering structure 631 is disposed on the side of the composite insulating layer 20 away from the substrate 10 and is in direct contact with the composite insulating layer 20.

[0266] In an exemplary embodiment, as shown in Figures 30 to 34, the second covering structure 632 is disposed on the side of the isolation column 300 away from the substrate 10. The second covering structure 632 disposed on the two isolation columns 300 between which the insulating filling structure 400 is filled is interconnected, and the orthographic projection on the substrate 10 covers the orthographic projection of the insulating filling structure 400 on the substrate 10.

[0267] In an exemplary embodiment, as shown in Figures 30 to 34, a third covering structure 633 is disposed on the first surface of a first insulating structure 312 between two insulating pillars 300 filled with insulating filling structure 400, and on the side away from the substrate 10 of the first and third surfaces of the first insulating structure 312 between two insulating pillars 300 without insulating filling structure 400. A fourth covering structure 634 is disposed on the fourth surface of a second insulating structure 314 between two insulating pillars 300 filled with insulating filling structure 400, and on the side away from the substrate 10 of the fourth and sixth surfaces of the second insulating structure 314 between two insulating pillars 300 without insulating filling structure 400.

[0268] Figure 35 is a schematic diagram of the membrane layer provided in Figure 14. Figure 35 is illustrated using the isolation pillars including: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315, a third insulating structure 316, a fourth conductive structure 317, and a fourth insulating structure 318 as an example. As shown in Figure 35, the display substrate includes a substrate 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 disposed on the substrate 10. When the first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fourth insulating layer 104, the third conductive structure 315 is located in the third gate metal layer, the third insulating structure 316 is located in the fifth insulating layer 105, the fourth conductive structure 317 is located in the first source / drain metal layer, and the fourth insulating structure 318 is located in the sixth insulating layer 106, the composite insulating layer includes the first insulating layer 101 and the second insulating layer 102.

[0269] In an exemplary embodiment, as shown in FIG35, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10, the orthographic projection of the first insulating structure 312 on the substrate 10 covers the orthographic projection of the second conductive structure 313 on the substrate 10, the orthographic projection of the second conductive structure 313 on the substrate 10 covers the orthographic projection of the second insulating structure 314 on the substrate 10, the orthographic projection of the second insulating structure 314 on the substrate 10 covers the orthographic projection of the third conductive structure 315 on the substrate 10, the orthographic projection of the third conductive structure 315 on the substrate 10 covers the orthographic projection of the third insulating structure 316 on the substrate 10, the orthographic projection of the third insulating structure 316 on the substrate 10 covers the orthographic projection of the fourth conductive structure 317 on the substrate 10, and the orthographic projection of the fourth conductive structure 317 on the substrate 10 covers the orthographic projection of the fourth insulating structure 318 on the substrate 10.

[0270] In an exemplary embodiment, the surface of the first insulating structure 312 away from the substrate 10 includes a first surface, a second surface, and a third surface. The first surface and the third surface are located on opposite sides of the second surface. The orthographic projection of the second surface onto the substrate 10 coincides with the orthographic projection of the second conductive structure 313 onto the substrate 10. For two isolation pillars filled with an insulating filling structure, the first surface is located on the side of the second surface away from the insulating filling structure, and the third surface is located on the side of the second surface close to the insulating filling structure.

[0271] In an exemplary embodiment, the surface of the second insulating structure 314 away from the substrate 10 includes a fourth surface, a fifth surface, and a sixth surface. The fourth surface and the sixth surface are located on opposite sides of the fifth surface. The orthographic projection of the fifth surface onto the substrate 10 coincides with the orthographic projection of the third conductive structure 315 onto the substrate 10. For the two isolation pillars that are filled with an insulating filling structure, the fourth surface is located on the side of the fifth surface away from the insulating filling structure, and the sixth surface is located on the side of the fifth surface closer to the insulating filling structure.

[0272] In an exemplary embodiment, the surface of the third insulating structure 316 away from the substrate 10 includes a seventh surface, an eighth surface, and a ninth surface. The seventh surface and the ninth surface are located on opposite sides of the eighth surface. The orthographic projection of the eighth surface onto the substrate 10 coincides with the orthographic projection of the fourth conductive structure 317 onto the substrate 10. For the two isolation pillars that are filled with an insulating filling structure, the seventh surface is located on the side of the eighth surface away from the insulating filling structure, and the ninth surface is located on the side of the eighth surface closer to the insulating filling structure.

[0273] In an exemplary embodiment, as shown in FIG35, the display substrate further includes a first cover structure 641, a second cover structure 642, a third cover structure 643, a fourth cover structure 644, and a fifth cover structure 645 disposed at intervals.

[0274] The first covering structure 641 is disposed on the side of the composite insulation layer away from the substrate 10 and is in direct contact with the composite insulation layer. The second covering structure 642 is disposed on the side of the isolation pillar 300 away from the substrate 10. The second covering structures 642 disposed on the two isolation pillars 300 between which the insulating filling structure 400 is filled are interconnected, and their orthogonal projection on the substrate 10 covers the orthogonal projection of the insulating filling structure 400 on the substrate 10. The third covering structure 643 is disposed on the first surface of the first insulating structure 312 between the two isolation pillars 300 between which the insulating filling structure 400 is filled and the second surface of the first insulating structure 312 between the two isolation pillars 300 between which the insulating filling structure 400 is not disposed. The fourth covering structure 644 is disposed on the side away from the substrate 10 of the first and third surfaces, on the side where the first and third surfaces are away from the substrate 10, and the fourth and sixth surfaces of the second insulating structure 314 between the two insulating pillars 300 filled with insulating filling structure 400 and the second insulating structure 314 between the two insulating pillars 300 without insulating filling structure 400. The fifth covering structure 645 is disposed on the side away from the substrate 10 of the seventh surface of the third insulating structure 316 between the two insulating pillars 300 filled with insulating filling structure 400 and the seventh and ninth surfaces of the third insulating structure 316 between the two insulating pillars 300 without insulating filling structure 400.

[0275] In an exemplary embodiment, at least one of the first to fifth covering structures includes an organic structure and a cathode structure, wherein the orthographic projection of the cathode structure onto the substrate coincides with the orthographic projection of the organic structure onto the substrate; the organic structure is located in the organic light-emitting layer, and the cathode structure is located in the cathode layer.

[0276] In the exemplary embodiment, Figures 15 to 20 show a single power-off at the location of the isolation pillar, Figures 21 to 29 show a second power-off at the location of the isolation pillar, Figures 30 to 34 show a third power-off at the location of the isolation pillar, and Figure 35 shows a fourth power-off at the location of the isolation pillar. The display substrate provided in Figures 15 to 35 is disconnected at least once at the location of the isolation pillar, which can effectively solve the technical problem of black spots on the display substrate caused by conductivity in the bezel area and improve the display effect of the display substrate.

[0277] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0278] The following describes the manufacturing process of the display substrate provided in the embodiments of this disclosure in further detail with reference to Figures 9 and 13.

[0279] (1) Forming a composite insulating layer. In an exemplary embodiment, forming a composite insulating layer includes: sequentially forming a plurality of insulating layers on a substrate, thereby forming a composite insulating layer 20. As shown in FIG36, FIG36 is a schematic diagram after the composite insulating layer is formed.

[0280] In an exemplary embodiment, the composite insulating layer 20 covers the substrate and is located in the display area and the bezel area. Exemplarily, the composite insulating layer may include an inorganic insulating layer located on the side of the top source / drain metal layer near the substrate, for example, it may include at least one film layer among the first to sixth insulating layers.

[0281] In an exemplary embodiment, when at least one isolation pillar includes at least one of the second isolation structure to the (K+1)th isolation structure, forming a composite insulating layer further includes forming the composite insulating layer and at least one isolation pillar by at least one of the second isolation structure to the (K+1)th isolation structure.

[0282] (2) Forming a first isolation structure with at least one isolation pillar. In an exemplary embodiment, forming a first isolation structure with at least one isolation pillar includes: depositing a metal thin film on a composite insulating layer, and patterning the metal thin film using a patterning process to form a first isolation structure 310 with at least one isolation pillar located in the border region. As shown in FIG37, FIG37 is a schematic diagram after the formation of the first isolation structure.

[0283] In an exemplary embodiment, the step further includes: patterning the metal thin film using a patterning process to form at least one signal line located in the display area, such as a first power line or a data signal line.

[0284] (3) Forming an insulating fill structure and an isolation dam. In an exemplary embodiment, forming the insulating fill structure includes: forming an insulating fill structure 400 and an isolation dam 510 between at least two adjacent isolation pillars located in the border region on the composite insulating layer by a patterning process. As shown in FIG38, FIG38 is a schematic diagram after the insulating fill structure is formed.

[0285] In an exemplary embodiment, the first insulating filler structure and the second insulating filler structure may be formed sequentially or at the same time, and this disclosure does not impose any limitation on this.

[0286] In an exemplary embodiment, when the first insulating fill structure is located in the Nth flat layer, the first insulating structure and at least one dam base of at least one isolation dam are formed at the same time; when the first insulating fill structure is located in the pixel definition layer, the first insulating structure and the topmost dam base of at least one isolation dam are formed at the same time.

[0287] The fabrication process of the display substrate shown in Figures 15 to 20 below further illustrates the embodiments of this disclosure. The isolation pillars in the display substrates shown in Figures 15 to 20 include: a first conductive structure and a first insulating structure.

[0288] (1) Forming a first insulating layer. Forming the first insulating layer includes: forming a composite insulating layer on a substrate, depositing a metal thin film on the composite insulating layer, patterning the metal thin film using a patterning process to form a first original conductive structure 3110, and coating an insulating film on the first original conductive structure to form a first insulating layer 3120. As shown in Figure 39, Figure 39 is a schematic diagram of the first insulating layer after it has been formed in Figures 15 to 20.

[0289] In an exemplary embodiment, the sidewalls of the first original conductive structure are straight.

[0290] In an exemplary embodiment, the composite insulating layer comprises all inorganic insulating layers located near the substrate within the film layer containing the first original conductive structure. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes a first insulating layer and a second insulating layer; when the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer, and so on.

[0291] (2) Forming a first insulating structure. Forming the first insulating structure includes: etching the first insulating layer 3120 using a mask to form the first insulating structure 312. As shown in Figure 40, Figure 40 is a schematic diagram of the first insulating structure formed in Figures 15 to 20.

[0292] In an exemplary embodiment, the photomask has vias that expose the first insulating layer, and the orthographic projection of the vias on the substrate is within the range of the orthographic projection of the first original conductive structure on the substrate, and the width of the vias is smaller than the width of the first original conductive structure, wherein the width is the length extending in the direction parallel to the substrate.

[0293] In an exemplary embodiment, the first insulating structure may be formed after the top source / drain metal layer is formed and before the first electrode of the light-emitting element is formed; this disclosure does not limit this in any way.

[0294] (3) Forming a first conductive structure. Forming the first conductive structure includes etching the first original conductive structure to form the first conductive structure 311. As shown in Figure 41, Figure 41 is a schematic diagram of the first conductive structure formed in Figures 15 to 20.

[0295] In an exemplary embodiment, the sidewall of the first conductive structure 311 is grooved.

[0296] In an exemplary embodiment, the first conductive structure 311 may be formed after the first electrode of the light-emitting element.

[0297] (4) Forming an insulating filler structure. Forming an insulating filler structure includes: depositing an insulating filler film, and patterning the insulating filler film using a patterning process to form an insulating filler structure 400. As shown in Figure 42, Figure 42 is a schematic diagram of the insulating filler structure formed in Figures 15 to 20.

[0298] In an exemplary embodiment, the insulating filler film may be the same film as the film forming the top planarization layer, or the same film as the film forming the pixel definition layer.

[0299] (5) Forming multiple capping structures. Forming multiple capping structures includes: depositing an organic material layer and a cathode conductive layer, and forming a capping structure including organic and cathode structures through a patterning process. As shown in Figure 43, Figure 43 is a schematic diagram of the multiple capping structures formed in Figures 15 to 20.

[0300] In an exemplary embodiment, the plurality of overlay structures include: a first overlay structure 611 and a second overlay structure 612.

[0301] The fabrication process of the display substrate shown in Figures 21 to 29 below further illustrates the embodiments of this disclosure. The isolation pillars in the display substrates shown in Figures 20 to 29 include: a first conductive structure, a first insulating structure, a second conductive structure, and a second insulating structure.

[0302] (1) Forming a second insulating layer. Forming the second insulating layer includes: forming a composite insulating layer on a substrate; depositing a first metal thin film on the composite insulating layer; patterning the first metal thin film using a patterning process to form a first original conductive structure 3110; coating the first insulating film on the first original conductive structure to form a first insulating layer 3120; depositing a second metal thin film on the first insulating layer; patterning the second metal thin film using a patterning process to form a second original conductive structure 3130; and coating the second insulating film on the second original conductive structure to form a second insulating layer 3140. As shown in Figure 44, Figure 44 is a schematic diagram of the second insulating layer after it has been formed in Figures 21 to 29.

[0303] In an exemplary embodiment, the sidewalls of the first and second original conductive structures are straight lines.

[0304] In an exemplary embodiment, the composite insulating layer comprises all inorganic insulating layers located near the substrate within the film layer containing the first original conductive structure. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes a first insulating layer and a second insulating layer; when the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer, and so on.

[0305] In an exemplary embodiment, the first insulating layer may be a single-layer structure or a multi-layer structure, and the second insulating layer may be a single-layer structure. The structure of the first insulating layer depends on the film layers in which the first and second original conductive structures are located. For example, when the film layers in which the first and second original conductive structures are located are adjacent metal layers, the first insulating layer is a single-layer structure; when other metal layers are disposed between the film layers in which the first and second original conductive structures are located, the first insulating layer is a multi-layer structure.

[0306] (2) Forming the first insulating structure and the second insulating structure. Forming the first insulating structure and the second insulating structure includes: etching the first insulating layer and the second insulating layer using a mask to form the first insulating structure 312 and the second insulating structure 314. As shown in Figure 45, Figure 45 is a schematic diagram of the first insulating structure and the second insulating structure after they have been formed in Figures 21 to 29.

[0307] In an exemplary embodiment, the photomask has vias that expose the second insulating layer, and the orthographic projection of the vias on the substrate is within the range of the orthographic projection of the second original conductive structure on the substrate, and the width of the vias is smaller than the width of the second original conductive structure, wherein the width is the length extending in the direction parallel to the substrate.

[0308] In an exemplary embodiment, the formation of the first insulating structure and the second insulating structure may be performed after the formation of the top source / drain metal layer and before the formation of the first electrode of the light-emitting element, and this disclosure does not limit this in any way.

[0309] (3) Forming the first conductive structure and the second conductive structure. Forming the first conductive structure and the second conductive structure includes etching the first original conductive structure and the second original conductive structure to form the first conductive structure 311 and the second conductive structure 313. As shown in Figure 46, Figure 46 is a schematic diagram of the first conductive structure and the second conductive structure after they have been formed in Figures 20 to 29.

[0310] In an exemplary embodiment, the sidewalls of the first conductive structure 311 and the second conductive structure 313 are grooved.

[0311] In an exemplary embodiment, the first conductive structure 311 and the second conductive structure 313 may be formed after the first electrode of the light-emitting element.

[0312] (4) Forming an insulating filler structure. Forming an insulating filler structure includes: depositing an insulating filler film, and patterning the insulating filler film using a patterning process to form an insulating filler structure 400. As shown in Figure 47, Figure 47 is a schematic diagram of the insulating filler structure formed in Figures 21 to 29.

[0313] In an exemplary embodiment, the insulating filler film may be the same film as the film forming the top planarization layer, or the same film as the film forming the pixel definition layer.

[0314] (5) Forming multiple capping structures. Forming multiple capping structures includes: depositing an organic material layer and a cathode conductive layer, and forming a capping structure including organic and cathode structures through a patterning process. As shown in Figure 48, Figure 48 is a schematic diagram of the multiple capping structures formed in Figures 21 to 29.

[0315] In an exemplary embodiment, the plurality of overlay structures include: a first overlay structure 621, a second overlay structure 622, and a third overlay structure 623.

[0316] The fabrication process of the display substrate shown in Figures 30 to 34 below further illustrates the embodiments of this disclosure. The isolation pillars in the display substrates shown in Figures 30 to 34 include: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, and a third insulating structure.

[0317] (1) Forming a third insulating layer. Forming the third insulating layer includes: forming a composite insulating layer on a substrate; depositing a first metal thin film on the composite insulating layer; patterning the first metal thin film using a patterning process to form a first original conductive structure 3110; coating the first original conductive structure with a first insulating film to form a first insulating layer 3120; depositing a second metal thin film on the first insulating layer; patterning the second metal thin film using a patterning process to form a second original conductive structure 3130; coating the second original conductive structure with a second insulating film to form a second insulating layer 3140; depositing a third metal thin film on the second insulating layer; patterning the third metal thin film using a patterning process to form a third original conductive structure 3150; and coating the third original conductive structure with a third insulating film to form a third insulating layer 3160. As shown in Figure 49, Figure 49 is a schematic diagram of the third insulating layer after it has been formed in Figures 30 to 34.

[0318] In an exemplary embodiment, the sidewalls of the first original conductive structure, the second original conductive structure, and the third original conductive structure are straight lines.

[0319] In an exemplary embodiment, the composite insulating layer comprises all inorganic insulating layers located near the substrate within the film layer containing the first original conductive structure. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes a first insulating layer and a second insulating layer; when the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer, and so on.

[0320] In an exemplary embodiment, the first and second insulating layers can be single-layer or multi-layer structures, and the third insulating layer is a single-layer structure. The structure of the first insulating layer depends on the film layers containing the first and second original conductive structures. For example, when the film layers containing the first and second original conductive structures are located in adjacent metal layers, the first insulating layer is a single-layer structure; when other metal layers are disposed between the film layers containing the first and second original conductive structures, the first insulating layer is a multi-layer structure. The structure of the second insulating layer depends on the film layers containing the second and third original conductive structures. For example, when the film layers containing the second and third original conductive structures are located in adjacent metal layers, the second insulating layer is a single-layer structure; when other metal layers are disposed between the film layers containing the second and third original conductive structures, the second insulating layer is a multi-layer structure.

[0321] (2) Forming the first insulating structure, the second insulating structure, and the third insulating structure. Forming the first insulating structure, the second insulating structure, and the third insulating structure includes: etching the first insulating layer, the second insulating layer, and the third insulating layer using a mask to form the first insulating structure 312, the second insulating structure 314, and the third insulating structure 316. As shown in Figure 50, Figure 50 is a schematic diagram of the first insulating structure, the second insulating structure, and the third insulating structure after they have been formed as shown in Figures 30 to 34.

[0322] In an exemplary embodiment, the photomask has vias that expose the third insulating layer, and the orthographic projection of the vias on the substrate is within the range of the orthographic projection of the third original conductive structure on the substrate, and the width of the vias is smaller than the width of the third original conductive structure, wherein the width is the length extending in the direction parallel to the substrate.

[0323] In an exemplary embodiment, the formation of the first insulating structure, the second insulating structure, and the third insulating structure may be performed after the formation of the top source / drain metal layer and before the formation of the first electrode of the light-emitting element, and this disclosure does not limit this in any way.

[0324] (3) Forming the first conductive structure, the second conductive structure, and the third conductive structure. Forming the first conductive structure, the second conductive structure, and the third conductive structure includes etching the first original conductive structure, the second original conductive structure, and the third original conductive structure to form the first conductive structure 311, the second conductive structure 313, and the third conductive structure 315. As shown in Figure 51, Figure 51 is a schematic diagram of the first conductive structure, the second conductive structure, and the third conductive structure after they have been formed in Figures 30 to 34.

[0325] In an exemplary embodiment, the sidewalls of the first conductive structure 311, the second conductive structure 313, and the third conductive structure 315 are grooved.

[0326] In an exemplary embodiment, the first conductive structure 311, the second conductive structure 313, and the third conductive structure 315 may be formed after the first electrode of the light-emitting element.

[0327] (4) Forming an insulating filler structure. Forming an insulating filler structure includes: depositing an insulating filler film, and patterning the insulating filler film through a patterning process to form an insulating filler structure 400, as shown in Figure 52. Figure 52 is a schematic diagram of the insulating filler structure formed in Figures 30 to 34.

[0328] In an exemplary embodiment, the insulating filler film may be the same film as the film forming the top planarization layer, or the same film as the film forming the pixel definition layer.

[0329] (5) Forming multiple capping structures. Forming multiple capping structures includes depositing an organic material layer and a cathode conductive layer, and forming a capping structure including organic and cathode structures through a patterning process. As shown in Figure 53, Figure 53 is a schematic diagram of the multiple capping structures formed in Figures 30 to 34.

[0330] In an exemplary embodiment, the plurality of overlay structures include: a first overlay structure 631, a second overlay structure 632, a third overlay structure 633, and a fourth overlay structure 634.

[0331] The fabrication process of the display substrate shown in Figure 35 below further illustrates the embodiments of this disclosure. The isolation pillars in the display substrate shown in Figure 35 include: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, a third insulating structure, a fourth conductive structure, and a fourth insulating structure.

[0332] (1) Form a third insulating layer. The formation of the third insulating layer includes: forming a composite insulating layer on a substrate; depositing a first metal thin film on the composite insulating layer; patterning the first metal thin film using a patterning process to form a first original conductive structure 3110; coating the first insulating film on the first original conductive structure to form a first insulating layer 3120; depositing a second metal thin film on the first insulating layer; patterning the second metal thin film using a patterning process to form a second original conductive structure 3130; coating the second insulating film on the second original conductive structure to form a second insulating layer 3140; depositing a third metal thin film on the second insulating layer; patterning the third metal thin film using a patterning process to form a third original conductive structure 3150; coating the third insulating film on the third original conductive structure to form a third insulating layer 3160; depositing a fourth metal thin film on the third insulating layer; patterning the fourth metal thin film using a patterning process to form a fourth original conductive structure 3170; and coating the fourth insulating film on the third original conductive structure to form a fourth insulating layer 3180, as shown in Figure 54, which is a schematic diagram of the fourth insulating layer formed in Figure 35.

[0333] In an exemplary embodiment, the sidewalls of the first original conductive structure, the second original conductive structure, the third original conductive structure, and the fourth original conductive structure are straight lines.

[0334] In an exemplary embodiment, the composite insulating layer comprises all inorganic insulating layers located near the substrate within the film layer containing the first original conductive structure. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes a first insulating layer and a second insulating layer; when the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer, and so on.

[0335] In an exemplary embodiment, the first, second, and third insulating layers can be single-layer or multi-layer structures, with the third insulating layer being a single-layer structure. The structure of the first insulating layer depends on the film layers containing the first and second original conductive structures. For example, when the film layers containing the first and second original conductive structures are located in adjacent metal layers, the first insulating layer is a single-layer structure; when other metal layers are disposed between the film layers containing the first and second original conductive structures, the first insulating layer is a multi-layer structure. The structure of the second insulating layer depends on the film layers containing the second and third original conductive structures. For example, when the film layers containing the second and third original conductive structures are located in adjacent metal layers, the second insulating layer is a single-layer structure; when other metal layers are disposed between the film layers containing the second and third original conductive structures, the second insulating layer is a multi-layer structure.

[0336] (2) Forming the first insulating structure, the second insulating structure, the third insulating structure, and the fourth insulating structure. Forming the first insulating structure, the second insulating structure, the third insulating structure, and the fourth insulating structure includes: etching the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer using a mask to form the first insulating structure 312, the second insulating structure 314, the third insulating structure 316, and the fourth insulating structure 318. As shown in Figure 55, Figure 55 is a schematic diagram after the formation of the first insulating structure, the second insulating structure, the third insulating structure, and the fourth insulating structure in Figure 35.

[0337] In an exemplary embodiment, the photomask has vias that expose the fourth insulating layer, and the orthographic projection of the vias onto the substrate is within the range of the orthographic projection of the fourth original conductive structure onto the substrate, and the width of the vias is less than the width of the fourth original conductive structure, wherein the width is the length extending in the direction parallel to the substrate.

[0338] In an exemplary embodiment, the formation of the first insulating structure, the second insulating structure, the third insulating structure, and the fourth insulating structure may be performed after the formation of the top source / drain metal layer and before the formation of the first electrode of the light-emitting element, and this disclosure does not limit this in any way.

[0339] (3) Forming the first conductive structure, the second conductive structure, and the fourth conductive structure. Forming the first conductive structure, the second conductive structure, and the third conductive structure includes etching the first original conductive structure, the second original conductive structure, the third original conductive structure, and the fourth original conductive structure to form the first conductive structure 311, the second conductive structure 313, the third conductive structure 315, and the fourth conductive structure 317. As shown in Figure 56, Figure 56 is a schematic diagram after the formation of the first conductive structure, the second conductive structure, the third conductive structure, and the fourth conductive structure in Figure 35.

[0340] In an exemplary embodiment, the sidewalls of the first conductive structure 311, the second conductive structure 313, the third conductive structure 315, and the fourth conductive structure 317 are grooved.

[0341] In an exemplary embodiment, the first conductive structure 311, the second conductive structure 313, the third conductive structure 315, and the fourth conductive structure 317 may be formed after the first electrode of the light-emitting element.

[0342] (4) Forming an insulating filler structure. Forming an insulating filler structure includes: depositing an insulating filler film, and patterning the insulating filler film through a patterning process to form an insulating filler structure 400, as shown in Figure 57. Figure 57 is a schematic diagram of the insulating filler structure formed in Figure 35.

[0343] In an exemplary embodiment, the insulating filler film may be the same film as the film forming the top planarization layer, or the same film as the film forming the pixel definition layer.

[0344] (5) Forming multiple capping structures. Forming multiple capping structures includes depositing an organic material layer and a cathode conductive layer, and forming a capping structure including organic and cathode structures through a patterning process. As shown in Figure 58, Figure 58 is a schematic diagram of the multiple capping structures formed in Figure 35.

[0345] In an exemplary embodiment, the plurality of overlay structures include: a first overlay structure 641, a second overlay structure 642, a third overlay structure 643, a fourth overlay structure 644, and a fifth overlay structure 645.

[0346] Figure 59 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 59, this embodiment provides a display device 91, including the display substrate 910 provided in any of the foregoing embodiments.

[0347] In an exemplary embodiment, the display substrate 910 can be an OLED display substrate, such as an OLED display substrate with an integrated touch structure. The display device 91 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, or it can be a product or component with both touch and display functions. In an exemplary embodiment, the display device 91 can be a wearable display device, such as one that can be worn on the human body in some way. For example, the display device 91 can be a smartwatch, smart bracelet, etc. However, this embodiment is not limited to this.

[0348] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0349] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: A display area and a hole area are provided, the display area being arranged around the hole area, the hole area including: a first area and a second area arranged sequentially away from the display area; the first area and the second area are provided with a plurality of isolation pillars, and an insulating filling structure is filled between at least two adjacent isolation pillars in the first area and the second area, and at least one insulating filling structure at least partially covers the sidewalls of the two adjacent isolation pillars near the insulating filling structure; The thickness of at least one first insulating filler structure is less than the thickness of at least one second insulating filler structure. The first insulating filler structure is disposed between adjacent first isolation pillars, which are isolation pillars located in a first region. The second insulating filler structure is disposed between adjacent second isolation pillars, which are isolation pillars located in a second region.

2. The display substrate according to claim 1, wherein, The ratio of the thickness of the second insulating filler structure to the thickness of the first insulating filler structure is between 1.05 and 3.

85.

3. The display substrate according to claim 1, wherein, The second insulating filling structure includes a second sub-filling structure, or includes a first sub-filling structure and a second sub-filling structure. When the second insulating filling structure includes a first sub-filling structure and a second sub-filling structure, the first sub-filling structure is located on the side of the second sub-filling structure closer to the display area. The thickness of the first sub-filling structure is less than the thickness of the second sub-filling structure.

4. The display substrate according to claim 3, wherein, The thickness of the first insulating fill structure is less than the thickness of the second sub-fill structure.

5. The display substrate according to claim 1, wherein, The display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate. The light-emitting structure layer includes: an organic light-emitting layer and a cathode layer. The organic light-emitting layer and the cathode layer extend from the display area to the second border area. The organic light-emitting layer and the cathode layer located in the first frame region or the second frame region are separated by at least one isolation pillar located in the first frame region or the second frame region; The organic light-emitting layer located in the first frame region or the second frame region includes: a first organic structure and a second organic structure arranged at intervals between each other; the cathode layer located in the first frame region or the second frame region includes: a first cathode structure and a second cathode structure arranged at intervals between each other, wherein the first cathode structure corresponds one-to-one with the first organic structure and the second cathode structure corresponds one-to-one with the second organic structure. The first organic structure is disposed between at least some adjacent isolation pillars and at least partially covers at least a portion of the sidewalls of the adjacent isolation pillars. The second organic structure is disposed on the surface of at least one isolation pillar away from the substrate. The first cathode structure is disposed between at least some adjacent isolation pillars and at least partially covers the sidewalls of the adjacent isolation pillars. The second cathode structure is disposed on the side of the second organic structure away from the substrate. The maximum distance between the surface of at least one second organic structure away from the substrate and the substrate is greater than the maximum distance between the surface of the first cathode structure away from the substrate and the substrate.

6. The display substrate according to claim 5, wherein, The second organic structure disposed on the two isolation pillars filled with insulating filler structure is interconnected, and its orthographic projection on the substrate covers the orthographic projection of the insulating filler structure on the substrate. The second cathode structure disposed on the two isolation pillars filled with insulating filler structure is interconnected, and its orthographic projection on the substrate covers the orthographic projection of the insulating filler structure on the substrate.

7. The display substrate according to any one of claims 1 to 6, wherein, The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: M source and drain metal layers, wherein the (m+1)th source and drain metal layer is located on the side of the mth source and drain metal layer away from the substrate, M≥2, 1≤m≤M-1. At least one of the plurality of isolation pillars includes: a first isolation structure, wherein the first isolation structure of the at least one of the plurality of isolation pillars is located in one of the M source / drain metal layers.

8. The display substrate according to any one of claims 1 to 6, wherein, The display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer stacked sequentially on the substrate. The light-emitting structure layer includes: a pixel definition layer. The circuit structure layer includes: N planarization layers stacked sequentially on the substrate, where the (n+1)th planarization layer is located on the side of the nth planarization layer away from the substrate, and 1≤N≤M, 1≤n≤N-1. The first insulating fill structure is located in the Nth flat layer or pixel definition layer.

9. The display substrate according to any one of claims 3 to 6, wherein, The display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer stacked sequentially on the substrate. The light-emitting structure layer includes: a pixel definition layer. The circuit structure layer includes: N planarization layers stacked sequentially on the substrate, where the (n+1)th planarization layer is located on the side of the nth planarization layer away from the substrate, and 1≤N≤M, 1≤n≤N-1. The first sub-fill structure is located in the Nth flat layer or pixel definition layer.

10. The display substrate according to any one of claims 3 to 6, wherein, The display substrate includes: a substrate and a light-emitting structure layer disposed on the substrate, the light-emitting structure layer including: a pixel definition layer and spacers disposed on the pixel definition layer; The second sub-filling structure is disposed in the same layer as the spacer.

11. The display substrate according to claim 7, wherein, The circuit structure layer further includes: K gate metal layers stacked sequentially on the substrate, wherein the Kth gate metal layer is located on the side of the first source / drain metal layer closest to the substrate; At least one of the plurality of isolation pillars further includes at least one of the second isolation structure to the (K+1)th isolation structure, wherein the orthographic projection of at least one of the second isolation structure to the (K+1)th isolation structure on the substrate overlaps with the orthographic projection of the first isolation structure. The (k+1)th isolation structure is located in the kth gate metal layer, where 1 ≤ k ≤ K.

12. The display substrate according to claim 1, wherein, The aperture area further includes a third region and a fourth region, wherein the third region is located between the first region and the second region, and the fourth region is located on the side of the second region away from the display area; The third area is provided with at least one isolation dam, and the fourth area is provided with a cutting groove or at least one isolation column.

13. The display substrate according to claim 12, wherein, The display substrate includes: a substrate and a circuit structure layer disposed on the substrate, the circuit structure layer further including: a plurality of inorganic insulating layers and a plurality of organic insulating layers; the frame region includes: a composite insulating layer, the composite insulating layer including: a plurality of inorganic insulating layers located on the side of the Mth source / drain metal layer near the substrate, the inorganic insulating layer extending from the display region to the fourth region; The cutting groove is disposed within the composite insulation layer.

14. The display substrate according to claim 7, wherein, The first isolation structure of at least one of the plurality of isolation pillars includes: a first isolation portion, a second isolation portion and a third isolation portion, wherein the first isolation portion is located on the side of the second isolation portion closer to the substrate, and the third isolation portion is located on the side of the second isolation portion away from the substrate; The orthographic projection of the surface of the second isolation portion near the substrate onto the substrate is within the range of the orthographic projection of the surface of the first isolation portion away from the substrate onto the substrate, and the orthographic projection of the surface of the second isolation portion away from the substrate onto the substrate is within the range of the orthographic projection of the surface of the third isolation portion near the substrate onto the substrate.

15. The display substrate according to claim 14, wherein, The first insulating filling structure overlaps with the orthographic projection of the third isolation portion of the first isolation pillar on the substrate, and the second insulating filling structure overlaps with the orthographic projection of the third isolation portion of the second isolation pillar on the substrate.

16. The display substrate according to any one of claims 1 to 6, wherein, include: A substrate, wherein the isolation pillar is disposed on the substrate, and at least one of the isolation pillars comprises: L conductive structures and L insulating structures stacked together, the L conductive structures and L insulating structures being alternately arranged, the l-th insulating structure being located on the side of the l-th conductive structure away from the substrate, and L being a positive integer greater than or equal to 1; At least one of the conductive structures has a groove-shaped sidewall.

17. The display substrate according to claim 16, wherein, When L is greater than or equal to 2, the orthographic projection of the surface of the l-th conductive structure near the substrate onto the substrate is within the range of the orthographic projection of the surface of the (l-1)-th insulating structure away from the substrate onto the substrate, and the maximum distance between the sidewall of the l-th conductive structure and the centerline of the isolation post is less than the minimum distance between the sidewall of the (l-1)-th insulating structure and the centerline of the isolation post.

18. The display substrate according to claim 16, wherein, The isolation pillar includes: a first conductive structure and a first insulating structure; The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: K gate metal layers and M source / drain metal layers disposed on the substrate. The (k+1)th gate metal layer is located on the side of the kth gate metal layer away from the substrate. The kth gate metal layer is located on the side of the first source / drain metal layer close to the substrate. The (m+1)th source / drain metal layer is located on the side of the mth source / drain metal layer away from the substrate. K≥2, 1≤k≤K-1, M≥2, 1≤m≤M-1. The circuit structure layer further includes: multiple inorganic insulating layers and multiple organic insulating layers, and at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer; The first conductive structure is located in one of the K gate metal layers and M source / drain metal layers, and the first insulating structure is located in one of the plurality of inorganic insulating layers.

19. The display substrate according to claim 16, wherein, The isolation column includes: a first conductive structure, a first insulating structure, a second conductive structure, and a second insulating structure; The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: K gate metal layers and M source / drain metal layers disposed on the substrate. The (k+1)th gate metal layer is located on the side of the kth gate metal layer away from the substrate. The kth gate metal layer is located on the side of the first source / drain metal layer close to the substrate. The (m+1)th source / drain metal layer is located on the side of the mth source / drain metal layer away from the substrate. K≥2, 1≤k≤K-1, M≥2, 1≤m≤M-1. The circuit structure layer further includes: multiple inorganic insulating layers and multiple organic insulating layers, and at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer; At least one of the first conductive structure and the second conductive structure is located in two of the K gate metal layers and M source / drain metal layers, and the first conductive structure and the second conductive structure are located in different layers; the first insulating structure and the second insulating structure are located in two of the multilayer inorganic insulating layers, and the first insulating structure and the second insulating structure are located in different layers.

20. The display substrate according to claim 16, wherein, The isolation pillar includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, and a third insulating structure; The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: K gate metal layers and M source / drain metal layers disposed on the substrate. The (k+1)th gate metal layer is located on the side of the kth gate metal layer away from the substrate. The kth gate metal layer is located on the side of the first source / drain metal layer close to the substrate. The (m+1)th source / drain metal layer is located on the side of the mth source / drain metal layer away from the substrate. K≥2, 1≤k≤K-1, M≥2, 1≤m≤M-1. The circuit structure layer further includes: multiple inorganic insulating layers and multiple organic insulating layers, and at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer; The first conductive structure, the second conductive structure, and the third conductive structure are located in three of the K gate metal layers and M source / drain metal layers, and the first conductive structure, the second conductive structure, and the third conductive structure are located in different layers; the first insulating structure, the second insulating structure, and the third insulating structure are located in three of the multilayer inorganic insulating layers, and the first insulating structure, the second insulating structure, and the third insulating structure are located in different layers.

21. The display substrate according to claim 12, wherein, The display substrate includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate. The light-emitting structure layer includes: a pixel definition layer. The circuit structure layer includes: a plurality of planarization layers sequentially stacked on the substrate. At least one isolation dam includes: a plurality of dam foundations stacked sequentially in a direction away from the base, at least one of the plurality of dam foundations being located in at least one flat layer, and at least one of the plurality of dam foundations being located in a pixel definition layer.

22. A display device, comprising: The display substrate as described in any one of claims 1 to 21.

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