Mitigating noise in digitally controlled quantum computing

Abstract

Systems and methods for quantum computing are disclosed. A stack of chips includes a quantum chip and a classical chip. The quantum chip includes a quantum circuit including a plurality of quantum elements fabricated on the quantum chip. The classical chip is bonded to the quantum chip and includes a classical circuit configured to manipulate or measure the plurality of quantum elements. The classical circuit includes a plurality of Josephson junctions fabricated on the classical chip. The classical chip is bonded to the quantum chip such that the plurality of quantum elements of the quantum circuit is not directly facing the plurality of Josephson junctions of the classical circuit, and each Josephson junction of the plurality of Josephson junctions is configured to have a critical current value below 20 microamperes.

Description

Docket No. 600248 / 0015 / PCTMITIGATING NOISE IN DIGITALLY CONTROLLED QUANTUM COMPUTINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of and priority to U.S. Provisional Application No. 63 / 695,886, filed September 18, 2024. The entire contents of each and every priority application are hereby incorporated by reference herein.FIELD

[0002] The present disclosure relates generally to quantum computing, and more specifically, to the use, configuration, integration and / or fabrication of classical cryogenic control circuitry such as SFQ circuitry in quantum computing.BACKGROUND

[0003] Quantum computing leverages the principles of quantum mechanics to perform computations that are intractable for classical computers. Superconducting qubits are among the leading platforms for realizing quantum processors, owing to their scalability and compatibility with existing fabrication technologies. However, the operation and control of superconducting qubits require precise manipulation and measurement, often facilitated by classical control electronics.

[0004] Single Flux Quantum (SFQ) circuits, which utilize superconducting loops interrupted by Josephson junctions, have emerged as a promising technology for high-speed, low-power classical control of quantum circuits at cryogenic temperatures. SFQ circuits are capable of generating and processing digital signals at extremely high speeds and low power dissipation, making them suitable for interfacing with quantum processors.

[0005] Despite their advantages, the integration of SFQ circuits with quantum circuits presents significant challenges. The switching of Josephson junctions (JJ) in SFQ circuits releases energy, among others, in the form of phonons and high-frequency electromagnetic radiation. This energy can propagate through the chip and interact with quantum elements, leading to quasiparticle generation and decoherence, which may degrade the performance of quantum processors. For example, the released energy can manifest as propagating phonons in the chip, breaking cooper-pairs and thereby poisoning the chip with quasiparticles. Additionally, JJ switching emits electromagnetic radiation at tens to hundreds of GigahertzDocket No. 600248 / 0015 / PCT(GHz), which can exacerbate quasiparticle poisoning. These quasiparticles can affect the quantum states of quantum elements, compromising the encoded quantum information.

[0006] Traditional approaches to mitigate these effects include physically separating the SFQ and quantum circuits to a considerable distance or operating them at different temperature stages. Locating the SFQ circuits at a higher temperature stage (at, e.g., 3 Kelvin (K)) than the quantum circuits (at, e.g., 10 millikelvin (mK)) may mitigate these effects. However, this approach may not be scalable as it requires the SFQ circuits to be physically distant from the quantum circuits, requiring a large number of cables to interface between the two. Placing the SFQ circuits at the same temperature as the quantum circuits, but on a separate chip, can mitigate the propagation of phonons due to JJ switching. This may be achieved, for example, by using a flip-chip configuration where two chips are stacked and where the quantum elements on one chip directly face the SFQ circuits on the second chip. However, this arrangement leads to direct photon radiation affecting the quantum circuit.

[0007] Accordingly, there is a need for improved systems and methods for integrating SFQ circuits with quantum circuits that mitigate the harmful effects of SFQ-generated noise, while maintaining scalability and efficient operation of quantum computing devices.SUMMARY

[0008] In accordance with aspects of the present disclosure, a stack of chips includes a quantum chip, which includes a quantum circuit and a classical chip. The quantum circuit includes a plurality of quantum elements fabricated on the quantum chip. The classical chip is bonded to the quantum chip and includes a classical circuit configured to manipulate or measure the plurality of quantum elements. The classical circuit includes a plurality of Josephson junctions fabricated on the classical chip. The classical chip is bonded to the quantum chip such that the plurality of quantum elements of the quantum circuit is not directly facing the plurality of Josephson junctions of the classical circuit, and each Josephson junction of the plurality of Josephson junctions is configured to have a critical current value below 20 microamperes.

[0009] In various embodiments of the stack of chips, the classical chip is bonded to the quantum chip such that the plurality of quantum elements of the quantum circuit is not facing the plurality of Josephson junctions of the classical circuit.

[0010] In various embodiments of the stack of chips, the quantum chip includes first and second opposite surfaces and the plurality of quantum elements are fabricated on the firstDocket No. 600248 / 0015 / PCT surface of the quantum chip; the classical chip includes first and second opposite surfaces, and the plurality of Josephson junctions are fabricated on the first surface of the classical chip; and the classical chip is bonded to the quantum chip such that the second surface of the quantum chip faces the first surface of the classical chip.

[0011] In various embodiments of the stack of chips, the quantum chip further includes one or more superconducting coupling vias connecting the two opposite surfaces of the quantum chip by traversing the entirety of the quantum chip.

[0012] In various embodiments of the stack of chips, the stack of chips further includes a radiation absorbing layer encapsulating the classical circuit.

[0013] In various embodiments of the stack of chips, the stack of chips further includes one or more radiation absorbing structures disposed on the second surface of the quantum chip.

[0014] In various embodiments of the stack of chips, the quantum chip is opaque to high- frequency radiation.

[0015] In various embodiments of the stack of chips, each Josephson junction of the plurality of Josephson junctions is configured to have critical current values between ten nanoamperes and five microamperes.

[0016] In various embodiments of the stack of chips, each Josephson junction of the plurality of Josephson junctions is configured to have critical current values equal to two hundred nanoamperes.

[0017] In various embodiments of the stack of chips, the classical circuit includes a plurality of inductors, where the magnetic induction value of at least one inductor of the plurality of inductors is at least one hundred picohenry.

[0018] In various embodiments of the stack of chips, a portion of the classical circuit is made of high kinetic inductance material.

[0019] In various embodiments of the stack of chips, the high kinetic inductance material is selected from: Granular Aluminum (GrAl), Titanium Niobium Nitride (NbTiN) or Niobium Nitride (NbN).

[0020] In various embodiments of the stack of chips, the GrAl was grown at a temperature below 100 Kelvin.

[0021] In various embodiments of the stack of chips, the duration of pulses output by the classical circuit is above eight picoseconds.

[0022] In accordance with aspects of the present disclosure, a quantum processor includes at least one stack of chips according to the disclosure.Docket No. 600248 / 0015 / PCT

[0023] In accordance with aspects of the present disclosure, a method for fabricating a stack of chips includes bonding a quantum chip and a classical chip. The classical chip includes a plurality of Josephson junctions, having a critical current value below 20 microamperes, and fabricated thereon. The quantum chip includes a plurality of quantum elements fabricated thereon. The quantum chip and the classical chip are bonded such that the plurality of Josephson junctions is not directly facing the plurality of quantum elements.

[0024] In various embodiments of the method, the quantum chip and the classical chip are bonded such that the plurality of Josephson junctions is not facing the plurality of quantum elements.

[0025] In various embodiments of the method, the quantum chip includes first and second opposite surfaces, the plurality of quantum elements are fabricated on the first surface of the quantum chip, the classical chip includes first and second opposite surfaces, the plurality of Josephson junctions are fabricated on the first surface of the classical chip, and the classical chip is bonded to the quantum chip so that the second surface of the quantum chip faces the first surface of the classical chip.

[0026] In various embodiments of the method, the plurality of Josephson junctions has critical current values between ten nanoamperes and five microamperes.

[0027] In various embodiments of the method, the plurality of Josephson junctions has critical current values equal to two hundred nanoamperes.

[0028] In various embodiments of the method, the classical circuit includes a plurality of inductors, wherein at least one inductor of the plurality of inductors has a magnetic induction value of at least one hundred picohenry.

[0029] In various embodiments of the method, a portion of the classical circuit is made of high kinetic inductance material.

[0030] In various embodiments of the method, the high kinetic inductance material is selected from: Granular Aluminum (GrAl), Titanium Niobium Nitride (NbTiN) or Niobium Nitride (NbN).

[0031] In accordance with aspects of the present disclosure, a method for fabricating a quantum processor includes fabricating multiple stacks of chips, where each stack of chips of the multiple stacks of chips is fabricated according to the disclosed methods, and placing the multiple stacks of chips in a cryogenic environment.Docket No. 600248 / 0015 / PCTBRIEF DESCRIPTION OF THE DRAWINGS

[0032] Aspects and features of the disclosure will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0033] Figure 1 is an illustration of an exemplary stack of chips in a flip-chip configuration including a reversed quantum chip, in accordance with embodiments of the present disclosure;

[0034] Figure 2 is an illustration of absorption of high-frequency electromagnetic radiation by antennas disposed on the substrate of the quantum chip of the stack of chips of FIG. 1, in accordance with embodiments of the present disclosure;

[0035] Fig. 3 A is a graph showing the output SFQ pulse from a circuit with low II critical currents with respect to a typical SFQ pulse, in accordance with embodiments of the present disclosure; and

[0036] Fig. 3B is a graph showing the Fourier transforms of the SFQ pulses of Fig. 3A, in accordance with embodiments of the present disclosure. It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions and / or aspect ratio of some of the elements can be exaggerated relative to other elements for clarity.DETAILED DESCRIPTION

[0037] The present disclosure allows protection of quantum elements from the noise generated by an SFQ circuit or other I -based circuits, such as Rapid Single Flux Quantum (RSFQ) circuits, Reciprocal Quantum Logic (RQL) circuits, Adiabatic Quantum-Flux- Parametron (AQFP) circuits, losephson Transmission Line (JTL) circuits, circuit-based Radiofrequency (RF) elements such as parametric amplifiers and mixers, superconducting memory elements (e.g., osephson Magnetic Random Access Memory (IMRAM)) and programmable osephson logic arrays. The disclosed systems and methods integrate SFQ circuits with quantum circuits, allowing SFQ-based control and measurement while mitigating the harmful effects of energy released by switching osephson junctions.

[0038] The term “quantum element” as referred to herein may include any component within a quantum processing unit that exhibits quantum mechanical behavior and may participate in quantum operations. The term “quantum element” as referred to herein may include, for example, a qubit, a coupler or a resonator.

[0039] In the following detailed description, specific details are set forth in order to provide an understanding of the disclosure. However, it will be understood by those skilled in the artDocket No. 600248 / 0015 / PCT that the disclosure may be practiced without these specific details. In other instances, well- known procedures and components have not been described in detail so as not to obscure the present disclosure. Some features or elements described with respect to one system may be combined with features or elements described with respect to other systems. For the sake of clarity, discussion of same or similar features or elements may not be repeated.

[0040] Although the disclosure is not limited in this regard, the terms “plurality” and “a plurality” as used herein may include, for example, “multiple” or “two or more.” The terms “plurality” or “a plurality” may be used throughout the specification to describe two or more components, devices, elements, units, parameters, or the like.

[0041] Although the disclosure is not limited in this regard, by using the term “or” when listing two or more items or options, it is meant that each item, and each plausible or feasible combination of the listed items including a combination of all listed items may be considered.

[0042] The present disclosure provides mitigation of SFQ-generated noise or JJ-generated noise such as quasiparticle poisoning by utilizing at least one of two key features. The first key feature is a stack of a quantum chip including a plurality of quantum elements and a classical chip, e.g., an SFQ chip, bonded by structural interconnecting elements (e.g., bump bonds or dielectric spacers), such that the quantum elements are not directly facing the SFQ circuits or circuitry of the classical chip. The classical chip may include a classical circuit configured to manipulate or measure the plurality of quantum elements. The term “manipulation,” as used herein in relation to quantum elements or quantum circuits, may refer to the application of control signals, pulses, or operations, whether classical or quantum, that are intended to change, adjust, or otherwise influence the quantum state, resonance frequency, coherence, entanglement, or any other quantum property of a quantum element or quantum circuit. Manipulation may include, but is not limited to, initialization, quantum gate operations, state transitions, error correction, routing of control signals, or any other process by which the behavior or state of a quantum element is actively controlled or altered by the classical circuit or associated control electronics.

[0043] According to some aspects, the quantum elements may face away from the SFQ circuits. According to some aspects, the quantum chip may include additional quantum elements, which face or directly face the SFQ circuits or circuitry of the classical chip, such as readout resonators. According to some aspects, the quantum chip and the classical chip may have two opposite sides or surfaces. According to some aspects, the quantum chip and the classical chip may be planar or substantially planar. The side or surface of the quantum chip,Docket No. 600248 / 0015 / PCT on which the quantum elements are fabricated, may not directly face or face away from, the side or surface of the classical chip, on which the JJs are fabricated. This may be achieved, for example, by reversing the orientation of a quantum chip in a flip-chip configuration, to make the quantum elements (or quantum circuits) face away from the SFQ circuits, as shown in Fig. 1, or by encapsulating the SFQ circuitry, e.g., by a radiation absorbing layer, to make the quantum elements not directly face the SFQ circuits, regardless of the quantum elements or quantum circuitry location with respect to the SFQ circuits.

[0044] Optionally, the quantum chip may be additionally made opaque to high-frequency radiation, ensuring that direct radiation, e.g., from the circuits in the classical chip (e.g., SFQ circuits) is absorbed by the substrate of the quantum chip, preventing it from reaching the quantum circuits. Additionally, or alternatively, one or more radiation absorbing structures, such as a ground plane or an array of antennas, may be placed on a side or a surface of the quantum chip which faces the classical chip.

[0045] The second key feature is using or implementing JJs with a low critical current in the classical chip. This results in a lowering of the switching energy and a broadening of the SFQ pulse duration, e.g., to a total pulse duration of 20 picoseconds (ps), to a pulse duration equal to or between 10 and 200 ps or 8 and 1000 ps, or to a pulse duration of above 8 ps. Hence, the spectral bandwidth of the emitted radiation is reduced accordingly.

[0046] The first key feature addresses the direct radiation from JJ switching. To prevent the radiation from affecting the quantum circuit, the stack of classical chip and quantum chip may be configured so that the quantum elements of the quantum circuits do not directly face the Josephson junctions of the SFQ circuits (e.g., by orientation or by encapsulation). According to some aspects, the stack of classical chip and quantum chip may be configured so that the quantum elements do not face the SFQ circuits and additionally the SFQ circuits are encapsulated by a radiation absorbing layer. According to some aspects, the quantum chip (or the classical chip) may be oriented so that the quantum elements do not face or face away from the Josephson junctions of the SFQ circuit. According to some aspects, reversal of the quantum chip in a flip-chip configuration may be performed to prevent direct exposure of the quantum chip to high-frequency radiation. According to some aspects, the quantum chip may be covered with, e.g., a ground plane or dense array of resonant antennas to absorb high-frequency radiation generated by the switching SFQ components.

[0047] Reference is now made to Fig. 1, which shows an illustration of an exemplary stack of chips 100 in a flip-chip configuration including a reversed quantum chip 110 . Stack of chipsDocket No. 600248 / 0015 / PCT100 includes a quantum chip 110 and an SFQ chip 120. Quantum chip 110 and SFQ chip 120 are planar or substantially planar. Accordingly, each of quantum chip 110 and SFQ chip 120 have two opposite sides or surfaces, opposite sides 115A and 115B of quantum chip 110 and opposite sides 125A and 125B of SFQ chip 120. The side of the chip on which its main elements are fabricated will be also referred to as the frontside or front surface and the opposite side of the chip will be also referred to as the backside or back surface of the chip. Quantum chip 110 and SFQ chip 120 may be coupled, e.g., via bump bonds 170. Quantum chip 110 includes quantum circuits (not shown) and SFQ chip 120 includes SFQ circuits (not shown). The quantum circuits include quantum elements 130, such as qubits, fabricated on quantum chip 110 on side or surface 115A of quantum chip 110. The SFQ circuits include a plurality of SFQ elements 160. SFQ elements 160 may include superconducting loops interrupted by one or more JJs fabricated on side or surface 125A of SFQ chip 120 (not shown). Quantum chip 110 is reversed such that side or surface 115A, on which quantum elements 130 are disposed, is oriented within stack of chips 100 such that it faces away from or is disposed opposite to side or surface 125A of SFQ chip 120, on which SFQ elements 160 and the one or more JJs, in particular, are disposed.

[0048] In case the substrate of quantum chip 110 is not opaque, like in the typical case of a silicon substrate, the backside or back surface, e.g., the side or surface facing the SFQ circuits, may be covered with a ground plane or a dense array of resonant antennas 140, e.g., low-quality factor (Q) antennas, as shown in Fig. 1, with resonances spanning the required frequency range, e.g. 15GHz to 300GHz. These may be, for example, standard antennas of tens of microns (um) to hundreds of um in lateral size.

[0049] Reference is now made to Fig. 2, which illustrates absorption of high-frequency electromagnetic radiation 180 by an antenna 140 disposed on back surface 115B of a portion of quantum chip 110 of stack of chips 100 of FIG. 1. Antenna 140 may absorb radiation 180 emitted by an SFQ element 160 or a portion thereof (e.g., JJs of SFQ element 160) and dissipate the energy through internal loss, thereby preventing it from reaching the front surface, surface 115A, of quantum chip 110 facing away from SFQ chip 120. Antennas 140 may be made from superconducting materials or from lossier non-superconducting materials, such as copper with impurities or thin films of gold (Au). The absorbed radiation may not reach quantum elements 130 fabricated on surface 115A of quantum chip 110, and it is converted to heat in the quantum chip. This generated heat from absorbing radiation 180 is negligible and does not affect quantum elements 130. A single JJ switching event dissipates an energy of about (|)o*Ic, whereDocket No. 600248 / 0015 / PCT(|)o is the magnetic flux quantum and Ic is the critical current of the JJ. As shown in L. N. Bulaevskii and A. E. Koshelev, “Radiation from a Single Josephson Junction into Free Space due to Josephson Oscillations”, Physical Review Letters 97, 267001 (2006), the amount of energy emitted as radiation is about five orders of magnitude lower, assuming a scenario similar to SFQ circuits, where the JJ is embedded in a dielectric. If using, for example, junctions of about one microampere (uA) critical current, the absorbed energy may be 10A(-26) Joule per bit flip at most. At a switching rate of, e.g., 10 GHz, this amounts to 0.1 femtowatt (fW) per junction, which is well within a working range, if hundreds of millions of junctions are considered.

[0050] According to some aspects, the control pulses from SFQ chip 120 may be transmitted to quantum elements 130 of quantum chip 110 through one or more superconducting coupling vias 150 (or vias 150) connecting the two surfaces, surface 115A and surface 115B, of quantum chip 110. Vias 150 may be either galvanically coupled (direct contact) to the SFQ circuits of SFQ chip 120 or galvanically isolated (e.g., through capacitive or inductive coupling). Vias 150 must traverse the entirety of quantum chip 110, extending a few hundred microns, significantly longer than the quasiparticle diffusion length. Thus, any quasi-particles generated in the coupling on the surface facing the SFQ circuits of SFQ chip 120, e.g., surface 115B, from direct radiation will recombine before affecting quantum elements 130 disposed on surface 115A of quantum chip 110. This allows SFQ pulses to be transmitted and control quantum elements 130 of quantum chip 110 without inducing quasiparticles in close proximity to quantum elements 130.

[0051] The second key feature causes the emitted radiation to include lower frequencies, thereby reducing the potential harm caused by the radiation, e.g. by quasiparticle generation. This may be achieved by causing the JJ switching events to be slower, e.g., broader in time. As a result, the emitted radiation, as well as the generated SFQ control pulses will include fewer high-frequency components.

[0052] The slower switching and resulting slower SFQ pulses may be achieved by using JJs in the classical chip with reduced critical current (e.g., lower than 20 uA, lower than 10 uA, lower than five uA, lower than one uA or equal to 0.2 uA, or between 0.2 uA and 20 uA, 0.2 uA and 10 uA, 0.2 uA and five uA, 0.2 uA and one uA or between 0.01 uA and 5 uA) and sufficiently high inductances (hundreds to thousands of picohenry (pH)) in the superconducting loops. According to some aspects, the classical circuits (e.g., SFQ circuits, such as SFQ circuits of SFQ chip 120 of Fig. 1) may include one or more inductors, where the magnetic inductionDocket No. 600248 / 0015 / PCT of the inductors is hundreds or thousands of picohenry. The term "inductor" may refer to any component, structure, or element that is configured to provide inductance, whether geometric or kinetic including but not limited to discrete inductors, integrated inductive elements, superconducting loops, transmission lines, or vias that exhibit inductive properties, an array of JJs, regardless of their specific physical form or method of fabrication.

[0053] The coupling via traversing the chip also naturally has a high inductance of hundreds of pH. According to some aspects, employing the reversed flip-chip feature without lowering the JJ critical current may lead to impedance-mismatched circuits, suppressing the transfer of SFQ pulses to the quantum elements. The higher inductances to be used in the frame of the second key feature naturally fit the impedance-matching requirements. Additionally, the low critical current has the advantage of reducing the dissipated energy by the switching JJs. In particular, for JJs with one uA critical currents, for example, which is 100 times lower than typical SFQ circuits, the dissipated heat is reduced by a factor of 100.

[0054] Reference is now made to Figures 3 A and 3B. Fig. 3 A shows a graph 200 presenting the output SFQ pulse from a circuit with low JJ critical currents with respect to typical SFQ pulses. Fig. 3B shows a graph 210 presenting the Fourier transforms of the SFQ pulses of Fig. 3 A.

[0055] In Fig. 3A, the output SFQ pulse from a circuit with low JJ critical currents compared to typical SFQ pulse, which are much narrower in time, is shown by presenting voltage Amplitude (arbitrary units; y-axis) as a function of time in picoseconds (ps) (x-axis). A typical pulse in SFQ electronic circuits has a standard deviation ranging from 0.1 picoseconds (ps), as shown by the dashed Gaussian curve (having a standard deviation (c) of 0.1 ps), to two ps (G=2.0), as shown by the dash-dotted Gaussian curve. Using reduced critical currents and increased inductances, a pulse (indicated “SFQ pulse”) shown by the solid curve is created, which is similar to a Gaussian with a standard deviation of approximately 5.0 ps (dotted curve).

[0056] When looking at the Fourier transforms of these pulses, as shown in Fig. 3B, which presents magnitude in logarithmic scale as a function of frequency (in Gigahertz (GHz)) one may observe that the spectral content of the pulses is substantially narrowed, reducing potential harmful effects of high-frequency components, in particular those beyond the spectral gap of aluminum of ~90 GHz.

[0057] According to performed simulations, the spectral weight of SFQ pulses generated via the disclosed systems and methods (and hence of the emitted radiation) above 40 GHz isDocket No. 600248 / 0015 / PCT suppressed by over 90% compared to typical SFQ pulses. As shown in the literature (e.g., in: Liu, Chuan-Hong, et al. "Quasiparticle poisoning of superconducting qubits from resonant absorption of pair-breaking photons." Physical Review Letters 132.1 (2024): 017001), the sensitivity of the quantum element to the emitted electromagnetic radiation below a certain frequency (around 100 GHz, depending on the quantum element geometry) decreases exponentially with decreasing frequency. Thus, the strong suppression of the spectral content of the emitted radiation above frequencies of 40 GHz indicates that these pulses will drastically reduce the harmful effects of radiation impact on the quantum elements.

[0058] As disclosed hereinabove, according to some aspects, the realization of SFQ circuits with such low critical current of JJs may require high inductances (up to hundreds or thousands of pH). In addition, certain SFQ circuit elements may require hundreds of nanohenry (nH) inductances. Such inductances may be achieved, for example, either through JJ arrays or through high kinetic inductance materials, such as Niobium nitride (NbN) and Titanium nitride (TiN), or alloys of Ti and Nb.

[0059] According to some aspects, Granular Aluminum (GrAl) may be used in fabricating the classical circuits (e.g., SFQ circuits). GrAl may enable even higher kinetic inductances. According to some aspects, GrAl may be grown at ultralow temperatures (e.g., lower than 100 Kelvin (K) or at about 70 K) for achieving relatively high kinetic inductances (higher than 1 nH / square (Leonard Jr, Edward, et al. "Digital coherent control of a superconducting qubit." Physical Review Applied 11.1 (2019): 014009)), and integrated with the SFQ circuits using standard lithography, etching, and in-situ ion-milling / etching. The low-temperature growth may create smaller grains, leading to a lower density of superconducting carriers, yet anomalously also to a higher critical temperature Tc. This is unlike the use of impurities, which also reduces the density of superconducting carriers, but does so at the cost of a lower Tc. GrAl has a Tc lower than 3.5 K. Therefore, it is not suitable for standard SFQ circuits operating at 4K. As opposed to that, the disclosed low critical current circuits operate under 1 K, making GrAl a viable option.

[0060] According to some aspects, one or more inductors of the SFQ circuits of the SFQ chip, such as SFQ chip 120 of Fig. 1, are made of high kinetic inductance material. According to some aspects, the high kinetic inductance material is Granular Aluminum (GrAl). According to some aspects, the GrAl is grown at a temperature below 100 Kelvin or at about 70 K.Docket No. 600248 / 0015 / PCT

[0061] A method for fabricating a stack of chips, e.g., to be used in quantum computing, is hereby disclosed. The method may be implemented or applied by the devices and systems disclosed herein, such as stack of chips 100 of Figs. 1 and 2.

[0062] The method includes bonding a quantum chip and a classical chip. The classical chip includes a plurality of Josephson junctions fabricated thereon and the quantum chip includes a plurality of quantum elements fabricated thereon. The quantum chip and the classical chip are bonded such that the plurality of Josephson junctions (or classical circuitry) is not directly facing the plurality of quantum elements (or quantum circuitry) or vice versa.

[0063] According to some aspects, the quantum chip may include first and second opposite surfaces, where the plurality of quantum elements or the quantum circuitry is fabricated on the first surface of the quantum chip. The classical chip may also include first and second opposite surfaces, where the plurality of Josephson junctions or the classical or SFQ circuitry is fabricated on the first surface of the classical chip. The classical chip may then be bonded to the quantum chip such that the second surface of the quantum chip faces the first surface of the classical chip.

[0064] According to some aspects, the method may further include adding, fabricating, integrating or utilizing components, such as a radiation absorbing layer, superconducting coupling vias, radiation absorbing structures and inductors, as described herein. According to some aspects, the method may further include fabricating the quantum chip, the classical chip or the JJs, from materials which have properties as described herein.

[0065] According to some aspects, the plurality of Josephson junctions may have critical current values between ten nanoamperes and five microamperes or equal to two hundred nanoamperes.

[0066] According to some aspects, the classical circuit may include a plurality of inductors. According to some aspects, at least one inductor of the plurality of inductors may have a magnetic induction value of at least one hundred picohenry. According to some aspects, a portion or the entire plurality of inductors may have a magnetic induction value of at least one hundred picohenry.

[0067] According to some aspects, a portion of the classical circuit may be made of high kinetic inductance material. According to some aspects, the high kinetic inductance material may include Granular Aluminum (GrAl), Titanium Niobium Nitride (NbTiN) or Niobium Nitride (NbN).Docket No. 600248 / 0015 / PCT

[0068] According to some aspects, a method for fabricating a quantum processor is further disclosed. The method may include fabricating multiple stacks of chips, where each stack of chips may be fabricated according to the stack of chips fabricating method disclosed hereinabove. According to some aspects, the method for fabricating a quantum processor may further include placing the multiple stacks of chips in a cryogenic environment. The multiple stacks of chips may then be used to perform quantum computation.

[0069] The disclosed systems and methods for mitigating noise generated by SFQ and other Josephson junction (JJ)-based circuits in quantum computing environments introduce a stack of chips architecture in which a quantum chip and a classical chip (e.g., an SFQ chip) are bonded such that the quantum elements do not directly face the Josephson junctions of the classical circuit. This reversed chip orientation, optionally combined with radiation absorbing layers or structures, significantly reduces the direct exposure of quantum elements to high- frequency electromagnetic radiation and phonons generated by JJ switching events. Furthermore, the classical chip is designed with Josephson junctions having low critical current values, which broadens the duration of the output SFQ pulses. This broadening reduces the spectral bandwidth of the emitted radiation, thereby suppressing high-frequency components that are most detrimental to quantum coherence and information integrity.

[0070] The combination of these architectural and circuit-level aspects provides several functional advantages. By orienting the quantum and classical chips such that quantum elements face away from the noise-generating components, and by integrating radiationabsorbing features, the system effectively blocks or dissipates harmful energy before it can impact sensitive quantum states. The use of low critical current Josephson junctions not only reduces the energy released per switching event but also ensures that the resulting SFQ pulses are temporally broader and spectrally narrower. This dramatically lessens the risk of quasiparticle generation and decoherence in the quantum elements. As a result, the disclosed stack of chips enables scalable, high-fidelity quantum computing with improved noise resilience, facilitating the integration of fast, low-power classical control circuitry in close proximity to quantum processors without sacrificing quantum performance.

[0071] The aspects, features and embodiments described above are exemplary and variations are contemplated to be within the scope of the present disclosure. Features of certain embodiments can be combined with features of other aspects; thus, certain aspects can be combinations of features of multiple aspects.Docket No. 600248 / 0015 / PCT

[0072] While several embodiments of the disclosure have been described herein and / or shown in the drawings, it is not intended that the disclosure be limited thereto, as it is intended that the disclosure be as broad in scope as the art will allow and that the specification be read likewise. Therefore, the above description should not be construed as limiting, but merely as exemplifications of particular embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto.

Claims

Docket No. 600248 / 0015 / PCTCLAIMSWhat is Claimed is:

1. A stack of chips, the stack of chips comprising: a quantum chip comprising a quantum circuit, the quantum circuit comprising a plurality of quantum elements fabricated on the quantum chip; a classical chip, bonded to the quantum chip, comprising a classical circuit configured to manipulate or measure the plurality of quantum elements, the classical circuit comprising a plurality of Josephson junctions fabricated on the classical chip; wherein the classical chip is bonded to the quantum chip such that the plurality of quantum elements of the quantum circuit is not directly facing the plurality of Josephson junctions of the classical circuit, and wherein each Josephson junction of the plurality of Josephson junctions is configured to have a critical current value below 20 microamperes.

2. The stack of chips according to claim 1, wherein the classical chip is bonded to the quantum chip such that the plurality of quantum elements of the quantum circuit is not facing the plurality of Josephson junctions of the classical circuit.

3. The stack of chips according to claim 2, wherein: the quantum chip comprises first and second opposite surfaces, the plurality of quantum elements are fabricated on the first surface of the quantum chip, the classical chip comprises first and second opposite surfaces, the plurality of Josephson junctions are fabricated on the first surface of the classical chip, and the classical chip is bonded to the quantum chip such that the second surface of the quantum chip faces the first surface of the classical chip.

4. The stack of chips according to claim 3, wherein the quantum chip further comprises one or more superconducting coupling vias connecting the two opposite surfaces of the quantum chip by traversing the entirety of the quantum chip.

5. The stack of chips according to claim 3, further comprising one or more radiation absorbing structures disposed on the second surface of the quantum chip.

6. The stack of chips according to claim 1, further comprising a radiation absorbing layer encapsulating the classical circuit.

7. The stack of chips according to claim 1, wherein the quantum chip is opaque to high- frequency radiation.Docket No. 600248 / 0015 / PCT8. The stack of chips according to claim 1, wherein each Josephson junction of the plurality of Josephson junctions is configured to have critical current values between ten nanoamperes and five microamperes.

9. The stack of chips according to claim 1, wherein each Josephson junction of the plurality of Josephson junctions is configured to have critical current values equal to two hundred nanoamperes.

10. The stack of chips according to claim 1, wherein the classical circuit comprises a plurality of inductors, and wherein the magnetic induction value of at least one inductor of the plurality of inductors is at least one hundred picohenry.

11. The stack of chips according to claim 1, wherein a portion of the classical circuit is made of high kinetic inductance material.

12. The stack of chips according to claim 11, wherein the high kinetic inductance material is selected from: Granular Aluminum (GrAl), Titanium Niobium Nitride (NbTiN) or Niobium Nitride (NbN).

13. The stack of chips according to claim 12, wherein the GrAl was grown at a temperature below 100 Kelvin.

14. The stack of chips according to claim 1, wherein the duration of pulses output by the classical circuit is above eight picoseconds.

15. A quantum processor comprising at least one stack of chips according to any of claims 1-14.

16. A method for fabricating a stack of chips, the method comprising bonding a quantum chip and a classical chip, the classical chip comprising a plurality of Josephson junctions, having a critical current value below 20 microamperes, fabricated thereon and the quantum chip comprising a plurality of quantum elements fabricated thereon, wherein the quantum chip and the classical chip are bonded such that the plurality of Josephson junctions is not directly facing the plurality of quantum elements.

17. The method according to claim 16, wherein the quantum chip and the classical chip are bonded such that the plurality of Josephson junctions is not facing the plurality of quantum elements.

18. The method according to claim 17, wherein: the quantum chip comprises first and second opposite surfaces, the plurality of quantum elements are fabricated on the first surface of the quantum chip,Docket No. 600248 / 0015 / PCT the classical chip comprises first and second opposite surfaces, the plurality of Josephson junctions are fabricated on the first surface of the classical chip, and the classical chip is bonded to the quantum chip so that the second surface of the quantum chip faces the first surface of the classical chip.

19. The method according to claim 16, wherein the plurality of Josephson junctions has critical current values between ten nanoamperes and five microamperes.

20. The method according to claim 16, wherein the plurality of Josephson junctions has critical current values equal to two hundred nanoamperes.

21. The method according to claim 16, wherein the classical circuit comprises a plurality of inductors, wherein at least one inductor of the plurality of inductors has a magnetic induction value of at least one hundred picohenry.

22. The method according to claim 16, wherein a portion of the classical circuit is made of high kinetic inductance material.

23. The stack of chips according to claim 22, wherein the high kinetic inductance material is selected from: Granular Aluminum (GrAl), Titanium Niobium Nitride (NbTiN) or Niobium Nitride (NbN).

24. A method for fabricating a quantum processor, the method comprises: fabricating multiple stacks of chips, wherein each stack of chips of the multiple stacks of chips is fabricated according to the method of any one of claims 16- 23; and placing the multiple stacks of chips in a cryogenic environment.

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