Sharing tag comparators for reservation stations

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharing tag comparators. One of the methods includes obtaining, by a shared comparator, a broadcast destination tag, wherein the shared comparator operates for an instruction stored in the RSV; selecting, by a selection logic module, a source tag from among tags that include a tag of a first source and a tag of a second source, wherein the first source and the second source are used by the instruction; and comparing, by the shared comparator, the selected tag and the broadcast destination tag.

Description

Attorney Docket No. 56113-0783WO1SHARING TAG COMPARATORS FOR RESERVATION STATIONSBACKGROUND

[0001] This specification relates to devices that contain one or more reservation stations (RSVs) that can assist with out-of-order (OoO) instruction execution on computing devices.

[0002] In modem out-of-order (OoO) processors, instruction throughput (e.g., instructions per cycle (IPC)) typically improves by increasing the OoO window size. Reservation stations (RSVs) are components in OoO processors that hold decoded instructions in an age-order queue until they are ready to be issued for execution by one of multiple execution units. Commonly, an instruction stored by an RSV becomes ready for execution when data needed to execute the instruction, e.g., arguments to an ADD instruction or an address of a LOAD instruction, becomes available. Thus, one of the tasks for an RSV is to determine when such data dependencies have been resolved for an instruction and to then issue the instruction. Generally, RSVs operate by issuing the oldest instruction that is ready to be executed.

[0003] RSVs are one of the components that typically constrain the instruction w indow size. Larger RSVs with more RSV entries can enhance instruction and memory' level parallelism, which helps in improving the IPC.

[0004] However, increasing the effective size of an RSV. e.g., by making the instruction queue deeper or by adding additional RSVs in a distributed design, creates cycle time challenges and constrains the frequency of the processor. A timing path representing the timing of w aking up an instruction, such as a Wake up-Select timing path, can be tied to RSV size and is one of the tightest timing paths in modem OoO CPUs which can constrain overall CPU frequency. Increasing RSV size puts pressure on each component on the Wake up-Select path. For example, wake-up delay increases by increasing the RSV size because the load on the tag broadcast wire increases. In addition, select delay increases because more instructions are participating in the selection process, and determining selection priority among them takes longer. Because IPC and frequency both contribute to overall performance, simply increasing RSV size may not result in higher overall performance because the increased parallelism could be offset by increased delays, e.g., delays caused by increased capacitance from closely packed wires. Increased delays can lead to OoO processing that is limited to a lower frequency.Attorney Docket No. 56113-0783WO1

[0005] Some RSVs attempt to reduce the timing pressure by implementing sequential wake up using a staged and a non-staged bus. This approach can reduce the fanout on the broadcast bus and involve a first source using the non-staged bus and a second source using the staged bus. If both sources become available at the same time, the non-staged bus can wake up a first source immediately, while the staged bus introduces a one-cycle delay by design. However, if the first source was already ready, the second source will still impose a one-cycle delay because it is using the staged bus.SUMMARY

[0006] This specification describes technologies for source elements of an RSV entry’ to share a comparator (CAM) for determining when sources are ready. This arrangement allows both a first source and a second source of an RSV entry to use a non-staged bus, for example, in the case that the first source was already ready. In this specification, a CAM can refer to a comparator for content addressable memory'. CAM is used interchangeably with comparator in the context of this disclosure. A CAM can include an array or register file which takes data to compare and mux down to generate a result. A CAM can refer to a CAM comparator, e.g., an element that compares data indicating content addressable memory. The described techniques use the sharing of a CAM to increase the chances that a producer and consumer can be issued in back to back cycles.

[0007] These technologies generally involve obtaining destination tag broadcasts in an OoO processing system and using at least one shared CAM for comparing the broadcasted tag to source tags of source elements in the RSV. In some cases, the destination tag broadcasts are broadcasted on a staged and non-staged bus. For example, a broadcast on the staged bus can occur in a compute cycle following a broadcast on the non-staged bus. Each source element in the RSV can have a corresponding CAM for comparing a source tag with the broadcasted destination tag. Some source CAMs can obtain the staged signal and some source CAMs can obtain the non-staged signal. A multiplexor (MUX) can be used to combine two or more source tags for comparison which can result in reduced compute cycle delays, e.g., between a producer instruction being selected for execution and a dependent instruction source being set as ready.

[0008] The technologies described in this specification can be implemented so as to realize one or more of the following advantages. For example, techniques can reduce the compute cycle delay between a producer instruction being selected for execution and a dependent instruction source being set as ready. A MUX can be used to obtain sourceAttorney Docket No. 56113-0783WO1 tags from two or more sources to be used by a processing instruction. The MUX can be configured to select the source tag of the source that is not ready in a case where one or more of the other sources are ready. The MUX can provide the not ready source tag to a shared CAM that compares the not ready source tag with a broadcasted destination tag on a non-staged bus. If the not ready source tag matches the broadcasted destination tag, the shared CAM can transmit a signal to wake up the not ready source in the same cycle. This reduces a compute cycle delay in traditional OoO systems because, e.g.. the not ready source does not have to wait for a later staged signal that occurs in a following compute cycle and instructions can be executed in back-to-back compute cycles. Compute cycle processing delays, such as compute cycle delays between instruction execution, can cause substantial latency in program operations.

[0009] These techniques can also reduce the processing delays caused in traditional OoO systems by broadcast wires connected to each source CAM that cany destination tag signals. Such signals, sent in one cycle, can increase capacitance and require repeat buffers or other elements that can further slow processing and increase energy usage. Proposed techniques include staged and non-staged broadcasts, broadcasted in different compute cycles, thus reducing the capacitance issue that is present in existing systems.

[0010] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is an overview of an example system implementation.

[0012] FIG. 2 is a detailed view of an example system implementation.

[0013] FIG. 3 is a flow chart of an example process.

[0014] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0015] FIG. 1 is an overview' of an example OoO processing system 100. The system 100 includes a fetch module 102. a decode module 104, a dispatch module 106. one or more RS Vs 108. an instruction selection module 109a, a CAM sharing source wake up module 109b, a reorder buffer 110, a commit module 112, and a store buffer 114. The variousAttorney Docket No. 56113-0783WO1“modules” as mentioned above may be implemented using various logic circuitry' components, such as AND, OR, NOT. NAND, or XOR gates. Other implementations may choose to use other circuitry components.

[0016] The fetch module 102 retrieves incoming instructions for decoding. The decode module 104 analyzes the incoming instructions to determine their consumers. The dispatch module 106 sends instructions to the RSVs 108. The RSVs 108 can take various forms between a fully distributed and fully unified system.

[0017] The instruction selection module 109a selects an instruction for execution, e.g., based on an age parameter stored with each instruction of the RSV. For example, the instruction selection module 109a can identify a set of instructions from the RSV that each have all sources ready and select an oldest instruction from that set to be executed. Upon selection, or after at least partially being executed, the selected instruction can broadcast a destination tag representing a register where a result of processing is to be written.

[0018] The CAM sharing source wake up module 109b obtains the broadcasted destination tag and can wake up one or more sources based on one or more comparisons between source tags and broadcasted destination tags. Waking up one or more sources can include setting a ready bit associated with the given one or more sources. An instruction whose sources are ready, e.g., as indicated by the CAM sharing source wake up module 109b. can be selected by the instruction selection module 109a.

[0019] Aspects of the instruction selection module 109a and the CAM sharing source wake up module 109b are described in more detail with reference to FIG. 2. After instructions are selected, the instructions are then processed by a reorder buffer 110 and a commit module 112 before reaching the store buffer 114.

[0020] FIG. 2 is a detailed view of an example system 200. The system 200 includes an RSV 202, an instruction selection module 206, a non-staged bus 210, a staged bus 212, and a CAM sharing source wake up module 214 that maintains multiple entries for instructions awaiting execution. Each of the entries can include a shared comparator, e.g., the shared CAM 220 as well as a non-shared comparator, e.g. the CAM 222. The nonstaged bus 210 and the staged bus 212 can include communication pathways within the system 200 to transfer data. The staged bus 212 can perform transfer one or more compute cycles after the non-staged bus 210.

[0021] In general, the instruction selection module 206 obtains RSV instructions 204 and selects a first instruction 208. The first instruction 208 then broadcasts a destination tagAttorney Docket No. 56113-0783WO1 using the non-staged bus 210, e.g., as part of a first compute cycle, and using the staged bus 212, e.g.. as part of a subsequent compute cycle. The CAM sharing source wake up module 214 obtains the broadcasted data and wakes up one or more sources using a set of one or more CAMs and MUXs. Waking up a source can include changing a status of the source from not ready to ready.

[0022] In some cases, the system 200 can perform operations described in reference to FIG. 1. For example, the RSV 202 can be an example of the RSV 108 of FIG. 1. The instruction selection module 206 can be an example of the instruction selection module 109a of FIG. 1. The CAM sharing source wake up module 214 can be an example of the CAM sharing source wake up module 109b of FIG. 1.

[0023] The following describes the operations of the CAM sharing source wake up module 214 in more detail. In some cases, the CAM sharing source wake up module 214 includes one or more CAMs and MUXs associated with one or more instructions stored in the RSV 202. For example, the second instruction 216 can be included in the RSV 202 and the RSV 202 can have elements for managing the second instruction 216, such as a shared CAM XI 220, a CAM 222, and a MUX 234.

[0024] The CAM sharing source wake up module 214 obtains a broadcast destination tag from the non-staged bus 210 and, later in time, can obtain the broadcast destination tag from the staged bus 212. Broadcasting, and using broadcasted information for comparison, by the non-staged bus 210 compared to the staged bus 212 can help avoid a cycle penalty, e.g., due to the CAM sharing source wake up module 214 obtaining the destination tag from the staged bus. The destination tag can be broadcasted from the first instruction entry 208 upon selection by the instruction selection module 206, upon partial execution of a first instruction corresponding to the first instruction entry 208, or upon the first instruction completing its execution, e.g., using one or more execution modules. The instruction selection module 206 can be configured to select the first instruction 208 based on characteristics of the first instruction 208. For example, the instruction selection module 206 can determine an instruction with sources that are ready and that has a largest age parameter, where the age parameter can include a monotonically increasing value counter. The determined instruction can be selected by the instruction selection module 206. In the example of FIG. 2, the instruction selection module 206 selects the first instruction 208.

[0025] Destination tags received from a non-staged and staged bus can be separated in time. For example, the CAM sharing source wake up module 214 can obtain aAttorney Docket No. 56113-0783WO1 destination tag signal from the non-staged bus 210 at a first time and obtain a destination tag signal from the staged bus 212 at a time later than the first time. In some cases, the difference in time corresponds to a clock frequency of a processor of the system 200. For example, the non-staged bus 210 can broadcast a destination tag signal as part of a compute cycle. After the completion of that compute cycle, the staged bus 212 can broadcast the same destination tag signal in a subsequent compute cycle. The staged bus 212 can include a flop module or other element to store the destination tag between broadcasts on the non-staged bus 210 in a first compute cycle and broadcasts on the staged bus 212 in a second compute cycle subsequent to the first compute cycle.

[0026] The shared CAM XI 220 and the CAM X2 222 can each obtain and process signals from at least one of the non-staged bus 210 or the staged bus 212. The shared CAM XI 220 receives a destination tag signal from the non-staged bus 210. The CAM X2 222 receives a destination tag signal from the staged bus 212. Both the shared CAM XI 220 and the CAM X2 222 help manage the wake up of source XI 230 and source X2 232. The shared CAM XI 220 is used as a shared CAM. For example, the shared CAM XI 220 receives signals from the source XI 230 and the source X2 232, e.g., via a signal from the MUX 234. The MUX 234 can select, using signals from the source XI 230 and the source X2 232, a source that is not ready. In some implementations, if the source XI 230 is not ready, it will have priority over the source X2 232. This not ready source can be compared by the shared CAM XI 220 to the destination tag broadcasted on the nonstaged bus 210, e.g., if source XI 230 is not ready it can get priority over source X2 232.

[0027] The shared CAM XI 220 can, in response to comparing a not ready source tag with a destination tag, wake up either the source XI 230 or the source X2 232 (e.g., the source X2 232 can “share” the CAM XI 220 with the source XI 230). For example, the shared CAM XI 220 can wake up the source XI 230 if the MUX 234 selects a tag representing the source XI 230 — indicating that the source XI 230 is not ready — and the selected tag matches the destination tag from the non-staged bus 210. The shared CAM XI 220 can wake up the source X2 232 if the MUX 234 selects a tag representing the source X2 232 — indicating that the source X2 232 is not ready — and the selected tag matches the destination tag from the non-staged bus 210.

[0028] By enabling waking up of sources using a shared CAM and a single broadcast signal, the system 200 can help reduce processing delay caused by broadcast fan out in RSVs with multiple instructions each receiving a destination tag. For example, fan out can be reduced because, per cycle, a destination tag is provided to less than all CAMs forAttorney Docket No. 56113-0783WO1 all instructions in the RSV. Processing can be improved especially in cases where a source has already been set to ready (e.g., the source XI 230). With the shared CAM (e.g., the shared CAM XI 220), if the source XI 230 has already been set to ready and the source X2 232 is not ready, the system 200 saves one entire compute cycle in waking up the source X2 232 because the shared CAM XI 220 can do the waking up that would have, without the shared CAM XI 220 acting as a shared CAM, been performed by the CAM X2 222 in a subsequent compute cycle (e.g., based on the destination tag broadcasted by the staged bus 212).

[0029] In some implementations, the shared CAM XI 220 wakes up the source XI 230 and the CAM X2 wakes up the source X2 232. For example, the CAM X2 222 can obtain a destination tag signal from the staged bus 212. The CAM X2 222 can obtain a source tag from the source X2 232. If the source tag from the source X2 232 matches the destination tag from the staged bus 212, the CAM X2 222 can send a wake-up signal configured to wake up the source X2 232. In some cases, an OR gate 236 can be used to wake up the source X2 232 based on receiving a wake up signal from either the shared CAM XI 220 or the CAM X2 222. Output of the OR gate 236 can include setting a ready bit.

[0030] Operations performed with respect to the second instruct on 216 can be performed with respect to other instructions, such as the Nth instruction 218. Although not shown, such additional instructions can include CAMs, including, e.g., shared CAMs, such as the shared CAM XI 220.

[0031] In some implementations, the system 200 can include a processor that includes an RSV, such as the RSV 202. The RSV can include a plurality of instruction entries for instructions waiting to be executed. Each instruction entry can include one or more source tag elements storing tags that represent one or more sources on which a corresponding instruction depends. For example, the RSV 202 can include the second instruction 216 that includes the source XI 230 and the source X2 232 upon which the second instruction 216 depends.

[0032] An entry of the RSV. such as the RSV 202, can include a first source element, a second source element, a shared comparator, and selection logic. For example, the RSV 202 can include an element for each of the sources XI 230 and X2 232 for the second instruction 216. The RSV 202 can include the shared CAM XI 220 and the MUX 234 to perform selection logic for the shared CAM XI 220. Selection logic can include selecting between a tag of a first source and a tag of a second source, e.g., selecting fromAttorney Docket No. 56113-0783WO1 among tags that include tags for both of the sources XI 230 and X2 232. In some cases, the tag of at least one of the first or second source is stored in that source. In some cases, selection logic can include selecting between a tag of a plurality of different sources which include at least one of a first source and a second source. For example, the selection logic can select between a tag of a first source, a tag of a second source, and a tag of one or more different third source elements.

[0033] A shared comparator, such as the shared CAM XI 220, can be configured to compare a broadcast destination tag to a source tag selected by the selection logic. For example, the shared CAM XI 220 can be configured to compare a destination tag from the non-staged bus 210 with a source tag selected by the MUX 234.

[0034] In some implementations, the selection logic configures the MUX 234 to always select the first source tag whenever the first source is not ready. For example, the MUX 234 can select a tag corresponding to the source XI 230 when the source XI 230 is not ready, e.g., when the source XI 230 has not yet been woken up. A source might not be ready if a producer instruction, configured to generate data to be used as the source, has not yet been selected or has not yet executed and generated the required data for the source.

[0035] In some implementations, the selection logic is configured to select the second source tag when the first source is ready. For example, the MUX 234 can select a tag corresponding to the source X2 232 when data from the source XI 230 indicates that the source XI 230 is ready.

[0036] In some implementations, each entry' of the RSV further includes a non-shared comparator configured to compare the destination tag to the second source tag. For example, the CAM X2 222 can be a non-shared comparator, e.g., that compares a destination tag corresponding to the first instruction 208 with a tag corresponding to the source X2 232.

[0037] In some implementations, each entry further includes a staging element configured to store the destination tag. wherein the non-shared comparator is configured to read the destination tag from the staging element. For example, the CAM X2 222 can obtain a broadcast destination tag from the staged bus 212. The staged bus 212 can store a destination tag broadcasted by the first instruction 208. The staged bus 212 can be an example of a staging element.

[0038] In some implementations, the RSV is configured to designate the first source element as ready for execution when the shared comparator determines that theAttorney Docket No. 56113-0783WO1 destination tag matches the first source tag. For example, the RSV 202 can designate the source XI 230 as ready for execution when the shared CAM XI 220 determines that the destination tag matches a tag corresponding to the source XI 230. In some cases, the RSV 202 can designate the source XI 230 using a signal transmitted by the shared CAM XI 220 to the source XI 230.

[0039] In some implementations, the RSV is configured to designate the second source element as ready for execution when the shared comparator or the non-shared comparator determine that the destination tag matches the second source tag. For example, either the shared CAM XI 220 or the CAM X2 222 can be used to compare a destination tag to a tag of the source X2 232 and transmit a signal configured to wake up the source X2 232.

[0040] In some implementations, the RSV is configured to issue an instruction when both the first source element and the second source element are designated as ready for execution. For example, the RSV 202 can issue the second instruction 216 after the source XI 230 and the source X2 232 are ready.

[0041] FIG. 3 is a flowchart of an example process 300. For convenience, the process 300 will be described as being performed by a system of one or more computers, located in one or more locations, and programmed appropriately in accordance with this specification. For example, a system, e.g., the system 100 of FIG. 1 or the system 200 of FIG. 2, appropriately programmed, can perform the process 300.

[0042] The process 300 includes obtaining a broadcast destination tag (302). For example, a shared comparator, such as the shared CAM XI 220, can obtain a broadcast destination tag, such as a destination tag broadcasted on the non-staged bus 210.

[0043] The process 300 includes selecting a source tag from among tags that include a tag of a first source and a tag of a second source (304). For example, a selection logic module can select a tag from one or more source tags, such as the MUX 234 selecting a tag from among a tag of the source XI 230 and the source X2 232. A first source and second source can be used by the instruction, such as the instruction 208.

[0044] The process 300 includes comparing the selected tag and the broadcast destination tag (306). For example, a shared comparator, such as the shared CAM XI 220, can compare a destination tag and a selected source tag, e.g., a destination tag received from the non-staged bus 210 and a destination tag selected from tags representing the source XI 230 and the source X2 232.

[0045] The subject matter and the actions and operations described in this specification can be implemented in digital electronic circuitry, in tangibly -embodied computerAttorney Docket No. 56113-0783WO1 software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The subject matter and the actions and operations described in this specification can be implemented as or in one or more computer programs, e.g., one or more modules of computer program instructions, encoded on a computer program carrier, for execution by, or to control the operation of, data processing apparatus. The carrier can be a tangible non-transitory computer storage medium. Alternatively or in addition, the carrier can be an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be or be part of a machine-readable storage device, a machine- readable storage substrate, a random or serial access memory device, or a combination of one or more of them. A computer storage medium is not a propagated signal.

[0046] The term “data processing apparatus” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. Data processing apparatus can include special-purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit) , or a GPU (graphics processing unit). The apparatus can also include, in addition to hardware, code that creates an execution environment for computer programs, e.g.. code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0047] A computer program can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it can be deployed in any form, including as a stand-alone program, e.g., as an app, or as a module, component, engine, subroutine, or other unit suitable for executing in a computing environment, which environment may include one or more computers interconnected by a data communication network in one or more locations.

[0048] A computer program may, but need not, correspond to a file in a file system. A computer program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code.Attorney Docket No. 56113-0783WO1

[0049] The processes and logic flows described in this specification can be performed by one or more computers executing one or more computer programs to perform operations by operating on input data and generating output. The processes and logic flows can also be performed by special-purpose logic circuitry, e.g., an FPGA, an ASIC, or a GPU, or by a combination of special-purpose logic circuitry and one or more programmed computers.

[0050] Computers suitable for the execution of a computer program can be based on general or special-purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory or a random access memory' or both. The essential elements of a computer are a central processing unit for executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by, or incorporated in, special-purpose logic circuitry.

[0051] Generally, a computer will also include, or be operatively coupled to, one or more mass storage devices, and be configured to receive data from or transfer data to the mass storage devices. The mass storage devices can be, for example, magnetic, magnetooptical, or optical disks, or solid state drives. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0052] To provide for interaction with a user, the subject matter described in this specification can be implemented on one or more computers having, or configured to communicate with, a display device, e g., a LCD (liquid crystal display) monitor, or a virtual-reality’ (VR) or augmented-reality (AR) display, for displaying information to the user, and an input device by which the user can provide input to the computer, e.g., a keyboard and a pointing device, e.g., a mouse, a trackball or touchpad. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback and responses provided to the user can be any form of sensory’ feedback, e.g., visual, auditory, speech, or tactile feedback or responses; and input from the user can be received in any form, including acoustic, speech, tactile, or eye tracking input, including touch motion or gestures, or kinetic motion or gestures or orientation motion or gestures. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user’s device in response to requests received from the web browser, orAttorney Docket No. 56113-0783WO1 by interacting with an app running on a user device, e.g., a smartphone or electronic tablet. Also, a computer can interact with a user by sending text messages or other forms of message to a personal device, e.g., a smartphone that is running a messaging application, and receiving responsive messages from the user in return.

[0053] This specification uses the term “configured to” in connection with sy stems, apparatus, and computer program components. That a system of one or more computers is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions. That special-purpose logic circuitry is configured to perform particular operations or actions means that the circuitry has electronic logic that performs the operations or actions.

[0054] The subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet.

[0055] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some implementations, a server transmits data, e.g., an HTML page, to a user device, e.g., for purposes of displaying data to and receiving user input from a user interacting with the device, which acts as a client. Data generated at the user device, e.g., a result of the user interaction, can be received at the server from the device.

[0056] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what is being claimed, which isAttorney Docket No. 56113-0783WO1 defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claim may be directed to a subcombination or variation of a subcombination.

[0057] Similarly, while operations are depicted in the drawings and recited in the claims in a particular order, this by itself should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0058] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Aspects and embodiments of the disclosed subject matter may be as set out in the following numbered examples. The following examples may be combined in any suitable way. For example, while examples I to 11 relate to a processor, the features of examples 1 to 11 may be included in method examples 12 to 21.Example 1. A processor comprising: a reservation station (RSV) comprising: a plurality of instruction entries for instructions waiting to be executed, wherein each instruction entry comprises a one or more source elementsAttorney Docket No. 56113-0783WO1 configured to store tags that represent one or more sources on which a corresponding instruction depends, wherein an entry of the RSV comprises: a first source element, a second source element, a shared comparator, and selection logic configured to select between a tag of the first source element and a tag of the second source element, wherein the shared comparator is configured to compare a broadcast destination tag to a source tag selected by the selection logic.Example 2. The processor of example 1, wherein the entry of the RSV comprises a third source element and the selection logic is configured to select between the tag of the first source element, the tag of the second source element, and a tag of the third source element.Example 3. The processor of any one of examples 1-2, wherein the selection logic is configured to select the first source tag when the first source is not ready.Example 4. The processor of any one of examples 1-3, wherein the selection logic is configured to select the second source tag when the first source is ready.Example 5. The processor of any one of examples 1-4, wherein the processor comprises a staged bus and a non-staged bus configured to carry destination tags, and wherein the selection logic is configured to cause the second source tag to be compared to a destination tag received on the non-staged bus when the first source is ready.Example 6. The processor of any one of examples 1-5, wherein the comparing the second source tag to the destination tag when the first source is ready avoids a cycle penalty due to obtaining the destination tag from the staged bus.Example 7. The processor of any one of examples 1-6, wherein each entry further comprises a non-shared comparator configured to compare the broadcast destination tag to the second source tag.Attorney Docket No. 56113-0783WO1Example 8. The processor of any one of examples 1-7, each entry further comprises a staging element configured to store the destination tag, wherein the nonshared comparator is configured to read the destination tag from the staging element.Example 9. The processor of any one of examples 1-8, wherein the RSV is configured to designate the first source element as ready for execution when the shared comparator determines that the destination tag matches the first source tag.Example 10. The processor of any one of examples 1-10, wherein the RSV is configured to designate the second source element as ready for execution when the shared comparator or the non-shared comparator determine that the destination tag matches the second source tag.Example 11. The processor of any one of examples 1-10, wherein the RSV is configured to issue an instruction when both the first source element and the second source element are designated as ready for execution.Example 12. A method performed by a processor having a reservation station (RSV). the method comprising: obtaining, by a shared comparator, a broadcast destination tag, wherein the shared comparator operates for an instruction stored in the RSV ; selecting, by a selection logic module, a source tag from among tags that include a tag of a first source and a tag of a second source, wherein the first source and the second source are used by the instruction; and comparing, by the shared comparator, the selected tag and the broadcast destination tag.Example 13. The method of example 12. wherein selecting the source tag comprises: selecting the tag of the first source when the first source is not ready.Example 14. The method of any one of examples 12-13. wherein selecting the source tag comprises:Attorney Docket No. 56113-0783WO1 selecting the tag of the second source when the first source is ready.Example 15. The method of any one of examples 12-14, wherein the processor comprises a staged bus and a non-staged bus to carry destination tags, and further comprising comparing the second source tag to a destination tag received on the nonstaged bus when the first source is ready.Example 16. The method of any one of examples 12-15, wherein the comparing the second source tag to the destination tag when the first source is ready avoids a cycle penalty due to obtaining the destination tag from the staged bus.Example 17. The method of any one of examples 12-16, comprising: determining, based on the comparison, that the selected tag and the broadcast destination tag match; and in response to determining that the selected tag and the broadcast destination tag match, designating a source corresponding to the selected tag as ready.Example 18. The method of any one of examples 12-17, comprising: issuing the instruction when both the first source and the second source are designated as ready for execution.Example 19. The method of any one of examples 12-18, comprising: based on the comparison, designating the first source as ready; determining the second source was previously designated as ready; and issuing the instruction that uses both the first source and the second source.Example 20. The method of any one of examples 12-19, comprising: based on the comparison, designating the first source as ready; based on a comparison of a non-shared comparator, designating the second source as ready; and issuing the instruction that uses both the first source and the second source.Example 21. The method of any one of examples 12-20. comprising:Attorney Docket No. 56113-0783WO1 obtaining, by the non-shared comparator, the broadcast destination tag from a staging element configured to store the destination tag; and comparing, by the non-shared comparator, the tag of the first source to the broadcast destination tag.

[0059] What is claimed is:

Claims

Attorney Docket No. 56113-0783WO1CLAIMS1. A processor comprising: a reservation station (RSV) comprising: a plurality of instruction entries for instructions waiting to be executed, wherein each instruction entry comprises a one or more source elements configured to store tags that represent one or more sources on which a corresponding instruction depends, wherein an entry of the RSV comprises: a first source element, a second source element, a shared comparator, and selection logic configured to select between a tag of the first source element and a tag of the second source element, wherein the shared comparator is configured to compare a broadcast destination tag to a source tag selected by the selection logic.

2. The processor of claim 1, wherein the entry7of the RSV comprises a third source element and the selection logic is configured to select between the tag of the first source element, the tag of the second source element, and a tag of the third source element.

3. The processor of any one of claims 1-2, wherein the selection logic is configured to select the first source tag when the first source is not ready.

4. The processor of any one of claims 1-3, wherein the selection logic is configured to select the second source tag when the first source is ready.

5. The processor of any one of claims 1-4, wherein the processor comprises a staged bus and a non-staged bus configured to carry destination tags, and wherein the selection logic is configured to cause the second source tag to be compared to a destination tag received on the non-staged bus when the first source is ready.Attorney Docket No. 56113-0783WO16. The processor of any one of claims 1-5, wherein the comparing the second source tag to the destination tag when the first source is ready avoids a cycle penalty due to obtaining the destination tag from the staged bus.

7. The processor of any one of claims 1-6, wherein each entry7further comprises a non-shared comparator configured to compare the broadcast destination tag to the second source tag.

8. The processor of any one of claims 1-7, each entry7further comprises a staging element configured to store the destination tag, wherein the non-shared comparator is configured to read the destination tag from the staging element.

9. The processor of any one of claims 1-8, wherein the RSV is configured to designate the first source element as ready for execution when the shared comparator determines that the destination tag matches the first source tag.

10. The processor of any one of claims 1-10, wherein the RSV is configured to designate the second source element as ready for execution when the shared comparator or the non-shared comparator determine that the destination tag matches the second source tag.

11. The processor of any one of claims 1-10, wherein the RSV is configured to issue an instruction when both the first source element and the second source element are designated as ready for execution.

12. A method performed by a processor having a reservation stat on (RSV), the method comprising: obtaining, by a shared comparator, a broadcast destination tag, wherein the shared comparator operates for an instruction stored in the RSV; selecting, by a selection logic module, a source tag from among tags that include a tag of a first source and a tag of a second source, wherein the first source and the second source are used by the instruction; and comparing, by the shared comparator, the selected tag and the broadcast destination tag.Attorney Docket No. 56113-0783WO113. The method of claim 12, wherein selecting the source tag comprises: selecting the tag of the first source when the first source is not ready.

14. The method of any one of claims 12-13, wherein selecting the source tag comprises: selecting the tag of the second source when the first source is ready.

15. The method of any one of claims 12-14, wherein the processor comprises a staged bus and a non-staged bus to carry destination tags, and further comprising comparing the second source tag to a destination tag received on the non-staged bus when the first source is ready.

16. The method of any one of claims 12-15, wherein the comparing the second source tag to the destination tag when the first source is ready avoids a cycle penalty due to obtaining the destination tag from the staged bus.

17. The method of any one of claims 12-16, comprising: determining, based on the comparison, that the selected tag and the broadcast destination tag match; and in response to determining that the selected tag and the broadcast destination tag match, designating a source corresponding to the selected tag as ready.

18. The method of any one of claims 12-17, comprising: issuing the instruction when both the first source and the second source are designated as ready for execution.

19. The method of any one of claims 12-18, comprising: based on the comparison, designating the first source as ready; determining the second source was previously designated as ready; and issuing the instruction that uses both the first source and the second source.

20. The method of any one of claims 12-19, comprising: based on the comparison, designating the first source as ready;Attorney Docket No. 56113-0783WO1 based on a comparison of a non-shared comparator, designating the second source as ready; and issuing the instruction that uses both the first source and the second source.

21. The method of any one of claims 12-20, comprising: obtaining, by the non-shared comparator, the broadcast destination tag from a staging element configured to store the destination tag; and comparing, by the non-shared comparator, the tag of the first source to the broadcast destination tag.

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