Pixel driving circuit and driving method therefor, and display device

Abstract

A pixel driving circuit and a driving method therefor, and a display device. The pixel driving circuit comprises: a driving sub-circuit configured to, under the control of signals of a first node and a second node, provide a driving signal to a third node; a first control sub-circuit configured to, under the control of a signal of a first scan signal line, control a signal of the first node by means of at least one among a signal of a third node and a signal of at least one of a data signal line and a reference signal line; a second control sub-circuit configured to, under the control of a signal of a second scan signal line, provide a signal of a first initial signal line to the first node and provide a signal of a second initial signal line to a fourth node; and a third control sub-circuit configured to, under the control of signals of the first scan signal line and the second scan signal line, provide a signal of a first power supply line to the second node and provide a signal of the third node to the fourth node.

Description

Pixel driving circuit and its driving method, display device

[0001] This application claims priority to Chinese Patent Application No. 202411466137.6, filed on October 18, 2024, entitled "Pixel Driving Circuit and Driving Method Thereof, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a pixel driving circuit and driving method thereof, as well as a display device.

[0006] In a first aspect, this disclosure provides a pixel driving circuit, including: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit;

[0007] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0008] The first control sub-circuit is electrically connected to the first scan signal line, the data signal line, the reference signal line, the first node, and the third node, respectively, and is configured to control the signal of the first node through the signal of at least one of the data signal line and the reference signal line and the signal of the third node under the control of the signal of the first scan signal line.

[0009] The second control sub-circuit is electrically connected to the second scan signal line, the first initial signal line, the second initial signal line, the first node, and the fourth node, respectively, and is configured to provide the first initial signal line signal to the first node and the second initial signal line signal to the fourth node under the control of the signal of the second scan signal line.

[0010] The third control sub-circuit is electrically connected to the first scan signal line, the second scan signal line, the first power line, the second node, the third node, and the fourth node, respectively. It is configured to provide the first power line signal to the second node and the third node signal to the fourth node under the control of the signals of the first scan signal line and the second scan signal line.

[0011] In an exemplary embodiment, the first control sub-circuit includes: a first write sub-circuit, a second write sub-circuit, a storage sub-circuit, and a connection sub-circuit;

[0012] The first write sub-circuit is electrically connected to the first scan signal line, the data signal line and the fifth node respectively, and is configured to provide the data signal line signal to the fifth node under the control of the signal of the first scan signal line;

[0013] The second write sub-circuit is electrically connected to the first scan signal line, the reference signal line and the fifth node respectively, and is configured to provide the reference signal line signal to the fifth node under the control of the signal of the first scan signal line;

[0014] The storage sub-circuit is electrically connected to the first node and the fifth node respectively, and is configured to store the voltage difference between the signals of the first node and the fifth node.

[0015] The connecting sub-circuit is electrically connected to the first scan signal line, the first node, and the third node, respectively, and is configured to connect the first node and the third node under the control of the signal from the first scan signal line.

[0016] In an exemplary embodiment, the first write sub-circuit includes a fourth transistor, the second write sub-circuit includes an eighth transistor, the communication sub-circuit includes a second transistor, and the storage sub-circuit includes a capacitor, which includes a first plate and a second plate.

[0017] The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0018] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0019] The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the reference signal line, and the second electrode of the eighth transistor is electrically connected to the fifth node.

[0020] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the fifth node.

[0021] In an exemplary embodiment, the second control sub-circuit includes a first transistor and a seventh transistor, and the third control sub-circuit includes a fifth transistor and a sixth transistor;

[0022] The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node.

[0023] The control electrode of the fifth transistor is electrically connected to the second scan signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node.

[0024] The control electrode of the sixth transistor is electrically connected to the first scan signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0025] The control electrode of the seventh transistor is electrically connected to the second scan signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0026] In an exemplary embodiment, the driving sub-circuit includes a third transistor; the first control sub-circuit includes a second transistor, a fourth transistor, an eighth transistor, and a capacitor, the capacitor including a first plate and a second plate; the second control sub-circuit includes a first transistor and a seventh transistor; and the third control sub-circuit includes a fifth transistor and a sixth transistor.

[0027] The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node.

[0028] The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0029] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0030] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0031] The control electrode of the fifth transistor is electrically connected to the second scan signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node.

[0032] The control electrode of the sixth transistor is electrically connected to the first scan signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0033] The control electrode of the seventh transistor is electrically connected to the second scan signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0034] The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the reference signal line, and the second electrode of the eighth transistor is electrically connected to the fifth node.

[0035] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the fifth node.

[0036] In an exemplary embodiment, at least two of the first transistor, the second transistor, the fourth transistor, and the seventh transistor are of the same transistor type;

[0037] At least two of the fifth, sixth, and eighth transistors are of the same transistor type;

[0038] The transistor types of at least one of the first, second, fourth, and seventh transistors and at least one of the fifth, sixth, and eighth transistors are opposite.

[0039] In an exemplary embodiment, the signal lines connected to at least one row of pixel driving circuits satisfy at least one of the following conditions: the signal received by the reference signal line is the same as the signal received by the first power line, and the signal received by the first initial signal line is the same as the signal received by the second initial signal line.

[0040] In an exemplary embodiment, the pixel driving circuit has multiple rows, and the signal received by the second scan signal line connected to at least one row of pixel driving circuits is the same as the signal received by the first scan signal line connected to the previous row of pixel driving circuits.

[0041] In a second aspect, this disclosure also provides a display device, including a substrate, the substrate having a display area and a non-display area located in at least one of the display areas, the display area having the aforementioned pixel driving circuit, a plurality of first scan signal lines and a plurality of second scan signal lines arranged in an array, and the non-display area having a gate driving circuit;

[0042] The gate drive circuit is electrically connected to at least one first scan signal line and at least one second scan signal line, respectively.

[0043] In an exemplary embodiment, the gate drive circuit includes: M+1 cascaded shift registers;

[0044] The first-level shift register is electrically connected to the second scan signal line of the first row pixel driving circuit. The m-th level shift register is electrically connected to the first scan signal line of the (m-1)-th row pixel driving circuit and the second scan signal line of the m-th row pixel driving circuit, respectively. The M+1-th level shift register is electrically connected to the first scan signal line of the M-th row pixel driving circuit. m is a positive integer greater than 1 and less than M.

[0045] In an exemplary embodiment, at least one pixel driving circuit is connected to two first scan signal lines, the first scan signal lines extending at least partially along a first direction;

[0046] The first scan signal line connected to at least one pixel driving circuit has a single-layer structure, and the second scan signal line connected to at least one pixel driving circuit includes a first scan line and a second scan line that are interconnected and arranged in different layers.

[0047] The orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate at least partially overlap, and at least one of the first scan line and the second scan line is located on the side of the first scan line away from the substrate.

[0048] In an exemplary embodiment, at least one pixel driving circuit is connected to two second scan signal lines, the second scan signal lines extending at least partially along a first direction;

[0049] The first second scan signal line connected to at least one pixel driving circuit has a single-layer structure, and the second second scan signal line connected to at least one pixel driving circuit includes a third scan line and a fourth scan line that are interconnected and arranged in different layers.

[0050] The orthographic projection of the third scan line on the substrate at least partially overlaps with the orthographic projection of the fourth scan line on the substrate, and at least one of the third and fourth scan lines is located on the side of the first and second scan signal lines away from the substrate.

[0051] In an exemplary embodiment, at least one pixel driving circuit is connected to two first scan signal lines and two second scan signal lines respectively;

[0052] The orthographic projection of one of the two second scan signal lines connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first first scan signal line connected to at least one pixel driving circuit on the substrate and the orthographic projection of the second first scan signal line connected to at least one pixel driving circuit on the substrate. The orthographic projection of the other signal line connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of one of the two first scan signal lines connected to at least one pixel driving circuit away from the orthographic projection of the other signal line connected to at least one pixel driving circuit on the substrate.

[0053] In an exemplary embodiment, the orthographic projections of the first first scan signal line connected to at least one pixel driving circuit on the substrate, the orthographic projections of the second second scan signal line on the substrate, the orthographic projections of the second first scan signal line on the substrate, and the orthographic projections of the first second scan signal line on the substrate are arranged sequentially along a second direction, wherein the first direction and the second direction intersect.

[0054] In an exemplary embodiment, it further includes: a plurality of first initial signal lines, at least one of the plurality of first initial signal lines extending at least partially along a first direction;

[0055] The orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first second scan signal line connected to the pixel driving circuit on the substrate.

[0056] In an exemplary embodiment, it further includes: a plurality of second initial signal lines, at least one of the plurality of second initial signal lines extending at least partially along a first direction;

[0057] The orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate is located on the side away from the orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate.

[0058] In an exemplary embodiment, it further includes: a plurality of data signal lines and a plurality of first power lines; at least one of the plurality of data signal lines and at least one of the plurality of first power lines extend at least partially along a second direction, wherein the first direction and the second direction intersect.

[0059] The display device further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; at least one pixel driving circuit including: at least one capacitor and at least one transistor; at least one transistor including: at least one P-type transistor and at least one N-type transistor; at least one capacitor including: a first electrode plate and a second electrode plate.

[0060] The first semiconductor layer includes at least: an active pattern of at least one P-type transistor of at least one pixel driving circuit;

[0061] The first conductive layer includes at least: at least one first scan signal line and one second scan signal line connected to at least one pixel driving circuit, and a first plate of a capacitor located in at least one pixel driving circuit;

[0062] The second conductive layer includes at least: a first scan line of a second first scan signal line connected to at least one pixel driving circuit, a third scan line of a second second scan signal line and a second initial signal line, and a second plate of a capacitor located in at least one pixel driving circuit;

[0063] The second semiconductor layer includes at least: an active pattern of at least one N-type transistor of at least one pixel driving circuit;

[0064] The third conductive layer includes at least: a second scan line of the second first scan signal line connected to at least one pixel driving circuit, a fourth scan line of the second second scan signal line, and a first initial signal line;

[0065] The fourth conductive layer includes at least: the first and second electrodes of at least one transistor of at least one pixel driving circuit;

[0066] The fifth conductive layer includes at least: at least one first power line and data signal line connected to a pixel driving circuit.

[0067] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0068] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0069] The first control sub-circuit, under the control of the signal of the first scan signal line, controls the signal of the first node through the signal of at least one of the data signal line and the reference signal line and the signal of the third node.

[0070] Under the control of the signal from the second scan signal line, the second control sub-circuit provides the signal from the first initial signal line to the first node and the signal from the second initial signal line to the fourth node;

[0071] The third control sub-circuit, under the control of the signals from the first and second scan signal lines, provides the first power line signal to the second node and the third node signal to the fourth node.

[0072] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0073] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0074] Overview of the attached figures

[0075] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0076] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0077] Figure 2 is a schematic diagram of the first control sub-circuit;

[0078] Figure 3 is the equivalent circuit diagram of the first control sub-circuit provided in Figure 2;

[0079] Figure 4 shows the equivalent circuit diagram of the second control sub-circuit and the drive sub-circuit;

[0080] Figure 5 shows the equivalent circuit diagram of the third control sub-circuit;

[0081] Figure 6 shows the equivalent circuit diagram of the pixel driving circuit.

[0082] Figure 7 shows the equivalent circuit diagram of the pixel driving circuit (II).

[0083] Figure 8 is the first driving timing diagram of the pixel driving circuit provided in Figure 6;

[0084] Figure 9 is the second driving timing diagram of the pixel driving circuit provided in Figure 6;

[0085] Figure 10 is the first driving timing diagram of the pixel driving circuit provided in Figure 7;

[0086] Figure 11 is the second driving timing diagram of the pixel driving circuit provided in Figure 7;

[0087] Figure 12 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure;

[0088] Figure 13 is a top view of the display area of ​​the display device shown in Figure 12;

[0089] Figure 14 is a schematic diagram of a portion of the film layers in Figure 13;

[0090] Figure 15 is a schematic diagram of the structure of the first and second scan signal lines connected by the pixel driving circuit.

[0091] Figure 16 is a schematic diagram of the pattern of the first semiconductor layer in Figure 13;

[0092] Figure 17 is a schematic diagram of the first conductive layer pattern in Figure 13;

[0093] Figure 18 is a schematic diagram after the first conductive layer pattern is formed in Figure 13;

[0094] Figure 19 is a schematic diagram of the second conductive layer pattern in Figure 13;

[0095] Figure 20 is a schematic diagram after the second conductive layer pattern is formed in Figure 13;

[0096] Figure 21 is a schematic diagram of the pattern of the second semiconductor layer in Figure 13;

[0097] Figure 22 is a schematic diagram after the second semiconductor layer pattern is formed in Figure 13;

[0098] Figure 23 is a schematic diagram of the third conductive layer pattern in Figure 13;

[0099] Figure 24 is a schematic diagram after the formation of the third conductive layer pattern in Figure 13;

[0100] Figure 25 is a schematic diagram after the fifth insulating layer pattern is formed in Figure 13;

[0101] Figure 26 is a schematic diagram of the fourth conductive layer pattern in Figure 13;

[0102] Figure 27 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 13;

[0103] Figure 28 is a schematic diagram of the planarization layer pattern formed in Figure 13;

[0104] Figure 29 is a schematic diagram of the fifth conductive layer pattern in Figure 13;

[0105] Figure 30 is a schematic diagram of the fifth conductive layer pattern formed in Figure 13.

[0106] Detailed Explanation

[0107] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0108] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0109] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0110] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0111] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0112] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0113] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0114] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0115] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0116] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0117] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0118] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0119] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0120] The display product includes a display area and a non-display area. The display area has at least one sub-pixel, and each sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby realizing the display. The non-display area has a driving circuit that provides control signals to the pixel driving circuit. The pixel driving circuit has many signal lines, resulting in a large number of driving circuits that need to provide control signals to it. This leads to a larger area in the non-display area, making it impossible to achieve a narrow bezel.

[0121] Therefore, this disclosure provides a pixel driving circuit.

[0122] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. As shown in Figure 1, the pixel driving circuit provided in this embodiment of the disclosure is configured to drive the light-emitting device L to emit light. The pixel driving circuit may include: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit.

[0123] As shown in Figure 1, the driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0124] As shown in Figure 1, the first control sub-circuit is electrically connected to the first scan signal line Gate1, the data signal line Data, the reference signal line REF, the first node N1, and the third node N3, respectively. It is configured to control the signal of the first node N1 through at least one of the signals of the data signal line Data and the reference signal line REF and at least one of the signals of the third node N3, under the control of the signal of the first scan signal line Gate1.

[0125] As shown in Figure 1, the second control sub-circuit is electrically connected to the second scan signal line Gate2, the first initial signal line INIT1, the second initial signal line INIT2, the first node N1, and the fourth node N4, respectively. It is configured to provide the signal of the first initial signal line INIT1 to the first node N1 and the signal of the second initial signal line INIT2 to the fourth node N4 under the control of the signal of the second scan signal line Gate2.

[0126] As shown in Figure 1, the third control sub-circuit is electrically connected to the first scan signal line Gate1, the second scan signal line Gate2, the first power supply line VDD, the second node N2, the third node N3, and the fourth node N4, respectively. It is configured to provide the first power supply line VDD signal to the second node N2 and the third node N3 signal to the fourth node N4 under the control of the signals of the first scan signal line Gate1 and the second scan signal line Gate2.

[0127] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device L to emit light.

[0128] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0129] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0130] In an exemplary embodiment, the light-emitting device L may include a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the first electrode of the light-emitting device is electrically connected to a fourth node N4 in a pixel driving circuit, and the second electrode of the light-emitting device is electrically connected to a second power line VSS.

[0131] In an exemplary embodiment, the voltage value of the signal on the first initial signal line INIT1 is constant and is a DC signal; the voltage value of the signal on the first initial signal line INIT1 can be -3V. In an exemplary embodiment, a DC signal can be one in which neither the magnitude nor the direction of the signal changes with time.

[0132] In an exemplary embodiment, the voltage value of the signal on the second initial signal line INIT2 is constant and is a DC signal; the voltage value of the signal on the second initial signal line INIT2 can be 0V.

[0133] In an exemplary embodiment, the voltage value of the reference signal line REF is constant and is a DC signal.

[0134] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0135] The pixel driving circuit in this disclosure is electrically connected only to the first and second scan signal lines that provide control signals, which reduces the number of signal lines that provide control signals to the pixel driving circuit, thereby reducing the number of driving circuits and reducing the area occupied by non-display areas, thus realizing a display product.

[0136] In an exemplary embodiment, FIG2 is a schematic diagram of the structure of the first control sub-circuit. As shown in FIG2, the first control sub-circuit may include: a first write sub-circuit, a second write sub-circuit, a storage sub-circuit, and a connection sub-circuit.

[0137] As shown in Figure 2, the first write sub-circuit is electrically connected to the first scan signal line Gate1, the data signal line Data, and the fifth node N5, respectively, and is configured to provide the data signal line Data to the fifth node N5 under the control of the signal of the first scan signal line Gate1.

[0138] As shown in Figure 2, the second write sub-circuit is electrically connected to the first scan signal line Gate1, the reference signal line REF, and the fifth node N5, respectively, and is configured to provide the reference signal line REF to the fifth node N5 under the control of the signal of the first scan signal line Gate1.

[0139] As shown in Figure 2, the storage sub-circuit is electrically connected to the first node N1 and the fifth node N5 respectively, and is configured to store the voltage difference between the signals of the first node N1 and the fifth node N5.

[0140] As shown in Figure 2, the connected sub-circuit is electrically connected to the first scan signal line Gate1, the first node N1 and the third node N3 respectively, and is configured to connect the first node N1 and the third node N3 under the control of the signal of the first scan signal line Gate1.

[0141] Figure 3 is an equivalent circuit diagram of the first control sub-circuit provided in Figure 2. As shown in Figure 3, in an exemplary embodiment, the first write sub-circuit may include a fourth transistor T4. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. The fourth transistor T4 may be referred to as the data write transistor.

[0142] As shown in Figure 3, in an exemplary embodiment, the second write sub-circuit may include an eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the first scan signal line Gate1, the first electrode of the eighth transistor T8 is electrically connected to the reference signal line REF, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5.

[0143] As shown in Figure 3, in an exemplary embodiment, the connected sub-circuit may include a second transistor T2. The control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3.

[0144] As shown in Figure 3, in an exemplary embodiment, the storage sub-circuit may include a capacitor C, which may include a first plate C1 and a second plate C2. The first plate C1 of capacitor C is electrically connected to a first node N1, and the second plate C2 of capacitor C is electrically connected to a fifth node N5.

[0145] The capacitor C in this disclosure can ensure the stability of the signal of the first node N1, thereby improving the reliability of the pixel driving circuit.

[0146] Figure 3 shows only one exemplary structure of the first control sub-circuit. Those skilled in the art will readily understand that the implementation of the first control sub-circuit is not limited to this.

[0147] Figure 4 is an equivalent circuit diagram of the second control sub-circuit and the drive sub-circuit. As shown in Figure 4, in an exemplary embodiment, the second control sub-circuit includes a first transistor T1 and a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the second scan signal line Gate2, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the seventh transistor T7 is electrically connected to the second scan signal line Gate2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first transistor T1 can be referred to as the first initialization transistor, and the seventh transistor T7 can be referred to as the seventh initialization transistor.

[0148] Figure 4 shows only one exemplary structure of the second control sub-circuit. Those skilled in the art will readily understand that the implementation of the second control sub-circuit is not limited to this.

[0149] As shown in Figure 4, in an exemplary embodiment, the driving sub-circuit may include a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 may be referred to as the driving transistor.

[0150] Figure 4 shows only one exemplary structure of the driver sub-circuit. Those skilled in the art will readily understand that the implementation of the driver sub-circuit is not limited to this.

[0151] Figure 5 is an equivalent circuit diagram of the third control sub-circuit. As shown in Figure 5, in the exemplary embodiment, the third control sub-circuit may include a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the second scan signal line Gate2, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the first scan signal line Gate1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (LEDs).

[0152] Figure 5 shows only one exemplary structure of the third control sub-circuit. Those skilled in the art will readily understand that the implementation of the third control sub-circuit is not limited to this.

[0153] Figure 6 shows the equivalent circuit diagram of the pixel driving circuit (Figure 1), and Figure 7 shows the equivalent circuit diagram of the pixel driving circuit (Figure 2). As shown in Figures 6 and 7, in the pixel driving circuit, the driving sub-circuit includes: the third transistor T3; the first control sub-circuit includes: the second transistor T2, the fourth transistor T4, the eighth transistor T8, and capacitor C; the second control sub-circuit includes: the first transistor T1 and the seventh transistor T7; and the third control sub-circuit includes: the fifth transistor T5 and the sixth transistor T6.

[0154] As shown in Figures 6 and 7, the control electrode of the first transistor T1 is electrically connected to the second scan signal line Gate2, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; the control electrode of the fifth transistor T5 is electrically connected to the second scan signal line Gate2. The first terminal of the fifth transistor T5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2. The control terminal of the sixth transistor T6 is connected to the first scan signal line Gate1, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal of the sixth transistor T6 is connected to the fourth node N4. The control terminal of the seventh transistor T7 is connected to the second scan signal line Gate2, the first terminal of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T7 is connected to the fourth node N4. The control terminal of the eighth transistor T8 is connected to the first scan signal line Gate1, the first terminal of the eighth transistor T8 is connected to the reference signal line REF, and the second terminal of the eighth transistor T8 is connected to the fifth node N5. The first plate C1 of capacitor C is connected to the first node N1, and the second plate C2 of capacitor C is connected to the fifth node N5.

[0155] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0156] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active pattern of the oxide thin-film transistor uses oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, which can reduce power consumption and improve display quality.

[0157] In an exemplary embodiment, capacitor C can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, capacitor C can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of capacitor C includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the voltage level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0158] In an exemplary embodiment, at least two of the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are of the same transistor type.

[0159] In an exemplary embodiment, at least two of the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are of the same transistor type.

[0160] In an exemplary embodiment, at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7, and at least one of the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8, have opposite transistor types.

[0161] In an exemplary embodiment, as shown in FIG6, any one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 is a P-type transistor, and any one of the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 is an N-type transistor.

[0162] In an exemplary embodiment, as shown in FIG7, any one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 is an N-type transistor, and any one of the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 is a P-type transistor.

[0163] In an exemplary embodiment, when the pixel driving circuit includes P-type transistors and N-type transistors, that is, low-temperature polycrystalline silicon transistors and oxide transistors are integrated on a display substrate to form a display substrate combining low-temperature polycrystalline silicon and oxide (LTPO), the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0164] In an exemplary embodiment, the signal lines connected to at least one row of pixel driving circuits satisfy at least one of the following conditions: the signal received by the reference signal line REF is the same as the signal received by the first power supply line VDD, and the signal received by the first initial signal line INIT1 is the same as the signal received by the second initial signal line INIT2.

[0165] In an exemplary embodiment, the fact that the signal received by the reference signal line REF is the same as the signal received by the first power line VDD can mean that the reference signal line REF and the first power line VDD can be the same signal line, or they can be different signal lines that receive the same signal.

[0166] In an exemplary embodiment, the fact that the signal received by the first initial signal line INIT1 is the same as the signal received by the second initial signal line INIT2 can mean that the first initial signal line INIT1 and the second initial signal line INIT2 can be the same signal line, or they can be different signal lines that receive the same signal.

[0167] In an exemplary embodiment, when the signal received by the reference signal line REF is different from the signal received by the first power line VDD, the setting of the reference signal line REF can adjust the range of the written data signal.

[0168] In an exemplary embodiment, the pixel driving circuit has multiple rows, and the signal received by the second scan signal line Gate2 connected to at least one row of pixel driving circuits is the same as the signal received by the first scan signal line Gate1 connected to the previous row of pixel driving circuits.

[0169] In an exemplary embodiment, having at least two signal lines connected to the pixel driving circuit receive the same signal can reduce the number of signal lines connected to the pixel driving circuit, thereby achieving a high PPI for the display device.

[0170] In an exemplary embodiment, when any one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 is a P-type transistor, and any one of the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 is an N-type transistor, the period during which the signal of the first scan signal line Gate1 is low-level occurs after the period during which the signal of the second scan signal line Gate2 is low-level; or, the period during which the signal of the first scan signal line Gate1 is low-level overlaps at least partially with the period during which the signal of the second scan signal line Gate2 is low-level, the start time of the period during which the signal of the first scan signal line Gate1 is low-level is earlier than the end time of the period during which the signal of the second scan signal line Gate2 is low-level, and the start time of the period during which the signal of the second scan signal line Gate2 is low-level is later than the start time of the period during which the signal of the second scan signal line Gate2 is low-level, and the end time of the period during which the signal of the first scan signal line Gate1 is low-level is later than the end time of the period during which the signal of the second scan signal line Gate2 is low-level.

[0171] In an exemplary embodiment, when any one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 is an N-type transistor, and any one of the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 is a P-type transistor, the period during which the signal of the first scan signal line Gate1 is high-level occurs after the period during which the signal of the second scan signal line Gate2 is high-level; or, the period during which the signal of the first scan signal line Gate1 is high-level overlaps at least partially with the period during which the signal of the second scan signal line Gate2 is high-level, the start time of the period during which the signal of the first scan signal line Gate1 is high-level is earlier than the end time of the period during which the signal of the second scan signal line Gate2 is high-level, and the start time of the period during which the signal of the second scan signal line Gate2 is high-level is later than the start time of the period during which the signal of the second scan signal line Gate2 is high-level, and the end time of the period during which the signal of the first scan signal line Gate1 is high-level is later than the end time of the period during which the signal of the second scan signal line Gate2 is high-level.

[0172] Figure 8 is a timing diagram of the pixel driving circuit provided in Figure 6. As shown in Figure 8, the operation of the pixel driving circuit provided in Figure 6 may include:

[0173] In the first stage, P1, the initialization stage, the signal on the first scan signal line Gate1 is high, and the signal on the second scan signal line Gate2 is low. Transistors T1, T6, T7, and T8 are turned on, while transistors T2, T4, and T5 are turned off.

[0174] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node N1, initializing the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1, where VIN1 is the voltage value of the signal on the first initial signal line INIT1. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fifth node N5 (also the first terminal of the light-emitting device L), initializing the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = VIN2, where VIN2 is the voltage value of the signal on the second initial signal line INIT2. The sixth transistor T6 is turned on, and the signal of the fifth node N5 is written to the third node N3, initializing the third node N3. The voltage value of the signal at the third node N3 is V3 = VIN2. When the eighth transistor T8 is turned on, the signal from the first power line VDD or the reference signal line REF is written to the fourth node N4 to initialize the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vref, where Vref is the voltage value of the signal from the reference signal line REF. During this stage, the amount of charge stored in capacitor C is Vref - VIN1.

[0175] In the second stage, P2, the threshold compensation and data writing stage, the signal on the first scan signal line Gate1 is a low-level signal, and the signal on the second scan signal line Gate2 is a high-level signal. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on, while the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0176] When the fourth transistor T4 is turned on, the signal on the data signal line Data is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vdata, where Vdata is the voltage value of the signal on the data signal line Data. When the fifth transistor T5 is turned on, the signal on the first power line VDD charges the first node N1 through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 is V1 = Vdd + Vth, where Vdd is the voltage value of the signal on the first current line VDD, and Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in capacitor C is Vdd + Vth - Vdata.

[0177] In the third stage, P3, the light-emitting stage, the signals on the first scan signal line Gate1 and the second scan signal line Gate2 are high-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are off, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are on.

[0178] The eighth transistor T8 is turned on, and the signal from the reference signal line REF is written to the second node N2. The voltage value of the signal at the second node N2 jumps from Vdata in the previous stage to Vref in this stage. Under the coupling effect of capacitor C, the voltage value of the signal at the first node N1 is V1 = Vdd + Vth + Vref - Vdata. The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output from the first power line VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0179] Figure 9 is a second timing diagram of the pixel driving circuit provided in Figure 6. As shown in Figure 9, the operation of the pixel driving circuit provided in Figure 6 can include:

[0180] In the first stage, P1, the initialization stage, the signal on the first scan signal line Gate1 is high, and the signal on the second scan signal line Gate2 is low. Transistors T1, T6, T7, and T8 are turned on, while transistors T2, T4, and T5 are turned off.

[0181] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node N1, initializing the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1, where VIN1 is the voltage value of the signal on the first initial signal line INIT1. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fifth node N5 (also the first terminal of the light-emitting device L), initializing the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = VIN2, where VIN2 is the voltage value of the signal on the second initial signal line INIT2. The sixth transistor T6 is turned on, and the signal of the fifth node N5 is written to the third node N3, initializing the third node N3. The voltage value of the signal at the third node N3 is V3 = VIN2. When the eighth transistor T8 is turned on, the signal from the first power line VDD or the reference signal line REF is written to the fourth node N4 to initialize the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vref, where Vref is the voltage value of the signal from the reference signal line REF. During this stage, the amount of charge stored in capacitor C is Vref - VIN1.

[0182] In the second stage, the signals of P2, the first scan signal line Gate1, and the second scan signal line Gate2 are low-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0183] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is continuously written to the first node N1, initializing the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fifth node N5 (also the first terminal of the light-emitting device L), initializing the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = VIN2. The second transistor T2 is turned on, and the signal of the first node N1 is written to the third node N3, initializing the third node N3. The voltage value of the signal at the third node N3 is V3 = VIN1. The fourth transistor T4 is turned on. At this time, no data signal is written to the data signal line Data, and the fourth node N4 is floating.

[0184] In the third stage, P3, the threshold compensation and data writing stage, the signal on the first scan signal line Gate1 is a low-level signal, and the signal on the second scan signal line Gate2 is a high-level signal. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on, while the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0185] When the fourth transistor T4 is turned on, the signal on the data signal line Data is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vdata, where Vdata is the voltage value of the signal on the data signal line Data. When the fifth transistor T5 is turned on, the signal on the first power line VDD charges the first node N1 through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 is V1 = Vdd + Vth, where Vdd is the voltage value of the signal on the first current line VDD, and Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in capacitor C is Vdd + Vth - Vdata.

[0186] In the fourth stage, P4, the light-emitting stage, the signals on the first scan signal line Gate1 and the second scan signal line Gate2 are high-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are off, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are on.

[0187] The eighth transistor T8 is turned on, and the signal from the reference signal line REF is written to the second node N2. The voltage value of the signal at the second node N2 jumps from Vdata in the previous stage to Vref in this stage. Under the coupling effect of capacitor C, the voltage value of the signal at the first node N1 is V1 = Vdd + Vth + Vref - Vdata. The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output from the first power line VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0188] Figure 10 is a timing diagram of the pixel driving circuit provided in Figure 7. As shown in Figure 10, the operation of the pixel driving circuit provided in Figure 7 may include:

[0189] In the first stage, P1, the initialization stage, the signal on the first scan signal line Gate1 is low, and the signal on the second scan signal line Gate2 is high. Transistors T1, T6, T7, and T8 are turned on, while transistors T2, T4, and T5 are turned off.

[0190] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node N1, initializing the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1, where VIN1 is the voltage value of the signal on the first initial signal line INIT1. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fifth node N5 (also the first terminal of the light-emitting device L), initializing the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = VIN2, where VIN2 is the voltage value of the signal on the second initial signal line INIT2. The sixth transistor T6 is turned on, and the signal of the fifth node N5 is written to the third node N3, initializing the third node N3. The voltage value of the signal at the third node N3 is V3 = VIN2. When the eighth transistor T8 is turned on, the signal from the first power line VDD or the reference signal line REF is written to the fourth node N4 to initialize the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vref, where Vref is the voltage value of the signal from the reference signal line REF. During this stage, the amount of charge stored in capacitor C is Vref - VIN1.

[0191] In the second stage, P2, the threshold compensation and data writing stage, the signal on the first scan signal line Gate1 is a high-level signal, and the signal on the second scan signal line Gate2 is a low-level signal. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on, while the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0192] When the fourth transistor T4 is turned on, the signal on the data signal line Data is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vdata, where Vdata is the voltage value of the signal on the data signal line Data. When the fifth transistor T5 is turned on, the signal on the first power line VDD charges the first node N1 through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 is V1 = Vdd + Vth, where Vdd is the voltage value of the signal on the first current line VDD, and Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in capacitor C is Vdd + Vth - Vdata.

[0193] In the third stage, P3, the light-emitting stage, the signals on the first scan signal line Gate1 and the second scan signal line Gate2 are low-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are off, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are on.

[0194] The eighth transistor T8 is turned on, and the signal from the reference signal line REF is written to the second node N2. The voltage value of the signal at the second node N2 jumps from Vdata in the previous stage to Vref in this stage. Under the coupling effect of capacitor C, the voltage value of the signal at the first node N1 is V1 = Vdd + Vth + Vref - Vdata. The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output from the first power line VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0195] Figure 11 is a second timing diagram of the pixel driving circuit provided in Figure 7. As shown in Figure 11, the operation of the pixel driving circuit provided in Figure 7 can include:

[0196] In the first stage, P1, the initialization stage, the signal on the first scan signal line Gate1 is low, and the signal on the second scan signal line Gate2 is high. Transistors T1, T6, T7, and T8 are turned on, while transistors T2, T4, and T5 are turned off.

[0197] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node N1, initializing the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1, where VIN1 is the voltage value of the signal on the first initial signal line INIT1. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fifth node N5 (also the first terminal of the light-emitting device L), initializing the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = VIN2, where VIN2 is the voltage value of the signal on the second initial signal line INIT2. The sixth transistor T6 is turned on, and the signal of the fifth node N5 is written to the third node N3, initializing the third node N3. The voltage value of the signal at the third node N3 is V3 = VIN2. When the eighth transistor T8 is turned on, the signal from the first power line VDD or the reference signal line REF is written to the fourth node N4 to initialize the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vref, where Vref is the voltage value of the signal from the reference signal line REF. During this stage, the amount of charge stored in capacitor C is Vref - VIN1.

[0198] In the second stage, the signals of P2, the first scan signal line Gate1, and the second scan signal line Gate2 are high-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0199] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is continuously written to the first node N1, initializing the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fifth node N5 (also the first terminal of the light-emitting device L), initializing the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = VIN2. The second transistor T2 is turned on, and the signal of the first node N1 is written to the third node N3, initializing the third node N3. The voltage value of the signal at the third node N3 is V3 = VIN1. The fourth transistor T4 is turned on. At this time, no data signal is written to the data signal line Data, and the fourth node N4 is floating.

[0200] In the third stage, P3, the threshold compensation and data writing stage, the signal on the first scan signal line Gate1 is a high-level signal, and the signal on the second scan signal line Gate2 is a low-level signal. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on, while the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0201] When the fourth transistor T4 is turned on, the signal on the data signal line Data is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vdata, where Vdata is the voltage value of the signal on the data signal line Data. When the fifth transistor T5 is turned on, the signal on the first power line VDD charges the first node N1 through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 is V1 = Vdd + Vth, where Vdd is the voltage value of the signal on the first current line VDD, and Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in capacitor C is Vdd + Vth - Vdata.

[0202] In the fourth stage, P4, the light-emitting stage, the signals on the first scan signal line Gate1 and the second scan signal line Gate2 are low-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are off, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are on.

[0203] The eighth transistor T8 is turned on, and the signal from the reference signal line REF is written to the second node N2. The voltage value of the signal at the second node N2 jumps from Vdata in the previous stage to Vref in this stage. Under the coupling effect of capacitor C, the voltage value of the signal at the first node N1 is V1 = Vdd + Vth + Vref - Vdata. The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output from the first power line VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0204] According to the driving timing provided in Figures 8 to 11, during the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the first node N1 is V1 = Vdd + Vth + Vref - Vdata, and the voltage value of the signal at the second node N2 is V2 = Vdd. At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0205] I = K * (Vgs - Vth) 2

[0206] =K*(V1-V3-Vth) 2

[0207] =K*(Vref-Vdata) 2

[0208] Where K is a constant related to the process and design, and Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3.

[0209] When the signal received by the reference signal line is the same as the signal received by the first power line, Vref = Vdd, and at this time, I = K*(Vdd - Vdata). 2 .

[0210] Compared with the driving timing provided in Figure 9, the driving timing provided in Figure 8 shows that during the time period between the initialization phase and the threshold compensation and data writing phase, the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are both high-level signals. At this time, the fifth transistor and the sixth transistor T6 are both turned on, and the light-emitting device L will emit light during the non-light-emitting phase. However, during the time period between the initialization phase and the threshold compensation and data writing phase in Figure 9, the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are both low-level signals. At this time, the fifth transistor T5 and the sixth transistor T6 are both turned off, and the light-emitting device L will not emit light during the non-light-emitting phase.

[0211] Compared with the driving timing provided in Figure 11, the driving timing provided in Figure 10 shows that during the time period between the initialization phase and the threshold compensation and data writing phase in Figure 13, the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are both low-level signals. At this time, the fifth transistor and the sixth transistor T6 are both turned on, and the light-emitting device L will emit light during the non-light-emitting phase. However, during the time period between the initialization phase and the threshold compensation and data writing phase in Figure 11, the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are both high-level signals. At this time, the fifth transistor T5 and the sixth transistor T6 are both turned off, and the light-emitting device L will not emit light during the non-light-emitting phase, which can ensure the reliability of the pixel driving circuit.

[0212] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments. The method for driving a pixel driving circuit provided in this disclosure includes:

[0213] Step 100: The driving sub-circuit provides a driving signal to the third node under the control of the signals from the first and second nodes.

[0214] Step 200: Under the control of the signal of the first scan signal line, the first control sub-circuit controls the signal of the first node through the signal of at least one of the data signal line and the reference signal line and the signal of the third node.

[0215] Step 300: Under the control of the signal from the second scan signal line, the second control sub-circuit provides the signal from the first initial signal line to the first node and the signal from the second initial signal line to the fourth node.

[0216] Step 400: Under the control of the signals from the first scan signal line and the second scan signal line, the third control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node.

[0217] Figure 12 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. As shown in Figure 12, this disclosure also provides a display device, which includes a display substrate. The display substrate includes a base, and the base is provided with a display area 100 and a non-display area 200 located in at least one of the display areas 100. The display area 100 is provided with a pixel driving circuit P, a plurality of first scan signal lines Gate1, and a plurality of second scan signal lines Gate2 arranged in an array as provided in any of the preceding embodiments. The non-display area is provided with a gate driving circuit 300. The gate driving circuit 300 is electrically connected to at least one first scan signal line Gate1 and at least one second scan signal line Gate2, respectively.

[0218] In an exemplary embodiment, the gate driving circuit 300 may be located on at least one side of the display area. FIG13 illustrates an example where the gate driving circuit 300 may be located on opposite sides of the display area.

[0219] In an exemplary embodiment, as shown in FIG12, the gate driving circuit includes: M+1 cascaded shift registers, namely the first-stage shift register GOA(1) to the (M+1)th-stage shift register GOA(M+1). The first-stage shift register GOA(1) is electrically connected to the second scan signal line Gate2 connected to the first row pixel driving circuit. The m-th stage shift register GOA(m) is electrically connected to the first scan signal line Gate1 connected to the (m-1)th row pixel driving circuit and the second scan signal line Gate2 connected to the m-th row pixel driving circuit. The (M+1)th stage shift register GOA(M+1) is electrically connected to the first scan signal line Gate1 connected to the M-th row pixel driving circuit. m is a positive integer greater than 1 and less than M. For example, the second-level shift register GOA(2) is electrically connected to the first scan signal line Gate1 connected to the first row pixel driving circuit and the second scan signal line Gate2 connected to the second row pixel driving circuit, respectively. The third-level shift register GOA(3) is electrically connected to the first scan signal line Gate1 connected to the second row pixel driving circuit and the second scan signal line Gate2 connected to the third row pixel driving circuit, respectively, and so on.

[0220] This disclosure reduces the area occupied by the non-display area by providing control signals to the pixel driving circuit with only one gate driving circuit, thus enabling a narrow bezel.

[0221] In an exemplary embodiment, FIG13 is a top view of the display area of ​​the display device provided in FIG12, FIG14 is a partial film layer schematic diagram of FIG13, and FIG15 is a structural schematic diagram of the first scan signal line and the second scan signal line connected by the pixel driving circuit. FIG13 and FIG14 are illustrated using a two-row, four-column pixel driving circuit, wherein the reference signal line and the first power supply line in at least one pixel driving circuit are the same power supply line, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T are P-type transistors, and the fifth transistor T5, the sixth transistor T61 and the eighth transistor T8 are N-type transistors.

[0222] In an exemplary embodiment, as shown in Figures 13 to 15, at least one pixel driving circuit is connected to two first scan signal lines Gate1, and the first scan signal lines Gate1 extend at least partially along a first direction D1.

[0223] In an exemplary embodiment, as shown in FIG15, the first first scan signal line Gate1 connected to at least one pixel driving circuit is a single-layer structure, and the second first scan signal line Gate1 connected to at least one pixel driving circuit includes a first scan line Gate1A and a second scan line Gate1B that are interconnected and disposed in different layers. The orthographic projection of the first scan line Gate1A on the substrate at least partially overlaps with the orthographic projection of the second scan line Gate1B on the substrate, and at least one of the first and second scan lines is located on the side of the first scan signal line away from the substrate. Exemplarily, the orthographic projection of the first scan line Gate1A on the substrate covers the orthographic projection of the second scan line Gate1B on the substrate.

[0224] In an exemplary embodiment, as shown in Figures 13 to 15, at least one pixel driving circuit is connected to two second scan signal lines Gate2, which extend at least partially along a first direction D1.

[0225] In an exemplary embodiment, as shown in FIG15, the first second scan signal line Gate2 connected to at least one pixel driving circuit has a single-layer structure, and the second second scan signal line Gate2 connected to at least one pixel driving circuit includes a third scan line Gate2A and a fourth scan line Gate2B that are interconnected and disposed in different layers. The orthographic projection of the third scan line Gate2A on the substrate at least partially overlaps with the orthographic projection of the fourth scan line Gate2B on the substrate, and at least one of the third scan line Gate2A and the fourth scan line Gate2B is located on the side of the first second scan signal line away from the substrate.

[0226] In an exemplary embodiment, the orthographic projection of one of the two second scan signal lines Gate2 connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first first scan signal line Gate1 connected to at least one pixel driving circuit on the substrate and the orthographic projection of the second first scan signal line Gate1 connected to at least one pixel driving circuit on the substrate. The orthographic projection of the other signal line of the two second scan signal lines Gate2 connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of one of the two first scan signal lines Gate1 connected to at least one pixel driving circuit away from the orthographic projection of the other signal line of the two first scan signal lines Gate1 connected to at least one pixel driving circuit on the substrate.

[0227] In an exemplary embodiment, as shown in Figures 13 to 15, the orthographic projections of the first first scan signal line Gate1, the second second scan signal line Gate2, the second first scan signal line Gate1, and the first second scan signal line Gate2 on the substrate connected to at least one pixel driving circuit are arranged sequentially along the second direction D2, and the first direction D1 and the second direction D2 intersect.

[0228] In an exemplary embodiment, as shown in Figures 13 and 14, the display device further includes: a plurality of first initial signal lines INIT1, at least one of the plurality of first initial signal lines INIT1 extending at least partially along a first direction D1.

[0229] In an exemplary embodiment, as shown in Figures 13 and 14, the orthographic projection of the first initial signal line INIT1 connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first second scan signal line Gate2 connected to the pixel driving circuit on the substrate. This at least partial overlap reduces the area occupied by the pixel driving circuit and enables a high PPI.

[0230] In an exemplary embodiment, as shown in Figures 13 and 14, the display device further includes: a plurality of second initial signal lines INIT2, at least one of the plurality of second initial signal lines INIT2 extending at least partially along a first direction D1.

[0231] In an exemplary embodiment, as shown in Figures 13 and 14, the orthographic projection of the second initial signal line INIT2 connected to the pixel driving circuit on the substrate is located on the side where the orthographic projection of the first initial signal line INIT1 connected to the pixel driving circuit on the substrate is far from the orthographic projection of at least one first scan signal line Gate1 connected to the pixel driving circuit on the substrate.

[0232] In an exemplary embodiment, as shown in FIG13, the display device further includes: a plurality of data signal lines Data and a plurality of first power lines VDD; at least one of the plurality of data signal lines Data and at least one of the plurality of first power lines VDD extend at least partially along a second direction D2, and the first direction D1 and the second direction D2 intersect.

[0233] In an exemplary embodiment, the width of the data signal line Data is smaller than the width of the first power line VDD.

[0234] In an exemplary embodiment, the display device further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; at least one pixel driving circuit including: at least one capacitor and at least one transistor; at least one transistor including: at least one P-type transistor and at least one N-type transistor; at least one capacitor including: a first electrode plate and a second electrode plate.

[0235] The first semiconductor layer includes at least: an active pattern of at least one P-type transistor of at least one pixel driving circuit.

[0236] The first conductive layer includes at least: a first first scan signal line Gate1 and a first second scan signal line Gate2 connected to at least one pixel driving circuit, and a first plate of a capacitor located in at least one pixel driving circuit.

[0237] The second conductive layer includes at least: a first scan line of Gate1 connected to at least one pixel driving circuit, a third scan line of Gate2 connected to at least one second scan signal line, and a second plate of a capacitor located in at least one pixel driving circuit.

[0238] The second semiconductor layer includes at least: an active pattern of at least one N-type transistor of at least one pixel driving circuit.

[0239] The third conductive layer includes at least: a second scan line of Gate1, a second scan line of Gate2, and a first initial signal line connected to at least one pixel driving circuit.

[0240] The fourth conductive layer includes at least: the first and second poles of at least one transistor of at least one pixel driving circuit.

[0241] The fifth conductive layer includes at least: a first power line VDD and a data signal line Data connected to at least one pixel driving circuit.

[0242] In an exemplary embodiment, the display substrate can be a low-temperature polycrystalline oxide (LTPO) display substrate.

[0243] The structure of a display substrate is illustrated below using an example of the fabrication process of the display substrate. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying and spin coating; and etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0244] Figures 16 to 30 are schematic diagrams illustrating the fabrication process of a display substrate provided in an exemplary embodiment. Figures 16 to 30 are illustrated using a two-row, four-column pixel driving circuit as an example.

[0245] The fabrication process of the display substrate provided in this disclosure may include, as shown in Figures 16 to 30:

[0246] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: sequentially depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film through a patterning process to form a first semiconductor layer pattern, as shown in FIG16, FIG16 being a schematic diagram of the first semiconductor layer pattern in FIG13.

[0247] In an exemplary embodiment, as shown in FIG16, the first semiconductor layer pattern may include at least an active pattern of at least one P-type transistor located in at least one pixel driving circuit. FIG16 is illustrated using an example where the active pattern of at least one P-type transistor includes: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, an active pattern 31 of a third transistor, an active pattern 41 of a fourth transistor, and an active pattern 71 of a seventh transistor.

[0248] In an exemplary embodiment, for at least one pixel driving circuit, the active pattern 21 of the second transistor and the active pattern 31 of the third transistor are an integral structure. The active pattern 11 of the first transistor, the active pattern 41 of the fourth transistor, and the active pattern 71 of the seventh transistor are separately configured.

[0249] In an exemplary embodiment, in the first direction D1, the active pattern 21 of the second transistor of the current column pixel driving circuit is located on the side of the active pattern 41 of the fourth transistor of the current column pixel driving circuit near the next column pixel driving circuit, and the active pattern 71 of the seventh transistor of the current column pixel driving circuit is located on the side of the active pattern 11 of the first transistor of the current column pixel driving circuit near the next column pixel driving circuit. In the second direction D2, the active patterns 21 and 41 of the second transistor of the current row pixel driving circuit are located on the side of the active pattern 31 of the third transistor of the current row pixel driving circuit near the pixel driving circuit of the previous row sub-pixel, and the active patterns 11 and 71 of the first transistor of the current row pixel driving circuit are located on the side of the active pattern 31 of the third transistor of the current row pixel driving circuit near the pixel driving circuit of the previous row sub-pixel.

[0250] In an exemplary embodiment, the active pattern 31 of the third transistor may be in the shape of an inverted “Ω”.

[0251] In an exemplary embodiment, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor can be in the shape of an "n".

[0252] In an exemplary embodiment, the active pattern 41 of the fourth transistor may be in the shape of a "7".

[0253] In an exemplary embodiment, the active pattern 71 of the seventh transistor may be in the shape of an "I".

[0254] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for at least one pixel driving circuit, the second region 31-2 of the active pattern 31 of the third transistor may simultaneously serve as the second region 21-2 of the active pattern 21 of the second transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 21-1 of the active pattern 21 of the second transistor, the first region 31-1 of the active pattern 31 of the third transistor, the first region 41-1 and the second region 41-2 of the active pattern 41 of the fourth transistor, and the first region 71-1 and the second region 71-2 of the active pattern 71 of the seventh transistor may be configured individually.

[0255] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed; patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, as shown in Figures 17 and 18. Figure 17 is a schematic diagram of the first conductive layer pattern in Figure 13, and Figure 18 is a schematic diagram of Figure 13 after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0256] In an exemplary embodiment, as shown in Figures 17 and 18, the first conductive layer pattern may include: a first first scan signal line Gate1, a first second scan signal line Gate2, and a control electrode of at least one P-type transistor located in at least one pixel driving circuit, and a first electrode C1 of a capacitor. The figures illustrate an example where the control electrodes of at least one P-type transistor include: a control electrode 12 of a first transistor, a control electrode 22 of a second transistor, a control electrode 32 of a third transistor, a control electrode 42 of a fourth transistor, and a control electrode 72 of a seventh transistor.

[0257] For at least one row of sub-pixels, the first first scan signal line Gate1 and the first second scan signal line Gate2 connected by the pixel driving circuit are arranged sequentially along the second direction D2, and the first first scan signal line Gate1 is located on the side of the first plate C1 of the capacitor of the pixel driving circuit closer to the previous row of pixel driving circuit, and the first second scan signal line Gate1 is located on the side of the first plate C1 of the capacitor of the pixel driving circuit closer to the next row of pixel driving circuit.

[0258] In an exemplary embodiment, the shape of the first scan signal line Gate1 can be a line shape extending along the first direction D1 of the main body. The area where the first scan signal line Gate1, connected to at least one pixel driving circuit, overlaps with the active pattern of the second transistor can be the control electrode 22 of the second transistor, and the area where the first scan signal line Gate1, connected to at least one pixel driving circuit, overlaps with the active pattern of the fourth transistor can be the control electrode 42 of the fourth transistor. Since there are two overlapping areas between the first scan signal line Gate1, connected to at least one pixel driving circuit, and the active pattern of the second transistor, the second transistor has a dual-gate structure.

[0259] In an exemplary embodiment, the shape of the first second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The area where the first second scan signal line Gate2, connected to at least one pixel driving circuit, overlaps with the active pattern of the first transistor can be the control electrode 12 of the first transistor, and the area where the first second scan signal line Gate2, connected to at least one pixel driving circuit, overlaps with the active pattern of the seventh transistor can be the control electrode 72 of the seventh transistor. Since there are two overlapping areas between the first second scan signal line Gate2, connected to at least one pixel driving circuit, and the active pattern of the first transistor, the first transistor has a dual-gate structure.

[0260] In an exemplary embodiment, the first plate C1 of the capacitor in at least one pixel driving circuit can be rectangular in shape, and the corners of the rectangle can be chamfered. Exemplarily, the first plate C1 of the capacitor can serve as the control electrode 32 of the third transistor.

[0261] In an exemplary embodiment, the first first scan signal line Gate1 and the first second scan signal line Gate2 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0262] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel regions of the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, while the first semiconductor layer in the area not shielded by the first conductive layer is conducted.

[0263] In an exemplary embodiment, the control electrode of the first transistor is disposed across the active pattern of the first transistor, the control electrode of the second transistor is disposed across the active pattern of the second transistor, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, and the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0264] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer, as shown in Figures 19 and 20. Figure 19 is a schematic diagram of the second conductive layer pattern in Figure 13, and Figure 20 is a schematic diagram of the second conductive layer pattern after it has been formed in Figure 13. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0265] In an exemplary embodiment, as shown in Figures 19 and 20, the second conductive layer pattern may include: a first scan line Gate1A of a second first scan signal line Gate1, a third scan line Gate2A of a second second scan signal line Gate2, a second initial signal line INIT2, a second electrode C2 of a capacitor located in at least one pixel driving circuit, and a first control electrode of at least one N-type transistor. The first control electrode of at least one N-type transistor may include: a first control electrode 52A of a fifth transistor, a first control electrode 62A of a sixth transistor, and a first control electrode 82A of an eighth transistor.

[0266] For at least one row of sub-pixels, the first scan line GateA1 of the second first scan signal line Gate1, the third scan line Gate2A of the second second scan signal line Gate2, and the second initial signal line INIT2 connected to the pixel driving circuit are arranged sequentially along the second direction D2. The orthographic projection of the third scan line Gate2A of the second second scan signal line Gate2 connected to the pixel driving circuit on the substrate is located between the orthographic projection of the first first scan signal line connected to the pixel driving circuit on the substrate and the orthographic projection of the first plate of the capacitor of the pixel driving circuit on the substrate. The orthographic projection of the first scan line GateA1 of the second first scan signal line Gate1 connected to the pixel driving circuit on the substrate is located between the orthographic projection of the first second scan signal line connected to the pixel driving circuit on the substrate and the orthographic projection of the first plate of the capacitor of the pixel driving circuit on the substrate. The second initial signal line connected to the pixel driving circuit is located on the side of the first scan line GateA1 of the second first scan signal line Gate1 away from the third scan line Gate2A of the second second scan signal line Gate2.

[0267] In an exemplary embodiment, the shape of the first scan line Gate1A of the second first scan signal line Gate1 can be a line shape in which the main body extends along the first direction D1. The area where the first scan line Gate1A of the second first scan signal line Gate1, which is connected to at least one pixel driving circuit, overlaps with the active pattern of the sixth transistor can be the first control electrode 62A of the sixth transistor, and the area where the first scan line Gate1A of the second first scan signal line Gate1, which is connected to at least one pixel driving circuit, overlaps with the active pattern of the eighth transistor can be the first control electrode 82A of the eighth transistor.

[0268] In an exemplary embodiment, the shape of the third scan line Gate2A of the second second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The area where the third scan line Gate2A of the second second scan signal line Gate2, to which at least one pixel driving circuit is connected, overlaps with the active pattern of the fifth transistor can be the first control electrode 52A of the fifth transistor.

[0269] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a line shape in which the main body extends along the first direction D1.

[0270] In an exemplary embodiment, the first scan line Gate1A of the second first scan signal line Gate1, the third scan line Gate2A of the second second scan signal line Gate2, and the second initial signal line INIT2 can be designed with equal width or non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0271] In an exemplary embodiment, the main outline of the second plate C2 of the capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second plate C2 on the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor on the substrate. The second plate C2 of the capacitor is provided with an opening V, which can be rectangular in shape and located in the middle of the second plate C2, so that the second plate C2 of the capacitor forms a ring structure. The opening V exposes the second insulating layer covering the first plate of the capacitor, and the orthographic projection of the first plate of the capacitor on the substrate covers the orthographic projection of the opening V on the substrate. In the exemplary embodiment, the opening V exposes the first plate of the capacitor, so that the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor and the first electrode of the eighth transistor) is connected to the first plate of the capacitor.

[0272] In an exemplary embodiment, the second plate C22 of the capacitors of adjacent pixel driving circuits located in the same row is electrically connected.

[0273] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: on the substrate on which the aforementioned pattern is formed, including: sequentially depositing a third insulating film and a second semiconductor film on the substrate, and patterning the third insulating film and the second semiconductor film by a patterning process to form a third insulating layer pattern and a second semiconductor layer pattern located on the third insulating layer, as shown in Figures 21 and 22. Figure 21 is a schematic diagram of the second semiconductor layer pattern in Figure 13, and Figure 22 is a schematic diagram of the second semiconductor layer pattern after it is formed in Figure 13.

[0274] In an exemplary embodiment, as shown in Figures 21 and 22, the second semiconductor layer pattern may include an active pattern of at least one N-type transistor located in at least one pixel driving circuit. The active pattern of at least one N-type transistor includes: an active pattern 51 of a fifth transistor, an active pattern 61 of a sixth transistor, and an active pattern 81 of an eighth transistor.

[0275] In an exemplary embodiment, as shown in Figures 21 and 22, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, and the active pattern 81 of the eighth transistor are individually configured.

[0276] In an exemplary embodiment, the active pattern 51 of the fifth transistor can be in the shape of a horizontally flipped "7", and the active patterns 61 of the sixth transistor and the active patterns 81 of the eighth transistor are in the shape of an "I".

[0277] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for at least one pixel driving circuit, the first region 51-1 and the second region 51-2 of the active pattern 51 of the fifth transistor, the first region 61-1 and the second region 61-2 of the active pattern 61 of the sixth transistor, and the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor are separately configured.

[0278] In an exemplary embodiment, the active pattern 51 of the fifth transistor is disposed across the first control electrode of the fifth transistor, the active pattern 61 of the sixth transistor is disposed across the first control electrode of the sixth transistor, and the active pattern 81 of the eighth transistor is disposed across the first control electrode of the eighth transistor.

[0279] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the fourth insulating film and the third conductive film using a patterning process to form a fourth insulating layer pattern and a third conductive layer pattern located on the fourth insulating layer, as shown in Figures 23 and 24. Figure 23 is a schematic diagram of the third conductive layer pattern in Figure 13, and Figure 24 is a schematic diagram of the third conductive layer pattern after it has been formed in Figure 13. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0280] In an exemplary embodiment, as shown in Figures 23 and 24, the third conductive layer pattern may include: a second scan line Gate1B of the second first scan signal line Gate1, a fourth scan line Gate2B of the second second scan signal line Gate2, a first initial signal line INIT1, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit. The first control electrode of the at least one N-type transistor may include: a second control electrode 52B of the fifth transistor, a second control electrode 62B of the sixth transistor, and a second control electrode 82B of the eighth transistor.

[0281] In an exemplary embodiment, the shape of the second scan line Gate1B of the second first scan signal line Gate1 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second scan line Gate1B of the second first scan signal line Gate1 on the substrate at least partially overlaps with the orthographic projection of the first scan line of the second first scan signal line Gate1 on the substrate. Exemplarily, the orthographic projection of the first scan line of the second first scan signal line Gate1 on the substrate covers the orthographic projection of the second scan line Gate1B of the second first scan signal line Gate1 on the substrate. The area where the second scan line Gate1B of the second first scan signal line Gate1 overlaps with the active pattern of the sixth transistor can serve as the second control electrode 62B of the sixth transistor, and the area where the second scan line Gate1B of the second first scan signal line Gate1 overlaps with the active pattern of the eighth transistor can serve as the second control electrode 82B of the eighth transistor.

[0282] In an exemplary embodiment, the shape of the fourth scan line Gate2B of the second second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the fourth scan line Gate2B of the second second scan signal line Gate2 on the substrate at least partially overlaps with the orthographic projection of the third scan line of the second second scan signal line Gate2 on the substrate. Exemplarily, the orthographic projection of the third scan line of the second second scan signal line Gate2 on the substrate covers the orthographic projection of the fourth scan line of the second second scan signal line Gate2 on the substrate. The area where the fourth scan line Gate2B of the second second scan signal line Gate2 overlaps with the active pattern of the fifth transistor can serve as the second control electrode 52B of the fifth transistor.

[0283] In an exemplary embodiment, the shape of the first initial signal line INIT1 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the first initial signal line INIT1 on the substrate at least partially overlaps with the orthographic projection of the first second scan signal line on the substrate.

[0284] In an exemplary embodiment, the second scan line Gate1B of the second first scan signal line Gate1, the fourth scan line Gate2B of the second second scan signal line Gate2, and the first initial signal line INIT1 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0285] (6) Forming a fifth insulating layer pattern includes: depositing a fifth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern. The fifth insulating layer has multiple via patterns, as shown in Figure 25. Figure 25 is a schematic diagram of the fifth insulating layer pattern formed in Figure 13.

[0286] In an exemplary embodiment, as shown in FIG25, the plurality of vias in the fifth insulating layer pattern include at least: a first via V1 to a nineteenth via V19 located in at least one pixel driving circuit.

[0287] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active layer of the first transistor through the via.

[0288] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor) to be connected to the second region of the active pattern of the first transistor through the via.

[0289] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the orthographic projection range of the first region of the active pattern of the second transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the second transistor. The third via V3 is configured to allow the second electrode (which is also the first electrode of the second transistor) of the subsequently formed first transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0290] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the third transistor) onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the third transistor). The fourth via V4 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the sixth transistor) to be connected to the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the third transistor) through the via.

[0291] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the orthographic projection of the first region of the active pattern of the third transistor onto the substrate. The fourth, third, second, and first insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the third transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fifth transistor) to be connected to the first region of the active pattern of the third transistor through the via.

[0292] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0293] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the orthographic projection of the second region of the active pattern of the fourth transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the seventh via V7 are etched away, exposing the surface of the second region of the active pattern of the fourth transistor. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the eighth transistor) to be connected to the second region of the active pattern of the fourth transistor through the via.

[0294] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0295] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the orthographic projection of the second region of the active pattern of the seventh transistor onto the substrate. The fourth, third, second, and first insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the active pattern of the seventh transistor. The ninth via V9 is configured to allow the second terminal of the subsequently formed sixth transistor (which is also the second terminal of the seventh transistor) to be connected to the second region of the active pattern of the seventh transistor through the via.

[0296] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is located within the orthographic projection of the first electrode of the capacitor (which is also the second electrode of the third transistor) onto the substrate. The fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the first electrode of the capacitor (which is also the second electrode of the third transistor). The tenth via V10 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor) to be connected to the first electrode of the capacitor (which is also the second electrode of the third transistor) through the via.

[0297] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second plate of the capacitor onto the substrate. The fourth and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the second plate of the capacitor. The eleventh via V11 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the eighth transistor) to be connected to the second plate of the capacitor through the via.

[0298] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the second initial signal line on the substrate. The fourth and third insulating layers within the twelfth via V12 are etched away, exposing the surface of the second initial signal line. The twelfth via V12 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the second initial signal line through the via.

[0299] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the orthographic projection range of the first region of the active pattern of the fifth transistor onto the substrate. The fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The thirteenth via V13 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0300] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection of the second region of the active pattern of the fifth transistor onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the second region of the active pattern of the fifth transistor. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fifth transistor) to be connected to the second region of the active pattern of the fifth transistor through the via.

[0301] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate is within the orthographic projection of the first region of the active pattern of the sixth transistor onto the substrate. The fourth insulating layer within the fifteenth via V15 is etched away, exposing the surface of the first region of the active pattern of the sixth transistor. The fifteenth via V15 is configured to allow the second terminal of the subsequently formed second transistor (which is also the second terminal of the third transistor and the first terminal of the sixth transistor) to be connected to the first region of the active pattern of the sixth transistor through the via.

[0302] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate is within the orthographic projection of the second region of the active pattern of the sixth transistor onto the substrate. The fourth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the second region of the active pattern of the sixth transistor. The sixteenth via V16 is configured to allow the second terminal of the subsequently formed sixth transistor (which is also the second terminal of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor through the via.

[0303] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the orthographic projection range of the first region of the active pattern of the eighth transistor onto the substrate. The fourth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The seventeenth via V17 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the first region of the active pattern of the eighth transistor through the via.

[0304] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The fourth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the second region of the active pattern of the eighth transistor. The eighteenth via V18 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the eighth transistor) to be connected to the second region of the active pattern of the eighth transistor through the via.

[0305] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is within the range of the orthographic projection of the first initial signal line on the substrate. The nineteenth via V19 exposes the surface of the first initial signal line. The nineteenth via V19 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first initial signal line through the via.

[0306] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern, as shown in Figures 26 and 27. Figure 26 is a schematic diagram of the fourth conductive layer pattern in Figure 13, and Figure 27 is a schematic diagram of the fourth conductive layer pattern after it has been formed in Figure 13.

[0307] In an exemplary embodiment, as shown in Figures 26 and 27, the fourth conductive layer pattern may include: the first pole 13 and the second pole 14 of the first transistor of at least one pixel driving circuit to the first pole 83 and the second pole 84 of the eighth transistor.

[0308] In an exemplary embodiment, the first electrode 13 of the first transistor is separately disposed and is shaped as a strip extending at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a first via and is electrically connected to the first initial signal line through a nineteenth via.

[0309] In an exemplary embodiment, the second electrode 14 of the first transistor and the first electrode 23 of the second transistor are integrally formed and are strip-shaped, extending at least partially along the second direction D2. The second electrode 14 of the first transistor (which is also the first electrode 23 of the second transistor) is connected to the second region of the active pattern of the first transistor through a second via, to the first region of the active pattern of the second transistor through a third via, and to the first plate of the capacitor (which is also the second electrode of the third transistor) through a tenth via.

[0310] In an exemplary embodiment, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor are an integral structure and are shaped like an "I". The second electrode 24 of the second transistor (which is also the second electrode 34 of the third transistor and the first electrode 63 of the sixth transistor) is connected to the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the third transistor) through a fourth via, and is connected to the first region of the active pattern of the sixth transistor through a fifteenth via.

[0311] In an exemplary embodiment, the first electrode 33 of the third transistor and the second electrode 54 of the fifth transistor are an integral structure and are shaped like an "I". The first electrode 33 of the third transistor (which is also the second electrode 54 of the fifth transistor) is connected to the first region of the active pattern of the third transistor through a fifth via and to the second region of the active pattern of the fifth transistor through a fourteenth via.

[0312] In an exemplary embodiment, the first electrode 43 of the fourth transistor is separately disposed and is block-shaped. The first electrode 43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through a sixth via.

[0313] In an exemplary embodiment, the second electrode 44 of the fourth transistor and the second electrode 84 of the eighth transistor are an integral structure, and are strip-shaped extending along the second direction D2. The second electrode 44 of the fourth transistor (which is also the second electrode 84 of the eighth transistor) is connected to the second region of the active pattern of the fourth transistor through the seventh via, connected to the second plate of the capacitor through the eleventh via, and connected to the second region of the active pattern of the eighth transistor through the eighteenth via.

[0314] In an exemplary embodiment, the first electrode 53 of the fifth transistor is separately disposed and is strip-shaped extending along the second direction D2. The first electrode 53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through a thirteenth via.

[0315] In an exemplary embodiment, the second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is shaped like an inverted "T". The second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the seventh transistor through the ninth via and to the second region of the active pattern of the sixth transistor through the sixteenth via.

[0316] In an exemplary embodiment, the first electrode 73 of the seventh transistor is separately provided and is in the shape of a strip extending at least partially along the first direction D1. The first electrode 73 of the seventh transistor is connected to the first region of the active pattern of the seventh transistor through an eighth via and is connected to the second initial signal line through a twelfth via.

[0317] In an exemplary embodiment, the first electrode 83 of the eighth transistor is separately provided and is in the shape of a strip extending at least partially along the second direction D2. The first electrode 83 of the eighth transistor is connected to the first region of the active pattern of the eighth transistor through the seventeenth via.

[0318] (8) Forming a planarization layer pattern. In an exemplary embodiment, forming a planarization layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer, coating a planarization film on the sixth insulating layer, and patterning the planarization film using a patterning process to form a planarization layer pattern covering the aforementioned pattern. The planarization layer has a plurality of via patterns, as shown in FIG28, which is a schematic diagram of FIG13 after the planarization layer pattern is formed.

[0319] In an exemplary embodiment, as shown in FIG28, the plurality of via patterns on the planarization layer pattern include: the twentieth via V20 to the twenty-third via V23.

[0320] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the range of the orthographic projection of the first electrode of the fourth transistor onto the substrate. The sixth insulating layer within the twentieth via V20 is etched away, exposing the surface of the first electrode of the fourth transistor. The twentieth via V20 is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0321] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor onto the substrate. The sixth insulating layer within the 21st via V21 is etched away, exposing the surface of the first electrode of the fifth transistor. The 21st via V21 is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0322] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the substrate is located within the orthogonal projection of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) onto the substrate. The sixth insulating layer within the 22nd via V22 is etched away, exposing the surface of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor). The 22nd via V22 is configured to allow the subsequently formed anode connection electrode to be connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the via.

[0323] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the range of the orthographic projection of the first electrode of the eighth transistor onto the substrate. The sixth insulating layer within the 23rd via V23 is etched away, exposing the surface of the first electrode of the eighth transistor. The 23rd via V23 is configured to allow a subsequently formed first power line to be connected to the first electrode of the eighth transistor through the via.

[0324] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film by a patterning process to form a fifth conductive layer pattern, as shown in Figures 29 and 30. Figure 29 is a schematic diagram of the fifth conductive layer pattern in Figure 13, and Figure 30 is a schematic diagram of the fifth conductive layer pattern after it is formed in Figure 13.

[0325] In an exemplary embodiment, as shown in Figures 29 and 30, the fifth conductive layer pattern may include at least: a data signal line Data, a first power supply line VDD, and an anode connection electrode AL located in at least one pixel driving circuit.

[0326] In an exemplary embodiment, the data signal line Data can be a line shape in which the main body extends along the second direction D2, and is electrically connected to the first electrode of the fourth transistor through the twentieth via.

[0327] In an exemplary embodiment, the data signal line VDD can be a line shape in which the main body extends along the second direction D2. The data signal line VDD is electrically connected to the first electrode of the fifth transistor through a twenty-first via and to the first electrode of the eighth transistor through a twenty-third via.

[0328] In an exemplary embodiment, the orthographic projection of the data signal line VDD onto the substrate at least partially overlaps with the orthographic projection of the capacitor onto the substrate.

[0329] In an exemplary embodiment, the line width of the first power line VDD is greater than the line width of the data signal line Data.

[0330] In an exemplary embodiment, the anode connection electrode AL is block-shaped and is electrically connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the twenty-second via.

[0331] At this point, the circuit structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple pixel driving circuits and multiple signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate. The pixel driving circuit for at least one sub-pixel includes at least one P-type transistor, at least one N-type transistor, and at least one capacitor, the capacitor including a first electrode and a second electrode.

[0332] The pixel driving circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a first planarization layer, and a fifth conductive layer, which are sequentially disposed on the substrate.

[0333] In an exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0334] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0335] In an exemplary embodiment, at least one of the first to fifth conductive layers may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0336] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0337] In an exemplary embodiment, the planarization layer may be made of organic materials.

[0338] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0339] On the substrate with the aforementioned pattern, an anodic conductive film is deposited, and the anodic conductive film is patterned using a patterning process to form an anodic conductive layer pattern disposed on a second planarization layer. On the substrate with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern that exposes the anodic conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0340] At this point, the luminescent structure layer has been successfully fabricated on the substrate.

[0341] In an exemplary embodiment, the anode conductive layer includes at least the anodes of a plurality of light-emitting devices.

[0342] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0343] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0344] In an exemplary embodiment, the cathode conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0345] In an exemplary embodiment, the cathode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0346] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0347] The display substrate described in this embodiment can be used in display products of any resolution.

[0348] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0349] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0350] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0351] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, comprising: The driving sub-circuit, the first control sub-circuit, the second control sub-circuit, and the third control sub-circuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The first control sub-circuit is electrically connected to the first scan signal line, the data signal line, the reference signal line, the first node, and the third node, respectively, and is configured to control the signal of the first node through the signal of at least one of the data signal line and the reference signal line and the signal of the third node under the control of the signal of the first scan signal line. The second control sub-circuit is electrically connected to the second scan signal line, the first initial signal line, the second initial signal line, the first node, and the fourth node, respectively, and is configured to provide the first initial signal line signal to the first node and the second initial signal line signal to the fourth node under the control of the signal of the second scan signal line. The third control sub-circuit is electrically connected to the first scan signal line, the second scan signal line, the first power line, the second node, the third node, and the fourth node, respectively. It is configured to provide the first power line signal to the second node and the third node signal to the fourth node under the control of the signals of the first scan signal line and the second scan signal line.

2. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a first write sub-circuit, a second write sub-circuit, a storage sub-circuit, and a connection sub-circuit; The first write sub-circuit is electrically connected to the first scan signal line, the data signal line and the fifth node respectively, and is configured to provide the data signal line signal to the fifth node under the control of the signal of the first scan signal line; The second write sub-circuit is electrically connected to the first scan signal line, the reference signal line and the fifth node respectively, and is configured to provide the reference signal line signal to the fifth node under the control of the signal of the first scan signal line; The storage sub-circuit is electrically connected to the first node and the fifth node respectively, and is configured to store the voltage difference between the signals of the first node and the fifth node. The connecting sub-circuit is electrically connected to the first scan signal line, the first node, and the third node, respectively, and is configured to connect the first node and the third node under the control of the signal from the first scan signal line.

3. The pixel driving circuit according to claim 2, wherein, The first write sub-circuit includes a fourth transistor; the second write sub-circuit includes an eighth transistor; the communication sub-circuit includes a second transistor; and the storage sub-circuit includes a capacitor, which includes a first plate and a second plate. The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the reference signal line, and the second electrode of the eighth transistor is electrically connected to the fifth node. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the fifth node.

4. The pixel driving circuit according to claim 1, wherein, The second control sub-circuit includes a first transistor and a seventh transistor, and the third control sub-circuit includes a fifth transistor and a sixth transistor; The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the fifth transistor is electrically connected to the second scan signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the first scan signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second scan signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.

5. The pixel driving circuit according to claim 1, wherein, The driving sub-circuit includes a third transistor; the first control sub-circuit includes a second transistor, a fourth transistor, an eighth transistor, and a capacitor, the capacitor including a first plate and a second plate; the second control sub-circuit includes a first transistor and a seventh transistor; the third control sub-circuit includes a fifth transistor and a sixth transistor. The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode of the fifth transistor is electrically connected to the second scan signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the first scan signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second scan signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node. The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the reference signal line, and the second electrode of the eighth transistor is electrically connected to the fifth node. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the fifth node.

6. The pixel driving circuit according to claim 5, wherein, At least two of the first transistor, the second transistor, the fourth transistor, and the seventh transistor are of the same transistor type; At least two of the fifth, sixth, and eighth transistors are of the same transistor type; The transistor types of at least one of the first, second, fourth, and seventh transistors and at least one of the fifth, sixth, and eighth transistors are opposite.

7. The pixel driving circuit according to claim 1, wherein, The signal lines connected to at least one row of pixel driving circuits satisfy at least one of the following conditions: the signal received by the reference signal line is the same as the signal received by the first power line, and the signal received by the first initial signal line is the same as the signal received by the second initial signal line.

8. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit has multiple rows, and the signal received by the second scan signal line connected to at least one row of pixel driving circuits is the same as the signal received by the first scan signal line connected to the previous row of pixel driving circuits.

9. A display device comprising a substrate, the substrate having a display area and a non-display area located in at least one of the display areas, the display area having an array of pixel driving circuits as described in any one of claims 1 to 8, a plurality of first scan signal lines and a plurality of second scan signal lines, and the non-display area having a gate driving circuit; The gate drive circuit is electrically connected to at least one first scan signal line and at least one second scan signal line, respectively.

10. The display device according to claim 9, wherein, The gate drive circuit includes: M+1 cascaded shift registers; The first-level shift register is electrically connected to the second scan signal line of the first row pixel driving circuit. The m-th level shift register is electrically connected to the first scan signal line of the (m-1)-th row pixel driving circuit and the second scan signal line of the m-th row pixel driving circuit, respectively. The M+1-th level shift register is electrically connected to the first scan signal line of the M-th row pixel driving circuit. m is a positive integer greater than 1 and less than M.

11. The display device according to claim 9, wherein, At least one pixel driving circuit is connected to two first scan signal lines, the first scan signal lines extending at least partially along a first direction; The first scan signal line connected to at least one pixel driving circuit has a single-layer structure, and the second scan signal line connected to at least one pixel driving circuit includes a first scan line and a second scan line that are interconnected and arranged in different layers. The orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate at least partially overlap, and at least one of the first scan line and the second scan line is located on the side of the first scan signal line away from the substrate.

12. The display device according to claim 11, wherein, At least one pixel driving circuit is connected to two second scan signal lines, the second scan signal lines extending at least partially along a first direction; The first second scan signal line connected to at least one pixel driving circuit has a single-layer structure, and the second second scan signal line connected to at least one pixel driving circuit includes a third scan line and a fourth scan line that are interconnected and arranged in different layers. The orthographic projection of the third scan line on the substrate at least partially overlaps with the orthographic projection of the fourth scan line on the substrate, and at least one of the third and fourth scan lines is located on the side of the first and second scan signal lines away from the substrate.

13. The display device according to claim 9, wherein, At least one pixel driving circuit is connected to two first scan signal lines and two second scan signal lines respectively; The orthographic projection of one of the two second scan signal lines connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first first scan signal line connected to at least one pixel driving circuit on the substrate and the orthographic projection of the second first scan signal line connected to at least one pixel driving circuit on the substrate. The orthographic projection of the other signal line connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of one of the two first scan signal lines connected to at least one pixel driving circuit away from the orthographic projection of the other signal line connected to at least one pixel driving circuit on the substrate.

14. The display device according to claim 13, wherein, The orthographic projections of the first scanning signal line connected to at least one pixel driving circuit on the substrate, the orthographic projections of the second scanning signal line on the substrate, the orthographic projections of the second scanning signal line on the substrate, and the orthographic projections of the first scanning signal line on the substrate are arranged sequentially along a second direction, wherein the first direction and the second direction intersect.

15. The display device according to claim 12, further comprising: A plurality of first initial signal lines, wherein at least one of the plurality of first initial signal lines extends at least partially along a first direction; The orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first second scan signal line connected to the pixel driving circuit on the substrate.

16. The display device according to claim 15, further comprising: A plurality of second initial signal lines, wherein at least one of the plurality of second initial signal lines extends at least partially along a first direction; The orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate is located on the side away from the orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate.

17. The display device according to claim 16, further comprising: Multiple data signal lines and multiple first power lines; at least one of the multiple data signal lines and at least one of the multiple first power lines extends at least partially along a second direction; The display device further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; at least one pixel driving circuit including: at least one capacitor and at least one transistor; at least one transistor including: at least one P-type transistor and at least one N-type transistor; at least one capacitor including: a first electrode plate and a second electrode plate. The first semiconductor layer includes at least: an active pattern of at least one P-type transistor of at least one pixel driving circuit; The first conductive layer includes at least: at least one first scan signal line and one second scan signal line connected to at least one pixel driving circuit, and a first plate of a capacitor located in at least one pixel driving circuit; The second conductive layer includes at least: a first scan line of a second first scan signal line connected to at least one pixel driving circuit, a third scan line of a second second scan signal line and a second initial signal line, and a second plate of a capacitor located in at least one pixel driving circuit; The second semiconductor layer includes at least: an active pattern of at least one N-type transistor of at least one pixel driving circuit; The third conductive layer includes at least: a second scan line of the second first scan signal line connected to at least one pixel driving circuit, a fourth scan line of the second second scan signal line, and a first initial signal line; The fourth conductive layer includes at least: the first and second electrodes of at least one transistor of at least one pixel driving circuit; The fifth conductive layer includes at least: at least one first power line and data signal line connected to a pixel driving circuit.

18. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 8, the method comprising: The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes; The first control sub-circuit, under the control of the signal of the first scan signal line, controls the signal of the first node through the signal of at least one of the data signal line and the reference signal line and the signal of the third node. Under the control of the signal from the second scan signal line, the second control sub-circuit provides the signal from the first initial signal line to the first node and the signal from the second initial signal line to the fourth node; The third control sub-circuit, under the control of the signals from the first and second scan signal lines, provides the first power line signal to the second node and the third node signal to the fourth node.

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