Magnetic skyrmion memory

Abstract

Provided is a magnetic skyrmion memory, comprising: a magnetic structural racetrack, a magnetic tunnel junction and a ferroelectric back gate. The magnetic structure racetrack comprises a topological material layer and a ferrimagnetic layer, and is constructed to comprises a middle region and extension parts respectively extending from both sides of the middle region; the ferrimagnetic layer of the extension parts on the both sides are respectively pinned by means of antiferromagnetic coupling in opposite magnetic moment directions; the magnetic tunnel junction is located above the middle region of the magnetic structure racetrack, and is configured to electrically read a resistance state change of the memory; the ferroelectric back gate comprises a ferroelectric layer and a bottom electrode, and is located below the middle region of the magnetic structure racetrack; when a current is injected into the topological material layer, a spin orbit moment is generated, so as to control the motion of the magnetic structure of the ferrimagnetic layer in the ferrimagnetic layer; a gate voltage is applied to adjust the polarization direction of the ferroelectric layer, so as to control the magnitude of an antisymmetric exchange interaction at an interface between the topological material layer and the ferrimagnetic layer, thereby finally enabling the memory to operate in a skyrmion mode or in a binary mode.

Description

Magnetic Skymin memory Technical Field

[0001] This disclosure relates to the field of magnetic storage technology, and more particularly to a magnetic skyrmion memory. Background Technology

[0002] Magnetic skyrmions, as topology-protected chiral magnetic structures, offer advantages such as small size, low driving circuitry, and topology protection, making them promising candidates for next-generation high-density, high-efficiency spintronic devices. However, traditional ferromagnetic skyrmions exhibit a significant skyrmion Hall effect, easily annihilating at device edges. Furthermore, their slow motion limits device operating speed. While subferromagnetic and antiferromagnetic skyrmions address these issues, achieving efficient electrical readout remains challenging. Skyrmions can be nucleated and driven via spin-transfer torque or spin-orbit torque excitation, but this requires high current density and energy consumption.

[0003] Public content

[0004] In view of this, in order to at least partially solve at least one of the aforementioned technical problems, this disclosure provides a magnetic skyrmion memory.

[0005] To achieve the above objectives, the technical solution disclosed herein is as follows:

[0006] According to one embodiment of this disclosure, a magnetic skyrmion memory is provided, comprising: a magnetic track structure, a magnetic tunnel junction, and a ferroelectric back gate.

[0007] The magnetic track structure includes a topological material layer and a ferrimagnetic layer, and is configured to include a central region and extensions extending from both sides of the central region. The ferrimagnetic layers of the two extensions are pinned to opposite magnetic moment directions by antiferromagnetic coupling. A magnetic tunnel junction is located on the central region of the magnetic track structure and is configured for electrical read-memory memory resistance changes. The ferroelectric back gate includes a ferroelectric layer and a bottom electrode, and the ferroelectric back gate is located below the central region of the magnetic track structure.

[0008] When current is injected into the topological material layer, a spin orbital moment is generated to regulate the movement of the magnetic structure in the ferrimagnetic layer. By applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is controlled, ultimately enabling the memory to operate in skyminster mode or binary mode.

[0009] According to an embodiment of this disclosure, the central area of ​​the magnetic structure track is circular, and the extension is elongated; the magnetic tunnel junction is located above the central area of ​​the magnetic structure track, and the magnetic tunnel junction is constructed to be circular with a diameter not greater than the circular diameter of the central area of ​​the magnetic structure track.

[0010] According to an embodiment of this disclosure, the memory further includes an interface layer, which is prepared between the topological material layer and the ferrimagnetic layer. The interface layer is configured to improve the interface properties between the topological material layer and the ferrimagnetic layer and increase the driving efficiency of the spin orbital moment of the topological material layer.

[0011] According to embodiments of this disclosure, the magnetic structure includes magnetic domain walls and / or skyrmions.

[0012] According to embodiments of this disclosure, the ferroelectric layer may be HfZrO. x One or a combination of HfO2, BiFeO3, BaTiO3, and In2Se3;

[0013] The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, and topological half-metals PtSe2, WSe2, PtTe2, and WTe2; the material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, and TbCo; the material of the pinning material layer is selected from (Co / Tb) periodic multilayer film, GdFeCo, GdFeO, TbCo, and GdCo alloy materials. By adjusting the chemical composition ratio, the pinning materials on both sides have different coercivities; the pinning material layers on both sides are configured with opposite magnetic moment directions by an external magnetic field.

[0014] According to an embodiment of this disclosure, a magnetic tunnel junction includes a ferromagnetic free layer and a ferromagnetic reference layer, wherein the ferromagnetic free layer and the ferromagnetic reference layer are separated by a nonmagnetic insulating barrier layer; the ferromagnetic free layer and the subferromagnetic layer are antiferromagnetically coupled through a space layer located between them; the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; the materials of the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the material of the insulating barrier layer is selected from MgO and AlO. x One or a combination thereof; the space layer material is selected from one or a combination of Ru, Cu, and W.

[0015] According to embodiments of this disclosure, by applying different voltages to the back gate to change the polarization direction of the ferroelectric layer, the polarization direction can regulate the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the subferromagnetic layer, thereby changing the device's operating mode. When the interface antisymmetric exchange interaction is greater than a set threshold, skyrmions can exist stably, and the memory operates in skyrmion mode. When the interface antisymmetric exchange interaction is less than the set threshold, skyrmions cannot exist stably, and the device operates in binary mode.

[0016] According to an embodiment of this disclosure, the two ends of the subferromagnetic layer are pinned in opposite magnetic moment directions, and a stable magnetic domain wall exists at the edge of the pinned region at one end. By applying a driving current to the topological material layer, the magnetic domain wall can be driven to the edge of the middle region of the magnetic structure track. The two ends of the magnetic domain wall at the edge of the middle region are pinned, and the non-uniform tension acting on the magnetic domain wall will break to form skyrmions. Due to the strong antiferromagnetic coupling between the subferromagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistive state of the magnetic tunnel junction.

[0017] According to embodiments of this disclosure, more resistive states are achieved by making more skyrmions stably exist in the middle region of the magnetic structure track; and the operating speed of the device is increased by increasing the speed of skyrmion movement.

[0018] According to embodiments of this disclosure, the memory further includes three transistors: a gate control transistor, a write control transistor, and a read control transistor. The gate control transistor is configured as a select gate; when switching operating modes, the select gate voltage is pulled high to the power supply voltage V. DD When the gate control transistor is turned on, the write word line WBL voltage is pulled high to the mode select voltage Vselect, and the remaining metal lines are grounded. The gate voltage is applied to control the polarization direction of the ferroelectric layer. When operating in binary mode and performing a write 0 operation, the write bit line WWL voltage is pulled high to the power supply voltage V. DD The write line WBL is pulled high to the first write voltage V. write1 The remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the domain wall movement and flip the magnetic moment of the subferromagnetic layer; when performing a write 1 operation, the source line voltage is pulled up to the first write voltage V. write1 The write bit line is grounded to achieve a write 1 operation; when operating in Skymin mode, the write bit line WWL voltage is pulled high to the power supply voltage V during a write operation. DD The voltage on the write line WBL is pulled up to the second write voltage V. write2 V write2 ≠V write1 With the remaining metal wires grounded, under the non-uniform tension generated by the current, the magnetic domain walls break to form skyrmions; the cumulative number of skyrmions is linearly related to the resistance of the magnetic tunnel junction; during a reset operation, the write line WWL voltage is pulled high to the power supply voltage V. DD The source line voltage is pulled up to the first write voltage V. write1 The magnetic domain walls will be driven back to their initial position. Because the antiferromagnetic nails at both ends of the magnetic structure track are anchored, the magnetic domain walls will not be annihilated.

[0019] The magnetic skyrmion memory disclosed herein utilizes a ferroelectric back-gate to control the memory's operating mode, enriching device functionality. The topological material employed possesses a spin Hall angle significantly larger than that of conventional heavy metal materials, improving device efficiency. The subferromagnetic skyrmions effectively suppress the skyrmion Hall effect, reduce skyrmion size, and increase skyrmion velocity, allowing more skyrmions to exist stably and achieving more resistive states. This simultaneously improves device operating speed and efficiency. High-efficiency electrical readout can be achieved using a conventional CoFeB-based magnetic tunnel junction through antiferromagnetic coupling between the subferromagnetic layer and the ferromagnetic free layer. The two ends of the subferromagnetic layer are pinned to opposite magnetization directions through antiferromagnetic coupling with the pinning material, resulting in stable magnetic domain walls within the memory. Spin orbital moments drive these domain walls to break into skyrmions in a circular region below the magnetic tunnel junction, significantly reducing skyrmion nucleation energy consumption and improving device efficiency. Attached Figure Description

[0020] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1A is a schematic diagram of a magnetic skyrmion memory main film stack structure provided in an embodiment of the present disclosure;

[0022] Figure 1B is a schematic diagram of another magnetic skyrmion memory body film stack structure provided in an embodiment of this disclosure;

[0023] Figure 2 is a schematic diagram of the three-dimensional structure of the magnetic skyrmion memory provided in an embodiment of this disclosure;

[0024] Figure 3 is a schematic diagram of the working mode mechanism of ferroelectric layer ferroelectric polarization control in an embodiment of this disclosure;

[0025] Figure 4 is a schematic diagram of antiferromagnetic coupling between the subferromagnetic layer and the ferromagnetic layer in an embodiment of this disclosure;

[0026] Figure 5 is a schematic diagram of the mechanism by which magnetic domain walls are converted into skyrmions according to an embodiment of the present disclosure;

[0027] Figure 6 is a schematic diagram of the resistance state switching curves of the magnetic skyrmion memory under different operating modes according to an embodiment of the present disclosure.

[0028] Figure 7 is a schematic diagram of a magnetic skyrmion memory connected to an external circuit and related operating parameters according to an embodiment of the present disclosure. Detailed Implementation

[0029] This disclosure provides a magnetic skyrmion memory with advantages such as small size, low driving voltage, and topology protection, which is expected to be applied to next-generation high-density, high-efficiency spintronic devices.

[0030] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0031] In this embodiment, a magnetic skyrmion memory is provided. Referring to Figures 1A, 1B, and 2, the memory includes: a magnetic raceway, a magnetic tunnel junction, and a ferroelectric back gate. The magnetic raceway comprises a topological material layer and a ferrimagnetic layer, configured to include a central region and extensions extending from both sides of the central region. The ferrimagnetic layers of the two extensions are antiferromagnetically pinned to opposite magnetic moment directions. The magnetic tunnel junction is located on the central region of the magnetic raceway and configured for electrically reading the memory's resistance state changes. The ferroelectric back gate includes a ferroelectric layer and a bottom electrode, located below the central region of the magnetic raceway. When current is injected into the topological material layer, a spin orbital moment is generated to control the movement of the magnetic structure in the ferrimagnetic layer. By applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is controlled, ultimately enabling the memory to operate in skyrmion mode or binary mode.

[0032] According to an embodiment of this disclosure, as shown in FIG2, the middle region of the magnetic structure track is circular, and the extension is elongated; the magnetic tunnel junction is located above the middle region of the magnetic structure track, and the magnetic tunnel junction is constructed to be circular with a diameter not greater than the circular diameter of the middle region of the magnetic structure track.

[0033] According to an embodiment of this disclosure, as shown in FIG1B, the memory may further include an interface layer, which is prepared between the topological material layer and the ferrimagnetic layer. The interface layer is configured to improve the interface properties between the topological material layer and the ferrimagnetic layer, improve the driving efficiency of the spin orbital moment of the topological material layer, and improve the energy efficiency of the memory device.

[0034] According to embodiments of this disclosure, the magnetic structure includes magnetic domain walls and / or skyrmions.

[0035] According to embodiments of this disclosure, the ferroelectric layer may be HfZrO. x One or a combination of HfO2, BiFeO3, BaTiO3, and In2Se3;

[0036] The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, and topological half-metals PtSe2, WSe2, PtTe2, and WTe2; the material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, and TbCo; the material of the pinning material layer is selected from (Co / Tb) periodic multilayer film, GdFeCo, GdFeO, TbCo, and GdCo alloy materials. By adjusting the chemical composition ratio, the pinning materials on both sides have different coercivities; the pinning material layers on both sides are configured with opposite magnetic moment directions by an external magnetic field.

[0037] According to an embodiment of this disclosure, a magnetic tunnel junction includes a ferromagnetic free layer and a ferromagnetic reference layer, wherein the ferromagnetic free layer and the ferromagnetic reference layer are separated by a nonmagnetic insulating barrier layer; as shown in FIG2, the ferromagnetic free layer and the subferromagnetic layer are antiferromagnetically coupled through a space layer located between them; the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; the materials of the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the material of the insulating barrier layer is selected from MgO and AlO. x One or a combination thereof, where x represents a component; the space layer material is selected from one or a combination of Ru, Cu, and W.

[0038] According to embodiments of this disclosure, by applying different voltages to the back gate to change the polarization direction of the ferroelectric layer, the polarization direction can regulate the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the subferromagnetic layer, thereby changing the device's operating mode. When the interface antisymmetric exchange interaction is greater than a set threshold, skyrmions can exist stably, and the memory operates in skyrmion mode. When the interface antisymmetric exchange interaction is less than the set threshold, skyrmions cannot exist stably, and the device operates in binary mode.

[0039] According to an embodiment of this disclosure, the two ends of the subferromagnetic layer are pinned in opposite magnetic moment directions, and a stable magnetic domain wall exists at the edge of the pinned region at one end. By applying a driving current to the topological material layer, the magnetic domain wall can be driven to the edge of the middle region of the magnetic structure track. The two ends of the magnetic domain wall at the edge of the middle region are pinned, and the non-uniform tension acting on the magnetic domain wall will break to form skyrmions. Due to the strong antiferromagnetic coupling between the subferromagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistive state of the magnetic tunnel junction.

[0040] According to embodiments of this disclosure, more resistive states are achieved by making more skyrmions stably exist in the middle region of the magnetic structure track; and the operating speed of the device is increased by increasing the speed of skyrmion movement.

[0041] According to an embodiment of this disclosure, the memory further includes three transistors: a gate control transistor, a write control transistor, and a read control transistor. The gate control transistor is configured as a select gate; when switching operating modes, the select gate voltage is pulled high to the power supply voltage V. DD When the gate control transistor is turned on, the write word line WBL voltage is pulled high to the mode select voltage Vselect, and the remaining metal lines are grounded. The gate voltage is applied to control the polarization direction of the ferroelectric layer. When operating in binary mode and performing a write 0 operation, the write bit line WWL voltage is pulled high to the power supply voltage V. DD The write line WBL is pulled high to the first write voltage V. write1 The remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the domain wall movement and flip the magnetic moment of the subferromagnetic layer; when performing a write 1 operation, the source line voltage is pulled up to the first write voltage V. write1 The write bit line is grounded to achieve a write 1 operation; when operating in Skymin mode, the write bit line WWL voltage is pulled high to the power supply voltage V during a write operation. DD The voltage on the write line WBL is pulled up to the second write voltage V. write2 V write2 ≠V write1 With the remaining metal wires grounded, under the non-uniform tension generated by the current, the magnetic domain walls break to form skyrmions; the cumulative number of skyrmions is linearly related to the resistance of the magnetic tunnel junction; during a reset operation, the write line WWL voltage is pulled high to the power supply voltage V. DD The source line voltage is pulled up to the first write voltage V. write1 The magnetic domain walls will be driven back to their initial position. Because the antiferromagnetic nails at both ends of the magnetic structure track are anchored, the magnetic domain walls will not be annihilated.

[0042] In this embodiment, as shown in Figure 3, the interface between the topological material layer and the subferromagnetic layer exhibits a strong antisymmetric exchange interaction (Dzyaloshinskii–Moriya interaction, DMI) due to strong spin-orbit coupling. In the figure, the character D represents the DMI constant, and the character P represents ferroelectric polarization. This strong interface DMI ensures the existence of room-temperature stable skyrmions in the system. The ferroelectric polarization of the ferroelectric layer can modulate the amplitude of the interface DMI. When the DMI decreases to a threshold, room-temperature stable skyrmions cannot be formed in the memory system. For example, when the ferroelectric polarization is upward (denoted as P>0), the interface DMI is enhanced beyond the threshold, and skyrmions can exist stably; in this case, the device will operate in skyrmion mode. Conversely, when the ferroelectric polarization is downward (denoted as P<0), the DMI decreases below the threshold, and skyrmions cannot exist stably; in this case, the device operates in binary mode.

[0043] In the embodiments of this disclosure, as shown in Figure 4, subferromagnetic skyrmions can effectively suppress the skyrmion Hall effect, provide skyrmion migration speed, and reduce skyrmion size. However, efficient electrical readout of subferromagnetic materials urgently needs to be addressed. In ferromagnetic materials, skyrmions are prone to annihilation at device boundaries due to the skyrmion Hall effect, and their slow migration speed limits device operating speed. However, ferromagnetic materials, represented by CoFeB, can achieve magnetic tunnel junctions with high tunneling magnetoresistance ratios (TMR), enabling efficient electrical readout. Therefore, in the skyrmion memory of this disclosure, the subferromagnetic layer and the ferromagnetic free layer are antiferromagnetically coupled. Skyrmions nucleate and move in the subferromagnetic track, and due to antiferromagnetic coupling, corresponding skyrmions are also formed in the ferromagnetic layer. The resistive state of the skyrmions is read out through the TMR effect.

[0044] In this embodiment of the disclosure, as shown in Figure 5, both ends of the subferromagnetic track in the magnetic structure track are pinned by antiferromagnetic coupling, thus forming stable domain walls at the edge of the pinned region. When a current is applied, the spin-orbit coupling torque generated by the spin Hall effect (SHE) or the Rashba-Edelstein effect drives the domain walls to move. When the domain walls move to the boundary of the circular region, both ends of the domain walls are pinned by the boundary. Due to the tension action as indicated by the arrow at the boundary of the circular region, the domain walls will break, forming stable skyrmions as in the middle region.

[0045] In this embodiment of the disclosure, as shown in FIG6, when the magnetic storage device operates in binary mode, skyrmions cannot be formed. Darker areas in the circular region represent magnetic moments pointing upwards, lighter areas represent magnetic moments pointing downwards, and the transition areas between the dark and light colors represent domain walls. At this time, current drives the expansion of the domain walls, causing the magnetic tunnel junction region to flip. When the magnetic storage device operates in skyrmion mode, skyrmions are stably generated at the boundary of the magnetic tunnel junction region under current excitation. As the number of accumulated skyrmions in the magnetic tunnel junction region varies, the resistance of the storage device varies, reflected as a multi-step flip curve as shown in FIG.

[0046] In this embodiment of the present disclosure, as shown in FIG7, the memory further includes three transistors: a gate control transistor, a write control transistor, and a read control transistor. The gate control transistor is configured as a select gate; when the memory device switches modes, the select gate voltage is pulled high to the power supply voltage V. DD The gate control transistor is turned on, the write word line WBL voltage is pulled high to the mode select voltage Vselect, and the remaining metal lines are grounded. The gate voltage is applied to control the polarization direction of the ferroelectric layer. When performing a write 0 operation, the write bit line WWL voltage is pulled high to the power supply voltage V. DD The write line WBL is pulled high to the first write voltage V. write1The remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the domain wall movement and flip the magnetic moment of the subferromagnetic layer; when performing a write 1 operation, the source line voltage is pulled up to the first write voltage V. write1 The write bit line is grounded to achieve a write 1 operation; when operating in Skymin mode, the write bit line WWL voltage is pulled high to the power supply voltage V during a write operation. DD The voltage on the write line WBL is pulled up to the second write voltage V. write2 , (V write2 ≠V write1 With the remaining metal wires grounded, under the non-uniform tension generated by the current, the magnetic domain walls break to form skyrmions; the cumulative number of skyrmions is linearly related to the resistance of the magnetic tunnel junction. During a reset operation, the write bit line WWL voltage is pulled high to the power supply voltage V. DD The source line voltage is pulled up to the first write voltage V. write1 The magnetic domain walls will be driven back to their initial position. Because the antiferromagnetic nails at both ends of the magnetic structure track are anchored, the magnetic domain walls will not be annihilated.

[0047] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0048] Based on the above description, those skilled in the art should have a clear understanding of the magnetic skyrmion memory disclosed herein.

[0049] In summary, this disclosure provides a magnetic skyrmion memory in which the two ends of the ferrimagnetic layer are pinned to opposite magnetization directions through antiferromagnetic coupling with the pinning material, resulting in stable magnetic domain walls in the memory. By using spin-orbit moments to drive the magnetic domain walls to break into skyrmions in the circular region below the magnetic tunnel junction, the energy consumption of skyrmion nucleation can be greatly reduced, thereby improving the energy efficiency of the memory device.

[0050] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Any other corresponding changes and modifications made based on the technical concept of this disclosure should be included within the scope of protection of the claims of this disclosure.

Claims

1. A magnetic skyrmion memory, comprising: The magnetic structure track includes a topological material layer and a ferrimagnetic layer, and is constructed to include a central region and extensions extending from both sides of the central region. The ferrimagnetic layers of the two extensions are pinned to opposite magnetic moment directions by antiferromagnetic coupling. A magnetic tunnel junction is located in the middle region of the magnetic structure track and is configured to electrically read the resistance state changes of the memory. The ferroelectric back gate includes a ferroelectric layer and a bottom electrode, and the ferroelectric back gate is located under the middle region of the magnetic structure track; When current is injected into the topological material layer, a spin orbital moment is generated to regulate the movement of the magnetic structure in the ferrimagnetic layer. By applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is controlled, ultimately enabling the memory to operate in skyminster mode or binary mode.

2. The memory according to claim 1, wherein: The central area of ​​the magnetic track is circular, while the extended section is elongated. The magnetic tunnel junction is located above the central area of ​​the magnetic structure track, and the magnetic tunnel junction is constructed to be circular with a diameter no larger than the circular diameter of the central area of ​​the magnetic structure track.

3. The memory according to claim 1 further includes an interface layer, the interface layer being prepared between the topological material layer and the ferrimagnetic layer, the interface layer being configured to improve the interface properties between the topological material layer and the ferrimagnetic layer, thereby increasing the driving efficiency of the spin-orbit moment of the topological material layer.

4. The memory according to claim 1, wherein the magnetic structure comprises magnetic domain walls and / or skyrmions.

5. The memory according to claim 1, wherein: The ferroelectric layer can be HfZrO. x One or a combination of HfO2, BiFeO3, BaTiO3, and In2Se3; The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, and topological half-metals PtSe2, WSe2, PtTe2, and WTe2. The material of the subferromagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, and TbCo; The pinning material layer used for pinning is selected from (Co / Tb) periodic multilayer film, GdFeCo, GdFeO, TbCo, and GdCo alloy materials. By adjusting the chemical composition ratio, the pinning materials on both sides have different coercivity. An external magnetic field is used to configure the pinning material layers on both sides with opposite magnetic moment directions.

6. The memory according to claim 1, wherein the magnetic tunnel junction comprises a ferromagnetic free layer and a ferromagnetic reference layer, the ferromagnetic free layer and the ferromagnetic reference layer being separated by a nonmagnetic insulating barrier layer; the ferromagnetic free layer and the subferromagnetic layer are antiferromagnetically coupled through a space layer located between them; the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; The materials for the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the material for the insulating barrier layer is selected from MgO and AlO. x One or a combination thereof; the space layer material is selected from one or a combination of Ru, Cu, and W.

7. The memory according to claim 1, by applying different voltages to the back gate to change the polarization direction of the ferroelectric layer, the polarization direction can regulate the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the subferromagnetic layer, thereby changing the device operating mode; When the interface antisymmetric exchange action is greater than a set threshold, the skymin can exist stably, and the memory operates in skymin mode. When the antisymmetric exchange interaction at the interface is less than a set threshold, the skyrmion cannot exist stably, and the device operates in binary mode.

8. The memory according to claim 1, wherein the two ends of the subferromagnetic layer are pinned in opposite magnetic moment directions, and a stable magnetic domain wall exists at the edge of the pinned region at one end; by applying a driving current to the topological material layer, the generated spin orbital moment can drive the magnetic domain wall to the edge of the middle region of the magnetic structure track; the two ends of the magnetic domain wall at the edge of the middle region are pinned, and the non-uniform tension acting on the magnetic domain wall will break to form skyrmions; due to the strong antiferromagnetic coupling between the subferromagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistive state of the magnetic tunnel junction.

9. The memory according to claim 1, wherein more resistive states are achieved by making more skyrmions stably exist in the middle region of the magnetic structure track; and the device operating speed is increased by increasing the skyrmion movement speed.

10. The memory according to claim 1 further includes three transistors: a gate control transistor, a write control transistor, and a read control transistor, wherein the gate control transistor is configured as a select gate; When switching operating modes, the selector gate voltage is pulled high to the power supply voltage V. DD Turn on the gate control transistor, and pull the write line WBL voltage high to the mode selection voltage V. select The remaining metal lines are grounded, and a gate voltage is applied to control the polarization direction of the ferroelectric layer. When operating in binary mode and performing a write 0 operation, the write bit line WWL voltage is pulled high to the power supply voltage V. DD The write line WBL is pulled high to the first write voltage V. write1 The remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the domain wall movement and flip the magnetic moment of the subferromagnetic layer; when performing a write 1 operation, the source line voltage is pulled up to the first write voltage V. write1 Writing line Grounding enables the write-1 operation; When operating in Skymin sub-mode, the write bit line WWL voltage is pulled high to the power supply voltage V during a write operation. DD The voltage on the write line WBL is pulled up to the second write voltage V. write2 V write2 ≠V write1 With the remaining metal wires grounded, under the non-uniform tension generated by the current, the magnetic domain walls break to form skyrmions; the cumulative number of skyrmions is linearly related to the resistance of the magnetic tunnel junction. When performing a reset operation, the write bit line WWL voltage is pulled high to the power supply voltage V. DD The source line voltage is pulled up to the first write voltage V. write1 The magnetic domain walls will be driven back to their initial position. Because the antiferromagnetic nails at both ends of the magnetic structure track are anchored, the magnetic domain walls will not be annihilated.

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