Communication methods, apparatus, and storage medium

Abstract

Provided in the present application are communication methods, an apparatus, and a storage medium, which can be applied to the field of satellite communications, such as NTN. A method comprises: a network device performing first channel encoding on a first bit sequence in DCI to obtain a first encoded sequence, the first encoded sequence being carried on N reserved bits in the DCI, the first bit sequence comprising at least one valid information bit in DCI, R≥M+N, R being the number of bits comprised in the DCI, M being the number of bits comprised in the first bit sequence, N being the number of bits comprised in the first encoded sequence, and M, N and R all being positive integers; performing second channel encoding on a second bit sequence to obtain a second encoded sequence, the second bit sequence being obtained by adding CRC bits to a third bit sequence; and sending the second encoded sequence. The solution of the present application can improve the decoding performance of DCI.

Description

Communication methods, devices and storage media

[0001] This application claims priority to Chinese Patent Application No. 202411539398.6, filed on October 30, 2024, entitled "Communication Method, Apparatus and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more particularly to a communication method, apparatus, and storage medium. Background Technology

[0003] Currently, to reduce the complexity of blind detection of the physical downlink control channel (PDCCH) by terminal equipment, the downlink control information (DCI) is size-aligned, and the size-aligned DCI is encoded and transmitted on the PDCCH. If the number of information bits in the DCI is small, DCI size alignment is achieved by adding reserved bits to the DCI.

[0004] During the encoding process of size-aligned DCI, the reserved bits in DCI are also encoded as information bits. This encoding method leads to poor decoding performance of DCI. Summary of the Invention

[0005] This application provides a communication method, apparatus, and storage medium to improve the decoding performance of DCI.

[0006] Firstly, this application provides a communication method that can be applied to a network device. For example, it can be executed by the network device or a communication module within the network device, or by a chip, chip system, or circuit within the network device; this application does not limit the scope of the method. For ease of description, the method is described below using a network device as an example.

[0007] For example, the method includes: a network device performing first channel coding on a first bit sequence in a DCI to obtain a first coded sequence, the first coded sequence being carried on N reserved bits in the DCI to obtain a third bit sequence; wherein the first bit sequence includes at least one valid information bit in the DCI, R ≥ M + N, R is the number of bits in the DCI, M is the number of bits in the first bit sequence, N is the number of bits in the first coded sequence, and M, N, and R are all positive integers. Then, the network device performs second channel coding on a second bit sequence to obtain a second coded sequence, and transmits the second coded sequence.

[0008] The second bit sequence is obtained by adding CRC bits to the third bit sequence. When R = M + N, the DCI consists of the first bit sequence and N reserved bits. Therefore, the third bit sequence consists of the first bit sequence and the first coding sequence. And / or, when R > M + N, the DCI includes the first bit sequence, (RMN) first bits and N reserved bits. Therefore, the third bit sequence includes the first bit sequence, the first coding sequence and (RMN) first bits. The (RMN) first bits are the bits in the DCI other than the first bit sequence and the N reserved bits.

[0009] Based on this technical solution, a first encoded sequence is obtained by performing first channel coding on the first bit sequence in the DCI. This first encoded sequence is then carried on N reserved bits in the DCI to obtain a third bit sequence. Therefore, the third bit sequence is essentially obtained by replacing the N reserved bits in the DCI with the first encoded sequence, and thus the number of bits in the third bit sequence is equal to that in the DCI. In other words, encoding the first bit sequence does not change the size of the DCI, and therefore does not increase the complexity of the terminal's blind detection PDCCH. Furthermore, since the first bit sequence includes at least one valid information bit, which carries valid information, the first encoded sequence obtained by performing first channel coding on the first bit sequence also carries valid information. Moreover, the first encoded sequence can, to some extent, correct transmission errors that occur during channel transmission of the first bit sequence, thereby improving the success rate of the first bit sequence transmission. Therefore, compared to directly encoding the DCI, the solution in this application, through a two-level coding approach, can improve the decoding performance of the DCI without changing its size.

[0010] Secondly, this application provides a communication method that can be applied to the terminal side. For example, it can be executed by the terminal, a communication module within the terminal, or a circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip). For ease of description, the method is described below using a terminal as an example.

[0011] For example, the method includes: a terminal receiving a second encoded sequence and determining a DCI based on the second encoded sequence.

[0012] The second encoded sequence is obtained by encoding the second bit sequence through the second channel. The second bit sequence is obtained by adding CRC bits to the third bit sequence. The third bit sequence includes the first bit sequence and the first encoded sequence. The first bit sequence is the bit sequence in the DCI and includes at least one valid information bit in the DCI.

[0013] The first encoded sequence is obtained by encoding the first bit sequence through the first channel, and the first encoded sequence is carried on N reserved bits in the DCI. R≥M+N, where R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first encoded sequence, and M, N, and R are all positive integers.

[0014] When R = M + N, the third bit sequence consists of the first bit sequence and the first coding sequence; and / or, when R > M + N, the third bit sequence includes the first bit sequence, the first coding sequence and (RMN) first bits, where (RMN) first bits are bits in the DCI other than the first bit sequence and N reserved bits.

[0015] Based on this technical solution, the DCI includes a first bit sequence and N reserved bits. Since the third bit sequence is obtained by carrying the first encoded sequence on the N reserved bits in the DCI, the number of bits in the third bit sequence is equal to that in the DCI. Therefore, by adding CRC bits to the third bit sequence to obtain the second bit sequence, and then performing second channel coding on the second bit sequence, the complexity of the terminal's blind detection PDCCH will not increase. Furthermore, since the first encoded sequence is obtained by performing first channel coding on the first bit sequence in the DCI, and the first bit sequence includes at least one valid information bit in the DCI, the first encoded sequence carries the valid information in the DCI. Moreover, the first encoded sequence can, to a certain extent, correct transmission errors that occur in the first bit sequence during channel transmission, increasing the probability that the terminal can successfully recover the first bit sequence, thereby increasing the likelihood that the terminal can successfully decode the DCI, and improving the decoding performance of the DCI without changing its size.

[0016] In conjunction with the second aspect, in some implementations of the second aspect, the terminal can perform second channel decoding on the second encoded sequence to obtain a second bit sequence, which includes a third bit sequence and CRC bits. Then, the terminal performs CRC check on the third bit sequence based on the CRC bits, and if the CRC check passes, determines the DCI from the third bit sequence.

[0017] Therefore, if the CRC check of the third bit sequence passes, it indicates that no transmission error occurred during the transmission of the third bit sequence from the network device to the terminal. The third bit sequence is obtained by carrying the first encoded sequence on N reserved bits in the DCI. Therefore, the third bit sequence includes all the valid information bits of the DCI. The terminal can obtain the DCI from the third bit sequence without performing the first channel decoding. The decoding complexity is low, and the DCI can be correctly obtained even for terminals that do not support concatenated decoding.

[0018] In conjunction with the second aspect, in some implementations of the second aspect, the terminal can perform second channel decoding on the second encoded sequence to obtain a fourth bit sequence, which includes a fifth bit sequence and CRC bits; wherein, when R = M + N, the fifth bit sequence is composed of a sixth bit sequence and a third encoded sequence; and / or, when R > M + N, the fifth bit sequence includes a sixth bit sequence, a third encoded sequence, and (RMN) first bits.

[0019] Then, the terminal obtains the third bit sequence based on the sixth bit sequence and the third coded sequence. The first bit sequence in the third bit sequence is obtained by first-channel decoding of the sixth bit sequence using the third coded sequence, and the first coded sequence in the third bit sequence is obtained by first-channel encoding of the first bit sequence. First-channel decoding of the sixth bit sequence using the third coded sequence can correct errors in the sixth bit sequence to some extent. Then, first-channel encoding is performed on the obtained first bit sequence to obtain the first coded sequence, thus enabling the generation of the third bit sequence from the first bit sequence and the first coded sequence.

[0020] Then, the terminal performs a CRC check on the third bit sequence based on the CRC bits. If the CRC check passes, it means that the correct third bit sequence has been successfully recovered through the first channel decoding. Therefore, the terminal can determine the DCI from the third bit sequence.

[0021] Therefore, it can be seen that by performing first-channel decoding on the sixth bit sequence using the first encoded sequence, the terminal can, to some extent, correct transmission errors that occur during the transmission of the first bit sequence, thereby increasing the likelihood of the terminal successfully decoding the DCI. Then, by performing first-channel encoding on the obtained first bit sequence to obtain the first encoded sequence, and based on the first bit sequence and the first encoded sequence, the third bit sequence is obtained. By performing CRC verification on the third bit sequence using CRC bits, it can be determined whether the above concatenated decoding process has successfully recovered the correct third bit sequence. If the correct third bit sequence is recovered, the terminal can determine the DCI from the third bit sequence.

[0022] In conjunction with the second aspect, in some implementations of the second aspect, before obtaining the third bit sequence based on the sixth bit sequence and the third encoded sequence, the terminal also performs CRC verification on the fifth bit sequence based on the CRC bits, and the CRC verification fails.

[0023] In conjunction with the first and second aspects, in certain implementations of the first and second aspects, the first bit sequence is one of the following: a portion of the valid information bits in the DCI; all the valid information bits in the DCI; all the valid information bits in the DCI and a portion of the reserved bits in the DCI.

[0024] Based on this, network devices can flexibly select the first bit sequence in DCI according to the number of bits included in the first bit sequence, thereby improving the flexibility of the first channel coding.

[0025] In conjunction with the first and second aspects, in some implementations of the first and second aspects, the encoding method of the first channel coding is BCH coding, and M = kQ, wherein: the first bit sequence includes Q sub-bit sequences, each sub-bit sequence includes k bits; the first coding sequence includes Q sub-coding sequences, which are obtained by performing BCH coding on the Q sub-bit sequences respectively, each sub-coding sequence includes N / Q bits, and k and Q are both positive integers.

[0026] In one possible implementation, M is 22, k is 11, and Q is 2.

[0027] When the encoding method of the first channel is BCH encoding, and the number of bits M in the first bit sequence is an integer multiple (Q times) of the number of information bits k, by dividing the first bit sequence into Q sub-bit sequences of length k, the network device can perform BCH encoding on these Q sub-bit sequences separately using a set of BCH encoding parameters, thus reducing the complexity of the first channel encoding. For the terminal, the decoding of the Q sub-bit sequences can be achieved using a set of decoding parameters, thus reducing the decoding complexity.

[0028] In conjunction with the first and second aspects, in some implementations of the first and second aspects, the encoding method of the first channel coding is BCH encoding, and the value of M is 22. The first bit sequence includes three sub-bit sequences, and the number of bits included in the three sub-bit sequences are 4, 7, and 11, respectively.

[0029] In conjunction with the first and second aspects, in some implementations of the first and second aspects, the second coding sequence is obtained by performing second channel coding on the input sequence of the second channel coding, and the input sequence of the second channel coding is generated based on the reliability of each bit in the second bit sequence, wherein the reliability of the first coding sequence is greater than the reliability of the first bit sequence.

[0030] Since the reliability of the first encoded sequence is greater than that of the first bit sequence, the first encoded sequence is more likely to be successfully transmitted than the first bit sequence. Even if the first bit sequence has a transmission error during transmission, the first encoded sequence can correct the transmission error of the first bit sequence and improve the overall decoding performance.

[0031] In conjunction with the first and second aspects, in some implementations of the first and second aspects, the second coding sequence is obtained by performing second channel coding on the input sequence of the second channel coding. The input sequence of the second channel coding is generated based on the reliability of each bit in the second bit sequence, wherein, when R>M+N and (RMN) first bits include K valid information bits, the reliability of the K valid information bits is greater than the reliability of the first bit sequence, and K is a positive integer.

[0032] Placing the K valid information bits in positions with higher reliability than the first bit sequence can increase the probability of successful transmission of the K valid information bits, thereby improving the overall decoding performance.

[0033] Combining the first and second aspects, in some implementations of the first and second aspects, the second coding sequence is obtained by performing second channel coding on the input sequence of the second channel coding, and the input sequence of the second channel coding is generated based on the reliability of each bit in the second bit sequence; the coding method of the first channel coding is BCH coding, the first bit sequence includes P sub-bit sequences, the first coding sequence includes P sub-coding sequences, and the P sub-coding sequences are obtained by performing BCH coding on the P sub-bit sequences respectively, where P is a positive integer greater than 1.

[0034] Optionally, the reliability of each of the P sub-bit sequences is positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding. By setting a positive correlation between the reliability of each of the P sub-bit sequences and the code rate of each of the P sub-bit sequences after the first channel coding, the probability of successful transmission of sub-bit sequences with larger code rates can be further increased, thereby improving the overall decoding performance.

[0035] Optionally, the reliability of the BCH code block corresponding to each of the P sub-bit sequences is positively correlated with the code rate after the first channel coding of each of the P sub-bit sequences. For each sub-bit sequence, the corresponding BCH code block includes the sub-bit sequence and the sub-coded sequence obtained by BCH coding the sub-bit sequence. By setting the reliability of the BCH code block corresponding to each of the P sub-bit sequences to be positively correlated with the code rate after the first channel coding of each of the P sub-bit sequences, the probability of successful transmission of the BCH code block corresponding to the sub-bit sequence with a larger code rate can be further improved, thereby improving the overall decoding performance.

[0036] Thirdly, this application provides a communication device. This communication device has the functionality to implement some or all of the functional embodiments described in the first aspect. The functionality can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes at least one unit or module corresponding to the aforementioned functionality.

[0037] Fourthly, this application provides a communication device. This communication device has the functionality to implement some or all of the functional embodiments described in the second aspect above. The functionality can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes at least one unit or module corresponding to the aforementioned functionality.

[0038] Fifthly, this application provides a communication device including one or more processors for executing a computer program (also referred to as code or instructions) in a memory, such that the communication device implements the communication method in the first aspect or the second aspect and any possible implementation of the first aspect or the second aspect.

[0039] One possible design is that the device further includes a memory for storing computer programs and data. This memory is coupled to the processor, which, when executing the computer program stored in the memory, can implement the methods described in the first or second aspect above.

[0040] One possible design is that the device also includes a communication interface for communicating with other devices. For example, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0041] For example, the device in the third aspect is a network device, or a component of a network device, such as a chip, chip system, processor, etc. The device in the fourth aspect is a terminal, or a component of a terminal, such as a chip, chip system, processor, etc.

[0042] Sixthly, this application provides a chip system including at least one processor for supporting the implementation of the functions involved in the first to second aspects and any possible implementations described above, such as processing the information involved in the methods described above.

[0043] In one possible design, the chip system also includes a memory for storing computer programs and data, which may be located inside or outside the processor.

[0044] The chip system can consist of chips or include chips and other discrete components.

[0045] One possible design is that the chip system also includes a power supply circuit for supplying power to the chip system.

[0046] In a seventh aspect, this application provides a computer-readable storage medium including a computer program that, when run on a computer, causes the computer to implement the methods in any of the foregoing aspects and any possible implementations of any of the foregoing aspects.

[0047] Eighthly, this application provides a computer program product comprising: a computer program (also referred to as code or instructions) that, when run, causes a computer to perform the methods of any of the above aspects and any possible implementations of any of the above aspects.

[0048] Ninthly, embodiments of this application provide a system including the aforementioned terminal and network device.

[0049] The beneficial effects achieved by the third to ninth aspects of this application are similar to those of the first to second aspects of this application and their corresponding feasible implementations, and will not be described again. Attached Figure Description

[0050] Figure 1 is a schematic diagram of the architecture of a communication system applicable to the communication method provided in this application;

[0051] Figure 2 is a schematic diagram of the architecture of a satellite communication system provided in an embodiment of this application;

[0052] Figure 3 is a schematic diagram of a DCI processing procedure;

[0053] Figure 4 is a schematic flowchart of the communication method provided in an embodiment of this application;

[0054] Figure 5 is a schematic diagram of performing a first channel coding on a first bit sequence according to an embodiment of this application;

[0055] Figure 6 is a schematic diagram of performing a first channel coding on a first bit sequence according to an embodiment of this application;

[0056] Figure 7 is a schematic diagram of performing a first channel coding on a first bit sequence according to an embodiment of this application;

[0057] Figure 8 is a schematic diagram of a DCI concatenated coding provided in an embodiment of this application;

[0058] Figure 9 is a schematic flowchart of the communication method provided in an embodiment of this application;

[0059] Figure 10 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0060] Figure 11 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0061] Figure 12 is another schematic block diagram of the communication device provided in an embodiment of this application;

[0062] Figure 13 is a schematic diagram of the structure of the terminal device provided in the embodiment of this application. Detailed Implementation

[0063] The technical solution provided in this application will now be described with reference to the accompanying drawings.

[0064] To facilitate understanding of the embodiments of this application, the following points will be explained first:

[0065] First, in the embodiments of this application, the use of prefixes such as "first" and "second" is merely for the purpose of distinguishing and describing different things belonging to the same name category, and does not constrain the order, size, or quantity of things. For example, "first configuration cycle" and "second configuration cycle" are simply different cycles, and do not limit the number of devices or their priority; similarly, "first information" and "second information" are simply different pieces of information, and there is no temporal sequence, size, or priority relationship between them.

[0066] Second, in this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the preceding and following related objects, but it does not exclude the possibility of indicating an "and" relationship; the specific meaning can be understood in context. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c; a and b; a and c; b and c; or a and b and c. Here, a, b, and c can be single or multiple.

[0067] Third, in the embodiments of this application, "send" and "receive" indicate the direction of signal transmission. For example, "send first information to the terminal device" can be understood as the destination of the information being the terminal device, which may include direct transmission via the air interface or indirect transmission via the air interface by other units or modules. "Receive second information from the network device" can be understood as the source of the configuration information being the network device, which may include direct reception from the network device via the air interface or indirect reception from the network device via the air interface by other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface.

[0068] In other words, sending and receiving can occur between devices, such as between terminal devices and network devices; or they can occur within a device, such as between components, modules, chips, software modules, or hardware modules within a device via a bus, wiring, or interface.

[0069] It is understandable that information may undergo necessary processing, such as encoding and modulation, before being sent from the source to the destination. Similarly, the destination, upon receiving information from the source, can also perform corresponding processing, such as decoding and demodulation, to interpret the valid information from the source. Similar expressions in this application can be understood in a similar way and will not be elaborated further.

[0070] Fourth, in this application, the indication includes explicit indication (also known as direct indication) and implicit indication (also known as indirect indication). Explicit indication information A refers to including information A; implicit indication information A refers to indicating information A through the correspondence between information A and information B, and direct indication information B. The correspondence between information A and information B can be predefined, pre-stored, pre-burned, or pre-configured; or it can refer to indicating information A through information B and preset rules.

[0071] Fifth, in this application, information C is used to determine information D, which includes both determining information D based solely on information C and determining it based on information C and other information. Furthermore, information C can also be used to determine information D indirectly, for example, in the case where information D is determined based on information E, and information E is determined based on information C.

[0072] Sixth, in the embodiments of this application, descriptions such as "when," "under the circumstances," "if," and "if" all refer to the fact that the device (e.g., network device or terminal device) will make corresponding processing under certain objective circumstances. They are not time limits, nor do they require the device (e.g., network device or terminal device) to make a judgment action when implementing it, nor do they mean that there are other limitations.

[0073] Seventh, the predefined terms in this application can be understood as: definition, pre-defined, storage, pre-storage, pre-negotiation, pre-configuration, solidification, or pre-firing.

[0074] The technical solutions provided in this application can be applied to various communication systems, such as: Long Term Evolution (LTE) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, sidelink (SL) communication systems, Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) communication systems, 5th Generation (5G) mobile communication systems or new radio access technology (NR), satellite communication systems, etc. Among them, 5G mobile communication systems can include non-standalone (NSA) and / or standalone (SA) networks. The technical solutions provided in this application can also be applied to future communication systems, such as 6th Generation (6G) mobile communication systems. Satellite communication systems can be satellite communication systems integrated with 5G mobile communication systems or future communication systems, such as non-terrestrial networks (NTN), etc., and this application does not limit this.

[0075] Figure 1 is a schematic diagram of the architecture of a communication system applicable to the communication method provided in this application. Figure 1 shows a schematic diagram of a possible, non-limiting system architecture. As shown in Figure 1, the communication system 100 includes a radio access network (RAN) 10 and a core network (CN) 20. Optionally, the communication system 100 also includes an Internet 30. RAN 10 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (120a-120j in Figure 1, collectively referred to as 120). RAN 10 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wiredly connected to core network 20. The core network equipment in core network 20 and RAN node 110 in RAN 10 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0076] RAN 10 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 10 can also be an open access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (Wi-Fi) system. RAN 10 can also be a communication system that integrates two or more of the above systems.

[0077] RAN node 110, sometimes also referred to as access network equipment, network equipment, RAN entity, or access node, is part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 100 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 10 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0078] In one possible scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a next-generation base station in a 6G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system. A RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). In satellite communication systems, a RAN node can be a satellite or a base station mounted on a satellite. A RAN node in satellite communication can also be a satellite communication terminal, such as a portable station, a fixed station, or a vehicle-mounted or airborne satellite communication terminal. It should be understood that satellite communication terminals communicate with satellites and can also act as micro base stations to provide data interfaces to accessed user equipment.

[0079] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0080] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0081] A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), satellite communication (e.g., NTN), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, etc.

[0082] In the embodiments of this application, the terminal and network device can be hardware devices, or software functions running on dedicated hardware, or software functions running on general-purpose hardware, such as virtualization functions instantiated on a platform (e.g., cloud platform), or entities that include dedicated or general-purpose hardware devices and software functions. This application does not limit the specific form of the terminal and network device.

[0083] With the development of information technology, there are more urgent requirements for the efficiency, mobility and diversity of communication. At present, in some fields, such as space communication, aviation communication, and military communication, satellites play an irreplaceable role.

[0084] Compared to terrestrial mobile communication networks, satellite communication utilizes high, medium, and low Earth orbit satellites to achieve wide-area or even global coverage, providing seamless communication services to users worldwide. The integration of satellite communication systems with 5G leverages their respective strengths to create a globally seamless, integrated communication network encompassing land, sea, air, and space, meeting users' diverse and ubiquitous service needs and representing a crucial direction for future communication development.

[0085] The integration of satellite and 5G will give full play to their respective advantages and provide users with more comprehensive and high-quality services. This is mainly reflected in: (1) In remote areas, on airplanes or ocean-going ships where terrestrial 5G networks cannot cover, satellites can provide economical and reliable network services, extending the network to places where terrestrial networks cannot reach; (2) Satellites can provide continuous and uninterrupted network connections for IoT devices and mobile carriers such as airplanes, ships, trains and cars. After the integration of satellite and 5G, the service capabilities of 5G systems in this regard can be greatly enhanced; (3) The superior broadcast / multicast capabilities of satellites can provide efficient data distribution services for network edges and terminals.

[0086] Compared to earlier satellite mobile communication systems, current satellite mobile communication development exhibits two key characteristics: Miniaturization of mobile terminals: supporting various mobile communication terminals, including handheld devices; and Broadband communication services: in addition to traditional narrowband voice services, providing high-speed data services and Internet multimedia communication services.

[0087] Figure 2 is a schematic diagram of the architecture of a satellite communication system provided in an embodiment of this application. As shown in Figure 2, the network elements involved in the satellite communication system may include, for example, terminals, base stations, core networks, ground stations, etc.

[0088] A terminal is a mobile device that supports 5G New Radio (NR). It can access satellite networks and initiate services such as calls and internet access through 5G NR. A base station primarily provides wireless access services, scheduling wireless resources for the terminal and providing reliable wireless transmission protocols and data encryption protocols.

[0089] The core network consists of multiple functional units that perform services such as user access control, mobility management, session management, user security authentication, and billing. These functional units can be categorized into control plane functional entities and data plane functional entities, as shown in Figure 2. Control plane functional entities may include, for example, the Access and Mobility Management Function (AMF) and the Session Management Function (SMF). The AMF is responsible for access management, security authentication, and mobility management, while the SMF is responsible for session establishment, modification, release, etc. Data plane functional entities may include, for example, the User Plane Function (UPF), responsible for managing user plane data transmission, traffic statistics, etc. The core network may also include other functional units; not all functional units are shown in Figure 2.

[0090] The interfaces involved between various network elements may include, for example, 5G New Radio (NR), Xn interface, NG interface, etc. Among them, 5G NR is the radio link between the terminal and the base station; Xn interface is the interface between base stations, mainly used for signaling interaction such as handover; NG interface is the interface between the base station and the core network, mainly used for signaling interaction such as Non-Access Stratum (NAS) of the core network, as well as the interaction of service data.

[0091] As shown in Figure 2, the ground terminal accesses the base station through the 5G New Radio interface. The base station is deployed on a satellite and connected to the ground core network via a wireless link (NG interface). Wireless links (Xn interface) exist between satellites, enabling signaling interaction and user data transmission between base stations.

[0092] To better understand the methods provided in the embodiments of this application, the terms involved in this application will be briefly explained below.

[0093] 1. DCI

[0094] DCI is a type of control information, typically carried on the PDCCH and sent to the terminal by network devices. It enables flexible scheduling of uplink and downlink data and optimizes transmission performance.

[0095] DCIs come in various types and formats, and their lengths (i.e., the number of bits they contain) may differ. Different types of DCIs may serve different purposes, and they can be scrambled using different radio network temporary identifiers (RNTIs). For example, a DCI carried in a PDCCH scrambled with a random access RNTI (RA-RNTI) is used to schedule message 2 (msg2), while a DCI carried in a PDCCH scrambled with a system information RNTI (SI-RNTI) is used to schedule broadcast messages, and so on.

[0096] 2. System code

[0097] Systematic codes are a type of encoding where the encoded codeword contains the original information sequence. During the encoding process, the original information sequence remains unchanged, and a generated check bit is appended to it. The original information sequence and the generated check bit together constitute the encoded codeword. Due to this characteristic of systematic codes, the original information sequence can be recovered by removing the generated check bit from the encoded codeword.

[0098] 3. BCH code

[0099] BCH codes are a type of multilevel, cyclic, error-corrected, variable-length digital code, belonging to the category of systematic codes. BCH codes are constructed based on a generator polynomial. During the encoding process, the original information sequence is divided into multiple message groups of fixed k bits each. Each message group is then encoded to obtain a corresponding codeword. For a given message group, the number of bits in the message group is k, where k represents the number of information bits. The number of bits in the codeword obtained by BCH encoding this message group is n, where n represents the codeword length.

[0100] For BCH codes, the information bit length k, code length n, generator polynomial g(x), and error correction bit length have specific values. An example of such values ​​can be found in Table 1 below:

[0101] Table 1

[0102] Referring to Table 1, when the information bit k of the message group is 4, the corresponding code length n = 7, the error correction bit t = 1, and the generator polynomial g(x) = 13; when the information bit k of the message group is 11, 7, or 5, the corresponding code length n = 15. From Table 1, the corresponding error correction bit t and generator polynomial g(x) can be determined, and so on.

[0103] During the process of a network device sending a DCI to a terminal, the network device needs to encode the DCI. The following describes an exemplary DCI encoding implementation scheme with reference to Figure 3.

[0104] Figure 3 is a schematic diagram of the DCI processing procedure. As shown in Figure 3, the initial DCI includes *a* valid information bits, where *a* is a positive integer greater than or equal to 1. The initial DCI is the DCI before size alignment. These *a* valid information bits carry valid information, which may include resource allocation information, modulation and coding schemes, etc. For different DCI formats, the number of valid information bits may vary, and the valid information carried by the valid information bits may also differ.

[0105] The DCI is transmitted over the PDCCH. To reduce the complexity of blind detection of the PDCCH by the terminal, the size of the DCI needs to be aligned. If the number of valid information bits in the initial DCI is small, the size of the DCI is aligned by adding reserved bits. Taking Figure 3 as an example, if the required number of bits in the DCI is R (R is a positive integer greater than a), since the number of valid information bits in the initial DCI is less than R, size alignment is performed by adding (Ra) reserved bits to the initial DCI to obtain the size-aligned DCI. As shown in Figure 3, the size-aligned DCI consists of two parts: one part is the a valid information bits in the initial DCI, and the other part is the (Ra) reserved bits.

[0106] As shown in Figure 3, after completing the size alignment of the DCI, the network device adds CRC bits to the size-aligned DCI (hereinafter referred to as DCI) to obtain sequence A. Then, the network device encodes sequence A to obtain sequence B and sends sequence B to the terminal device.

[0107] In the above encoding process, both the *a* valid information bits and the (Ra) reserved bits in the DCI are encoded as information bits. On the terminal device side, when the terminal device receives sequence B and decodes the DCI based on sequence B, it does not know which bits are valid information bits and which are reserved bits. Therefore, the terminal device needs to decode all bits in sequence B (including the *a* valid information bits and the (Ra) reserved bits). This process increases the complexity and computational load of decoding. Furthermore, the reserved bits do not carry any valid information. Therefore, the above encoding method leads to poor DCI decoding performance. For example, in the satellite communication scenario illustrated in Figure 2, due to the poor link budget, the above encoding method may cause DCI decoding failure.

[0108] DCI plays a crucial role in terminal access. In some scenarios, DCI does not support repeated transmission; if it did, it would significantly impact resource scheduling for other signals. For example, regarding DCI carried on a RA-RNTI scrambled PDCCH, the search space for the type 0 PDCCH control signal (i.e., the control signal for scheduling system information block 1 (SIB1)) is indicated by the master information block (MIB), and the type 0 PDCCHs corresponding to different synchronization signal block (SSB) indices have a certain temporal positional relationship. Therefore, the RA-RNTI scrambled PDCCH must be transmitted within a limited random access response window. Repeated transmission of DCI carried on the RA-RNTI scrambled PDCCH would excessively occupy the random access response window, affecting scheduling flexibility. Therefore, improving the decoding performance of DCI is essential.

[0109] Based on this, embodiments of this application provide a communication method, apparatus, and storage medium, which can effectively improve the decoding performance of DCI.

[0110] The communication method provided in the embodiments of this application is described in detail below with reference to the accompanying drawings. The communication method provided in the embodiments of this application can be applied to the communication systems illustrated in Figures 1 and 2, but the embodiments of this application are not limited thereto.

[0111] Figure 4 is a schematic flowchart of the communication method provided in an embodiment of this application. In the flowchart of Figure 4, the method is shown from the perspective of a network device, but the embodiments of this application do not limit the subject executing the method. For example, the network device in Figure 4 can be replaced by a chip, chip system, or processor that supports the network device in implementing the method, or it can be a logic module or software that can implement all or part of the functions of the network device.

[0112] As shown in Figure 4, the method may include steps S401, S402 and S403. The steps in the method will be described in detail below.

[0113] S401, perform first channel coding on the first bit sequence in the DCI to obtain the first coded sequence, which is carried on N reserved bits in the DCI.

[0114] The first bit sequence includes at least one valid information bit in the DCI, R≥M+N, where R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first coding sequence, and M, N, and R are all positive integers.

[0115] In this embodiment, the DCI is a DCI obtained after size alignment, therefore the DCI includes valid information bits and reserved bits. The valid information bits carry valid information, while the reserved bits do not carry valid information; the reserved bits are added during the size alignment process. Taking the number of valid information bits in the DCI as 'a', where 'a' is a positive integer greater than or equal to 1, and R > 'a', then the number of reserved bits in the DCI is Ra.

[0116] The first bit sequence is part of the DCI and includes at least one valid information bit in the DCI. This at least one valid information bit can be all the valid information bits in the DCI or a portion of the valid information bits in the DCI. The first bit sequence may or may not include some reserved bits in the DCI.

[0117] The first coded sequence is obtained by first channel coding of the first bit sequence. Optionally, the encoding method of the first channel coding is a systematic code, such as BCH coding, linear block code coding, etc.

[0118] The first encoded sequence includes N bits, where N satisfies: N ≤ Ra, and Ra is the number of reserved bits in the DCI. That is, the number of reserved bits in the DCI needs to be greater than or equal to the number of bits included in the first encoded sequence, so that the first encoded sequence can be carried on the reserved bits in the DCI.

[0119] S402, perform second channel coding on the second bit sequence to obtain the second coded sequence. The second bit sequence is obtained by adding CRC bits to the third bit sequence.

[0120] In the case of R = M + N, the third bit sequence consists of the first bit sequence and the first coding sequence; and / or, in the case of R > M + N, the third bit sequence includes the first bit sequence, the first coding sequence and (RMN) first bits, where (RMN) first bits are bits in the DCI other than the first bit sequence and N reserved bits.

[0121] After the network device performs first channel coding on the first bit sequence to obtain the first coded sequence, the first coded sequence is carried on N reserved bits in the DCI to obtain the third bit sequence.

[0122] For example, when the number of bits included in the DCI is R = M + N, the DCI consists of a first bit sequence and N reserved bits, where N is the number of bits included in the first encoded sequence. Therefore, the first encoded sequence just fills these N reserved bits, and the resulting third bit sequence consists of the first bit sequence and the first encoded sequence. In this case, the number of bits included in the third bit sequence is M + N, which is equal to the number of bits included in the DCI, R.

[0123] For example, when the number of bits in the DCI is R>M+N, the DCI includes a first bit sequence, N reserved bits, and (RMN) first bits. These (RMN) first bits can be all valid information bits, all reserved bits, or both. The first encoded sequence is carried on the N reserved bits in the DCI, resulting in a third bit sequence that includes the first bit sequence, the first encoded sequence, and (RMN) first bits.

[0124] After obtaining the third bit sequence, the network device adds CRC bits to the third bit sequence to obtain the second bit sequence, where the CRC bits are used to perform CRC verification on the third bit sequence.

[0125] After obtaining the second bit sequence, the network device performs second channel coding on the second bit sequence to obtain the second coded sequence. The second channel coding can be performed using methods such as polar coding or tail biting convolutional code (TBCC).

[0126] S403, send the second encoded sequence.

[0127] After obtaining the second encoded sequence, the network device sends it to the terminal. The network device can modulate the second encoded sequence and map it onto PDCCH resources for transmission. Correspondingly, the terminal acquires the relevant data by monitoring the PDCCH and demodulates the acquired data to obtain the second encoded sequence.

[0128] In this embodiment, the network device can perform first channel coding on the first bit sequence in the DCI to obtain a first coded sequence. The first coded sequence is carried on N reserved bits in the DCI, thereby obtaining a third bit sequence. When R = M + N, the third bit sequence consists of the first bit sequence and the first coded sequence. When R > M + N, the third bit sequence includes the first bit sequence, the first coded sequence, and (RMN) first bits. The (RMN) first bits are the bits in the DCI other than the first bit sequence and the N reserved bits, where R is the number of bits in the DCI, M is the number of bits in the first bit sequence, and N is the number of bits in the first coded sequence. Therefore, the number of bits in the third bit sequence is equal to the number of bits in the DCI; the third bit sequence is essentially obtained by replacing the N reserved bits in the DCI with the first coded sequence. Since the first bit sequence includes at least one valid information bit, and the at least one valid information bit carries valid information, the first encoded sequence obtained by first channel coding the first bit sequence also carries valid information. Furthermore, the first encoded sequence can improve the success rate of the transmission of the first bit sequence. Therefore, compared with the method of directly encoding the DCI, the scheme of this application embodiment can improve the decoding performance of the DCI without changing the size of the DCI through a two-level encoding method.

[0129] In one possible implementation, the first bit sequence exists in one of the following three cases:

[0130] Scenario 1: Partial valid information bits in DCI;

[0131] Scenario 2: All valid information bits in the DCI;

[0132] Scenario 3: All valid information bits in the DCI and some reserved bits in the DCI.

[0133] The following uses the example of the number of effective information bits included in the DCI being 'a' and the number of reserved bits included in the DCI being 'b', and introduces the above three cases in conjunction with Figures 5 to 7. Here, a and b are both positive integers, a + b = R, and R is the number of bits included in the DCI.

[0134] Figure 5 is a schematic diagram of performing a first channel coding on a first bit sequence according to an embodiment of this application. As shown in Figure 5, the number of bits included in the DCI is R, wherein the DCI includes a valid information bits and b reserved bits.

[0135] Regarding scenario one above, the first bit sequence consists of a portion of the valid information bits in the DCI. The first bit sequence includes M bits, meaning it contains M valid information bits. <a。

[0136] The network device performs first-channel encoding on the first bit sequence to obtain a first encoded sequence. The number of bits included in the first encoded sequence is N, and N ≤ b. Correspondingly, R = a + b > M + N. Therefore, in Case 1, the DCI includes the first bit sequence, N reserved bits, and (R - M - N) first bits. Among them, when N = b, the (R - M - N) first bits are the (R - M - N) valid information bits other than the first bit sequence among the a valid information bits of the DCI; when N < b, the (R - M - N) first bits include the (a - M) valid information bits other than the first bit sequence among the a valid information bits, and (b - N) reserved bits.

[0137] By carrying the first encoded sequence on the N reserved bits in the DCI, a third bit sequence can be obtained. Among them, the third bit sequence includes the first bit sequence, the first encoded sequence, and (R - M - N) first bits.

[0138] Figure 6 is a second schematic diagram of performing first-channel encoding on the first bit sequence provided by an embodiment of the present application. As shown in Figure 6, the number of bits included in the DCI is R, where the DCI includes a valid information bits and b reserved bits.

[0139] For the above Case 2, the first bit sequence is all the valid information bits in the DCI. The number of bits included in the first bit sequence is M, that is, the first bit sequence includes M valid information bits, and M = a.

[0140] The network device performs first-channel encoding on the first bit sequence to obtain a first encoded sequence. The number of bits included in the first encoded sequence is N, and N ≤ b. By carrying the first encoded sequence on the N reserved bits in the DCI, a third bit sequence can be obtained.

[0141] For the above Case 2, when R = M + N, the DCI is composed of the first bit sequence and N reserved bits, and the first encoded sequence just fills these N reserved bits. Therefore, the third bit sequence is composed of the first bit sequence and the first encoded sequence. In this case, b = N; when R > M + N, the DCI includes the first bit sequence, N reserved bits, and (R - M - N) first bits. The third bit sequence includes the first bit sequence, the first encoded sequence, and (R - M - N) first bits. Among them, the (R - M - N) first bits are all reserved bits. Since M = a, R - M - N = b - N.

[0142] Figure 7 is a third schematic diagram of performing first-channel encoding on the first bit sequence provided by an embodiment of the present application. As shown in Figure 7, the number of bits included in the DCI is R, where the DCI includes a valid information bits and b reserved bits.

[0143] Regarding scenario three above, the first bit sequence includes all valid information bits and some reserved bits in the DCI. The number of bits included in the first bit sequence is M, that is, the first bit sequence includes a valid information bits and (Ma) reserved bits, where M>a.

[0144] The network device performs first channel coding on the first bit sequence to obtain a first coded sequence, which includes N bits, where N ≤ b. The first coded sequence is then carried on N reserved bits in the DCI to obtain a third bit sequence.

[0145] Regarding scenario three above, when R = M + N, the DCI consists of a first bit sequence and N reserved bits, and the third bit sequence consists of a first bit sequence and a first coding sequence; when R > M + N, the DCI includes a first bit sequence, N reserved bits, and (RMN) first bits, and the third bit sequence includes a first bit sequence, a first coding sequence, and (RMN) first bits, where (RMN) first bits are all reserved bits.

[0146] In the above embodiments, several possible cases of the first bit sequence were introduced. The following are some specific examples.

[0147] Taking the DCI as an example, where the number of bits included is R=37 and the number of bits included in the first bit sequence is M=22.

[0148] If the DCI is carried on a PDCCH scrambled with SN-RNTI, then the number of reserved bits included in the DCI is 15 (for the non-shared spectrum case) or 17 (for the shared spectrum case). If the DCI includes 15 reserved bits, then the DCI includes 22 valid information bits. In this case, the first bit sequence can be all the valid information bits in the DCI. If the DCI includes 17 reserved bits, then the DCI includes 20 valid information bits. In this case, the first bit sequence can include all 20 valid information bits in the DCI and 2 reserved bits.

[0149] If the DCI is a DCI carried on a PDCCH scrambled with RA-RNTI, then the number of reserved bits included in the DCI is 16-A (for non-shared spectrum) or 18-A (for shared spectrum). Where A is 0 for four-step random access and 2 for two-step random access. Therefore, the number of reserved bits included in the DCI can be 14, 16, 18, etc. If the DCI includes 14 reserved bits, then it includes 23 valid information bits. In this case, the first bit sequence can include some of the valid information bits in the DCI (i.e., 22 valid information bits). If the DCI includes 16 reserved bits, then it includes 21 valid information bits. In this case, the first bit sequence can include all 21 valid information bits in the DCI and 1 reserved bit. If the DCI includes 18 reserved bits, then the DCI includes 19 valid information bits. In this case, the first bit sequence may include all 19 valid information bits and 3 reserved bits in the DCI.

[0150] It should be understood that in the above implementation, the values ​​of the number of bits R included in DCI and the number of bits M included in the first bit sequence are merely examples and do not constitute a limitation on the actual values.

[0151] In one possible implementation, the first channel coding method is BCH coding. For the first bit sequence, the network device divides the first bit sequence into multiple sub-bit sequences, and then performs BCH coding on each of the multiple sub-bit sequences to obtain the sub-coded sequences corresponding to each of the multiple sub-bit sequences. The first coding sequence includes the sub-coded sequences corresponding to each of the multiple sub-bit sequences.

[0152] For example, if the first channel coding uses BCH coding and M = kQ, then the network device can divide the first bit sequence into Q sub-bit sequences. That is, the first bit sequence includes Q sub-bit sequences, each of which contains k bits, where k and Q are both positive integers. Then, the network device performs BCH coding on each of the Q sub-bit sequences to obtain Q sub-coded sequences. The first coded sequence includes these Q sub-coded sequences, which are obtained by performing BCH coding on each of the Q sub-bit sequences. Each sub-coded sequence contains N / Q bits.

[0153] For example, M is 22, k is 11, Q is 2, and M is the number of bits in the first bit sequence. That is, the first bit sequence contains 22 bits, and the network device can divide the first bit sequence into two sub-bit sequences, each containing 11 bits.

[0154] Since these two sub-bit sequences contain the same number of bits, they can be BCH encoded separately using a single set of BCH encoding parameters. For example, referring to Table 1, when k is 11, the corresponding code length n = 15, the error correction bits t = 1, and the generator polynomial g(x) = 23. Using the aforementioned BCH encoding parameters, these two sub-bit sequences can be BCH encoded separately, resulting in two sub-coded sequences. Each sub-coded sequence contains N / Q = nk = 15 - 11 = 4 bits. The first coded sequence includes both sub-coded sequences, therefore the first coded sequence contains N = 8 bits.

[0155] For example, taking the DCI carried on a PDCCH scrambled with SI-RNTI as an example, the DCI includes R = 37 bits, of which 22 are valid information bits and 15 are reserved bits. If the number of bits M in the first bit sequence is 22, then the first bit sequence includes these 22 valid information bits. The network device can divide these 22 valid information bits into two sub-bit sequences, each including 11 valid information bits. Then, each sub-bit sequence is BCH encoded with a code length of 15 to obtain the corresponding sub-encoded sequence. Each sub-encoded sequence includes 15 - 11 = 4 bits, therefore the first encoded sequence includes N = 8 bits.

[0156] In this scenario, R > M + N, therefore the DCI includes a first bit sequence (i.e., 22 valid information bits), N reserved bits (N = 8), and (RMN) first bits, of which (RMN) first bits are 7 reserved bits. Then, the first bit sequence, the first encoded sequence, and (RMN) first bits are concatenated to obtain the third bit sequence. After obtaining the third bit sequence, the network device adds CRC bits to it to obtain the second bit sequence, and performs second channel coding on the second bit sequence to obtain the second encoded sequence.

[0157] In this embodiment of the application, when the encoding method of the first channel coding is BCH encoding and the number of bits M included in the first bit sequence satisfies M = kQ, by dividing the first bit sequence into multiple sub-bit sequences of equal length, it is possible to encode multiple sub-bit sequences based on a set of BCH encoding parameters, thereby reducing the implementation complexity of the first channel coding.

[0158] For example, the encoding method of the first channel coding is BCH encoding, and the value of M is 22. The first bit sequence includes 3 sub-bit sequences, and the number of bits included in the 3 sub-bit sequences are 4, 7, and 11 respectively.

[0159] For example, taking the DCI carried on a RA-RNTI scrambled PDCCH as an example, the DCI includes 37 bits R, of which 21 are valid information bits and 16 are reserved bits. If the number of bits M in the first bit sequence is 22, then the first bit sequence can be determined to include 21 valid information bits and 1 reserved bit.

[0160] When the encoding method of the first channel is BCH encoding, the network device can divide the first bit sequence into 3 sub-bit sequences, denoted as sub-bit sequence 1, sub-bit sequence 2, and sub-bit sequence 3, respectively. Sub-bit sequence 1 contains 4 bits, sub-bit sequence 2 contains 7 bits, and sub-bit sequence 3 contains 11 bits.

[0161] Then, BCH encoding is performed on these three sub-bit sequences respectively, resulting in three sub-coded sequences. Referring to the example in Table 1, since sub-bit sequence 1 contains 4 bits (k = 4), the number of bits in sub-coded sequence 1 obtained by BCH encoding sub-bit sequence 1 is 7 - 4 = 3. Similarly, the number of bits in sub-coded sequence 2 obtained by BCH encoding sub-bit sequence 2 is 15 - 7 = 8, and the number of bits in sub-coded sequence 3 obtained by BCH encoding sub-bit sequence 3 is 15 - 11 = 4. The first coded sequence includes sub-coded sequence 1, sub-coded sequence 2, and sub-coded sequence 3, so N = 3 + 8 + 4 = 15.

[0162] In this scenario, R = M + N, therefore the DCI includes a first bit sequence (i.e., 21 valid information bits and 1 reserved bit) and N reserved bits (N = 15). Then, the first bit sequence and the first coded sequence are concatenated to obtain the third bit sequence. After obtaining the third bit sequence, the network device adds a CRC bit to it to obtain the second bit sequence, and then performs second channel coding on the second bit sequence to obtain the second coded sequence.

[0163] Since the number of bits k in the sub-bit sequence has a specific value during BCH encoding, by using a portion of reserved bits as part of the first bit sequence for first channel encoding, the code length of the first channel encoding can be matched better, thus improving the flexibility of the first channel encoding.

[0164] After generating the third bit sequence, the network device adds CRC bits to it to obtain the second bit sequence. Then, the network device performs second-channel coding on the second bit sequence to obtain the second-coded sequence. Specifically, the network device generates the input sequence for the second-channel coding based on the reliability of each bit in the second bit sequence. For example, it can rearrange the bits in the second bit sequence according to their reliability to obtain the input sequence for the second-channel coding. Finally, the second-channel coding is performed on the input sequence to obtain the second-coded sequence.

[0165] The second bit sequence includes the third bit sequence and CRC bits. When R = M + N, the third bit sequence includes the first bit sequence and the first encoding sequence, so the second bit sequence includes the first bit sequence, the first encoding sequence, and CRC bits. When R > M + N, the third bit sequence includes the first bit sequence, the first encoding sequence, and (RMN) first bits, so the second bit sequence includes the first bit sequence, the first encoding sequence, (RMN) first bits, and CRC bits.

[0166] For example, the reliability of the first encoded sequence is greater than the reliability of the first bit sequence.

[0167] The second bit sequence includes a third bit sequence and CRC bits. The third bit sequence includes the first encoded sequence and the first bit sequence. When R>M+N, the third bit sequence also includes (RMN) first bits. Each bit to be encoded in the second bit sequence has its own reliability. With respect to the first encoded sequence and the first bit sequence, the reliability of the first encoded sequence is greater than the reliability of the first bit sequence. This means that the reliability of any bit in the first encoded sequence is greater than the reliability of any bit in the first bit sequence.

[0168] Since the reliability of the first coded sequence is greater than that of the first bit sequence, after the second bit sequence is encoded by the second channel to obtain the second coded sequence, the first coded sequence is more likely to be successfully transmitted during the transmission of the second coded sequence from the network device to the terminal. Even if the first bit sequence has a transmission error during transmission, the first coded sequence can be used to correct the transmission error of the first bit sequence, thereby improving the overall decoding performance.

[0169] For example, if R>M+N, and (RMN) first bits include K valid information bits, the reliability of the K valid information bits is greater than the reliability of the first bit sequence, where K is a positive integer.

[0170] The following example, with reference to the accompanying diagram, illustrates this implementation method.

[0171] Figure 8 is a schematic diagram of a DCI concatenated encoding provided in an embodiment of this application. As shown in Figure 8, the DCI includes 40 bits, including 32 valid information bits and 8 reserved bits.

[0172] When the first channel coding uses BCH coding, please refer to Table 1. The code length n of BCH includes specific values ​​such as 7, 15, 31, and 63, and different code lengths correspond to different values ​​of k. When the code length n of BCH does not match the size of DCI, a portion of the valid information bits can be selected as the first bit sequence, and then the first bit sequence is coded for the first channel.

[0173] As shown in Figure 8, the first bit sequence includes 30 valid information bits. This first bit sequence is then divided into two sub-bit sequences, each containing 4 and 26 bits respectively. These two sub-bit sequences are then BCH encoded, resulting in two sub-coded sequences containing 3 and 5 bits respectively. Therefore, the first encoded sequence contains N = 3 + 5 = 8 bits. The 4-bit sub-bit sequence and the 3-bit sub-coded sequence form a 7-bit codeword, and the 26-bit sub-bit sequence and the 5-bit sub-coded sequence form a 31-bit codeword.

[0174] Then, the first encoded sequence is carried on 8 reserved bits in the DCI to obtain the third bit sequence. The third bit sequence includes the first bit sequence (30 effective information bits), the first encoded sequence (the number of bits in the first encoded sequence is N=8), and (RMN) first bits. Among them, the (RMN) first bits are the 2 effective information bits in Figure 8 that have not undergone the first channel coding. They are part of the third bit sequence and are directly used for the second channel coding.

[0175] Since the network device performs first channel coding on the first bit sequence to obtain the first coded sequence, even if a transmission error occurs in the first bit sequence during transmission, the transmission error of the first bit sequence can be corrected through the first coded sequence. However, the K effective information bits are not subjected to first channel coding. Therefore, placing the K effective information bits in a position with higher reliability than the first bit sequence can increase the probability of successful transmission of the K effective information bits, thereby improving the overall decoding performance.

[0176] In one possible implementation, the first channel coding is BCH coding, the first bit sequence includes P sub-bit sequences, the first coding sequence includes P sub-coding sequences, and the P sub-coding sequences are obtained by performing BCH coding on the P sub-bit sequences respectively, where P is a positive integer greater than 1.

[0177] For example, the reliability of each of the P sub-bit sequences is positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding. That is, the higher the code rate of the sub-bit sequence after the first channel coding, the higher the reliability of the sub-bit sequence; the lower the code rate of the sub-bit sequence after the first channel coding, the lower the reliability of the sub-bit sequence.

[0178] For any sub-bit sequence A and sub-bit sequence B, if the code rate of sub-bit sequence A after the first channel coding is greater than the code rate of sub-bit sequence B after the first channel coding, then the reliability of sub-bit sequence A is greater than the reliability of sub-bit sequence B. This means that the reliability of any bit in sub-bit sequence A is greater than the reliability of any bit in sub-bit sequence B.

[0179] Optionally, the reliability of the sub-coded sequence corresponding to each of the P sub-bit sequences is positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding.

[0180] For example, the first bit sequence is divided into three sub-bit sequences: sub-bit sequence A (4 bits), sub-bit sequence B (7 bits), and sub-bit sequence C (11 bits). These are then BCH encoded to obtain sub-coded sequences A (3 bits), B (8 bits), and C (4 bits). Therefore, the code rate of sub-bit sequence A after first-channel encoding is 4 / (4+3) = 4 / 7, the code rate of sub-bit sequence B after first-channel encoding is 7 / (7+8) = 7 / 15, and the code rate of sub-bit sequence C after first-channel encoding is 11 / (11+4) = 11 / 15.

[0181] Since (11 / 15)>(4 / 7)>(7 / 15), the reliability of sub-bit sequence C is greater than that of sub-bit sequence A, and the reliability of sub-bit sequence A is greater than that of sub-bit sequence B.

[0182] Since (11 / 15)>(4 / 7)>(7 / 15), the reliability of sub-coded sequence C is greater than that of sub-coded sequence A, and the reliability of sub-coded sequence A is greater than that of sub-coded sequence B.

[0183] Since the higher the code rate of the sub-bit sequence after the first channel coding, the worse the decoding performance in the subsequent decoding process, by setting a positive correlation between the reliability of each of the P sub-bit sequences and the code rate of each of the P sub-bit sequences after the first channel coding, the probability of successful transmission of sub-bit sequences with higher code rates can be further improved. By combining the error correction performance of different code rates in the BCH coding process and the reliability ranking of each bit in the input sequence of the second channel coding, the overall decoding performance can be improved.

[0184] For example, the reliability of the BCH code block corresponding to each of the P sub-bit sequences is positively correlated with the code rate after the P sub-bit sequences are encoded using the first channel. For each sub-bit sequence, the corresponding BCH code block includes the sub-bit sequence and the sub-coded sequence obtained by BCH encoding the sub-bit sequence. That is, the higher the code rate after the first channel encoding of the sub-bit sequence, the higher the reliability of the BCH code block corresponding to that sub-bit sequence; the lower the code rate after the first channel encoding of the sub-bit sequence, the lower the reliability of the BCH code block corresponding to that sub-bit sequence.

[0185] For any sub-bit sequence A and sub-bit sequence B, if the code rate of sub-bit sequence A after the first channel coding is greater than the code rate of sub-bit sequence B after the first channel coding, then the reliability of the BCH code block corresponding to sub-bit sequence A is greater than the reliability of the BCH code block corresponding to sub-bit sequence B. This means that the reliability of any bit in the BCH code block corresponding to sub-bit sequence A is greater than the reliability of any bit in the BCH code block corresponding to sub-bit sequence B.

[0186] For example, the first bit sequence is divided into three sub-bit sequences: sub-bit sequence A (4 bits), sub-bit sequence B (7 bits), and sub-bit sequence C (11 bits). These are then BCH encoded to obtain sub-coded sequences A (3 bits), B (8 bits), and C (4 bits). Sub-bit sequence A and sub-coded sequence A constitute BCH block A, sub-bit sequence B and sub-coded sequence B constitute BCH block B, and sub-bit sequence C and sub-coded sequence C constitute BCH block C.

[0187] Therefore, the code rate of sub-bit sequence A after the first channel coding is 4 / (4+3) = 4 / 7, the code rate of sub-bit sequence B after the first channel coding is 7 / (7+8) = 7 / 15, and the code rate of sub-bit sequence C after the first channel coding is 11 / (11+4) = 11 / 15.

[0188] Since (11 / 15)>(4 / 7)>(7 / 15), the reliability of BCH block C is greater than that of BCH block A, and the reliability of BCH block A is greater than that of BCH block B.

[0189] Since the higher the code rate of the sub-bit sequence after the first channel coding, the worse the decoding performance in the subsequent decoding process, by setting the reliability of the BCH code block corresponding to each of the P sub-bit sequences to be positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding, the probability of successful transmission of the code block corresponding to the sub-bit sequence with a higher code rate can be further improved, thereby improving the overall decoding performance.

[0190] Optionally, if there are at least two sub-bit sequences with the same code rate after the first channel coding among the P sub-sequences, then the reliability of each of the at least two sub-bit sequences is negatively correlated with the code length of the BCH code block corresponding to the at least two sub-bit sequences. That is, the larger the code length of the BCH code block corresponding to the sub-bit sequence, the lower the reliability of the sub-bit sequence.

[0191] Optionally, if there are at least two sub-bit sequences with the same code rate after the first channel coding among the P sub-sequences, then the reliability of the BCH code block corresponding to each of the at least two sub-bit sequences is negatively correlated with the code length of the BCH code block corresponding to each of the at least two sub-bit sequences. That is, the larger the code length of the BCH code block corresponding to the sub-bit sequence, the lower the reliability of the BCH code block corresponding to the sub-bit sequence.

[0192] The above embodiments introduced the DCI encoding process. The DCI decoding process will be introduced below with reference to Figure 9.

[0193] Figure 9 is a schematic flowchart of the communication method provided in an embodiment of this application. In the flowchart of Figure 9, the method is shown from the perspective of the terminal, but the embodiments of this application do not limit the subject executing the method. For example, the terminal in Figure 9 can be replaced by a chip, chip system, or processor that supports the terminal in implementing the method, or it can be a logic module or software that can implement all or part of the terminal functions.

[0194] As shown in Figure 9, the method may include S901 and S902. The steps in the method will be described in detail below.

[0195] S901, receives the second encoded sequence.

[0196] The second encoding sequence is obtained by encoding the second bit sequence through the second channel. The second bit sequence is obtained by adding CRC bits to the third bit sequence. The third bit sequence includes the first bit sequence and the first encoding sequence. The first bit sequence is a bit sequence in the DCI and includes at least one valid information bit in the DCI. The first encoding sequence is obtained by encoding the first bit sequence through the first channel and is carried on N reserved bits in the DCI.

[0197] Where R≥M+N, R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first coding sequence, and M, N, and R are all positive integers; when R=M+N, the third bit sequence consists of the first bit sequence and the first coding sequence; and / or, when R>M+N, the third bit sequence includes the first bit sequence, the first coding sequence, and (RMN) first bits, where (RMN) first bits are bits in the DCI other than the first bit sequence and N reserved bits.

[0198] The terminal can obtain the corresponding data by monitoring the PDCCH and demodulate the obtained data to obtain the second encoded sequence.

[0199] The second coded sequence sent by the network device is received by the terminal after transmission through the channel. Due to factors such as channel interference, the second coded sequence sent by the network device and the second coded sequence received by the terminal may be completely identical or not completely identical. After receiving the second coded sequence, the terminal needs to decode the DCI based on the second coded sequence.

[0200] S902, DCI is determined based on the second coding sequence.

[0201] After receiving the second encoded sequence, the terminal needs to decode the second encoded sequence in order to determine the DCI.

[0202] The following describes several implementation methods for determining the DCI based on the second coding sequence.

[0203] Implementation Method 1

[0204] The terminal performs second-channel decoding on the second encoded sequence to obtain a second bit sequence, which includes a third bit sequence and CRC bits. The decoding method of the second channel decoding corresponds to the encoding method of the second channel encoding. For example, if the second channel encoding is polar encoding, then the second channel decoding is polar decoding; if the second channel encoding is TBCC encoding, then the second channel decoding is TBCC decoding.

[0205] After obtaining the second bit sequence, the terminal performs a CRC check on the third bit sequence based on the CRC bits. If the CRC check passes, it means that no transmission error occurred in the process of the third bit sequence being sent from the network device to the terminal. Therefore, the terminal can determine the DCI from the third bit sequence. The number of bits included in the DCI is the same as the number of bits included in the third bit sequence, which is R.

[0206] Since the third bit sequence is obtained by carrying the first encoded sequence on N reserved bits in the DCI, when R = M + N, the third bit sequence is composed of the first bit sequence and the first encoded sequence, and the DCI is composed of the first bit sequence and N reserved bits; when R > M + N, the third bit sequence includes the first bit sequence, the first encoded sequence and (RMN) first bits, and the DCI includes the first bit sequence, N reserved bits and (RMN) first bits.

[0207] In the above implementation method 1, the third bit sequence is checked by CRC bits. If the CRC check passes, it indicates that no transmission error occurred in the process of the third bit sequence being sent from the network device to the terminal. The third bit sequence is obtained by carrying the first encoded sequence on N reserved bits in the DCI. Therefore, the third bit sequence includes all the valid information bits of the DCI. The terminal can obtain the DCI from the third bit sequence without performing the first channel decoding. The decoding complexity is low, and the DCI can be correctly obtained even for terminals that do not support concatenated decoding.

[0208] Implementation Method 2

[0209] The terminal performs second channel decoding on the second encoded sequence to obtain a fourth bit sequence, which includes a fifth bit sequence and CRC bits; wherein, when R = M + N, the fifth bit sequence is composed of a sixth bit sequence and a third encoded sequence; and / or, when R > M + N, the fifth bit sequence includes a sixth bit sequence, a third encoded sequence and (RMN) first bits.

[0210] Due to factors such as channel interference, the fourth bit sequence obtained by the terminal after decoding through the second channel may or may not be completely identical to the second bit sequence used for second channel encoding by the network device. Correspondingly, the fifth bit sequence in the fourth bit sequence may also be different from the third bit sequence on the network device side. That is, when the network device performs second channel encoding, the second bit sequence includes the third bit sequence and CRC bits; however, due to channel interference, the terminal receives the fourth bit sequence, which includes the fifth bit sequence and CRC bits. The fifth bit sequence includes the sixth bit sequence and the third encoded sequence.

[0211] Then, the terminal obtains the third bit sequence based on the sixth bit sequence and the third coding sequence. Specifically, the terminal first performs first-channel decoding on the sixth bit sequence based on the third coding sequence to obtain the first bit sequence. The decoding method of the first channel decoding corresponds to the encoding method of the first channel coding. For example, if the first channel coding is BCH coding, then the first channel decoding is BCH decoding; if the first channel coding is linear block coding, then the first channel decoding is linear block decoding.

[0212] Then, the terminal performs first channel coding on the first bit sequence to obtain a first coded sequence. The encoding method used by the terminal to perform first channel coding on the first bit sequence is the same as the encoding method used by the network device to perform first channel coding on the first bit sequence, and the encoding parameters used by the terminal to perform first channel coding on the first bit sequence are the same as the encoding parameters used by the network device to perform first channel coding on the first bit sequence.

[0213] After obtaining the first bit sequence and the first encoded sequence, the terminal can acquire the third bit sequence. Specifically, when R = M + N, the third bit sequence consists of the first bit sequence and the first encoded sequence; and / or, when R > M + N, the third bit sequence includes the first bit sequence, the first encoded sequence, and (RMN) first bits. In other words, the first bit sequence in the third bit sequence is obtained by decoding the sixth bit sequence using the third encoded sequence using the first channel, and the first encoded sequence in the third bit sequence is obtained by encoding the first bit sequence using the first channel.

[0214] Then, the terminal performs a CRC check on the third bit sequence based on the CRC bits. If the CRC check passes, the terminal determines the DCI from the third bit sequence. Specifically, when R = M + N, the DCI consists of the first bit sequence and N reserved bits; and / or, when R > M + N, the DCI includes the first bit sequence, N reserved bits, and (RMN) first bits. If the CRC check fails, the terminal fails to decode the DCI.

[0215] In implementation method 2 above, the first channel decoding of the sixth bit sequence using the third encoding sequence can, to some extent, correct transmission errors that occur during the transmission of the first bit sequence, thereby increasing the probability of successfully decoding the DCI. Then, by performing the first channel encoding on the obtained first bit sequence, a first encoding sequence is obtained. Based on the first bit sequence and the first encoding sequence, a third bit sequence is obtained. Finally, a CRC check is performed on the third bit sequence using CRC bits, thereby determining whether the above concatenated decoding process successfully recovered the correct third bit sequence. If the correct third bit sequence is recovered, the DCI can be determined from the third bit sequence.

[0216] Implementation method 3

[0217] The terminal performs second-channel decoding on the second encoded sequence to obtain a fourth bit sequence, which includes a fifth bit sequence and CRC bits. Then, the terminal performs a CRC check on the fifth bit sequence based on the CRC bits. If the CRC check fails, it indicates that a transmission error occurred in the third bit sequence during its transmission from the network device to the terminal. In this case, the terminal executes the process described in implementation method 2 above to obtain the DCI.

[0218] The methods provided in the embodiments of this application have been described in detail above with reference to several accompanying drawings. The apparatus provided in the embodiments of this application will now be described with reference to the accompanying drawings.

[0219] Figures 10 to 13 are schematic block diagrams of possible devices provided in embodiments of this application. One communication device provided in this application is shown in Figure 10. The communication device 1000 includes a transceiver unit 1010 and a processing unit 1020.

[0220] One possible design is that the communication device 1000 is used to implement the functions of the network device in the method embodiment shown in FIG4 above. For example, the communication device 1000 may correspond to the network device in FIG4.

[0221] For example, processing unit 1020 performs first channel coding on the first bit sequence in the DCI to obtain a first coded sequence, which is carried on N reserved bits in the DCI; wherein the first bit sequence includes at least one valid information bit in the DCI, R≥M+N, R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first coded sequence, and M, N, and R are all positive integers; and performs second channel coding on the second bit sequence to obtain a second coded sequence, which is obtained by adding cyclic redundancy check (CRC) bits to the third bit sequence; wherein, when R=M+N, the third bit sequence is composed of the first bit sequence and the first coded sequence; and / or, when R>M+N, the third bit sequence includes the first bit sequence, the first coded sequence, and (RMN) first bits, where (RMN) first bits are bits in the DCI other than the first bit sequence and the N reserved bits. Transceiver unit 1010 is used to transmit the second coded sequence.

[0222] In one possible implementation, the first bit sequence is one of the following:

[0223] Partial effective information bits in DCI;

[0224] All valid information bits in the DCI;

[0225] All valid information bits in the DCI and some reserved bits in the DCI.

[0226] In one possible implementation, the first channel coding is performed using BCH coding, and M = kQ, where:

[0227] The first bit sequence includes Q sub-bit sequences, each of which contains k bits;

[0228] The first encoding sequence includes Q sub-encoding sequences, which are obtained by performing BCH encoding on Q sub-bit sequences respectively. Each sub-encoding sequence includes N / Q bits, where k and Q are both positive integers.

[0229] In one possible implementation, M is 22, k is 11, and Q is 2.

[0230] In one possible implementation, the first channel coding uses BCH coding, where M is 22, where:

[0231] The first bit sequence consists of three sub-bit sequences, with the number of bits in each sub-bit sequence being 4, 7, and 11, respectively.

[0232] In one possible implementation, the second coded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding, where the input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein:

[0233] The reliability of the first encoded sequence is greater than that of the first bit sequence.

[0234] In one possible implementation, the second coded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding, where the input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein:

[0235] When R>M+N, and (RMN) first bits include K valid information bits, the reliability of the K valid information bits is greater than the reliability of the first bit sequence, where K is a positive integer.

[0236] In one possible implementation, the second coding sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding, and the input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence; the first channel coding uses BCH coding, the first bit sequence includes P sub-bit sequences, and the first coding sequence includes P sub-coding sequences, which are obtained by performing BCH coding on each of the P sub-bit sequences, where P is a positive integer greater than 1.

[0237] The reliability of each of the P sub-bit sequences is positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding.

[0238] or,

[0239] The reliability of the BCH code block corresponding to each of the P sub-bit sequences is positively correlated with the code rate after the P sub-bit sequences are first channel encoded. For each sub-bit sequence, the BCH code block corresponding to the sub-bit sequence includes the sub-bit sequence and the sub-coded sequence obtained by BCH encoding the sub-bit sequence.

[0240] The communication device provided in this application is shown in FIG11. The communication device 1100 includes a transceiver unit 1110 and a processing unit 1120.

[0241] One possible design is that the communication device 1100 is used to implement the functions of the terminal in the method embodiment shown in FIG9 above. For example, the communication device 1100 may correspond to the terminal in FIG9.

[0242] For example, the transceiver unit 1110 is used to receive the second encoded sequence. The processing unit 1120 is used to determine the DCI based on the second encoded sequence.

[0243] The second encoded sequence is obtained by encoding the second bit sequence through the second channel. The second bit sequence is obtained by adding CRC bits to the third bit sequence. The third bit sequence includes the first bit sequence and the first encoded sequence. The first bit sequence is a bit sequence in the DCI and includes at least one valid information bit in the DCI. The first encoded sequence is obtained by encoding the first bit sequence through the first channel and is carried on N reserved bits in the DCI. Wherein, R≥M+N, R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first encoded sequence, and M, N, and R are all positive integers.

[0244] In the case of R = M + N, the third bit sequence consists of the first bit sequence and the first coding sequence; and / or, in the case of R > M + N, the third bit sequence includes the first bit sequence, the first coding sequence and (RMN) first bits, where (RMN) first bits are bits in the DCI other than the first bit sequence and N reserved bits.

[0245] In one possible implementation, the first bit sequence is one of the following:

[0246] Partial effective information bits in DCI;

[0247] All valid information bits in the DCI;

[0248] All valid information bits in the DCI and some reserved bits in the DCI.

[0249] In one possible implementation, the first channel coding is performed using BCH coding, and M = kQ, where:

[0250] The first bit sequence includes Q sub-bit sequences, each of which contains k bits;

[0251] The first encoding sequence includes Q sub-encoding sequences, which are obtained by performing BCH encoding on Q sub-bit sequences respectively. Each sub-encoding sequence includes N / Q bits, where k and Q are both positive integers.

[0252] In one possible implementation, M is 22, k is 11, and Q is 2.

[0253] In one possible implementation, the first channel coding uses BCH coding, where M is 22, where:

[0254] The first bit sequence consists of three sub-bit sequences, with the number of bits in each sub-bit sequence being 4, 7, and 11, respectively.

[0255] In one possible implementation, the second coded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding, where the input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein:

[0256] The reliability of the first encoded sequence is greater than that of the first bit sequence.

[0257] In one possible implementation, the second coded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding, where the input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein:

[0258] When R>M+N, and (RMN) first bits include K valid information bits, the reliability of the K valid information bits is greater than the reliability of the first bit sequence, where K is a positive integer.

[0259] In one possible implementation, the second coding sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding, and the input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence; the first channel coding uses BCH coding, the first bit sequence includes P sub-bit sequences, and the first coding sequence includes P sub-coding sequences, which are obtained by performing BCH coding on each of the P sub-bit sequences, where P is a positive integer greater than 1.

[0260] The reliability of each of the P sub-bit sequences is positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding.

[0261] or,

[0262] The reliability of the BCH code block corresponding to each of the P sub-bit sequences is positively correlated with the code rate after the P sub-bit sequences are first channel encoded. For each sub-bit sequence, the BCH code block corresponding to the sub-bit sequence includes the sub-bit sequence and the sub-coded sequence obtained by BCH encoding the sub-bit sequence.

[0263] In one possible implementation, the processing unit 1120 is specifically used for:

[0264] The second encoded sequence is decoded using a second channel to obtain a second bit sequence, which includes a third bit sequence and the CRC bits.

[0265] Perform CRC check on the third bit sequence based on the CRC bits;

[0266] If the CRC check passes, the DCI is determined from the third bit sequence.

[0267] In one possible implementation, the processing unit 1120 is specifically used for:

[0268] The second encoded sequence is decoded by the second channel to obtain the fourth bit sequence, which includes the fifth bit sequence and CRC bits; wherein, when R = M + N, the fifth bit sequence is composed of the sixth bit sequence and the third encoded sequence; and / or, when R > M + N, the fifth bit sequence includes the sixth bit sequence, the third encoded sequence and (RMN) first bits;

[0269] Based on the sixth bit sequence and the third coding sequence, the third bit sequence is obtained. The first bit sequence in the third bit sequence is obtained by first channel decoding of the sixth bit sequence based on the third coding sequence. The first coding sequence in the third bit sequence is obtained by first channel coding of the first bit sequence.

[0270] Perform CRC check on the third bit sequence based on the CRC bits;

[0271] If the CRC check passes, the DCI is determined from the third bit sequence.

[0272] In one possible implementation, before obtaining the third bit sequence based on the sixth bit sequence and the third encoded sequence, the processing unit 1120 is further configured to:

[0273] The CRC check of the fifth bit sequence based on the CRC bits failed.

[0274] It is understood that the division of units in the above-described device is merely a logical functional division. Each function can correspond to a functional unit, or two or more functions can be integrated into one functional unit. In actual implementation, all or some units can be integrated into a single physical entity, or they can be distributed across different physical entities. Furthermore, the aforementioned functional units can be implemented in hardware, software, or a combination of both. Whether a function is executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0275] Figure 12 is another schematic block diagram of the communication device provided in an embodiment of this application. As shown in Figure 12, the communication device 1200 includes one or more processors 1210. The processor 1210 can be a general-purpose processor or a dedicated processor, etc. For example, it can be a baseband processor or a central processing unit. The baseband processor can be used to process communication protocols and communication data, and the central processing unit can be used to control the device (e.g., a vehicle or a chip), execute software programs, and process data from the software programs.

[0276] Alternatively, in one design, processor 1210 may include a computer program (also referred to as code or instructions) that can be executed on processor 1210 to cause communication device 1200 to perform the methods performed by the terminal or network device in the above method embodiments. In yet another possible design, communication device 1200 includes circuitry (not shown in FIG12) for implementing the functions of the terminal or network device in the above method embodiments.

[0277] For example, processor 1210 can be used to execute a computer program in memory to implement the steps performed by a terminal or network device in the method embodiment shown in FIG4 or FIG9.

[0278] Optionally, the communication device 1200 may include one or more memories 1220 storing computer programs (sometimes referred to as code or instructions) that can be run on the processor 1210, causing the communication device 1200 to perform the methods performed by the terminal or network device in the above embodiments.

[0279] Optionally, the processor 1210 and / or memory 1220 may also store data. The processor and memory may be configured separately or integrated together.

[0280] Optionally, the device 1200 may also include a communication interface 1230. The processor 1210, sometimes referred to as a processing unit, controls the device (e.g., a terminal or network device). The communication interface 1230, sometimes referred to as a transceiver unit, transceiver, transceiver circuit, or transceiver, is used to implement the transceiver functions of the device; for example, the communication interface 1230 can be used to receive first configuration information.

[0281] Optionally, the communication device 1200 also includes a communication interface 1230. The processor 1210 and the communication interface 1230 are coupled to each other. It is understood that the communication interface 1230 can be a transceiver or an input / output interface.

[0282] When the communication device 1200 is used to implement the method shown in FIG4 or FIG9, the processor 1210 can be used to execute the functions of the processing unit 1020 or processing unit 1120, and the communication interface 1230 can be used to execute the functions of the transceiver unit 1010 or transceiver unit 1110. Whether the communication interface 1230 is used for sending or receiving depends on whether the communication device 1200 is used to perform a sending or receiving action in the scheme it is executing.

[0283] When the communication device 1200 is a chip applied to a terminal, the chip implements the functions of the terminal in the above method embodiments. The terminal chip receives signals from other modules (such as radio frequency modules or antennas) in the terminal, and these signals may be sent to the terminal by network devices; or, the terminal chip sends signals to other modules (such as radio frequency modules or antennas) in the terminal, and these signals may be sent to network devices by the terminal.

[0284] When the communication device 1200 is a chip used in a network device, the chip implements the functions of the network device in the above method embodiments. The chip of the network device receives signals from other modules in the network device, which may be signals sent by the terminal to the network device; or, the chip of the network device sends signals to other modules in the network device, which may be signals sent by the network device to the terminal.

[0285] It is understood that when the communication device 1200 is a terminal or network device, the communication interface 1230 can be a transceiver, specifically including a transmitter and a receiver, with the transmitter used to send signals and the receiver used to receive signals. When the communication device 1200 is a chip applied to a terminal or network device, the communication interface 1230 can be an input / output circuit, wherein the input circuit can be used for receiving and the output interface can be used for sending.

[0286] Optionally, the communication device 1200 also includes a power supply circuit for supplying power to the communication device 1200.

[0287] Figure 13 is a schematic diagram of the terminal device provided in an embodiment of this application. As shown in Figure 13, the terminal device 1300 can be applied to the system shown in Figure 1 to perform the functions of the terminal in the method embodiment shown in Figure 4 or Figure 9. As shown, the terminal device 1300 includes a processor 1301 and a transceiver 1302. Optionally, the terminal device 1300 also includes a memory 1303. The processor 1301, transceiver 1302, and memory 1303 can communicate with each other through an internal connection path to transmit control and / or data signals. The memory 1303 is used to store computer programs, and the processor 1301 is used to call and run the computer programs from the memory 1303 to control the transceiver 1302 to transmit and receive signals. Optionally, the terminal device 1300 may also include an antenna 1304 for transmitting uplink data or uplink control signaling output by the transceiver 1302 via wireless signals.

[0288] The processor 1301 and memory 1303 can be combined into a single processing device. The processor 1301 executes the program code stored in the memory 1303 to achieve the aforementioned functions. In specific implementations, the memory 1303 can be integrated into the processor 1301 or independent of the processor 1301. The processor 1301 can correspond to the processing unit in Figures 10-11 or the processor in Figure 12.

[0289] The transceiver 1302 described above may correspond to the transceiver unit in Figures 10-11 or the communication interface in Figure 12. The transceiver 1302 may include a receiver (or receiver circuit) and a transmitter (or transmitter circuit). The receiver is used to receive signals, and the transmitter is used to transmit signals.

[0290] It should be understood that the terminal device 1300 shown in Figure 13 can implement the various processes involving the terminal or network device in the method embodiments shown in Figure 4 or Figure 9. The operation and / or function of each module in the terminal device 1300 are respectively for implementing the corresponding processes in the above method embodiments. For details, please refer to the description in the above method embodiments; to avoid repetition, detailed descriptions are appropriately omitted here.

[0291] The processor 1301 described above can be used to execute the actions implemented internally by the terminal or network device as described in the preceding method embodiments, while the transceiver 1302 can be used to execute the actions described in the preceding method embodiments whereby the network device sends data to the terminal or the terminal receives data from the network device. Please refer to the descriptions in the preceding method embodiments for details, which will not be repeated here.

[0292] Optionally, the terminal device 1300 may also include a power supply 1305 for providing power to various devices or circuits in the terminal.

[0293] In addition, to make the terminal more functional, the terminal device 1300 may also include one or more of the following: an input unit 1306, a display unit 1307, an audio circuit 1308, a camera 1309, and a sensor 1310. The audio circuit may also include a speaker 1308a, a microphone 1308b, etc.

[0294] It should be noted that the above method embodiments can be applied to a processor, or implemented by a processor. A processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by software instructions.

[0295] The aforementioned processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0296] The steps of the method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in mature storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0297] The memory in this application embodiment can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0298] This application also provides a chip system including at least one processor for supporting the implementation of the functions of the terminal or network device involved in any of the above method embodiments, such as sending, receiving, or processing information involved in the above methods.

[0299] In one possible design, the chip system also includes a memory for storing computer program instructions and data, which may be located inside or outside the processor.

[0300] The chip system can consist of chips or include chips and other discrete components.

[0301] This application also provides a computer program product, which includes: a computer program (also referred to as code or instructions), wherein when the computer program is run, the method executed by the terminal in the embodiment shown in FIG4 or FIG9 is executed, or the method executed by the network device is executed.

[0302] This application also provides a computer-readable storage medium storing a computer program (also referred to as code or instructions). When the computer program is run, the method executed by the terminal in the embodiment shown in FIG4 or FIG9 is executed, or the method executed by the network device is executed.

[0303] This application also provides a communication system, which includes the aforementioned terminal and network equipment.

[0304] The methods provided in the above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a computer program product. This computer program product may include one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic disk), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0305] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0306] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0307] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0308] The unit described as a separate component may or may not be physically separate. The component shown as a unit may or may not be a physical unit; that is, it may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0309] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0310] If this function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or part of it, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

Claims

1. A communication method, characterized in that, The method includes: The first bit sequence in the downlink control information (DCI) is subjected to first channel coding to obtain a first coding sequence, which is carried on N reserved bits in the DCI; wherein, the first bit sequence includes at least one valid information bit in the DCI, R≥M+N, R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first coding sequence, and M, N, and R are all positive integers; The second bit sequence is subjected to second channel coding to obtain a second coded sequence, which is obtained by adding cyclic redundancy check (CRC) bits to the third bit sequence; wherein, when R = M + N, the third bit sequence is composed of the first bit sequence and the first coded sequence; and / or, when R > M + N, the third bit sequence includes the first bit sequence, the first coded sequence, and (RMN) first bits, wherein the (RMN) first bits are bits in the DCI other than the first bit sequence and the N reserved bits; Send the second encoded sequence.

2. A communication method, characterized in that, The method includes: Receive a second encoded sequence; wherein the second encoded sequence is obtained by encoding a second bit sequence through a second channel, and the second bit sequence is obtained by adding CRC bits to a third bit sequence; the third bit sequence includes a first bit sequence and a first encoded sequence, the first bit sequence is a bit sequence in the DCI and includes at least one valid information bit in the DCI, the first encoded sequence is obtained by encoding the first bit sequence through a first channel, and the first encoded sequence is carried on N reserved bits in the DCI; wherein R≥M+N, R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first encoded sequence, and M, N, and R are all positive integers; Wherein, when R = M + N, the third bit sequence is composed of the first bit sequence and the first encoding sequence; and / or, when R > M + N, the third bit sequence includes the first bit sequence, the first encoding sequence and (RMN) first bits, wherein the (RMN) first bits are bits in the DCI other than the first bit sequence and the N reserved bits; The DCI is determined based on the second encoded sequence.

3. The method according to claim 2, characterized in that, Determining the DCI based on the second encoded sequence includes: The second encoded sequence is decoded using a second channel to obtain a second bit sequence, which includes the third bit sequence and the CRC bits. Perform CRC verification on the third bit sequence based on the CRC bits; If the CRC check passes, the DCI is determined from the third bit sequence.

4. The method according to claim 2, characterized in that, Determining the DCI based on the second encoded sequence includes: The second encoded sequence is decoded using a second channel to obtain a fourth bit sequence, which includes a fifth bit sequence and the CRC bits; wherein, when R = M + N, the fifth bit sequence is composed of a sixth bit sequence and a third encoded sequence; and / or, when R > M + N, the fifth bit sequence includes the sixth bit sequence, the third encoded sequence, and the (RMN) first bits; The third bit sequence is obtained based on the sixth bit sequence and the third coding sequence, wherein the first bit sequence in the third bit sequence is obtained by first channel decoding of the sixth bit sequence based on the third coding sequence, and the first coding sequence in the third bit sequence is obtained by first channel coding of the first bit sequence; Perform CRC verification on the third bit sequence based on the CRC bits; If the CRC check passes, the DCI is determined from the third bit sequence.

5. The method according to claim 4, characterized in that, Before obtaining the third bit sequence based on the sixth bit sequence and the third encoded sequence, the method further includes: A CRC check is performed on the fifth bit sequence based on the CRC bits, and the CRC check fails.

6. The method according to any one of claims 1-5, characterized in that, The first bit sequence is one of the following: The effective information bits in the DCI; All valid information bits in the DCI; All valid information bits in the DCI and some reserved bits in the DCI.

7. The method according to any one of claims 1-6, characterized in that, The first channel coding scheme is BCH coding, and M = kQ, where: The first bit sequence includes Q sub-bit sequences, each of which contains k bits; The first encoding sequence includes the Q sub-encoding sequences, which are obtained by performing BCH encoding on the Q sub-bit sequences respectively. Each sub-encoding sequence includes N / Q bits, where k and Q are both positive integers.

8. The method according to claim 7, characterized in that, The value of M is 22, the value of k is 11, and the value of Q is 2.

9. The method according to any one of claims 1-6, characterized in that, The first channel coding uses BCH coding, where M is 22, and: The first bit sequence includes three sub-bit sequences, which contain 4, 7, and 11 bits respectively.

10. The method according to any one of claims 1-9, characterized in that, The second encoded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding. The input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein: The reliability of the first encoded sequence is greater than the reliability of the first bit sequence.

11. The method according to any one of claims 1-10, characterized in that, The second encoded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding. The input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein: When R>M+N, and the (RMN) first bits include K valid information bits, the reliability of the K valid information bits is greater than the reliability of the first bit sequence, where K is a positive integer.

12. The method according to any one of claims 1-10, characterized in that, The second encoding sequence is obtained by performing second channel encoding on the input sequence of the second channel encoding. The input sequence of the second channel encoding is generated based on the reliability of each bit in the second bit sequence. The encoding method of the first channel encoding is BCH encoding. The first bit sequence includes P sub-bit sequences, and the first encoding sequence includes P sub-encoding sequences. The P sub-encoding sequences are obtained by performing BCH encoding on each of the P sub-bit sequences, where P is a positive integer greater than 1. The reliability of each of the P sub-bit sequences is positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding. or, The reliability of the BCH code block corresponding to each of the P sub-bit sequences is positively correlated with the code rate after the P sub-bit sequences are encoded by the first channel. For each sub-bit sequence, the BCH code block corresponding to the sub-bit sequence includes the sub-bit sequence and the sub-coded sequence obtained by BCH encoding the sub-bit sequence.

13. A communication device, characterized in that, include: A processing unit is configured to perform first channel coding on a first bit sequence in the DCI to obtain a first coding sequence, wherein the first coding sequence is carried on N reserved bits in the DCI; wherein the first bit sequence includes at least one valid information bit in the DCI, R≥M+N, R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first coding sequence, and M, N, and R are all positive integers. The processing unit is further configured to perform second channel coding on the second bit sequence to obtain a second coded sequence, wherein the second bit sequence is obtained by adding cyclic redundancy check (CRC) bits to the third bit sequence; wherein, when R = M + N, the third bit sequence is composed of the first bit sequence and the first coded sequence; and / or, when R > M + N, the third bit sequence includes the first bit sequence, the first coded sequence, and (RMN) first bits, wherein the (RMN) first bits are bits in the DCI other than the first bit sequence and the N reserved bits; A transceiver unit is used to transmit the second encoded sequence.

14. A communication device, characterized in that, include: A transceiver unit is used to receive a second encoded sequence; wherein the second encoded sequence is obtained by encoding a second bit sequence through a second channel, and the second bit sequence is obtained by adding CRC bits to a third bit sequence; the third bit sequence includes a first bit sequence and a first encoded sequence, the first bit sequence is a bit sequence in a DCI and includes at least one valid information bit in the DCI, the first encoded sequence is obtained by encoding the first bit sequence through a first channel, and the first encoded sequence is carried on N reserved bits in the DCI; wherein R≥M+N, R is the number of bits included in the DCI, M is the number of bits included in the first bit sequence, N is the number of bits included in the first encoded sequence, and M, N, and R are all positive integers; Wherein, when R = M + N, the third bit sequence is composed of the first bit sequence and the first encoding sequence; and / or, when R > M + N, the third bit sequence includes the first bit sequence, the first encoding sequence and (RMN) first bits, wherein the (RMN) first bits are bits in the DCI other than the first bit sequence and the N reserved bits; A processing unit is configured to determine the DCI based on the second encoded sequence.

15. The apparatus according to claim 14, characterized in that, The processing unit is specifically used for: The second encoded sequence is decoded using a second channel to obtain a second bit sequence, which includes the third bit sequence and the CRC bits. Perform CRC verification on the third bit sequence based on the CRC bits; If the CRC check passes, the DCI is determined from the third bit sequence.

16. The apparatus according to claim 14, characterized in that, The processing unit is specifically used for: The second encoded sequence is decoded using a second channel to obtain a fourth bit sequence, which includes a fifth bit sequence and the CRC bits; wherein, when R = M + N, the fifth bit sequence is composed of a sixth bit sequence and a third encoded sequence; and / or, when R > M + N, the fifth bit sequence includes the sixth bit sequence, the third encoded sequence, and the (RMN) first bits; The third bit sequence is obtained based on the sixth bit sequence and the third coding sequence, wherein the first bit sequence in the third bit sequence is obtained by first channel decoding of the sixth bit sequence based on the third coding sequence, and the first coding sequence in the third bit sequence is obtained by first channel coding of the first bit sequence; Perform CRC verification on the third bit sequence based on the CRC bits; If the CRC check passes, the DCI is determined from the third bit sequence.

17. The apparatus according to claim 16, characterized in that, Before obtaining the third bit sequence based on the sixth bit sequence and the third encoded sequence, the processing unit is further configured to: A CRC check is performed on the fifth bit sequence based on the CRC bits, and the CRC check fails.

18. The apparatus according to any one of claims 13-17, characterized in that, The first bit sequence is one of the following: The effective information bits in the DCI; All valid information bits in the DCI; All valid information bits in the DCI and some reserved bits in the DCI.

19. The apparatus according to any one of claims 13-18, characterized in that, The first channel coding scheme is BCH coding, and M = kQ, where: The first bit sequence includes Q sub-bit sequences, each of which contains k bits; The first encoding sequence includes the Q sub-encoding sequences, which are obtained by performing BCH encoding on the Q sub-bit sequences respectively. Each sub-encoding sequence includes N / Q bits, where k and Q are both positive integers.

20. The apparatus according to claim 19, characterized in that, The value of M is 22, the value of k is 11, and the value of Q is 2.

21. The apparatus according to any one of claims 13-18, characterized in that, The first channel coding uses BCH coding, where M is 22, and: The first bit sequence includes three sub-bit sequences, which contain 4, 7, and 11 bits respectively.

22. The apparatus according to any one of claims 13-21, characterized in that, The second encoded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding. The input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein: The reliability of the first encoded sequence is greater than the reliability of the first bit sequence.

23. The apparatus according to any one of claims 13-22, characterized in that, The second encoded sequence is obtained by performing second-channel coding on the input sequence of the second-channel coding. The input sequence of the second-channel coding is generated based on the reliability of each bit in the second bit sequence, wherein: When R>M+N, and the (RMN) first bits include K valid information bits, the reliability of the K valid information bits is greater than the reliability of the first bit sequence, where K is a positive integer.

24. The apparatus according to any one of claims 13-22, characterized in that, The second encoding sequence is obtained by performing second channel encoding on the input sequence of the second channel encoding. The input sequence of the second channel encoding is generated based on the reliability of each bit in the second bit sequence. The encoding method of the first channel encoding is BCH encoding. The first bit sequence includes P sub-bit sequences, and the first encoding sequence includes P sub-encoding sequences. The P sub-encoding sequences are obtained by performing BCH encoding on each of the P sub-bit sequences, where P is a positive integer greater than 1. The reliability of each of the P sub-bit sequences is positively correlated with the code rate of each of the P sub-bit sequences after the first channel coding. or, The reliability of the BCH code block corresponding to each of the P sub-bit sequences is positively correlated with the code rate after the P sub-bit sequences are encoded by the first channel. For each sub-bit sequence, the BCH code block corresponding to the sub-bit sequence includes the sub-bit sequence and the sub-coded sequence obtained by BCH encoding the sub-bit sequence.

25. A communication device, characterized in that, It includes one or more processors, said one or more processors being configured to execute computer programs or instructions in memory, causing said communication device to perform the method as described in any one of claims 1 to 12.

26. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it causes the method as described in any one of claims 1 to 12 to be performed.

27. A computer program product, characterized in that, Includes a computer program, which, when run, causes the method as described in any one of claims 1 to 12 to be performed.

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