Method for testing single event effects in sip device

Abstract

A method for testing single event effects in a SiP device. The method comprises: on the basis of depth information of a sensitive area of a SiP device, decapping or thinning the SiP device; on the basis of the structures and models of embedded chips of the SiP device, determining a sensitive module of each embedded chip therein, and performing irradiation test analysis on each sensitive module, so as to obtain single event effects test items for the SiP device; determining a test plan, and performing a targeted design on test software and hardware; injecting an error mode into the designed software and hardware to perform simulation verification, and if the simulation verification fails, modifying test procedures, and re-performing the simulation verification; performing a single-event test on each embedded chip; performing an irradiation test on the SiP device; and after the test is completed, uploading, saving and analyzing test data, and ending the test. The present method solves the problems of a ground test of SiP single event effects being inaccurate, and the test method and a test apparatus being limited to specific models.

Description

A method for testing single-event effects in SiP devices

[0001] This application claims priority to Chinese Patent Application No. 2024115218192, filed on October 29, 2024, entitled "A General Method for Single-Event Effect Testing of SiP Devices", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to a method for testing single-event effects in SiP devices, belonging to the field of single-event testing technology. Background Technology

[0003] Since the beginning of the 21st century, with the rapid development of aerospace technology, higher demands have been placed on the integration and miniaturization of spaceborne computer electronic systems. From a system integration perspective, System-in-Package (SiP) is an effective method to promote the miniaturization, high performance, low power consumption, and high reliability of electronic systems. It uses three-dimensional stacked packaging technology to encapsulate multiple bare chips of electronic components with different functions into a microsystem, mainly including Field-Programmable Gate Arrays (FPGAs), memory, Analog-to-Digital Converters (ADCs), and Digital Signal Processors (DSPs). Due to its characteristics of miniaturization, high performance, low power consumption, low cost, short development cycle, and rapid iteration, it has become the primary choice for spaceborne computers.

[0004] In space, due to space radiation, when a single high-energy particle enters a SiP device, it generates a large number of electron-hole pairs near the particle's track. These electron-hole pairs are collected by the sensitive modules within the SiP, leading to device malfunction or failure, i.e., the single-event effect (SEE). Therefore, aerospace-grade SiPs require ground-based radiation hardening testing and evaluation.

[0005] Currently, in the field of single-event effect testing for SiP devices, there is no universal method for testing single-event effects in SiP devices due to the different chips packaged in different models of SiP devices. Summary of the Invention

[0006] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a single-event effect testing method for SiP devices, which solves the problems of inaccurate ground-based single-event effect testing of SiP devices and the limitation of testing methods and testing devices to specific models.

[0007] The technical solution of this invention is:

[0008] Firstly, a method for testing single-event effects in SiP devices is provided, including:

[0009] S1. Based on the depth information of the sensitive area of ​​the SiP device, the SiP device is subjected to capping or thinning treatment.

[0010] S2. Analyze each embedded chip of the SiP device to obtain the single-event effect test items of the SiP device;

[0011] S3. The test system for the single-event effect test of SiP devices includes hardware and software components. The hardware component includes the DUT test board and control board, and the software component includes the host computer software unit and the slave computer software unit.

[0012] S4. Simulate and verify the injection of errors into the hardware and software components. If the simulation verification fails, modify the test system and repeat the simulation verification. If the simulation verification passes, proceed to S5.

[0013] S5. Perform single-event experiments on each embedded chip of the SiP device. The DUT test board is connected to both the embedded chip of the SiP device and the control board, serving as the interface between the SiP device and the control board. The control board connects to the embedded chip of the SiP device and sends control commands to it, configures and reads the configuration code stream of the embedded chip of the SiP device, and analyzes and records the single-event flip information accordingly. The lower-level software unit connects to the control board to power it on, and monitors and records the operating current data of the SiP device. The control board and the lower-level software unit send the recorded data to the upper-level software unit for display and storage.

[0014] S6. Conduct an overall irradiation test on the SiP device.

[0015] Preferably, the embedded chips in the SiP device include: a field-programmable gate array (FPGA) chip, a PROM chip, and an analog-to-digital converter (ADC) chip.

[0016] Preferably, the DUT test board meets the requirements for self-starting power-on operation of SiP devices during testing, BPI and JTAG program configuration functions, and also provides a SelectMAP interface for communication between SiP devices and the control board. Specifically:

[0017] When designing the power-on circuit, two LTM4644 chips were selected as DC-DC power chips to output 8 voltage and current channels;

[0018] The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, which meets the self-starting test requirement during single-chip testing.

[0019] The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board, are brought out. The SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time, meeting the requirements of dual-chip testing.

[0020] Preferably, the control board is equipped with a main control FPGA chip, which enables remote control of the DUT test board and data communication with the host computer. Specifically:

[0021] The control board should bring out at least two general-purpose banks of the main control FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board;

[0022] The main control FPGA chip of the control board needs to be connected to an external storage chip to store the power-on configuration program and test data of the DUT test board;

[0023] When the control board interacts with the host computer, a serial port channel needs to be reserved.

[0024] Preferably, the host computer software unit is a remote control terminal developed based on LabVIEW, which receives, displays, and saves the recorded data from the control board and the slave computer software unit. Specifically:

[0025] Real-time display of single-event upset and single-event failure information of the device under test;

[0026] The curves of the working current of each SiP circuit changing with time under irradiation are monitored in real time to determine whether single-event lock-up occurs, and then all test results are saved in txt format.

[0027] Preferably, the lower-level software unit includes single-event test programs for the FPGA module, PROM module, and ADC module, which are used to power on the main control FPGA chip of the control board, monitor and record the operating current of the FPGA chip, PROM chip, and ADC chip, and send the recorded results to the upper-level software unit when performing single-event tests on the FPGA chip, PROM chip, and ADC chip, respectively.

[0028] Preferably, when performing single-event testing on the FPGA chip of a SiP device:

[0029] The power supply parameters of the main FPGA chip on the control board are set by the FPGA module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the FPGA chip of the SiP device is powered on by the DUT test board.

[0030] The control board sends control commands to the FPGA chip of the SiP device, loads the configuration code stream onto the FPGA chip of the SiP device, and then turns on the beam to conduct the irradiation test. The FPGA module in the lower-level software unit monitors the operating current of the FPGA chip of the SiP device in real time. When the operating current exceeds 1.5 times its operating current during irradiation, it is determined that a single-event lock has occurred. At this time, the FPGA chip of the SiP device is powered off and restarted, and the error information is recorded.

[0031] The control board reads the program configuration code stream of the FPGA chip of the SiP device in real time through the SelectMAP interface and compares it with the initially written configuration code stream. If they are inconsistent, it determines that a single event flip has occurred and records the number of single event flips and the frame address.

[0032] Finally, all test results were uploaded to the host computer software unit.

[0033] Preferably, when performing single-event testing on the PROM chip or ADC chip of a SiP device:

[0034] The power supply parameters of the main FPGA chip on the control board are set by the PROM module or ADC module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the PROM chip or ADC chip of the SiP device is powered on by the DUT test board.

[0035] The main control FPGA chip on the control board writes the configuration code stream into the ADC chip or PROM chip of the SiP device to put it into normal working state and start the irradiation test; during the irradiation process, the PROM module or ADC module in the lower computer software unit monitors the working current of the PROM chip or ADC chip in real time to determine whether single-event lock occurs.

[0036] During the irradiation process, the control board reads the configuration code stream of the ADC chip or PROM chip and compares it with the initial configuration code stream to obtain the single-event flip results of the PROM chip or ADC chip, as well as the single-event transient test data of the ADC chip.

[0037] All test data are uploaded to the host computer software unit for storage and display.

[0038] Preferably, when conducting an overall irradiation test on a SiP device, if the beam spot cannot completely cover the SiP device, the embedded chips are irradiated one by one.

[0039] Secondly, a single-event effect testing system for SiP devices is provided, comprising: a hardware part and a software part, wherein the hardware part includes a DUT test board and a control board, and the software part includes an upper computer software unit and a lower computer software unit.

[0040] The DUT test board is used to power on the SiP device and connect the embedded chip of the SiP device to the control board, serving as the interface between the SiP device and the control board.

[0041] The control board connects to the embedded chip of the SiP device through the DUT test board and sends control commands to it. It configures and reads the configuration code stream of the embedded chip of the SiP device, analyzes and records the single-particle flip information accordingly, and can communicate with the host computer.

[0042] The lower-level software unit is located in the lower-level machine. On the one hand, it connects to the control board to power it on. On the other hand, it includes single-event test programs developed for FPGA, PROM and ADC chips in SiP devices, monitors and records the operating current data of SiP devices and uploads the test data to the upper-level software unit.

[0043] The host computer software unit is located in the host computer, receives the recorded data from the control board and the slave computer software unit, and monitors the single-event test of the SiP device.

[0044] Preferably, the DUT test board meets the requirements for self-starting power-on operation of SiP devices during testing, BPI and JTAG program configuration functions, and also provides a SelectMAP interface for communication between SiP devices and the control board. Specifically:

[0045] Two LTM4644 chips were selected as DC-DC power supply chips, with 8 voltage and current outputs for the self-starting power-on of SiP devices.

[0046] The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, so as to meet the self-starting test requirements during single-chip testing.

[0047] The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board, are brought out. The SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time to meet the needs of dual-chip testing.

[0048] Preferably, the control board is equipped with a main control FPGA chip, which enables remote control of the DUT test board and data communication with the host computer software. The control board has at least two general-purpose banks of the main control FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board. The main control FPGA chip of the control board is connected to an external storage chip to store the power-on configuration program and test data of the DUT test board. When the control board interacts with the host computer, a serial port channel needs to be reserved.

[0049] Preferably, the host computer software unit is developed based on LabVIEW and can display the single-event upset and single-event interruption information of the sensitive module of the SiP device under test in real time; monitor the curves of the working current of each SiP under irradiation environment over time to determine whether single-event lock occurs, and then save all test results in txt format.

[0050] Preferably, when performing single-event testing on the FPGA chip of a SiP device:

[0051] The power supply parameters of the main FPGA chip on the control board are set by the FPGA module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the FPGA chip of the SiP device is powered on by the DUT test board.

[0052] The control board sends control commands to the FPGA chip of the SiP device, loads the configuration code stream onto the FPGA chip of the SiP device, and then turns on the beam to conduct the irradiation test. The FPGA module in the lower-level software unit monitors the operating current of the FPGA chip of the SiP device in real time. When the operating current exceeds 1.5 times its operating current during irradiation, it is determined that a single-event lock has occurred. At this time, the FPGA chip of the SiP device is powered off and restarted, and the error information is recorded.

[0053] The control board reads the program configuration code stream of the FPGA chip of the SiP device in real time through the SelectMAP interface and compares it with the initially written configuration code stream. If they are inconsistent, it determines that a single event flip has occurred and records the number of single event flips and the frame address.

[0054] Finally, all test results were uploaded to the host computer software unit.

[0055] Preferably, when performing single-event testing on a PROM chip or ADC chip:

[0056] The power supply parameters of the main FPGA chip on the control board are set by the PROM module or ADC module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the PROM chip or ADC chip of the SiP device is powered on by the DUT test board.

[0057] The main control FPGA chip on the control board writes the configuration code stream into the ADC chip or PROM chip of the SiP device to put it into normal working state and start the irradiation test; during the irradiation process, the PROM module or ADC module in the lower computer software unit monitors the working current of the PROM chip or ADC chip in real time to determine whether single-event lock occurs.

[0058] During the irradiation process, the control board reads the configuration code stream of the ADC chip or PROM chip and compares it with the initial configuration code stream to obtain the single-event flip results of the PROM chip or ADC chip, as well as the single-event transient test data of the ADC chip.

[0059] All test data are uploaded to the host computer software unit for storage and display.

[0060] Compared with the prior art, the present invention has the following advantages:

[0061] (1) This invention proposes a single-event effect testing method based on SiP devices and provides a single-event effect testing system for SiP devices, which can simply and effectively realize the single-event effect testing of SiP devices, instead of being limited to targeted testing of fixed SiP devices as in the prior art. This invention provides technical support for the overall single-event testing of other SiP devices and the independent single-event testing of each built-in chip.

[0062] (2) In developing the DUT test board, this invention designed two schemes to load the test code stream of the SiP chip: single-chip self-starting and dual-chip external control startup. Among them, the single-chip self-starting method uses the JTAG interface to directly configure the test code stream, which shortens the development cycle of the lower-level test program; the dual-chip control startup uses commercial development as the control board to load the code stream of the SiP under test, that is, there is no need to develop a control board, which shortens the hardware development time in the dual-chip startup mode and saves costs.

[0063] (3) This invention uses a remotely controlled digital power supply to measure the multi-channel operating current of the SiP chip in real time, preventing the chip from burning out due to SEL. Finally, the current data over time is saved in txt format, which helps to analyze the current change characteristics during subsequent SEU and SEFI analysis, improves the efficiency of test analysis, and has good economic benefits. Attached Figure Description

[0064] Figure 1 is an overall flowchart of the present invention;

[0065] Figure 2 is a frame diagram of the DUT test plate of the present invention;

[0066] Figure 3 is a diagram of the host computer interface of the FPGA chip of the present invention;

[0067] Figure 4 illustrates the design concept of the FPGA chip lower-level machine program of the present invention.

[0068] Figure 5 is a schematic diagram of the ADC and PROM chip programming concept of the present invention.

[0069] Figure 6 is a schematic diagram of FPGA module simulation injection according to the present invention. Detailed Implementation

[0070] This invention enables the testing of single-event lock-in (SEL), single-event function interruption (SEFI), and single-event flip (SEU) of different chips inside SiP devices, and can provide technical support for single-event effect testing of most SiP devices on the market.

[0071] Firstly, a method for testing single-event effects in SiP devices is provided, comprising the following steps:

[0072] (1) Perform capping or thinning treatment on SiP devices;

[0073] (2) Based on the information of the chip packaged inside the SiP device, obtain the single-event effect sensitive module of the embedded chip to be tested; usually, it mainly includes the SiP device's built-in FPGA chip (including configuration memory (CRAM), configurable logic block (CLB), block memory (BRAM) and interface circuit module), memory chip (PROM), ADC chip, DSP chip (including arithmetic processing module and interface circuit module, etc.).

[0074] (3) Determine the test plan and design the hardware and software; based on the single-event effect of the sensitive module to be tested in step (2), design the hardware and software. The hardware design includes the design of the test device (DUT) board and control board, and the software part includes the host computer software and the slave computer software. The host computer software is the test monitoring and control software developed based on LabVIEW, and the slave computer software is the single-event test program written in Verilog language for the SiP sensitive module.

[0075] (4) Verify the feasibility of the test system by injecting errors into the DUT through simulation. Before conducting single-particle experiments, it is necessary to verify whether the designed test system can meet the test requirements. Therefore, the method of injecting errors through simulation is used for board-level debugging and verification.

[0076] (5) Irradiation tests were conducted on the entire SiP device and individual internal chips to verify the feasibility of the test method and to evaluate whether the SiP device meets the radiation resistance index.

[0077] The specific steps of the present invention will now be described in detail with reference to the accompanying drawings.

[0078] As shown in Figure 1, the main steps of the single-event effect testing method based on SiP devices of the present invention are as follows:

[0079] (1) Based on the depth information of the sensitive region of SiP, the SiP is subjected to capping or thinning treatment. Most SiP devices used in aerospace are flip-chip devices with a sensitive region of about several hundred μm. However, the range of heavy ion accelerators in Si is generally less than 100 μm, so capping and thinning treatment of SiP is required. However, if proton and electron experiments are performed, the range of protons and electrons in Si is generally greater than several hundred μm due to their strong penetrating power, so only capping treatment is required.

[0080] (2) Based on the structure and model of the embedded chips in the SiP device, the sensitive modules of each chip are determined, and each module is subjected to irradiation test analysis to obtain the single-event effect test items of the SiP device. The embedded chips are usually a combination package of four chips: FPGA, DSP, ADC and PROM. Taking the FPGA chip as an example, its single-event test mainly focuses on the SEU test of the CRAM, BRAM and CLB modules; the SEFI test of the power-on startup circuit (POR circuit), communication interface circuit (SelectMAP or JTAG circuit), global control signal (GS signal) and frame address register (FAR); and the SEL test of the normal operating current of the entire chip in the irradiation environment.

[0081] (3) After determining the test items, it is necessary to determine the test plan and design the test software and hardware accordingly. This invention designs a software and hardware design method to meet the single-event test requirements of most sensitive modules of SiP devices, and selects a typical SiP device for design verification. The idea is as follows:

[0082] (a) In the hardware design, dual-chip and single-chip power-on startup modes are selected. The hardware design includes the design of the DUT test board and the control board. As shown in Figure 2, the design framework of the DUT test board is as follows: the DUT test board is used as a self-starting test board in single-chip testing and as a passively starting sub-board in dual-chip testing. Therefore, the test board needs to meet the requirements of self-starting power-on operation of SiP devices in single-chip testing, BPI and JTAG program configuration functions, and the design of the SiP device and the SelectMAP communication interface of the control board in dual-chip testing. First, regarding the power-on circuit design, since SiP devices require multiple operating voltages and currents, two LTM4644 DC-DC power supply chips were selected to provide eight voltage and current channels, meeting the power-on requirements of most SiP devices. Second, to meet the self-starting test requirements during single-chip testing, JTAG, BPI, and RS485 interface circuits were introduced. The JTAG and BPI interfaces allow for loading the SiP device configuration program, while the RS485 interface enables data transmission between the DUT test board and the host computer. Finally, to meet the requirements of dual-chip testing, a SiP device-SelectMAP interface circuit was introduced, and this interface was designed as a universal FMC interface. Through this interface, the control board can remotely control and monitor the DUT test board in real time.

[0083] The SiP device single-event effect test control board incorporates a main control FPGA chip. This control board relies on the board-level main control FPGA chip to remotely control the DUT test board and communicate with the host computer software. First, since the DUT test board has two reserved FMC data channels, the control board must expose at least two general-purpose banks on the FPGA chip to establish a data transmission channel with the DUT test board's FMC interface. Second, the control board's FPGA chip needs an external memory chip to store the DUT test board's power-on configuration program and test data. Finally, a serial port channel is required for data interaction between the control board and the host computer. Based on the control board requirements analysis, the commercial development board Qimingxing V2.0 can be selected as the control board to achieve dual-chip control, significantly saving development time.

[0084] (b) The software design is divided into host computer software and slave computer software. The host computer software is a remote control terminal developed based on LabVIEW. It can display the single event upset and single event interruption information of the sensitive module of the device under test in real time. At the same time, it can monitor the curve of the working current of each SiP under irradiation environment over time to determine whether SEL is generated. Then, all test results are saved in txt format. Taking the FPGA chip as an example, its host computer interface is shown in Figure 3.

[0085] The lower-level software is a test program developed based on ISE14.7, which includes the design of single-event test programs for various sensitive modules of the FPGA, PROM, and ADC chips. Specifically:

[0086] Figure 4 shows the flowchart of the FPGA chip's lower-level program design. First, the FPGA chip is powered on using a digital power supply, and its operating current is monitored in real time. If the operating current surges during irradiation (exceeding 1.5 times its normal operating current), a surge-induced failure (SEL) is detected. At this point, the FPGA chip is powered off and restarted, and the error information is recorded. Next, control commands are sent to the FPGA chip via the control board to load the configuration code streams for the FPGA chip's CRAM, BRAM, and CLB test programs. After the FPGA chip's program code stream configuration is complete, the beam is turned on, and the irradiation test is conducted. Finally, the FPGA chip's GS is monitored in real time. The system monitors the high and low levels of signals, communication interfaces, and POR signals to determine if a SEFI (Self-Enhancing Filter) is generated. If the level changes from 0 to 1, an SEFI is recorded, and the FPGA configuration stream is reloaded. If no SEFI is generated, a SEU (Self-Enhancing Unknown Filter) test is performed. Next, the control board reads the FPGA chip's CRAM, BRAM, and CLB program configuration streams in real time through the FPGA chip's SelectMAP interface and compares them with the initially written configuration stream. If they are inconsistent, an SEU is generated, and the number of SEUs and the frame address are recorded. Finally, all test results are uploaded to the host computer.

[0087] Figure 5 illustrates the programming logic for the ADC and PROM chips. First, the PROM and ADC chips are powered on using a digital power supply, and their operating currents are monitored in real-time during irradiation to determine if a single event fault (SEL) occurs. Then, the configuration code stream is written to the ADC and PROM via the FPGA chip to ensure normal operation, and the irradiation test is initiated. Next, the configuration code stream written to the ADC and PROM is read during irradiation and compared with the initial code stream to obtain the single event fault (SIF) results for the PROM and ADC, as well as the single event transient (SET) test data for the ADC. Finally, all test data is uploaded to the host computer for storage and display.

[0088] (4) Before conducting single-event experiments on each embedded chip, the feasibility of the entire software and hardware is verified by injecting error methods into the designed software and hardware. If the simulation test passes, a single-event experiment is conducted; otherwise, return to step (3) to modify the test program. Taking the FPGA chip as an example, in the FPGA single-event experiment, the host computer needs to display in real time the number of single-event flips, the number of single-event interrupts, and the real-time changes in the operating current of the sensitive modules of the FPGA chip. As can be seen from Figure 6, the module can capture the error information, error address, and current changes injected by the BRAM module and the DRAM (CLB) module, thus meeting the design requirements.

[0089] (5) Conduct an irradiation test on the entire SiP device. Since the SiP device is composed of multiple bare chips and has a certain size, if the beam spot cannot completely cover the SiP device during the irradiation test, the embedded chips will be irradiated one by one.

[0090] (6) After the SiP device as a whole is irradiated and tested or the embedded chip is tested individually, upload, save and analyze the test data, and then turn off the beam to end the test.

[0091] In a second aspect, the present invention provides a single-event effect testing system for SiP devices, comprising: a hardware part and a software part, wherein the hardware part includes a DUT test board and a control board, and the software part includes an upper computer software unit and a lower computer software unit.

[0092] The DUT test board is used for the self-starting power-on operation of SiP devices during single-chip testing, BPI and JTAG program configuration, and communication between SiP devices and the control board's SelectMAP interface during dual-chip testing.

[0093] The control board is used for remote control of the DUT test board and data communication with the host computer;

[0094] The host computer software unit is set in the host computer to monitor and control the SiP device;

[0095] The lower-level software unit is located in the lower-level machine and includes single-event test programs developed for each sensitive module of the FPGA, PROM and ADC chips in the SiP device. It combines the DUT test board and control board to perform single-event tests on the embedded chips of the SiP device and uploads the test data to the upper-level machine.

[0096] 2.1 In the DUT test board:

[0097] Two LTM4644 chips were selected as DC-DC power supply chips, with 8 voltage and current outputs for the self-starting power-on of SiP devices.

[0098] The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, so as to meet the self-starting test requirements during single-chip testing.

[0099] The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board, are brought out. The SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time to meet the needs of dual-chip testing.

[0100] 2.2 The control board is equipped with a main control FPGA chip, which enables remote control of the DUT test board and data communication with the host computer software. The control board should bring out at least two general-purpose banks of the main control FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board. The main control FPGA chip of the control board is connected to an external storage chip to store the power-on configuration program and test data of the DUT test board. When the control board interacts with the host computer, a serial port channel should be reserved.

[0101] 2.3 The host computer software unit is developed based on LabVIEW and can display the single-event upset and single-event interruption information of the sensitive module of the SiP device under test in real time; monitor the curves of the working current of each SiP under irradiation environment over time to determine whether single-event lock occurs, and then save all test results in txt format.

[0102] 2.4 When the FPGA module in the lower-level software unit performs single-event experiments on the FPGA chip of the SiP device:

[0103] The power supply parameters of the main FPGA chip on the control board are set by the lower-level software. Then, the main FPGA chip on the control board is powered on by the lower-level software. The operating current of the FPGA chip of the SiP device is monitored in real time. When the operating current exceeds 1.5 times its operating current during irradiation, it is determined that a single-event lock has occurred. At this time, the FPGA chip of the SiP device is powered off and restarted, and the error information is recorded.

[0104] The control board sends control commands to the FPGA chip of the SiP device, loads the configuration code stream onto the FPGA chip, and then turns on the beam to conduct an irradiation test.

[0105] By monitoring the level of the corresponding signal of the FPGA chip of the SiP device in real time, it is determined whether a single-event function interrupt (SEE) has occurred. If the level changes from 0 to 1, an SEE is recorded and the configuration stream is reloaded. If no SEE occurs, a single-event upset test is performed.

[0106] The control board reads the program configuration code stream of the FPGA chip of the SiP device in real time through the SelectMAP interface and compares it with the initially written configuration code stream. If they are inconsistent, it determines that a single event flip has occurred and records the number of single event flips and the frame address.

[0107] Finally, all test results were uploaded to the host computer.

[0108] 2.5 When the ADC module and PROM module in the lower-level software unit perform single-event experiments on the PROM chip and ADC chip:

[0109] Power on the PROM chip and ADC chip, and monitor the operating current of the PROM chip and ADC chip in real time during irradiation to determine whether single-event lock occurs.

[0110] The main control FPGA chip on the control board writes the configuration code stream into the ADC chip and PROM chip to put them into normal working condition and start the irradiation test.

[0111] During the irradiation process, the configuration code streams written to the ADC chip and PROM chip are read and compared with the initial configuration code stream to obtain the single-event flip results of the PROM chip and ADC chip, as well as the single-event transient test data of the ADC chip.

[0112] All experimental data are uploaded to the host computer for storage and display.

[0113] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

Claims

1. A method for testing single-event effects in SiP devices, characterized in that... include: S1. Based on the depth information of the sensitive area of ​​the SiP device, the SiP device is subjected to capping or thinning treatment. S2. Analyze each embedded chip of the SiP device to obtain the single-event effect test items of the SiP device; S3. The test system for the single-event effect test of SiP devices includes hardware and software components. The hardware component includes the DUT test board and control board, and the software component includes the host computer software unit and the slave computer software unit. S4. Simulate and verify the injection of errors into the hardware and software components. If the simulation verification fails, modify the test system and repeat the simulation verification. If the simulation verification passes, proceed to S5. S5. Perform single-event tests on each embedded chip of the SiP device. The DUT test board is connected to both the embedded chip of the SiP device and the control board, serving as the interface between the SiP device and the control board. The control board sends control commands to the embedded chip of the SiP device, configures and reads the configuration code stream of the embedded chip of the SiP device, analyzes and records the single-event flip information based on the configuration code stream. The lower-level software unit powers on the control board, monitors and records the operating current data of the SiP device. The control board and the lower-level software unit send the recorded data to the upper-level software unit for display and storage. S6. Conduct an overall irradiation test on the SiP device.

2. The single-event effect testing method for SiP devices according to claim 1, characterized in that: The embedded chips in SiP devices include: Field Programmable Gate Array (FPGA) chips, PROM chips, and Analog-to-Digital Converter (ADC) chips.

3. The method for testing single-event effects in SiP devices according to claim 1, characterized in that: The DUT test board supports self-starting power-on operation of SiP devices during testing, BPI and JTAG program configuration functions, and also provides a SelectMAP interface for communication between SiP devices and the control board. Specifically: When designing the power-on circuit, two LTM4644 chips were selected as DC-DC power chips to output 8 voltage and current channels; The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, which meets the self-starting test requirement during single-chip testing. The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board, are brought out. The SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time, meeting the requirements of dual-chip testing.

4. The single-event effect testing method for SiP devices according to claim 3, characterized in that: The control board contains a main control FPGA chip, which enables remote control of the DUT test board and data communication with the host computer. Specifically: The control board should bring out at least two general-purpose banks of the main control FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board; The main control FPGA chip of the control board needs to be connected to an external storage chip to store the power-on configuration program and test data of the DUT test board; When the control board interacts with the host computer, a serial port channel needs to be reserved.

5. The method for testing single-event effects in SiP devices according to claim 3, characterized in that: The host computer software unit is a remote control terminal developed based on LabVIEW. It receives, displays, and saves the recorded data from the control board and the slave computer software unit. Specifically: Real-time display of single-event upset and single-event failure information of the device under test; The curves of the working current of each SiP circuit changing with time under irradiation are monitored in real time to determine whether single-event lock-in occurs, and then all test results are saved in txt format.

6. The method for testing single-event effects in a SiP device according to claim 2, characterized in that: The lower-level software unit includes single-event test programs for the FPGA module, PROM module, and ADC module. These programs are used to power on the main FPGA chip of the control board, monitor and record the operating current of the FPGA chip, PROM chip, and ADC chip, and send the recorded results to the upper-level software unit when performing single-event tests on the FPGA chip, PROM chip, and ADC chip, respectively.

7. The method for testing single-event effects in a SiP device according to claim 6, characterized in that: When performing single-event testing on FPGA chips of SiP devices: The power supply parameters of the main FPGA chip on the control board are set by the FPGA module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the FPGA chip of the SiP device is powered on by the DUT test board. The control board sends control commands to the FPGA chip of the SiP device, loads the configuration code stream onto the FPGA chip of the SiP device, and then turns on the beam to conduct the irradiation test. The FPGA module in the lower-level software unit monitors the operating current of the FPGA chip of the SiP device in real time. When the operating current exceeds 1.5 times its operating current during irradiation, it is determined that a single-event lock has occurred. At this time, the FPGA chip of the SiP device is powered off and restarted, and the error information is recorded. The control board reads the program configuration code stream of the FPGA chip of the SiP device in real time through the SelectMAP interface and compares it with the initially written configuration code stream. If they are inconsistent, it determines that a single event flip has occurred and records the number of single event flips and the frame address. Finally, all test results were uploaded to the host computer software unit.

8. The method for testing single-event effects in a SiP device according to claim 7, characterized in that: When performing single-event testing on the PROM chip or ADC chip of a SiP device: The power supply parameters of the main FPGA chip on the control board are set by the PROM module or ADC module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the PROM chip or ADC chip of the SiP device is powered on by the DUT test board. The main control FPGA chip on the control board writes the configuration code stream into the ADC chip or PROM chip of the SiP device to put it into normal working state and start the irradiation test; during the irradiation process, the PROM module or ADC module in the lower computer software unit monitors the working current of the PROM chip or ADC chip in real time to determine whether single-event lock occurs. During the irradiation process, the control board reads the configuration code stream of the ADC chip or PROM chip and compares it with the initial configuration code stream to obtain the single-event flip results of the PROM chip or ADC chip, as well as the single-event transient test data of the ADC chip. All test data are uploaded to the host computer software unit for storage and display.

9. The single-event effect testing method for SiP devices according to claim 1, characterized in that: When conducting an overall irradiation test on a SiP device, if the beam spot cannot completely cover the SiP device, the embedded chips are irradiated one by one.

10. A single-event effect testing system for SiP devices, characterized in that... include: The hardware consists of a DUT test board and a control board, while the software consists of a host computer software unit and a slave computer software unit. The DUT test board is used to power on the SiP device and connect the embedded chip of the SiP device to the control board, serving as the interface between the SiP device and the control board. The control board connects to the embedded chip of the SiP device through the DUT test board and sends control commands to it. It configures and reads the configuration code stream of the embedded chip of the SiP device, analyzes and records the single-particle flip information accordingly, and can communicate with the host computer. The lower-level software unit is located in the lower-level machine. On the one hand, it connects to the control board to power it on. On the other hand, it includes single-event test programs developed for FPGA, PROM and ADC chips in SiP devices, monitors and records the operating current data of SiP devices and uploads the test data to the upper-level software unit. The host computer software unit is located in the host computer, receives the recorded data from the control board and the slave computer software unit, and monitors the single-event test of the SiP device.

11. The single-event effect testing system for SiP devices according to claim 10, characterized in that: The DUT test board supports self-starting power-on operation of SiP devices during testing, BPI and JTAG program configuration functions, and also provides a SelectMAP interface for communication between SiP devices and the control board. Specifically: Two LTM4644 chips were selected as DC-DC power supply chips, with 8 voltage and current outputs for the self-starting power-on of SiP devices. The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, so as to meet the self-starting test requirements during single-chip testing. The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board, are brought out. The SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time to meet the needs of dual-chip testing.

12. The single-event effect testing system for SiP devices according to claim 11, characterized in that: The control board is equipped with a main control FPGA chip, which enables remote control of the DUT test board and data communication with the host computer software. The control board has at least two general-purpose banks of the main control FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board. The main control FPGA chip of the control board is connected to an external storage chip to store the power-on configuration program and test data of the DUT test board. A serial port channel needs to be reserved when the control board interacts with the host computer.

13. The single-event effect testing system for SiP devices according to claim 10, characterized in that: The host computer software unit is developed based on LabVIEW and can display the single-event upset and single-event interruption information of the sensitive module of the SiP device under test in real time; monitor the curves of the working current of each SiP under irradiation environment over time to determine whether single-event lock occurs, and then save all test results in txt format.

14. The single-event effect testing system for SiP devices according to claim 10, characterized in that: When performing single-event testing on FPGA chips of SiP devices: The power supply parameters of the main FPGA chip on the control board are set by the FPGA module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the FPGA chip of the SiP device is powered on by the DUT test board. The control board sends control commands to the FPGA chip of the SiP device, loads the configuration code stream onto the FPGA chip of the SiP device, and then turns on the beam to conduct the irradiation test. The FPGA module in the lower-level software unit monitors the operating current of the FPGA chip of the SiP device in real time. When the operating current exceeds 1.5 times its operating current during irradiation, it is determined that a single-event lock has occurred. At this time, the FPGA chip of the SiP device is powered off and restarted, and the error information is recorded. The control board reads the program configuration code stream of the FPGA chip of the SiP device in real time through the SelectMAP interface and compares it with the initially written configuration code stream. If they are inconsistent, it determines that a single event flip has occurred and records the number of single event flips and the frame address. Finally, all test results were uploaded to the host computer software unit.

15. A single-event effect testing system for SiP devices according to claim 10, characterized in that: When performing single-event testing on PROM chips or ADC chips: The power supply parameters of the main FPGA chip on the control board are set by the PROM module or ADC module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the PROM chip or ADC chip of the SiP device is powered on by the DUT test board. The main control FPGA chip on the control board writes the configuration code stream into the ADC chip or PROM chip of the SiP device to put it into normal working state and start the irradiation test; during the irradiation process, the PROM module or ADC module in the lower computer software unit monitors the working current of the PROM chip or ADC chip in real time to determine whether single-event lock occurs. During the irradiation process, the control board reads the configuration code stream of the ADC chip or PROM chip and compares it with the initial configuration code stream to obtain the single-event flip results of the PROM chip or ADC chip, as well as the single-event transient test data of the ADC chip. All test data are uploaded to the host computer software unit for storage and display.

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