Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises sub-pixels, a pixel defining pattern, a first metal pattern, and a second metal pattern, wherein each sub-pixel comprises a light-emitting functional layer, a first electrode, and a second electrode; at least part of the pixel defining pattern is located between the light-emitting functional layer and the first electrode; the first metal pattern is located between the first electrodes of the sub-pixels and a base substrate; the second metal pattern is located between the first metal pattern and the base substrate; light-emitting regions of at least some of the sub-pixels overlap with the second metal pattern; the first metal pattern comprises a plurality of first body portions, at least some of the first body portions being connected to each other; and in a direction perpendicular to the base substrate, the orthographic projection of a light-emitting region of each of at least one sub-pixel on the base substrate falls within the orthographic projections of the first body portions on the base substrate. The first electrodes of the sub-pixels in the display panel have good flatness, thereby having a relatively low risk of color shift.

Description

Display panel and display device Technical Field

[0001] At least one embodiment of this disclosure relates to a display panel and a display device. Background Technology

[0002] With the increasing demand for lower power consumption in displays, many technologies are being integrated into displays to achieve products with lower power consumption. For example, color filter on encapsulation (COE) technology, low temperature polycrystalline oxide (LTPO) technology, and low-power narrow bezel technology (VSS in pixel, SIP) that distributes power signals (VSS) in a mesh pattern in the pixel emitting area have gradually been applied to many products.

[0003] Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display panel, comprising: a substrate, a plurality of subpixels, a pixel defining pattern, a first metal pattern, and a second metal pattern. The plurality of subpixels are located on the substrate, each subpixel including a light-emitting functional layer, and a first electrode and a second electrode located on opposite sides of the light-emitting functional layer along a direction perpendicular to the substrate. The first electrode is located between at least a portion of the light-emitting functional layer and the substrate. At least a portion of the pixel defining pattern is located between the light-emitting functional layer and the first electrode. The pixel defining pattern includes a plurality of pixel openings and a pixel defining portion located between adjacent pixel openings. The pixel openings expose at least a portion of the first electrode to define a light-emitting area of ​​the subpixel. The first metal pattern is located between the first electrode of the subpixel and the substrate. The second metal pattern is located between the first metal pattern and the substrate. In a direction perpendicular to the substrate, the light-emitting area of ​​at least a portion of the subpixel overlaps with the second metal pattern. The first metal pattern includes a plurality of first main bodies, at least a portion of the first main bodies being connected to each other. In a direction perpendicular to the substrate, the orthographic projection of the light-emitting area of ​​at least one subpixel on the substrate falls into the orthographic projection of the first main body on the substrate.

[0005] For example, in a display panel provided according to at least one embodiment of the present disclosure, the second metal pattern includes a plurality of second main bodies, at least some of the second main bodies being connected to each other, the at least some sub-pixels including first sub-pixels and second sub-pixels, in a direction perpendicular to the substrate, the orthographic projection of the light-emitting area of ​​each sub-pixel in the first sub-pixels onto the substrate falls into the orthographic projection of the second main body onto the substrate, and the light-emitting area of ​​each sub-pixel in the second sub-pixels does not overlap with the second main body.

[0006] For example, in a display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the light-emitting area of ​​each sub-pixel in the second portion of the sub-pixels onto the substrate falls into the orthographic projection of the first main body portion onto the substrate.

[0007] For example, in a display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the light-emitting area of ​​each sub-pixel in the first portion of sub-pixels onto the substrate falls into the orthographic projection of the first main body onto the substrate.

[0008] For example, in a display panel provided according to at least one embodiment of the present disclosure, the plurality of sub-pixels includes a first group of sub-pixels and a second group of sub-pixels, both the first group of sub-pixels and the second group of sub-pixels include at least one color sub-pixel, the light-emitting area of ​​each sub-pixel in the first group of sub-pixels overlaps with both the first main body and the second main body, and the light-emitting area of ​​each sub-pixel in the second group of sub-pixels overlaps with one of the first main body and the second main body.

[0009] For example, in a display panel provided according to at least one embodiment of the present disclosure, the first group of sub-pixels includes red sub-pixels and blue sub-pixels, and the second group of sub-pixels includes green sub-pixels; or the first group of sub-pixels includes green sub-pixels, and the second group of sub-pixels includes red sub-pixels and blue sub-pixels.

[0010] For example, in a display panel provided according to at least one embodiment of the present disclosure, the first metal pattern further includes a plurality of connecting portions, the first main body portion being connected to another first main body portion through the connecting portions, the orthographic projection of the connecting portion on the substrate being strip-shaped, and the orthographic projection of the connecting portion on the substrate not overlapping with the light-emitting area of ​​the sub-pixel.

[0011] For example, in a display panel provided according to at least one embodiment of the present disclosure, the plurality of first main body portions are arranged in an array along a first direction and a second direction to form a plurality of rows of first main body portions arranged along the second direction and a plurality of columns of first main body portions arranged along the first direction, wherein the first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction.

[0012] For example, in a display panel provided according to at least one embodiment of the present disclosure, the connecting portion extends along the first direction or the second direction, adjacent first main body portions in the first main body portion row are connected by the connecting portion, and adjacent first main body portions in the first main body portion column are connected by the connecting portion.

[0013] For example, in a display panel provided according to at least one embodiment of the present disclosure, the connecting portion extends along a first arrangement direction or a second arrangement direction, the first main body portion is connected to a first main body portion adjacent to it in the first arrangement direction or the second arrangement direction, the first arrangement direction and the second arrangement direction are both parallel to the substrate, and the first arrangement direction intersects the second arrangement direction, the first arrangement direction and the second arrangement direction both intersect the first direction and both intersect the second direction.

[0014] For example, in a display panel provided according to at least one embodiment of the present disclosure, the first metal pattern is an integral mesh structure.

[0015] For example, in a display panel provided according to at least one embodiment of the present disclosure, the orthographic projection shape of the first main body portion on the substrate is different from the orthographic projection shape of the second main body portion on the substrate.

[0016] For example, in a display panel provided according to at least one embodiment of the present disclosure, the orthographic projection shape of the light-emitting area of ​​the at least one sub-pixel on the substrate is the same as the orthographic projection shape of the first main body portion on the substrate.

[0017] For example, in a display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the light-emitting area of ​​each of the plurality of sub-pixels on the substrate falls into the orthographic projection of the first main body portion on the substrate.

[0018] For example, in a display panel provided according to at least one embodiment of the present disclosure, the first metal pattern is configured to transmit a first signal, and the second metal pattern is configured to transmit a second signal, wherein the first signal and the second signal are different.

[0019] For example, in a display panel provided according to at least one embodiment of the present disclosure, the second metal pattern includes a plurality of signal lines overlapping the first main body portion, and the signal lines extend along the second arrangement direction, wherein the surface of the first main body portion away from the substrate is flat.

[0020] For example, according to at least one embodiment of the present disclosure, the display panel further includes a light-shielding layer and a color filter layer. The light-shielding layer is located on the side of the second electrode away from the substrate. The light-shielding layer includes a plurality of first openings and a plurality of second openings. The orthographic projection of the first openings on the substrate at least partially overlaps with the orthographic projection of the pixel openings on the substrate. The color filter layer is located on the side of the light-shielding layer away from the substrate. The color filter layer includes a plurality of color filter portions. The orthographic projection of the light-emitting area of ​​the sub-pixel on the substrate falls into the orthographic projection of the color filter portion on the substrate. The sub-pixel further includes a pixel driving electrode. The pixel driving circuit is located at least a portion between the first electrode and the substrate and is configured to drive the light-emitting functional layer of the sub-pixel to emit light. The pixel defining pattern further includes a plurality of defining openings, the defining openings being spaced apart from the pixel openings. The orthographic projection of the defining openings on the substrate at least partially overlaps with the orthographic projection of the second opening on the substrate, and there is a gap between the orthographic projection of the defining openings on the substrate and the orthographic projection of at least a portion of the pixel driving circuit on the substrate. The orthographic projection of the defining openings on the substrate does not overlap with the orthographic projection of the color filter portion on the substrate.

[0021] For example, in a display panel provided according to at least one embodiment of the present disclosure, the minimum distance between the orthographic projection of the defining opening on the substrate and the orthographic projection of the first main body portion on the substrate is 1.5 to 10 micrometers.

[0022] At least one embodiment of this disclosure also provides a display device, the display device including the display panel provided in the embodiments of this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figures 1 to 3 are schematic diagrams of three types of metal mesh wiring.

[0025] Figure 4 is a partial planar schematic diagram of a display panel.

[0026] Figure 5 is a partial planar schematic diagram of another type of display panel.

[0027] Figure 6 is a partial cross-sectional schematic diagram of a display panel provided in at least one embodiment of the present disclosure.

[0028] Figure 7 is a schematic diagram of a first metal pattern provided in at least one embodiment of the present disclosure.

[0029] Figure 8 is a schematic diagram of a stacked first metal pattern and a second metal pattern provided in at least one embodiment of the present disclosure.

[0030] Figure 9 is a schematic diagram of another overlay of a first metal pattern and a second metal pattern provided in at least one embodiment of the present disclosure.

[0031] Figure 10 is a schematic diagram of another first metal pattern provided in at least one embodiment of the present disclosure.

[0032] Figure 11 is a schematic diagram of another layering of a first metal pattern and a second metal pattern provided in at least one embodiment of the present disclosure.

[0033] Figure 12 is a schematic diagram of another layering of a first metal pattern and a second metal pattern provided in at least one embodiment of the present disclosure.

[0034] Figure 13 is a partial plan view of a display panel provided in at least one embodiment of the present disclosure.

[0035] Figure 14 is another partial plan view of a display panel provided in at least one embodiment of the present disclosure.

[0036] Figure 15 is a partial cross-sectional schematic diagram of another display panel provided in at least one embodiment of the present disclosure.

[0037] Figure 16 is a schematic diagram of a pixel circuit provided in at least one embodiment of the present disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0040] The features "perpendicular," "parallel," and "identical" used in this disclosure include features in the strict sense of "perpendicular," "parallel," and "identical," as well as cases where "approximately perpendicular," "approximately parallel," and "approximately identical" include certain errors. Considering measurement and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The "center" in this disclosure can include a strictly geometrically central location and a roughly central location within a small area surrounding the geometrically central location.

[0041] Typically, SiP (Screen-in-Place) technology reduces power consumption by placing a metal mesh around the pixels in the pixel circuit design to reduce load. When SiP technology is applied to color organic EL (COE) products, the meshed wiring layout can affect the anode flatness of the sub-pixels. This effect needs to be carefully considered and controlled to ensure the performance and reliability of the display.

[0042] Figures 1 to 3 are schematic diagrams of three types of metal mesh traces. For example, both the metal mesh trace and the sub-pixel are located on the substrate. The metal mesh trace is disposed adjacent to the sub-pixel, that is, in the direction perpendicular to the substrate (not shown in the figure), no other metal trace is disposed between the sub-pixel and the metal mesh trace. The metal mesh trace can be the metal trace located on the side of the sub-pixel closest to the light-emitting area of ​​the sub-pixel on the side closest to the substrate.

[0043] For example, as shown in Figure 1, the metal mesh trace includes multiple metal meshes 010, and each metal mesh 010 surrounds the light-emitting area 020 of the sub-pixel. Figure 1 schematically shows that the orthographic projection of the metal meshes 010 on the substrate is approximately matrix-like, and the orthographic projection of the light-emitting area 020 of the sub-pixel on the substrate is approximately circular, but is not limited thereto.

[0044] For example, as shown in Figure 2, the metal mesh trace includes multiple metal meshes 010 and multiple extensions 011. The light-emitting area 020 of each sub-pixel in one part is surrounded by the metal meshes 010, while the light-emitting area 020 of each sub-pixel in another part is not surrounded by the metal meshes 010, but overlaps with the extensions 011.

[0045] For example, as shown in Figure 3, the metal mesh trace includes multiple metal meshes 010, and each metal mesh 010 surrounds the light-emitting area 020 of multiple sub-pixels. Figure 3 illustrates this by taking the example of each metal mesh 010 surrounding the light-emitting area 020 of at most two sub-pixels, but it is not limited to this.

[0046] For example, as can be seen from Figures 1 to 3, when other structures located between the metal mesh 010 and the substrate are asymmetrically arranged relative to the light-emitting area 020 of the sub-pixel, when the light-emitting area 020 of the sub-pixel is surrounded by the adjacent metal mesh 010, the metal mesh 010 has virtually no effect on improving the flatness of the anode (not shown in the figure) of the sub-pixel, and when the light-emitting area 020 of the sub-pixel overlaps with the extension 011 (as shown in Figure 2), the extension 011 may disrupt the anode flatness of the sub-pixel.

[0047] Figure 4 is a partial planar schematic diagram of one type of display panel; Figure 5 is a partial planar schematic diagram of another type of display panel.

[0048] For example, as shown in Figure 4, the display panel has a low-temperature polysilicon (LTPS) pixel circuit. The metal layer on the side of the sub-pixel's anode closest to the substrate contains multiple metal structures. These structures include, for example, data lines (DATA), power signal lines (VDD), a connection structure between the sub-pixel's light-emitting area (020) and the anode connection hole (N), and a connection block (BLO). Furthermore, these multiple metal structures are asymmetrically arranged relative to the sub-pixel's light-emitting area (020), which may disrupt the anode flatness of the sub-pixel, leading to a higher risk of color shift and color separation.

[0049] For example, as shown in Figure 5, the display panel has a low-temperature polysilicon (LTPS) pixel circuit. The metal layer on the side of the anode of the sub-pixel closest to the substrate has multiple metal structures, such as data lines (DATA) and power signal lines (VDD). In a portion of the sub-pixels, the light-emitting area (O20) of each sub-pixel is located on the power signal line (VDD), and the orthographic projection of the O20 onto the substrate completely falls within the orthographic projection of the VDD onto the substrate. Therefore, the anode of this portion of the sub-pixels has good flatness. However, in another portion of the sub-pixels (e.g., sub-pixels with a different light-emitting color than the aforementioned portion), the anode of each sub-pixel overlaps with two data lines (DATA), and the orthographic projection of the O20 onto the substrate does not completely fall within the orthographic projection of the VDD onto the substrate. This results in poorer flatness of the anode of this portion of the sub-pixels, leading to a higher risk of color shift and color separation. Therefore, in the display panel shown in Figure 5, the anode flatness of different color sub-pixels is different, which may result in uneven light emission of different color sub-pixels, affecting the overall display effect of the display panel.

[0050] As mentioned above, it is crucial to propose a solution that can effectively improve the anod flatness of subpixels, reduce the risk of color shift and color separation, and ensure a uniform and good overall display effect of the display panel.

[0051] Embodiments of this disclosure provide a display panel including a substrate, a plurality of subpixels, a pixel defining pattern, a first metal pattern, and a second metal pattern. The plurality of subpixels are located on the substrate, and each subpixel includes a light-emitting functional layer, and a first electrode and a second electrode located on both sides of the light-emitting functional layer in a direction perpendicular to the substrate. The first electrode is located between at least a portion of the light-emitting functional layer and the substrate. At least a portion of the pixel defining pattern is located between the light-emitting functional layer and the first electrode. The pixel defining pattern includes a plurality of pixel openings and a pixel defining portion located between adjacent pixel openings. The pixel openings expose at least a portion of the first electrode to define the light-emitting area of ​​the subpixel. The first metal pattern is located between the first electrode of the subpixel and the substrate. The second metal pattern is located between the first metal pattern and the substrate. In a direction perpendicular to the substrate, the light-emitting area of ​​at least a portion of the subpixel overlaps with the second metal pattern. The first metal pattern includes a plurality of first main bodies, and at least a portion of the first main bodies are connected to each other. In a direction perpendicular to the substrate, the orthographic projection of the light-emitting area of ​​at least one subpixel on the substrate falls into the orthographic projection of the first main body on the substrate.

[0052] In at least one embodiment of the present disclosure, a display panel is provided in which a first metal pattern is disposed between a second metal pattern and the light-emitting area of ​​a sub-pixel, and the orthogonal projection of the light-emitting area of ​​at least one sub-pixel on the substrate falls completely into the orthogonal projection of the first main body on the substrate. The first metal pattern can effectively improve the flatness of the first electrode of the sub-pixel and reduce the influence of other structures (such as a second metal pattern) located between the first metal pattern and the substrate on the flatness of the first electrode of the sub-pixel. This can effectively improve the flatness of the first electrode of the sub-pixel, reduce the risk of color shift and color separation, and make the overall display effect of the display panel uniform and good.

[0053] The display panel and display device provided in the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings, so that the corresponding technical solutions can be clearer and easier to understand.

[0054] Figure 6 is a partial cross-sectional schematic diagram of a display panel provided in at least one embodiment of the present disclosure; Figure 7 is a schematic diagram of the overlapping relationship between a first metal pattern and a light-emitting area provided in at least one embodiment of the present disclosure; Figure 8 is a schematic diagram of a stacked light-emitting area, a first metal pattern, and a second metal pattern provided in at least one embodiment of the present disclosure.

[0055] As shown in FIG6, the display panel includes a substrate 100 and a plurality of sub-pixels 10 located on the substrate 100. The sub-pixel 10 includes a light-emitting functional layer 130, and a first electrode 110 and a second electrode 120 located on both sides of the light-emitting functional layer 130 along a direction perpendicular to the substrate 100. The first electrode 110 is located between at least a portion of the light-emitting functional layer 130 and the substrate 100.

[0056] As shown in Figure 6, the light-emitting functional layer 130 may include multiple film layers. For example, the light-emitting functional layer 130 may include a light-emitting layer for emitting light and a charge-generating layer. The charge-generating layer has strong conductivity, which enables the light-emitting functional layer 130 to have advantages such as long lifespan, low power consumption, and high brightness. For example, the light-emitting functional layer 130 may be a film layer in an organic light-emitting element. For example, the light-emitting functional layer 130 may include a first light-emitting layer (EML), a charge-generating layer (CGL), and a second light-emitting layer (EML) stacked together, with the charge-generating layer located between the first light-emitting layer and the second light-emitting layer.

[0057] It should be noted that the light-emitting functional layer 130 may also include other film layers, such as a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), etc., and the embodiments disclosed herein do not limit this. For example, the hole injection layer, hole transport layer, electron transport layer, electron injection layer, charge generation layer, and second electrode 120 are all common film layers of multiple sub-pixels 10, and can be referred to as common layers. In addition, the thickness of each film layer shown in FIG. 6 is only for clear illustration of each film layer and does not represent the actual size.

[0058] For example, as shown in FIG6, other structures 0020 are also provided on the side of the first electrode 110 facing the substrate 100, such as a pixel driving circuit, signal lines, and various insulating layers electrically connected to the first electrode 110 of the sub-pixel 10. For example, the insulating layers may include a passivation layer, a buffer layer, a gate insulating layer, an interlayer insulating layer, etc., which are not limited in the embodiments of this disclosure. The pixel driving circuit is located between the first electrode 110 and the substrate 100 and is configured to drive the light-emitting functional layer 130 of the sub-pixel 10 to emit light. For example, the pixel driving circuit may include multiple transistors (such as thin-film transistors) and at least one capacitor (not shown in the figure). The first electrode 110 can be electrically connected to the pixel driving circuit through a connecting via to drive the light-emitting functional layer 130 to emit light. For example, the first electrode 110 can be an anode, and the second electrode 120 can be a cathode.

[0059] As shown in FIG. 6, the display panel further includes a pixel defining pattern 200, at least a portion of which is located between the light-emitting functional layer 130 and the first electrode 110. The pixel defining pattern 200 includes a plurality of pixel openings 201 and pixel defining portions 210 located between adjacent pixel openings 201. The pixel openings 201 expose at least a portion of the first electrode 110 to define the light-emitting area 101 of the sub-pixel 10. The light-emitting functional layer 130 is disposed in contact with the first electrode 110 through the pixel openings 201. For example, the first electrode 110 and the second electrode 120 located on both sides of the light-emitting functional layer 130 can drive the light-emitting functional layer 130 located between them to emit light. For example, the light-emitting area of ​​the sub-pixel 10 refers to the area where the sub-pixel 10 effectively emits light, and the shape of the light-emitting area refers to a two-dimensional shape. For example, the shape of the light-emitting area may be the same as the shape of the orthographic projection of the portion of the first electrode 110 exposed by the pixel openings 201 onto the substrate 100.

[0060] As shown in Figure 6, the display panel includes a first metal pattern 310 and a second metal pattern 320. The first metal pattern 310 is located between the first electrode 110 of the sub-pixel 10 and the substrate 100, and the second metal pattern 320 is located between the first metal pattern 310 and the substrate 100.

[0061] As shown in Figures 7 and 8, the first metal pattern 310 includes a plurality of first main body portions 311, at least some of which are connected to each other. In a direction perpendicular to the substrate 100, the orthographic projection of the light-emitting area 101 of at least one sub-pixel 10 onto the substrate 100 falls within the orthographic projection of the first main body portion 311 onto the substrate 100. At least some of the light-emitting areas 101 of the sub-pixel 10 overlap with the second metal pattern 320. For example, at least some of the light-emitting areas 101 of the sub-pixel 10 may fall within the orthographic projection of the second metal pattern 320 onto the substrate. For example, the second metal pattern 320 may be the metal film layer containing the data line DATA as shown in Figures 4 and 5, but is not limited thereto. As shown in Figure 6, the first metal pattern 310 is closer to the light-emitting area 101 of the sub-pixel 10 than the second metal pattern 320.

[0062] In the display panel provided by at least one embodiment of this disclosure, by setting a first metal pattern between a second metal pattern and the light-emitting area of ​​a sub-pixel, and making the orthogonal projection of the light-emitting area of ​​at least one sub-pixel on the substrate fall into the orthogonal projection of the first main body on the substrate, the flatness of the first electrode of the sub-pixel can be effectively improved by the first metal pattern, and the influence of other structures (such as a second metal pattern) located between the first metal pattern and the substrate on the flatness of the first electrode of the sub-pixel can be reduced. Therefore, the anode flatness of the sub-pixel can be effectively improved, the risk of color shift and color separation can be reduced, and the overall display effect of the display panel is uniform and good.

[0063] For example, as shown in FIG6, the first metal pattern 310 is configured to transmit a first signal, and the second metal pattern 320 is configured to transmit a second signal, and the first signal and the second signal are different. For example, the first signal can be a power signal VSS. For example, the second signal can include multiple sub-signals. For example, the second metal pattern 320 includes multiple signal lines overlapping with the first main body 311, and the signal lines extend along the second arrangement direction N (see FIG8). For example, the multiple signal lines can include data lines DATA, power signals VDD, etc. The surface of the first main body 311 away from the substrate is flat, thereby enabling the light-emitting area 101 of the sub-pixel to have good flatness.

[0064] When the second metal pattern 320 is the metal film layer where the data line DATA is located as shown in Figures 4 and 5, the multiple sub-signals may include data signals, power signals, etc.

[0065] By making the first signal different from the second signal, the influence of the second signal on the light-emitting functional layer of the sub-pixel can be reduced through the first signal, thereby enabling the sub-pixel to have a stable and good light-emitting effect.

[0066] For example, as shown in Figures 6 and 8, the orthographic projection shape of the first main body portion 311 on the substrate 100 is different from the orthographic projection shape of the second main body portion 321 on the substrate 100. For example, the orthographic projection shape of the first main body portion 311 on the substrate 100 is approximately circular, and the orthographic projection shape of the second main body portion 321 on the substrate 100 is approximately rectangular, but this is not a limitation. For example, the area of ​​the orthographic projection of the first main body portion 311 on the substrate 100 is different from the area of ​​the orthographic projection of the second main body portion 321 on the substrate 100, and the embodiments of this disclosure do not limit this.

[0067] This design simplifies the manufacturing process of the first main body and reduces the positional matching accuracy between the first and second main bodies.

[0068] For example, as shown in FIG8, the orthographic projection shape of the light-emitting area 101 of at least one sub-pixel on the substrate 100 is the same as the orthographic projection shape of the first main body portion 311 on the substrate, for example, both are approximately circular or the like.

[0069] This arrangement helps to ensure that the orthographic projection of the light-emitting area of ​​the sub-pixel on the substrate falls into the orthographic projection of the first main body on the substrate and maintains a uniform and appropriate distance from the orthographic projection of the first main body on the substrate, and also helps to reduce the layout space occupied by the first main body.

[0070] For example, as shown in FIG8, the second metal pattern 320 includes a plurality of second main body portions 321, at least some of which are connected to each other. For example, the plurality of second main body portions 321 are arranged in an array along a first arrangement direction M and a second arrangement direction N, forming a plurality of rows of second main body portions arranged along the second arrangement direction M and a plurality of columns of second main body portions arranged along the first arrangement direction N. Adjacent second main body portions 321 in a column of second main body portions are connected to each other, and adjacent second main body portions 321 in a row of second main body portions 321 are spaced apart.

[0071] For example, as shown in Figures 6 and 8, at least a portion of the sub-pixels 10 overlapping with the second metal pattern 320 includes a first portion of sub-pixels 11 and a second portion of sub-pixels 12. In a direction perpendicular to the substrate 100, the orthographic projection of the light-emitting area 101 of each sub-pixel 10 in the first portion of sub-pixels 11 onto the substrate 100 falls into the orthographic projection of the second main body portion 321 onto the substrate 100, and the light-emitting area 101 of each sub-pixel 10 in the second portion of sub-pixels 12 does not overlap with the second main body portion 321.

[0072] For example, as shown in FIG8, the orthographic projection of the light-emitting area 101 of each sub-pixel 10 in the second sub-pixel portion 12 onto the substrate 100 falls into the orthographic projection of the first main body portion 311 onto the substrate 100. That is, when the light-emitting area 101 of each sub-pixel 10 in the second sub-pixel portion 12 does not overlap with the second main body portion 321, the light-emitting area 101 of each sub-pixel 10 in the second sub-pixel portion 12 also overlaps with the first main body portion 311.

[0073] Therefore, the flatness of the first electrode of the second sub-pixel can be improved by the first main body, thereby reducing the flatness difference between the first electrode of the second sub-pixel and the first electrode of the first sub-pixel. This helps to reduce the risk of color shift and color separation, and makes the overall display effect of the display panel uniform and good.

[0074] For example, as shown in Figures 6 and 8, the orthographic projection of the light-emitting area 101 of each sub-pixel 10 in the first portion of sub-pixels 11 onto the substrate 100 also falls within the orthographic projection of the first main body 311 onto the substrate 100. In other words, the light-emitting area 101 of the first portion of sub-pixels 11 falls within both the orthographic projection of the second main body 321 onto the substrate 100 and the orthographic projection of the first main body 311 onto the substrate 100. This arrangement ensures that the first electrode 110 of the first portion of sub-pixels 11 has good flatness and effectively reduces the risk of color shift and color separation.

[0075] In some embodiments of this disclosure, multiple sub-pixels in the display panel may overlap with one of the first main body portion and the second main body portion, respectively. For example, the orthographic projection of the light-emitting area of ​​a portion of the sub-pixels onto the substrate falls into the orthographic projection of the first main body portion onto the substrate, while the orthographic projection of the light-emitting area of ​​another portion of the sub-pixels onto the substrate falls into the orthographic projection of the second main body portion onto the substrate. Thus, the flatness of the first electrode of the corresponding sub-pixel can be improved by using the first main body portion and the second main body portion, respectively.

[0076] Figure 9 is a schematic diagram of another overlay of a first metal pattern and a second metal pattern provided in at least one embodiment of the present disclosure.

[0077] For example, as shown in FIG8, the plurality of sub-pixels 10 includes a first group of sub-pixels 1100 and a second group of sub-pixels 1200, and both the first group of sub-pixels 1100 and the second group of sub-pixels 1200 include at least one color sub-pixel 10. For example, the sub-pixels 10 in the first group of sub-pixels 1100 and the sub-pixels 10 in the second group of sub-pixels 1200 have different emission colors. For example, the emission area 101 of each sub-pixel 10 in the first group of sub-pixels 1100 overlaps with both the first main body portion 311 and the second main body portion 321, and the emission area 101 of each sub-pixel 10 in the second group of sub-pixels 1200 overlaps with one of the first main body portion 311 and the second main body portion 321. In some embodiments, the first group of sub-pixels 1100 may be the first portion of sub-pixels 11 described in the above embodiments, and the second group of sub-pixels 1200 may be the second portion of sub-pixels 12 described in the above embodiments, but the embodiments of this disclosure are not limited thereto.

[0078] This setup balances the flatness of the first electrode of sub-pixels of different colors, resulting in a more uniform light emission effect from sub-pixels of different colors.

[0079] For example, as shown in Figure 8, the first group of sub-pixels 1100 includes red sub-pixels R and blue sub-pixels B, and the second group of sub-pixels 1200 includes green sub-pixels G, thereby ensuring good flatness of the first electrodes of red sub-pixels R and blue sub-pixels B, resulting in good light emission effect.

[0080] For example, compared with the display panel shown in FIG8, the position of the second metal pattern 320 relative to the first metal pattern 310 in the display panel shown in FIG9 is different, but the rest of the structure is the same, which will not be described in detail here.

[0081] For example, as shown in Figure 9, the first group of sub-pixels 1100 includes a green sub-pixel G, and the second group of sub-pixels 1200 includes a red sub-pixel R and a blue sub-pixel B, which can make the first electrode of the green sub-pixel G have good flatness and thus have good light emission effect.

[0082] It should be noted that the embodiments disclosed herein do not limit the emission colors of the first group of sub-pixels and the second group of sub-pixels, and the specific colors can be set according to design requirements.

[0083] For example, as shown in FIG7, the first metal pattern 310 further includes a plurality of connecting portions 305, and the first main body portion 311 is connected to another first main body portion 311 through the connecting portions 305. The orthographic projection of the connecting portion 305 on the substrate is strip-shaped, and the orthographic projection of the connecting portion 305 on the substrate does not overlap with the light-emitting area 101 of the sub-pixel 10. For example, the connecting portion 305 and the first main body portion 311 are made of the same material and formed by the same process.

[0084] For example, as shown in FIG7, a plurality of first main body portions 311 are arranged in an array along a first direction V and a second direction U to form a plurality of rows 3110 of first main body portions arranged along the first direction V and a plurality of columns 3120 of first main body portions arranged along the second direction U. Both the first direction V and the second direction U are parallel to the substrate, and the first direction V intersects the second direction U, for example, the first direction V is perpendicular to the second direction U.

[0085] For example, as shown in FIG7, the connecting portion 305 extends along a first direction V or a second direction U. Adjacent first main body portions 311 in the first main body portion row 3110 are connected by the connecting portion 305, and adjacent first main body portions 311 in the first main body portion column 3120 are connected by the connecting portion 305. For example, at least one first main body portion 311 is connected to four surrounding first main body portions 311, and the first main body portion 311 is surrounded by eight first main body portions 311. For example, one first main body portion 311 is connected to at most four first main body portions 311.

[0086] For example, Figures 6 and 7 also show a plurality of defined openings NS located in the pixel-defined pattern, so that the display panel has a transmittance that meets the requirements, so as to facilitate the normal operation of under-display sensors and fingerprint sensors installed under the screen. For the specific structure of the defined openings NS, please refer to the relevant description of the following embodiments. For example, the minimum distance between the orthographic projection of the defined openings NS on the substrate 100 and the orthographic projection of the first main body portion 311 on the substrate 100 is 1.5 to 10 micrometers, such as at least one of 1.5 to 2.0 micrometers, 2.5 to 3.0 micrometers, 4.0 to 6.0 micrometers, and 8.0 to 9.5 micrometers, or it may be other values ​​in the range of 1.5 to 10 micrometers. The embodiments of this disclosure do not limit this.

[0087] This design can reduce the impact of process fluctuations on the limited opening, reduce the risk of the first main body being exposed, and help to reserve sufficient space for the limited opening, thereby helping to enhance the transmittance of the display panel.

[0088] For example, as shown in Figure 7, the first metal pattern 310 is an integral mesh structure, which can simplify the manufacturing process of the first metal pattern 310 and improve the signal uniformity in the first metal pattern 310, thereby reducing the load on the first metal pattern 310.

[0089] For example, as shown in FIG7, the orthographic projection of the light-emitting area 101 of each of the plurality of sub-pixels 10 onto the substrate falls into the orthographic projection of the first main body portion 311 onto the substrate. For example, the plurality of sub-pixels 10 may be all the sub-pixels 10 in the display panel.

[0090] This configuration can improve the flatness of the first electrode of the sub-pixels in the display panel as a whole, making the light emission angle of multiple sub-pixels in the display panel more uniform, which helps to ensure good light emission effect.

[0091] Figure 10 is a schematic diagram of another first metal pattern provided in at least one embodiment of the present disclosure.

[0092] For example, the difference between the first metal pattern shown in Figure 10 and the first metal pattern shown in Figure 7 is that the way the connecting part is set is different, while the rest of the structure is the same. The similarities will not be described again.

[0093] For example, as shown in FIG10, the connecting portion 305 extends along a first arrangement direction M or a second arrangement direction N. The first main body portion 311 connects to adjacent first main body portions 311 in the first arrangement direction M or the second arrangement direction N. For example, two adjacent rows of first main body portions 311 in the second arrangement direction N are staggered, and two adjacent columns of first main body portions 311 in the first arrangement direction M are staggered. For example, one first main body portion 311 can be connected to at most two other first main body portions 311. For example, the connecting portion 305 extending along the first arrangement direction M intersects with another connecting portion 305 extending along the second arrangement direction N.

[0094] This arrangement helps to increase the density of the connecting parts, thereby reducing the load on the first metal pattern.

[0095] In some embodiments, to further reduce the load on the first metal pattern, the number of connecting portions can be increased. For example, connecting portions can be provided between adjacent first main body portions in a first main body portion row, and between adjacent first main body portions in a first main body portion column. The embodiments of this disclosure do not limit the manner or number of connecting portions. For example, the extension direction of the connecting portion can be non-linear; for instance, it may not extend along the first arrangement direction, the second arrangement direction, the first direction, or the second direction. The embodiments of this disclosure do not limit the extension direction of the connecting portion.

[0096] Figure 11 is a schematic diagram of another layering of a first metal pattern and a second metal pattern provided in at least one embodiment of the present disclosure; Figure 12 is a schematic diagram of another layering of a first metal pattern and a second metal pattern provided in at least one embodiment of the present disclosure.

[0097] For example, as shown in Figures 10 and 11, the first group of sub-pixels 1100 includes green sub-pixels G, and the second group of sub-pixels 1200 includes red sub-pixels R and blue sub-pixels B. Two connecting portions 305 are provided between two adjacent green sub-pixels G in the second arrangement direction N, and these two connecting portions 305 are intersecting each other. For example, the pixel defining pattern includes a plurality of defining openings NS, and the defining openings NS are located between adjacent green sub-pixels G in the first arrangement direction M.

[0098] This configuration allows the first electrode of the first group of sub-pixels to have good flatness while increasing the width of the connection portion (i.e., the dimension in the direction perpendicular to the extension direction of the connection portion), thereby reducing the resistance of the first metal pattern.

[0099] For example, as shown in Figures 10 and 12, the first group of sub-pixels 1100 includes a red sub-pixel R and a blue sub-pixel B, and the second group of sub-pixels 1200 includes a green sub-pixel G. Two connecting portions 305 are provided between two adjacent second main body portions 321 in the first arrangement direction M, and these two connecting portions 305 are intersecting each other. For example, the pixel defining pattern includes a plurality of defining openings NS, and in the second arrangement direction N, there is one defining opening NS between adjacent sub-pixels in the second group of sub-pixels 1200.

[0100] This configuration allows the first electrode of the second group of sub-pixels to have good flatness, while also increasing the width of the connection (i.e., the dimension in the direction perpendicular to the extension direction), thereby reducing the resistance of the first metal pattern.

[0101] Figure 13 is a partial plan view of a display panel provided in at least one embodiment of the present disclosure; Figure 14 is another partial plan view of a display panel provided in at least one embodiment of the present disclosure.

[0102] For example, as shown in FIG13, the second metal pattern 320 includes a data line DATA and a power signal line VDD. The structure of the first metal pattern 310 is shown in FIG7, where the orthographic projection of the light-emitting area 010 of the sub-pixel onto the substrate falls entirely within the orthographic projection of the first main body portion 311 onto the substrate. For example, at least 50% of the orthographic projection of the connecting portion 305 onto the substrate falls within the orthographic projection of the second metal pattern 320 onto the substrate. For example, at least a portion of the orthographic projection of the connecting portion 305 onto the substrate falls entirely within the orthographic projection of the second metal pattern 320 onto the substrate. For example, at least 70% of the orthographic projection of the first main body portion 311 onto the substrate falls within the orthographic projection of the second metal pattern 320 onto the substrate. For example, at least a portion of the orthographic projection of the first main body portion 311 onto the substrate falls entirely within the orthographic projection of the second metal pattern 320 onto the substrate. For example, the orthographic projection area of ​​the first main body portion 311 onto the substrate is smaller than the orthographic projection area of ​​the second main body portion 321 onto the substrate.

[0103] This configuration improves the flatness of the first electrode of the sub-pixel by using the first metal pattern, while also reducing the layout space occupied by the first metal pattern, thus making the layout distribution more reasonable.

[0104] For example, as shown in Figure 14, the second metal pattern 320 includes multiple metal structures, such as a data line DATA, a power signal line VDD, and a connecting block BLO located on the side of the light-emitting area 010 of the sub-pixel closer to the first metal pattern 310. The metal structures in the second metal pattern 320 are asymmetrically distributed relative to the light-emitting area 010 of the sub-pixel. The first metal pattern 310 is located between the second metal pattern 320 and the first electrode of the sub-pixel (see Figure 6), and the orthographic projection of the light-emitting area 010 of the sub-pixel on the substrate completely falls within the orthographic projection of the first main body 311 on the substrate. This allows the first electrode of the sub-pixel to have good flatness and effectively reduces the risk of color shift and color separation.

[0105] Figure 15 is a partial cross-sectional schematic diagram of another display panel provided in at least one embodiment of the present disclosure.

[0106] For example, as shown in FIG15, the display panel includes a first metal pattern 310, a second metal pattern 320, and a third metal pattern 330. The third metal pattern 330 is located between the second metal pattern 320 and the substrate 100. For the structure of the first metal pattern 310 and the second metal pattern 320, please refer to the relevant description in the above embodiments, which will not be repeated here. For example, the first electrode 110 of the sub-pixel 10 is connected to the first main body portion 311 in the first metal pattern 310 through a first via N01, and the first main body portion 311 in the first metal pattern 310 is connected to the second main body portion 321 in the second metal pattern 320 through a second via N02.

[0107] For example, as shown in FIG15, the display panel includes a pixel driving circuit 400, at least a portion of which is located between the first electrode 110 and the substrate 100, and is configured to drive the light-emitting functional layer 130 of the sub-pixel 10 to emit light. For example, the pixel driving circuit 400 includes a thin-film transistor, and the third metal pattern 330 includes a conductive structure 331 and a conductive structure 332. For example, the conductive structure 331 serves as the drain of the thin-film transistor, the conductive structure 332 serves as the source of the thin-film transistor, the gate of the thin-film transistor is located on the side of the third metal pattern 330 closest to the substrate 100, and the semiconductor structure POLE of the thin-film transistor is located between the gate and the substrate 100. For example, the second main body portion 321 in the second metal pattern 320 is connected to the conductive structure 331 through a third via NO3. For example, the display panel also includes a first gate insulating layer S1 and a second gate insulating layer S2 located between the third metal pattern 330 and the substrate 100, but is not limited thereto. For example, the display panel may also include other film layers not shown in FIG15, which are not limited by the embodiments of this disclosure.

[0108] For example, as shown in FIG15, the display panel further includes a light-shielding layer 500. The light-shielding layer 500 is located on the side of the second electrode 120 away from the substrate 100, and the light-shielding layer 500 includes a plurality of first openings 510 and a plurality of second openings 520. The pixel defining pattern 200 includes a plurality of defining openings NS, which are spaced apart from the pixel openings 201. For example, the orthographic projection of the first opening 510 on the substrate 100 at least partially overlaps with the orthographic projection of the pixel opening 201 on the substrate 100, the orthographic projection of the defining openings NS on the substrate 100 at least partially overlaps with the orthographic projection of the second openings 520 on the substrate 100, and there is a gap between the orthographic projection of the defining openings NS on the substrate 100 and at least a portion of the orthographic projection of the pixel driving circuit 400 on the substrate 100.

[0109] For example, as shown in FIG15, a sensor may be provided on the non-display side of the display panel (i.e., the side of the substrate 100 away from the pixel driving circuit 400), such as an ambient light sensor, an infrared distance sensor, or a fingerprint sensor. Since the transmittance of the light-shielding layer 500 is almost zero, ambient light (such as visible light or infrared light) can enter from the second opening 520 of the light-shielding layer 500 and then reach the sensor through the defined opening NS, so that the sensor can work normally.

[0110] For example, as shown in FIG15, the display panel further includes a color filter layer 600 located on the side of the light-shielding layer 500 away from the substrate 100. The color filter layer 600 includes a plurality of color filter portions 610, and the orthographic projection of the light-emitting area 101 of the sub-pixel 10 onto the substrate 100 falls into the orthographic projection of the color filter portion 610 onto the substrate 100. For example, the color of the color filter portion 610 is the same as the light-emitting color of the corresponding sub-pixel 10. For example, the color filter portion 610 can enhance the color intensity of light. For example, the display panel may also include a cover plate or other structures located on the light-emitting side of the display panel, which is not limited in the embodiments of this disclosure.

[0111] For example, as shown in FIG15, the orthographic projection of the opening NS on the substrate 100 does not overlap with the orthographic projection of the color filter portion 610 on the substrate 100, which helps to reduce the blocking of ambient light incident by the color filter portion 610 and thus enhance the transmittance of the display panel.

[0112] Figure 16 is a schematic diagram of a pixel circuit provided in at least one embodiment of the present disclosure.

[0113] For example, as shown in Figure 16, the pixel driving circuit 400 includes a first reset control transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset control transistor T7, and a storage capacitor C.

[0114] For example, the display panel also includes a reset power signal line, a scan signal line, a power signal line, a reset control signal line, an illumination control signal line, and a data line.

[0115] For example, as shown in Figure 16, the first terminal of the threshold compensation transistor T2 is electrically connected to the first terminal of the driving transistor T3, the second terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal; the first terminal of the data writing transistor T4 is electrically connected to the second terminal of the driving transistor T3, the second terminal of the data writing transistor T4 is electrically connected to the data line to receive the data signal Data, and the gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first terminal of the storage capacitor C is electrically connected to the power supply signal line, and the second terminal of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the first terminal of the first reset control transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit1, the second terminal of the first reset control transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the first reset control transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset(N); The first terminal of the second reset control transistor T7 is electrically connected to the reset power supply signal line to receive the reset signal Vinit2. The second terminal of the second reset control transistor T7 is electrically connected to the first electrode of the light-emitting element 100 (i.e., node N4). The gate of the second reset control transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1). The first terminal of the first light-emitting control transistor T5 is electrically connected to the power supply signal line to receive the power supply signal VDD. The second terminal of the first light-emitting control transistor T5 is electrically connected to the second terminal of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The first terminal of the second light-emitting control transistor T6 is electrically connected to the first terminal of the driving transistor T3. The second terminal of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 100. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The second electrode of the light-emitting element 100 is connected to the voltage terminal VSS. The aforementioned power supply signal line refers to the signal line for the output voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0116] For example, as shown in Figure 16, the scan signal and the compensation control signal can be the same. That is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can also be electrically connected to different signal lines. That is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thereby allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, increasing the flexibility of controlling the pixel driving circuit 200.

[0117] For example, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can receive the same light-emitting control signal. That is, the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 can be electrically connected to different light-emitting control signal lines, and the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0118] For example, the reset control signals input to the first reset control transistor T1 and the second reset control transistor T7 can be the same. That is, the gates of the first reset control transistor T1 and the second reset control transistor T7 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first reset control transistor T1 and the second reset control transistor T7 can be electrically connected to different reset control signal lines. In this case, the signals on the different reset control signal lines can be the same or different.

[0119] For example, as shown in Figure 16, when the display panel is working, in the first stage of screen display, the first reset control transistor T1 is turned on to initialize the voltage of node N1; in the second stage of screen display, data is stored in node N1 through data writing transistor T4, driving transistor T3 and threshold compensation transistor T2; in the third stage of light emission, the first light emission control transistor T5, driving transistor T3 and the second light emission control transistor T6 are all turned on, and the light emission element 100 is forward-biased to emit light.

[0120] It should be noted that, in the embodiments of this disclosure, each pixel driving circuit can be a 7T1C (i.e., seven transistors and one capacitor) structure as shown in FIG16, or it can be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure. This disclosure does not limit this. The equivalent diagram of the pixel driving circuit in the display panel shown in the above embodiments can be the same as the equivalent diagram of the pixel driving circuit 400 shown in FIG16.

[0121] At least one embodiment of this disclosure also provides a display device, which includes a display panel provided in the embodiments of this disclosure (e.g., the display panel described in the above embodiments). Therefore, the technical effects of the aforementioned display panel can also be reflected in this display device, and will not be repeated here.

[0122] For example, the display device can be an organic light-emitting diode display device or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator that includes the display device. This embodiment is not limited to this.

[0123] The following points need to be explained:

[0124] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0125] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0126] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display panel, comprising: Substrate; Multiple sub-pixels are located on the substrate. Each sub-pixel includes a light-emitting functional layer and a first electrode and a second electrode located on both sides of the light-emitting functional layer along a direction perpendicular to the substrate. The first electrode is located between at least a portion of the light-emitting functional layer and the substrate. A pixel-defined pattern, at least a portion of which is located between the light-emitting functional layer and the first electrode, the pixel-defined pattern including a plurality of pixel openings and pixel defining portions located between adjacent pixel openings, the pixel openings exposing at least a portion of the first electrode to define the light-emitting area of ​​the sub-pixel; A first metal pattern is located between the first electrode of the sub-pixel and the substrate. A second metal pattern is located between the first metal pattern and the substrate, and in a direction perpendicular to the substrate, at least a portion of the light-emitting area of ​​the sub-pixel overlaps with the second metal pattern. The first metal pattern includes a plurality of first main bodies, at least some of which are connected to each other. In a direction perpendicular to the substrate, the orthographic projection of the light-emitting area of ​​at least one sub-pixel on the substrate falls into the orthographic projection of the first main body on the substrate.

2. The display panel according to claim 1, wherein, The second metal pattern includes a plurality of second main body portions, at least some of which are connected to each other, and the at least some sub-pixels include first sub-pixels and second sub-pixels. In a direction perpendicular to the substrate, the orthographic projection of the light-emitting area of ​​each sub-pixel in the first portion of sub-pixels onto the substrate falls into the orthographic projection of the second main body onto the substrate, and the light-emitting area of ​​each sub-pixel in the second portion of sub-pixels does not overlap with the second main body.

3. The display panel according to claim 1 or 2, wherein, The orthographic projection of the light-emitting area of ​​each sub-pixel in the second part onto the substrate falls into the orthographic projection of the first main body onto the substrate.

4. The display panel according to any one of claims 1-3, wherein, The orthographic projection of the light-emitting area of ​​each sub-pixel in the first portion of the sub-pixels onto the substrate falls into the orthographic projection of the first main body onto the substrate.

5. The display panel according to claim 2, wherein, The plurality of sub-pixels includes a first group of sub-pixels and a second group of sub-pixels, both of which include at least one color sub-pixel. The light-emitting area of ​​each sub-pixel in the first group of sub-pixels overlaps with both the first main body and the second main body, and the light-emitting area of ​​each sub-pixel in the second group of sub-pixels overlaps with either the first main body or the second main body.

6. The display panel according to claim 5, wherein, The first group of sub-pixels includes red sub-pixels and blue sub-pixels, and the second group of sub-pixels includes green sub-pixels; or The first group of sub-pixels includes green sub-pixels, and the second group of sub-pixels includes red sub-pixels and blue sub-pixels.

7. The display panel according to any one of claims 1-6, wherein, The first metal pattern further includes multiple connecting portions. The first main body portion is connected to another first main body portion through the connecting portions. The orthographic projection of the connecting portion on the substrate is strip-shaped, and the orthographic projection of the connecting portion on the substrate does not overlap with the light-emitting area of ​​the sub-pixel.

8. The display panel according to claim 7, wherein, The plurality of first main body portions are arranged in an array along a first direction and a second direction to form a plurality of rows of first main body portions arranged along the first direction and a plurality of columns of first main body portions arranged along the second direction. Both the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction.

9. The display panel according to claim 8, wherein, The connecting portion extends along the first direction or the second direction, and adjacent first main body portions in the first main body portion row are connected by the connecting portion, and adjacent first main body portions in the first main body portion column are connected by the connecting portion.

10. The display panel according to claim 8, wherein, The connecting portion extends along a first arrangement direction or a second arrangement direction, and the first main body portion is connected to the adjacent first main body portion in the first arrangement direction or the second arrangement direction. Both the first and second arrangement directions are parallel to the substrate, and the first and second arrangement directions intersect. All directions intersect the first direction and also intersect the second direction.

11. The display panel according to any one of claims 1-10, wherein, The first metal pattern is an integral mesh structure.

12. The display panel according to any one of claims 1-11, wherein, The orthographic projection shape of the first main body on the substrate is different from the orthographic projection shape of the second main body on the substrate.

13. The display panel according to any one of claims 1-12, wherein, The orthographic projection shape of the light-emitting area of ​​the at least one sub-pixel on the substrate is the same as the orthographic projection shape of the first main body on the substrate.

14. The display panel according to any one of claims 1-13, wherein, The orthographic projection of the light-emitting area of ​​each of the plurality of sub-pixels on the substrate falls into the orthographic projection of the first main body portion on the substrate.

15. The display panel according to any one of claims 1-14, wherein, The first metal pattern is configured to transmit a first signal, and the second metal pattern is configured to transmit a second signal, wherein the first signal and the second signal are different.

16. The display panel according to claim 10, wherein, The second metal pattern includes multiple signal lines that overlap with the first main body, and the signal lines extend along the second arrangement direction, and the surface of the first main body away from the substrate is flat.

17. The display panel according to any one of claims 1-16, further comprising: A light-shielding layer is located on the side of the second electrode away from the substrate. The light-shielding layer includes a plurality of first openings and a plurality of second openings. The orthographic projection of the first openings on the substrate at least partially overlaps with the orthographic projection of the pixel openings on the substrate. A color filter layer is located on the side of the light-shielding layer away from the substrate. The color filter layer includes a plurality of color filter portions. The orthographic projection of the light-emitting area of ​​the sub-pixel on the substrate falls into the orthographic projection of the color filter portion on the substrate. The sub-pixel further includes a pixel driving circuit, at least a portion of which is located between the first electrode and the substrate, and is configured to drive the light-emitting functional layer of the sub-pixel to emit light. The pixel-defined pattern further includes a plurality of defining openings, which are spaced apart from the pixel openings. The orthographic projection of the defining openings on the substrate is parallel to that of the second opening on the substrate. The orthographic projections on the substrate at least partially overlap, and there is a gap between the orthographic projection of the defining opening on the substrate and the orthographic projection of at least a portion of the pixel driving circuit on the substrate, and the orthographic projection of the defining opening on the substrate does not overlap with the orthographic projection of the color filter portion on the substrate.

18. The display panel according to claim 17, wherein, The minimum distance between the orthographic projection of the defined opening on the substrate and the orthographic projection of the first main body on the substrate is 1.5 to 10 micrometers.

19. A display device comprising the display panel according to any one of claims 1-18.

Images