Chip package and manufacturing method therefor, and electronic device
By employing a stepped isolation trench design in the chip package, combined with etching and mechanical cutting processes, the problems of low cutting efficiency and low utilization rate of chips with a thickness exceeding 200μm are solved, achieving high-efficiency chip packaging.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2025-06-10
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies for 3D stacked packaging, the cutting efficiency of chips with a thickness exceeding 200μm is low, and mechanical cutting results in large cutting gaps, which reduces chip utilization.
The chip employs a stepped isolation trench design, with a narrow isolation trench on the front side to reduce area loss and a wide isolation trench on the back side for mechanical cutting. This combination of etching and mechanical cutting processes improves processing efficiency and chip utilization.
This reduces the cutting gaps on the front of the chip, improves the effective utilization rate of the chip, and reduces processing costs and difficulty.
Smart Images
Figure CN2025100203_15052026_PF_FP_ABST
Abstract
Description
Chip package, its fabrication method and electronic device
[0001] Cross-reference to related applications
[0002] This application claims priority to Chinese Patent Application No. 202411579754.7, filed on November 6, 2024, entitled "Chip Package and Method of Fabrication Thereof and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This application relates to the field of chip packaging, specifically to a chip package, its manufacturing method, and an electronic device. Background Technology
[0004] As chip manufacturing processes approach the limits of physical dimensions, three-dimensional (3D) stacked packaging technology has become a crucial approach to improving chip integration and performance. With the interconnect pin pitch in 3D stacked packaging shrinking to below 10 micrometers, conventional micro-bump (uBump) processes are no longer sufficient. Hybrid bonding (HB) technology, using smaller planar copper pads, is gradually becoming a key technology in 3D stacked packaging and architecture design. Chip dicing is particularly important in HB processes. HB typically uses plasma etching for chip dicing to achieve better edge quality. However, plasma etching is inefficient; for chips thicker than 200μm, the process time can exceed one hour, leading to high costs. Therefore, for chips thicker than 200μm, mechanical dicing is often used. However, mechanical dicing, such as wheel cutting, suffers from large kerfs and poor edge quality. Given the limited minimum cutting width, mechanical dicing usually reduces the effective area of the chip's front side, lowering chip utilization. Summary of the Invention
[0005] This application provides a chip package, a method for manufacturing the same, and an electronic device, to reduce the cutting gaps on the front side of the chip and improve the effective utilization rate of the chip.
[0006] In a first aspect, this application provides a chip package comprising a first chip layer and a second chip layer, wherein the first chip layer is stacked on one side of the second chip layer and connected to the second chip layer via an intermediate pad layer, the thickness of the first chip layer is greater than or equal to 200 μm, and the thickness of the second chip layer is less than 200 μm; the first chip layer comprises at least two spaced-apart chips along its layer direction, and an isolation trench is provided between two adjacent chips in the first chip layer; the isolation trench penetrates the first chip layer and the intermediate pad layer in the thickness direction of the first chip layer;
[0007] The isolation trench includes a first trench and a second trench in the thickness direction of the first chip layer. The first trench is disposed close to the second chip layer, and the second trench is disposed away from the second chip layer. Along the arrangement direction of two adjacent chips, the width of the first trench is smaller than the width of the second trench.
[0008] The chip packaging component of this application may include multiple stacked chip layers, such as a first chip layer and a second chip layer. The first chip layer is a thick chip layer with a thickness greater than or equal to 200 μm, and the second chip layer is a thin chip layer with a thickness less than 200 μm. The first chip layer may include multiple spaced-apart chips, with the isolation trenches between the chips having a stepped structure. The width of the trenches is smaller at the end near the second chip layer and larger at the end away from the second chip layer. The end of the first chip layer near the second chip layer is the front side of the chip, containing the functional layer. The smaller size of the isolation trenches in this area reduces cutting gaps and increases the effective area of the chip. The end of the first chip layer away from the second chip layer is a non-functional area. The larger width of the second trenches in this area facilitates processing and improves processing efficiency.
[0009] In one alternative implementation, the isolation trench is filled with an organic insulating material. Filling with this organic insulating material achieves a seal on the chip sides and improves the insulation between chips.
[0010] In one alternative implementation, a molding compound is provided at the edge of the first chip layer. By providing the molding compound to seal the edge of the first chip layer, the first chip layer is protected from moisture erosion.
[0011] In one alternative implementation, the molding compound has a ring-shaped structure along the layer direction of the first chip layer to provide better sealing protection around the first chip layer.
[0012] In one alternative implementation, the molding compound has a stepped structure along the thickness direction of the first chip layer, with the thickness of the end of the molding compound near the second chip layer being less than the thickness of the end of the molding compound away from the second chip layer. The smaller size at the end near the second chip layer reduces filler requirements and increases the utilization rate of the front side of the first chip layer. The larger size at the end away from the second chip layer provides better sealing and protection for the first chip layer.
[0013] In one alternative implementation, the second chip layer is at least one layer, and each second chip layer includes at least one chip.
[0014] Secondly, this application provides a method for manufacturing a chip package, the method comprising:
[0015] The first groove is formed by etching on the front side of the first wafer; an intermediate pad layer is provided on the front side of the first wafer, and the first groove penetrates the intermediate pad layer along the thickness direction of the first wafer and etches part of the first wafer.
[0016] The intermediate pad layer is bonded to the auxiliary support component. The back side of the first wafer is mechanically cut to form a second groove, and the second groove is made to connect with the first groove to form an isolation groove. The width of the first groove is smaller than the width of the second groove. The first wafer is divided into a first chip layer containing at least two chips by the isolation groove. The thickness of the first chip layer is greater than or equal to 200 μm.
[0017] Separate the auxiliary support component, attach the first chip layer to the surface of the second wafer, and thin the side of the second wafer away from the first chip layer to form the second chip layer; wherein, the thickness of the second chip layer is less than 200μm, and the surface of the first chip layer with the intermediate pad layer is bonded to the second wafer.
[0018] In the fabrication method of this application, when processing a relatively thick first wafer, a first groove can be etched on the front side of the first wafer using an etching method. The first groove formed by etching has a small width, which allows the front side of the first wafer to retain a large effective area with a smaller etching width. A second groove is formed on the back side of the first wafer using a mechanical cutting method, which can improve processing efficiency and reduce processing costs. After mechanical cutting, the second groove and the first groove are connected to achieve isolation between multiple chips in the second chip layer. After the first chip layer is processed, it is then bonded to the second chip layer to complete the packaging of multiple chips.
[0019] In one alternative implementation, after forming the isolation trench and before mounting the first chip layer onto the surface of the second wafer, the method for fabricating the chip package further includes: filling the isolation trench with an organic insulating material and molding the edges of the first chip layer. Molding allows the organic insulating material to be injected into the isolation trench, achieving both sealing protection of the chip and insulation between adjacent chips.
[0020] In one alternative implementation, after forming the second chip layer, the chip package fabrication method further includes: fabricating a wiring layer and a bottom pad layer on the back side of the second chip layer. The wiring layer and bottom pad layer enable connection to the PCB board.
[0021] Thirdly, this application provides an electronic device that includes the chip package of this application.
[0022] The electronic devices mentioned in this application may include servers, cloud computing devices, artificial intelligence devices, etc.
[0023] The technical effects that can be achieved by the second and third aspects mentioned above can be referred to the corresponding effect descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description
[0024] Figure 1 is a schematic diagram of the structure of a chip package according to an embodiment;
[0025] Figure 2 is a schematic diagram of the arrangement structure of the first chip layer according to an embodiment of this application;
[0026] Figure 3 is a schematic diagram of the arrangement structure of the first chip layer according to another embodiment of this application;
[0027] Figure 4 is a schematic diagram of the structure of a chip package according to another embodiment of this application;
[0028] Figure 5 is a schematic diagram of the structure of a chip package according to an embodiment of this application;
[0029] Figure 6 is a schematic diagram of the structure of a chip package according to another embodiment of this application;
[0030] Figure 7 is a schematic diagram of the structure of a chip package according to another embodiment of this application;
[0031] Figure 8 is a schematic diagram of the structure of a chip package according to another embodiment of this application;
[0032] Figure 9 is a schematic diagram of the structure of a chip package according to an embodiment of this application;
[0033] Figure 10 is a schematic diagram of the structure of a chip package according to another embodiment of this application;
[0034] Figure 11 is a schematic diagram of the structure of a chip package according to another embodiment of this application;
[0035] Figure 12 is a schematic diagram of the manufacturing process of a chip package according to one embodiment.
[0036] Reference numerals: 01-Device functional layer; 02-Substrate layer; 03-First wiring layer; 04-First through-silicon via; 10-First chip layer; 11-Chip; 111-I / O chip; 112-Computing chip; 12-Isolation trench; 121-First trench body; 122-Second trench body; 13-Molding component; 13a-Molding trench; 131-First protective trench; 132-Second protective trench; 14-Intermediate pad layer; 20-Second chip layer; 21-Bottom pad layer; 31-Adapter board; 32-Bridge circuit board; 321-Bridge chip; 33-PCB; 41-First wafer; 42-Second wafer; 43-Auxiliary support component; 44-Second wiring layer; 45-Isolation layer; 46-Second through-silicon via; 47-Transfer film; 50-Package shell; 51-Heat dissipation structure. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.
[0038] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise.
[0039] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0040] In HB (Helicopter Helicopter) processes, chip dicing methods can be categorized into four types: 1) rotary cutting; 2) laser cutting; 3) plasma cutting; and 4) various combinations of the above three methods. These cutting techniques typically face challenges such as thermomechanical damage, electrostatic discharge (ESD) of the chip, and low cutting efficiency. For conventional chip dicing with a thickness less than 100μm, plasma cutting is usually employed, and a dummy wafer is typically added as a support after chip-to-wafer (C2W) to ensure the strength requirements of the chip package. For chips with a thickness exceeding 200μm, plasma cutting is technically challenging and costly. Mechanical cutting, on the other hand, can increase the width of the dicing groove, reducing the effective area of the chip.
[0041] To address the aforementioned problems, this application provides a chip package. In this chip package, for chip layers with a thickness exceeding 200 micrometers, the isolation trenches formed by cutting are stepped. On the front side of the chip, the width of the isolation trenches is smaller, which reduces area loss on the front side of the chip and improves the utilization rate of the front side. On the back side of the chip, the width of the isolation trenches is larger, which can be formed by mechanical cutting, improving processing efficiency and reducing processing difficulty.
[0042] Figure 1 is a schematic diagram of a chip package according to an embodiment. As shown in Figure 1, the chip package includes a first chip layer 10 and a second chip layer 20. The first chip layer 10 is a thick chip layer with a thickness greater than or equal to 200 μm. The second chip layer 20 is a thin chip layer with a thickness less than 200 μm.
[0043] The first chip layer 10 can be a single layer. The first chip layer 10 can be disposed on one side of the second chip layer 20. Since the first chip layer 10 is relatively thick, it can be the top layer of the chip package, meaning that no other chip layers are disposed on top of the first chip layer 10, in order to ensure the structural stability and connection reliability of the chip package.
[0044] The second chip layer 20 can be a single layer disposed at the bottom of the chip package for connection to a printed circuit board (PCB). The first chip layer 10 and the second chip layer 20 are stacked and connected by an intermediate pad layer 14. The intermediate pad layer 14 can, for example, be a micro-bump structure. The intermediate pad layer 14 between the first chip layer 10 and the second chip layer 20 can achieve both mechanical and electrical connections between them.
[0045] The first chip layer 10 may include at least two spaced-apart chips 11 along its layer direction. Each chip 11 in the first chip layer 10 has its front side facing the second chip layer 20. A device functional layer 01 is provided on the front side of each chip 11. The surface of the device functional layer 01 is connected to an intermediate pad layer 14. The back side of each chip 11 is a substrate layer 02, such as a Si layer. The device functional layer 01 is disposed on the surface of the substrate layer 02. Adjacent chips 11 are insulated from each other. To achieve insulation between adjacent chips 11, an isolation trench 12 may be provided between adjacent chips 11.
[0046] Figure 2 is a schematic diagram of the arrangement structure of the first chip layer according to an embodiment of this application. As shown in Figure 2, the first chip layer 10 may include a plurality of chips 11, such as five chips 11. The five chips 11 may include, for example, one I / O chip 111 and four computing chips 112. The I / O chip 111 is located in the middle of the first chip layer 10, and two computing chips 112 are respectively arranged on both sides of the I / O chip 111. An isolation slot 12 is provided between the two computing chips 112 on either side of the I / O chip 111. An isolation slot 12 is also provided between the I / O chip 111 and any computing chip 112.
[0047] Figure 3 is a schematic diagram of the arrangement structure of the first chip layer according to another embodiment of this application. As shown in Figure 3, the first chip layer 10 of this embodiment may include two I / O chips 111 and four computing chips 112. One I / O chip 111 and two computing chips 112 constitute a structural unit, and the structural units are spaced apart, such as by setting isolation slots 12. In one structural unit, the two computing chips 112 are disposed on one side of one I / O chip 111. In each structural unit, an isolation slot 12 is provided between the two computing chips 112 and the I / O chip 111, and an isolation slot 12 is also provided between the two computing chips 112.
[0048] Referring again to Figure 1, the isolation trench 12 between adjacent chips 11 in the first chip layer 10 extends through the first chip layer 10 and the intermediate pad layer 14 along the thickness direction of the first chip layer 10, as shown in Figure 1 along the z-direction. Along the thickness direction of the first chip layer 10, the isolation trench 12 has a stepped structure. Along the z-direction, the isolation trench 12 includes a first trench body 121 and a second trench body 122. The first trench body 121 is disposed close to the second chip layer 20, and the second trench body 122 is disposed away from the second chip layer 20. Exemplarily, the first trench body 121 can penetrate the device functional layer 01 of each chip 11 in the first chip layer 10 and extend 3-30 μm, or 3-20 μm, or 3-10 μm, towards the base layer of each chip 11 in the second chip layer 20. The second trench body 122 extends from the back side of the chip 11 to the front side of the chip 11 and communicates with the first trench body 121. Along the arrangement direction of adjacent chips 11, as shown in the x-direction of Figure 1, the width of the first slot 121 is smaller than the width of the second slot 122. The width of the first slot 121 is the spacing between adjacent chips 11 at their corresponding positions in the first slot 121, and the width of the second slot 122 is the spacing between adjacent chips 11 at their respective positions in the second slot 122.
[0049] In the first chip layer 10, the front sides of each chip 11 are separated by a narrow first groove 121, which reduces the area occupied by the isolation groove 12 and increases the effective utilization area of the first chip layer 10. The second groove 122 is wider and can be mechanically cut, which facilitates processing, reduces processing difficulty, and improves processing efficiency. As shown in Figure 1, the isolation groove 12 is filled with organic insulating material. Filling with organic insulating material can seal the sides of the chip 11 and improve the insulation between the chips 11.
[0050] Referring to Figures 1 to 3, in one embodiment, a molding compound 13 is provided at the edge of the first chip layer 10. Along the surface direction of the first chip layer 10, the molding compound 13 may be annular. Along the thickness direction of the first chip layer 10, the molding compound 13 may also be stepped. Along the arrangement direction of adjacent chips 11, the thickness of the end of the molding compound 13 near the second chip layer 20 is less than the thickness of the end of the molding compound 13 away from the second chip layer 20. By providing the molding compound 13 to seal the edge of the first chip layer 10, the first chip layer 10 is protected from moisture erosion. The smaller size at the end near the second chip layer 20 reduces filler requirements and increases the utilization rate of the front side of the first chip layer 10. The larger size at the end away from the second chip layer 20 provides better sealing protection for the first chip layer 10.
[0051] In the chip package structure shown in Figure 1, the second chip layer 20 has one layer. Besides having only one layer, the second chip layer 20 can also have two or more layers.
[0052] Figure 4 is a schematic diagram of a chip package according to another embodiment of this application. As shown in Figure 4, in this embodiment, the second chip layer 20 has two layers. The two second chip layers 20 are stacked along the z-direction. The first chip layer 10 is located at the top and is connected to the second chip layer 20 below it through an intermediate pad layer 14. In the chip packages shown in Figures 1 and 4, the second chip layer 20 includes a single, integral chip 11. In addition, the second chip layer 20 may also include multiple spaced-apart chips.
[0053] Figure 5 is a schematic diagram of the structure of a chip package according to an embodiment of this application. As shown in Figure 5, the second chip layer 20 is still two layers. The difference from Figure 4 is that, in the structure shown in Figure 5, the middle second chip layer 20 includes at least two spaced-apart chips 11. Similar to the chip 11 arrangement structure in the first chip layer 10, when the second chip layer 20 contains multiple chips 11, the multiple chips 11 in the second chip layer 20 can also be spaced apart by isolation trenches 12. The trench walls of the isolation trenches 12 in the second chip layer 20 are straight walls in the thickness direction of the second chip layer 20, and there are no stepped surfaces. That is, in the thickness direction of the second chip layer 20, the width of the isolation trenches 12 penetrating the second chip layer 20 remains consistent in that direction.
[0054] Figure 6 is a schematic diagram of the structure of a chip package according to another embodiment of this application. As shown in Figure 6, the second chip layer 20 may have multiple layers, such as three or more. When the second chip layer 20 has multiple layers, some second chip layers 20 may contain only one chip 11, while other second chip layers 20 may contain at least two chips 11. It is understood that the number of layers of the second chip layer 20 can be designed according to the actual function of the chip 11, and no specific limitation is made here.
[0055] Figure 7 is a schematic diagram of the structure of a chip package according to another embodiment of this application. As shown in Figure 7, the second chip layer 20 may include at least two chips 11. The two chips 11 may be spaced apart. Each chip 11 in the second chip layer 20 may be a pre-fabricated chip 11, and during chip 11 packaging, the chip 11 can be directly mounted. Therefore, the gap between each chip 11 in the second chip layer 20 may be a gap reserved during the mounting process. After mounting is completed, an insulating material may be provided in the gap between the two and a first through-silicon via 04 may be formed. The first through-silicon via 04 may serve as a transmission line between the upper and lower chip layers. In the structure shown in Figure 7, the front faces of each chip 11 in the first chip layer 10 are arranged downwards, that is, the device functional layer 01 of each chip 11 in the first chip layer 10 is arranged downwards. The front faces of each chip 11 in the second chip layer 20 are arranged upwards, that is, the device functional layer 01 of each chip 11 in the second chip layer 20 is arranged upwards. This structure is a face-to-face (F2F) packaging structure.
[0056] Figure 8 is a schematic diagram of the structure of a chip package according to another embodiment of this application. As shown in Figure 8, the chip package of this embodiment differs from the structure shown in Figure 7 in that the device functional layers 01 of each chip 11 in the second chip layer 20 are arranged downwards, forming a face-to-back (F2B) package structure.
[0057] Referring to Figures 1 to 8, in the chip package of this embodiment, the surface of the second chip layer 20 facing away from the first chip layer 10 is further provided with a second wiring layer 44 and a bottom pad layer 21 for connection with other components. The bottom pad layer 21 may, for example, be a microbump structure.
[0058] The chip package of this application embodiment may include, in addition to the first chip layer and the second chip layer, at least one of the following: an adapter board, a bridging circuit board and a PCB, as well as a package shell, a heat dissipation structure, etc.
[0059] Figure 9 is a schematic diagram of a chip package according to an embodiment of this application. As shown in Figure 9, in addition to the first chip layer 10 and the second chip layer 20, the chip package of this embodiment may also include an adapter board 31. The second chip layer 20 is connected to the adapter board 31 through a bottom pad layer 21, for example, it may be connected to the device functional layer 01 of the adapter board 31. As shown in Figure 9, the first chip layer 10 and the second chip layer 20 may be disposed on the surface of the adapter board 31. On both sides of the first chip layer 10 and the second chip layer 20, I / O chips and high bandwidth memory (HBM) chips may also be disposed respectively, and the I / O chips and chips are also connected to the adapter board 31 respectively. The bottom of the adapter board 31 is provided with a second wiring layer 44, and the bottom of the second wiring layer 44 may also be provided with pads for connection with the PCB, such as microbump structures. The microbump structures may be solder balls or solder dots. A molding compound 13 may be disposed between the I / O chip and the first chip layer 10 and the second chip layer 20 for isolation. A molding compound 13 can also be provided between the HBM chip and the first chip layer 10 and the second chip layer 20 for isolation. Additionally, a molding compound 13 can also be provided around the I / O chip and the HBM chip for sealing and protection.
[0060] In the structure shown in Figure 9, the first chip layer 10 and the second chip layer 20 achieve 3D stacked packaging in the z-direction, while the I / O chip and HBM chip achieve 2.5D arrangement packaging in the x-direction. Therefore, the chip package of this embodiment can realize a 3D+2.5D packaging architecture.
[0061] Figure 10 is a schematic diagram of the chip package structure according to another embodiment of this application. As shown in Figure 10, the chip package of this embodiment, in addition to including the first chip layer 10 and the second chip layer 20, may also include a bridging circuit board 32. I / O chips and HBM chips may also be respectively disposed on both sides of the first chip layer 10 and the second chip layer 20. The placement position of the bridging circuit board 32 is the same as that of the adapter board 31 in the structure shown in Figure 9. The bridging circuit board 32 may include a bridging chip 321. The bridging chip 321 is used to realize the signal connection between different chips. Similarly, a second wiring layer 44 is provided at the bottom of the bridging circuit board 32, and the bottom of the second wiring layer 44 may also be provided with pads for connection with the PCB, such as microbump structures. The microbump structure may be solder balls or solder dots. A molding compound 13 may be disposed between the I / O chip and the first chip layer 10 and the second chip layer 20 for isolation. A molding compound 13 may also be disposed between the HBM chip and the first chip layer 10 and the second chip layer 20 for isolation.
[0062] Figure 11 is a schematic diagram of a chip package according to another embodiment of this application. As shown in Figure 11, the chip package of this embodiment, in addition to including a first chip layer 10 and a second chip layer 20, may also include a PCB 33. The second chip layer 20 is connected to the PCB 33 through a bottom pad layer 21 disposed on its bottom surface.
[0063] In addition, as shown in Figure 11, the chip package also includes a package shell 50, which can be a shell with a high thermal conductivity, such as a metal shell. Using a metal shell as the package shell of the chip package can facilitate heat dissipation. A heat dissipation structure 51 can be provided on the top of the package shell 50, and the heat dissipation structure 51 can contain heat dissipation teeth to accelerate heat dissipation. The top of the first chip layer 10 can directly contact the package shell 50 or the heat dissipation structure 51 to improve heat dissipation efficiency.
[0064] It is understood that non-chip structures, such as sensors, antennas, capacitors, and inductors, can also be installed in the adapter boards, bridging circuit boards, and PCBs described above, and connected to other chips via wires and connectors. Furthermore, the number of chips in the above embodiments is merely illustrative, and this application does not impose a specific limit on the number of chips.
[0065] The structure of the chip package has been explained above. The manufacturing method of the chip package according to the embodiments of this application will be explained below with reference to the accompanying drawings.
[0066] The method for manufacturing a chip package according to an embodiment of this application includes the following steps:
[0067] Step S1: An etching process is performed on the front side of the first wafer to form a first trench. The first wafer includes a substrate layer and a device functional layer disposed on the surface of the substrate layer. The side containing the substrate layer is the back side of the first wafer, and the side containing the device functional layer is the front side of the first wafer. An intermediate pad layer is provided on the surface of the device functional layer, and the first trench penetrates both the intermediate pad layer and the device functional layer along the thickness direction of the first wafer.
[0068] Step S2: Bond the intermediate pad layer to the auxiliary support component, mechanically cut the back side of the first wafer to form a second groove, and make the second groove and the first groove connect to form an isolation groove. The width of the first groove is smaller than the width of the second groove. The first wafer is divided into a first chip layer containing at least two chips by the isolation groove. The thickness of the first chip layer is greater than or equal to 200μm.
[0069] Step S3: Separate the auxiliary support, attach the first chip layer to the surface of the second wafer, and thin the side of the second wafer away from the first chip layer to form the second chip layer; wherein, the thickness of the second chip layer is less than 200μm, and the surface of the first chip layer with the intermediate pad layer is bonded to the second wafer.
[0070] In step S3, after separating the auxiliary support and before attaching the first chip layer to the surface of the second wafer, the chip package fabrication method further includes: filling the isolation trench with organic insulating material and molding the edges of the first chip layer. Molding allows the organic insulating material to be injected into the isolation trench, achieving both sealing protection of the chip and insulation between adjacent chips.
[0071] Following step S3, i.e., after forming the second chip layer, the chip package fabrication method further includes: fabricating a wiring layer and a bottom pad layer on the back side of the second chip layer. The wiring layer and bottom pad layer enable connection to the PCB.
[0072] Figure 12 is a schematic diagram of the manufacturing process of a chip package according to an embodiment. As shown in Figure 12, as an exemplary illustration, the method for manufacturing a chip package according to an embodiment of this application includes the following steps:
[0073] Step S11: Wafer processing: As shown in Figure 12(a), the first wafer 41 includes a substrate layer 02 and a device functional layer 01 disposed on one side surface of the substrate layer 02.
[0074] Step S12: Layer addition: As shown in Figures (b) and (c) of Figure 12, the first wiring layer 03 and the intermediate pad layer 14 are sequentially fabricated on the front side of the first wafer 41 using the damascus process.
[0075] Step S13: Isolation layer deposition: As shown in Figure 12(d), Ti, TiN and SiO2 are deposited sequentially on the surface of the intermediate pad layer 14 using chemical vapor deposition (CVD) or physical deposition methods as a temporary bonding isolation layer 45.
[0076] Step S14: Front-side cutting: As shown in Figure (e) of Figure 12, a groove is cut on the front side of the first wafer 41 by plasma etching or laser etching to form a first groove 121, and the edge part of the first wafer is etched to form a first protective groove 131. The depth of the first groove 121 and the first protective groove 131 penetrates the isolation layer 45, the intermediate pad layer 14, the first wiring layer 03 and the device functional layer 01, and can exceed the device functional layer by 3-30μm.
[0077] Step S15: Temporary bonding: As shown in Figure 12(f), the auxiliary support 43 is attached to the front side of the first wafer 41 to form a temporary bonding structure. The auxiliary support 43 has a bonding layer 431 on its surface, which is bonded to the isolation layer 45 on the surface of the first wafer 41.
[0078] Step S16: Thinning: As shown in Figure (g) of Figure 12, the back side of the first wafer 41 is thinned, and the thickness of the first wafer 41 after thinning is greater than or equal to 200 μm.
[0079] Step S17: Backside Cutting: As shown in Figure 12(h), after thinning, a cutting wheel process is used to cut the back side of the first wafer 41 to form a second groove 122. The second groove 122 and the first groove 121 are connected to form an isolation groove 12. Furthermore, the outer peripheral edge of the first wafer 41 is cut to form a second protective groove 132. The second protective groove 132 and the first protective groove 131 are connected to form a molding groove 13a. The width of the second groove 122 is greater than the width of the first groove 121. After cutting, a wet cleaning process is used to surface treat the walls of the first groove 121 and the second groove 122 to ensure the cleanliness of the groove walls.
[0080] Step S18: Remove the isolation layer: As shown in Figure 12(i), the back side of the first wafer 41 is attached to the surface of the transfer film 47, the temporary bond is released, the auxiliary support is removed, and the isolation layer on the surface of the first wafer 41 is removed by a wet process.
[0081] Step S19: Mounting: As shown in Figure 12(j), the front side of the first wafer 41 is mounted onto the surface of the second wafer 42 using hybrid bonding (HB). The second wafer 42 has a second through-silicon via 46 inside, and its front side sequentially has a device functional layer 01, a first wiring layer 03, and an intermediate pad layer 14. The intermediate pad layer 14 on the surface of the second wafer 42 is connected to the intermediate pad layer 14 on the surface of the first wafer 41.
[0082] Step S20: Molding and First Wafer Thinning: As shown in Figures (k) and (l) of Figure 12, the first wafer 41 is molded with an organic insulating material. The organic insulating material fills the isolation trench 12 and the periphery of the first wafer 41, forming a molding compound 13 on the periphery of the first wafer 41. The back side of the first wafer 41 is thinned to remove excess molding material.
[0083] Step S21: Second wafer thinning: As shown in Figure (m) of Figure 12, the second wafer 42 is thinned to the second through-silicon via 46 provided inside it using methods such as backside grinding (BG) or chemical mechanical polishing (CMP).
[0084] Step S22: Fabrication of the second wiring layer and bottom pads: As shown in Figure (n) of Figure 12, a second wiring layer 44 is fabricated at the bottom of the second wafer 42. The second wiring layer 44 includes metal wires and dielectric material disposed between the metal wires. The dielectric material forming the second wiring layer 44 can be inorganic materials such as SiO2, SiN, SiCN, and GaN, or organic materials such as PI and BCB. As shown in Figure (o) of Figure 12, a bottom pad layer 21 is fabricated at the bottom of the second wiring layer 44, including microbumps and solder balls.
[0085] Step S23: Segmentation: When each wafer includes multiple packaging units as shown in Figure 12(o), the multiple packaging units can be separated by dicing. Dicing methods include, but are not limited to, wheel dicing, plasma dicing, laser dicing, stealth dicing, etc.
[0086] In the chip package fabrication method of this application embodiment, when processing a relatively thick first wafer, a first groove can be etched on the front side of the first wafer using an etching method. The first groove formed by etching has a small width, which allows the front side of the first wafer to retain a higher effective area and a smaller etching width. A second groove is formed on the back side of the first wafer using a mechanical cutting method, which can improve processing efficiency and reduce processing costs. After mechanical cutting, the second groove and the first groove are connected to achieve isolation between multiple chips in the second chip layer. After the first chip layer is processed, it is then bonded to the second chip layer to complete the packaging of multiple chips.
[0087] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A chip package, characterized in that, It includes a first chip layer and a second chip layer. The first chip layer is stacked on one side of the second chip layer and connected to the second chip layer through an intermediate pad layer. The thickness of the first chip layer is greater than or equal to 200 μm, and the thickness of the second chip layer is less than 200 μm. The first chip layer includes at least two chips spaced apart along its surface direction, and an isolation trench is provided between two adjacent chips in the first chip layer; the isolation trench extends through the first chip layer and the intermediate pad layer in the thickness direction of the first chip layer. The isolation trench includes a first trench and a second trench in the thickness direction of the first chip layer. The first trench is disposed close to the second chip layer, and the second trench is disposed away from the second chip layer. Along the arrangement direction of two adjacent chips, the width of the first trench is smaller than the width of the second trench.
2. The chip package according to claim 1, characterized in that, The isolation groove is filled with organic insulating material.
3. The chip package according to claim 1 or 2, characterized in that, The edge of the first chip layer is provided with a molding compound.
4. The chip package according to claim 3, characterized in that, Along the layer direction of the first chip layer, the molding compound has a ring structure.
5. The chip package according to claim 3 or 4, characterized in that, Along the thickness direction of the first chip layer, the molding compound has a stepped structure, and the thickness of the end of the molding compound near the second chip layer is less than the thickness of the end of the molding compound away from the second chip layer.
6. The chip package according to any one of claims 1-5, characterized in that, The second chip layer is at least one layer, and each second chip layer includes at least one chip.
7. A method for manufacturing a chip package, characterized in that, include: A first trench is formed by etching on the front side of a first wafer; the first wafer includes a device functional layer disposed on the front side of the first wafer and a substrate layer disposed on the back side of the first wafer, the surface of the device functional layer is provided with an intermediate pad layer, and the first trench penetrates the intermediate pad layer and the device functional layer along the thickness direction of the first wafer. The intermediate pad layer is bonded to the auxiliary support component, and a second groove is formed by mechanical cutting on the back side of the first wafer. The second groove is made to communicate with the first groove to form an isolation groove. The width of the first groove is smaller than the width of the second groove. The first wafer is divided into a first chip layer containing at least two chips by the isolation groove. The thickness of the first chip layer is greater than or equal to 200 μm. The auxiliary support is separated, the first chip layer is attached to the surface of the second wafer, and the side of the second wafer opposite to the first chip layer is thinned to form the second chip layer; wherein, the thickness of the second chip layer is less than 200μm, and the surface of the first chip layer with the intermediate pad layer is bonded to the second wafer.
8. The method for manufacturing a chip package according to claim 7, characterized in that, The method for manufacturing the chip package after separating the auxiliary support and before attaching the first chip layer to the surface of the second wafer further includes: filling the isolation trench with organic insulating material and encapsulating the edge of the first chip layer.
9. The method for manufacturing a chip package according to claim 7 or 8, characterized in that, After forming the second chip layer, the method for manufacturing the chip package further includes: forming a wiring layer and a bottom pad layer on the back side of the second chip layer.
10. An electronic device, characterized in that, Includes the chip package as described in any one of claims 1-6.