Communication method, communication apparatus, storage medium, and program product

Abstract

Provided are a communication method, a communication apparatus, a storage medium, and a program product. The method comprises: a first node receives a signal sent by a second node, the signal comprising at least one of the following: a pilot part, a control part, and a data part, the pilot part comprising: a clock synchronization part, the clock synchronization part being used for indicating a chip length of the control part and / or a chip length of the data part. On the basis of the position of the pilot part, the first node performs at least one of the following: determining the position of the control part, and acquiring information of the control part; and determining the position of the data part, and acquiring information of the data part.

Description

Communication methods, communication devices, storage media and software products

[0001] This disclosure claims priority to Chinese patent application No. 202411604512.9, filed on November 8, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of communication technology, and in particular to a communication method, communication device, storage medium, and program product. Background Technology

[0003] In recent years, the Internet of Things (IoT), such as the ambient internet of things (Ambient-IoT), has attracted much attention in the field of wireless communication. The IoT connects multiple things to improve productivity or enhance comfort. Because IoT applications require the deployment of hundreds of millions of devices, these devices need to be small in size, low in complexity, and low in power consumption.

[0004] Due to the low-complexity design requirements of IoT devices, some IoT devices lack energy storage devices. Therefore, these devices need to obtain energy from the surrounding environment (e.g., a high level in downlink signaling). Uplink signals are transmitted via backscattering. Summary of the Invention

[0005] This disclosure provides a communication method, a communication device, a storage medium, and a program product.

[0006] On one hand, embodiments of this disclosure provide a communication method applied to a first node, comprising: the first node receiving a signal transmitted by a second node, the signal including at least one of the following: a pilot portion, a control portion, and a data portion; the pilot portion including a clock synchronization portion used to indicate the chip length of the control portion and / or the chip length of the data portion. Based on the position of the pilot portion, the first node performs at least one of the following: determining the position of the control portion and acquiring information about the control portion; determining the position of the data portion and acquiring information about the data portion.

[0007] On the other hand, embodiments of this disclosure provide a communication method applied to a second node, comprising: the second node sending a signal to a first node, the signal including at least one of the following: a pilot section, a control section, and a data section, the pilot section including: a clock synchronization section, the clock synchronization section being used to indicate the chip length of the control section and / or the chip length of the data section.

[0008] In another aspect, embodiments of this disclosure provide a communication device applied to a first node, the communication device comprising: a receiving module and a processing module.

[0009] A receiving module is configured to receive signals transmitted by a second node, the signals including at least one of the following: a pilot section, a control section, and a data section. The pilot section includes a clock synchronization section, which indicates the chip length of the control section and / or the chip length of the data section. A processing module is configured to, based on the position of the pilot section, have the first node perform at least one of the following: determine the position of the control section and acquire information about the control section; determine the position of the data section and acquire information about the data section.

[0010] In another aspect, embodiments of this disclosure provide a communication device applied to a second node, the communication device comprising: a transmitting module.

[0011] A transmitting module is used to transmit signals to a first node. The signals include at least one of the following: a pilot section, a control section, and a data section. The pilot section includes a clock synchronization section, which is used to indicate the chip length of the control section and / or the chip length of the data section.

[0012] In another aspect, embodiments of this disclosure provide a communication device, including a memory and a processor. The memory and the processor are coupled. The memory is used to store a computer program. When the processor executes the computer program, it implements the communication method described above.

[0013] In another aspect, embodiments of this disclosure provide a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the communication method described above.

[0014] In another aspect, embodiments of this disclosure provide a computer program product including computer program instructions that, when executed, implement the communication method described above. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1 is a schematic diagram of a communication system according to some embodiments;

[0017] Figure 2 is a flowchart of a communication method according to some embodiments;

[0018] Figure 3 is a schematic diagram of a waveform example of a high and low level according to some embodiments;

[0019] Figure 4 is a schematic diagram of another example of high and low level waveforms according to some embodiments;

[0020] Figure 5 is a schematic diagram of another example of a high and low level waveform according to some embodiments;

[0021] Figure 6 is a schematic diagram of another example of high and low level waveforms according to some embodiments;

[0022] Figure 7 is a flowchart of another communication method according to some embodiments;

[0023] Figure 8 is a flowchart of another communication method according to some embodiments;

[0024] Figure 9 is a block diagram of a communication device according to some embodiments;

[0025] Figure 10 is a block diagram of another communication device according to some embodiments;

[0026] Figure 11 is a block diagram of another communication device according to some embodiments. Detailed Implementation

[0027] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] It should be noted that in this disclosure, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts by way of example.

[0029] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0030] In the description of this disclosure, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "more than one" means two or more.

[0031] IoT devices can be categorized into several types. Most of them are passive (without batteries), and their signaling design and transmission considerations differ from those of active terminals such as mobile phones.

[0032] For passive IoT devices, the base station (or excitation source) needs to continuously send high-level signals to the IoT device to power, activate, or charge it. After the IoT device is activated, it receives downlink signaling sent by the base station and returns uplink signaling to the base station via backscatter.

[0033] In Ambient-IoT research, IoT devices (A-IoT devices) are considered simple devices such as tags. However, based on their functionality and complexity, device types are typically categorized into three types: Type 1 devices: power consumption is approximately 1 microwatt (μW), lacking downlink (DL) or uplink (UL) amplifiers, and feeding back uplink signals via backscatter. Type 2a devices: power consumption ≤ a few hundred μW, possessing DL and / or UL amplifiers, and feeding back uplink signals via backscatter. Type 2b devices: power consumption ≤ a few hundred μW, possessing DL and / or UL amplifiers, and autonomously generating uplink signals.

[0034] In A-IoT research, the device that communicates with the A-IoT device is called a reader, which can be a base station or user equipment (UE). The UE can be a mobile phone or other 5G terminal device.

[0035] In A-IoT communication, because A-IoT devices are simple, it is impossible to continuously maintain synchronization between A-IoT devices and readers. Therefore, before each uplink or downlink communication, it may be necessary to send a pilot or preamble sequence for synchronization, which may carry some information.

[0036] Downlink signaling primarily transmits pilot sequences and / or control information, and / or downlink data to IoT devices. The IoT devices, based on the received signaling, return corresponding data or feedback information uplink. For example, downlink signaling might include a read command and the read location (content). The IoT device retrieves the data at the indicated location and sends it to the base station. Similarly, downlink signaling might include a write command, the write location, and the data to be written. Upon receiving the signaling, the IoT device stores the downlink-transmitted data at the indicated location. Typically, a downlink signaling sequence contains pilots and data (data is sent after the pilot), or it might contain pilots, control information, and data (control information follows the pilot, and data follows the control information). Uplink signaling primarily includes preambles, data, etc., and returns information based on the downlink signaling.

[0037] In other words, IoT terminal devices are typically simple in structure and low in complexity, thus limiting their ability to handle complex processing. To enable IoT devices to recognize the presence of downlink signaling and begin decoding, a downlink preamble design is required. Typically, IoT devices detect signals by detecting level transitions (rising edge: low level --> high level, falling edge: high level --> low level). Therefore, the start of downlink signaling can be detected through level transitions.

[0038] In conclusion, how to design and manage the sequence of signaling or signals to match the data transmission requirements of different communication systems has become an urgent technical problem to be solved.

[0039] Based on this, to solve the aforementioned technical problems, this disclosure provides a communication method applied in data transmission communication scenarios. By reading the clock synchronization portion of the pilot section in the signal, the chip length of the control section and / or the chip length of the data section following the pilot section are identified, thereby obtaining information on the control section and / or the data section. Thus, by designing special signaling or signal sequences in the pilot section of the signal, a reference basis is provided for the subsequent reading of information from the control and data sections, matching the data transmission requirements of different communication systems.

[0040] In this embodiment of the disclosure, the network architecture of the mobile communication network (including but not limited to 2G, 3G, 4G, 5G and future mobile communication networks (such as the evolution of the fifth generation mobile communication technology (5G-A) and the sixth generation mobile communication technology (6G))) may include at least a first communication node and a second communication node, which may be referred to as the first node and the second node, respectively.

[0041] In some embodiments, FIG1 is a schematic diagram of a communication system according to some embodiments. As shown in FIG1, the communication system may include:

[0042] First node 101 and second node 102.

[0043] The second node 102 can send a signal to the first node 101 containing at least one of a pilot section, a control section, and a data section. The pilot section of the signal is specially designed to include a clock synchronization component for determining the chip length of the control section and / or the chip length of the data section. Subsequently, the first node 101 can receive the signal sent by the second node 102 and, based on the position of the pilot section in the signal, determine the position of the control section and / or the position of the data section within the signal, thereby obtaining information about the control section and / or the data section.

[0044] It should be noted that in this embodiment of the disclosure, the first node 101 can be a terminal, an A-IoT device, a radio frequency identification (RFID) tag, or a tag, etc., and the second node 102 can be a base station, a reader, or a UE.

[0045] Here, a base station (BS) can be a base station in LTE, Long Term Evolution Advanced (LTEA) or an evolved Node B (eNB or eNodeB), a base station device in a 5G network (next generation NodeB, gNB), or a base station in a future communication system. Base stations can include various macro base stations, micro base stations, femtocell base stations, wireless remote extensions, reconfigurable intelligent surfaces (RISS), routers, relay stations, transmission and reception points (TRPs), receivers, access points, wireless fidelity (Wi-Fi) devices, and other network-side equipment. A base station can sometimes also be referred to as a reader / writer used for communication with terminals.

[0046] A terminal can be a device with wireless transceiver capabilities. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control, wireless terminals in self-driving vehicles, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and so on. This disclosure does not limit the application scenarios. A terminal may also be referred to as a user, user equipment (UE), A-IoT device, access terminal, UE unit, UE station, mobile station, mobile station, remote station, transmitter, remote terminal, mobile device, UE terminal, wireless communication device, UE agent, or UE device, etc., and this disclosure does not limit these terms.

[0047] It should be noted that Figure 1 is only an exemplary framework diagram. The number of devices included in Figure 1 and the names of each device are not limited. In addition to the devices shown in Figure 1, the communication system may also include other devices, such as core network devices.

[0048] This disclosure does not limit the application scenarios. The system architecture and business scenarios described in the embodiments of this disclosure are for the purpose of more clearly illustrating the technical solutions of the embodiments of this disclosure, and do not constitute a limitation on the technical solutions provided by the embodiments of this disclosure. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of this disclosure are also applicable to similar technical problems.

[0049] Figure 2 is a flowchart of a communication method according to some embodiments. As shown in Figure 2, the communication method is applied to a first node, including S201.

[0050] In S201, the first node receives the signal sent by the second node.

[0051] The signals transmitted by the second node may include at least one of the following: pilot section, control section, and data section.

[0052] It should be noted that the pilot section refers to the known reference signal inserted into the signal to help the receiver perform channel estimation and synchronization, the control section contains various signaling information for controlling and managing the communication link, and the data section contains the user data that actually needs to be transmitted.

[0053] In other words, downlink transmission may include two parts besides the preamble: a control part and a data part.

[0054] In this embodiment of the disclosure, the pilot section may include a clock acquisition part (CAP). Here, the clock acquisition part is used to indicate the chip length of the control section and / or the chip length of the data section.

[0055] It should be noted that in an A-IoT system, the time unit or resource unit is a chip, and each bit corresponds to one chip. Bit 0 corresponds to a low level of one chip, and bit 1 corresponds to a high level of one chip.

[0056] Furthermore, A-IoT downlink uses on-off keying (OOK)-1 or OOK-4 modulation. Alternatively, the preamble (i.e., the pilot section) may not require encoding, with each bit corresponding to one chip.

[0057] Furthermore, in A-IoT systems, the M value represents the number of chips contained in an orthogonal frequency division multiplexing (OFDM) symbol. The length of a chip = the length of an OFDM symbol / M (i.e., the ratio of the length of an OFDM symbol to M). Therefore, the larger the M value, the shorter the chip length. There is a one-to-one correspondence between M values ​​and chip lengths. For example, Table 1 below shows the correspondence between M values ​​and chip lengths:

[0058] Table 1. Correspondence between M value and chip length

[0059] Based on the above description, in this embodiment of the disclosure, the chip length of the control part and the chip length of the data part each correspond to an M value. The M values ​​used for the chip length and the data part may be the same or different. Moreover, the M values ​​of the control part and the M values ​​of the data part are both candidate values ​​in the first preset candidate value set, which is {1, 2, 4, 6, 8, 12, 16, 24, 32}.

[0060] In one implementation, the clock synchronization section may include a first section and a second section. The chip length of the first section is the same as the chip length of the control section, and the chip length of the second section is the same as the chip length of the data section.

[0061] In other words, CAP can be divided into two parts: one part indicates the M value or chip length of the control section, and the other part indicates the M value or chip length of the data section. In this way, the first node can obtain the M value (chip length) information of the control section and / or the data section through CAP, and distinguish and locate the positions of the control section and the data section by referring to the chip length indicated by the clock synchronization section for the control section and the data section.

[0062] It should be noted that, in the embodiments disclosed herein, the control section and the data section satisfy at least one of the following (1)-(3):

[0063] (1) The chip length of the control section is greater than or equal to the chip length of the data section;

[0064] (2) The multiple between the chip length of the control section and the chip length of the data section is less than a preset threshold;

[0065] (3) The chip length of the control section is an integer multiple of the chip length of the data section (e.g., O = 1, 2, 3, 4, 6, ..., 32).

[0066] Regarding (1) above, if the chip length of the control section is greater than or equal to the chip length of the data section, then the M value of the control section is not greater than (i.e., less than or equal to) the M value of the data section. Thus, when the chip duration of the control section is greater than or equal to the chip duration of the data section, the range of possible values ​​for the chip duration of the data section varies with the chip duration of the control section. For example, the possible values ​​for the M value of the data section include at least one of the following: set A = {1, 2, 4, 6, 8, 12, 16, 24, 32}, and when the M value of the control section is Y, the possible values ​​for the M value of the data section are values ​​in set A that are greater than or equal to Y.

[0067] For (2) above, the preset threshold can be a positive integer less than or equal to 4. Alternatively, the preset threshold can be a positive integer less than or equal to 9. Or, the preset threshold can be a positive integer less than or equal to 17.

[0068] However, when the M value of the control part is different from the M value of the data part, some chips of the control part and the data part may not occupy a complete OFDM symbol. That is, an OFDM symbol may not be able to completely contain chips corresponding to the two M values.

[0069] In some embodiments, as shown in FIG3, the distribution of the first and second parts of CAP in an OFDM symbol is used to represent the distribution of the control and data parts in an OFDM symbol. Here, if the bit sequence of the first part and the bit sequence of the second part are both 1010, and the M value of the control part is 6 (i.e., the M value of the first part is 6) and the M value of the data part is 8 (i.e., the M value of the second part is 8), then the chip length corresponding to the four bits in the bit sequence of the first part is 1 / 6 of the OFDM symbol length and is located within the same OFDM symbol, while the chip length corresponding to the four bits in the bit sequence of the second part is 1 / 8 of the OFDM symbol length and the chip corresponding to the third bit spans two OFDM symbols.

[0070] In other words, at the boundary between the control section and the data section, the situation described in the above embodiment, where a chip spans two OFDM symbols, can also occur, affecting the differentiation and identification of the control section and the data section.

[0071] It should be noted that the above embodiments are merely an introduction to a chip spanning two OFDM symbols, and this disclosure does not limit the number of OFDM symbols that a chip can span. For example, a chip may span at least two OFDM symbols.

[0072] Therefore, to ensure the accuracy of identification of the control and data parts, the chip length of the control part can be managed to be an integer multiple of the chip length of the data part (i.e., as described in (3) above), or the M value of the data part can be managed to be an integer multiple of the M value of the control part, so as to ensure that each chip of the control and data parts is completely located within one OFDM symbol, and there is no situation where a chip in the control part and / or the data part spans two OFDM symbols. In this way, it can be guaranteed that even if the chips corresponding to two M values ​​are in the same OFDM symbol, there will be no situation where a chip spans an OFDM symbol.

[0073] However, in order to ensure that the chip lengths on the control section and the data section can meet the information carrying requirements and avoid the impact on the integrity of information carrying due to the short length of some chips caused by the large multiple, it is necessary to limit the multiple relationship between the chip length of the control section and the chip length of the data section (i.e., the above (2)), or limit the multiple relationship between the M value of the data section and the M value of the control section.

[0074] It should be noted that this disclosure does not limit the threshold (i.e., the preset threshold) for the above-mentioned control multiple relationship.

[0075] For example, the multiple cannot exceed 4 times (i.e., the preset threshold is 5). That is, the chip duration indicated by the first part is an integer multiple of the chip duration indicated by the second part, where 0 = 1, 2, 3, 4. Alternatively, the M value of the data part is an integer multiple of the M value of the control part, where 0 = 1, 2, 3, 4.

[0076] For example, the multiple cannot exceed 3 times (i.e., the preset threshold is 4). That is, the chip duration indicated by the first part is an integer multiple of the chip duration indicated by the second part, where 0 = 1, 2, or 3. Alternatively, the M value of the data part is an integer multiple of the M value of the control part, where 0 = 1, 2, or 3.

[0077] It should be noted that the above embodiments avoid a situation where a chip in the control section or data section spans two OFDM symbols by managing the multiple relationship between the chip length of the control section and the chip length of the data section. However, it is also possible to avoid a situation where a chip in the control section or data section spans two OFDM symbols by managing the end position of the control section to coincide with the OFDM symbol boundary.

[0078] In some embodiments, when the chip durations of the data portion and the control portion differ, the end position of the control portion is located at the end position of an OFDM symbol. That is, the end position of the control portion is located at the last chip of an OFDM symbol.

[0079] In one implementation, if the chip length of the control section is different from the chip length of the data section, and the end position of the control section is not located at the last chip of an OFDM symbol, the signal also includes a first padding bit located after the control section, the chip length of the first padding bit being the same as the chip length of the control section.

[0080] In other words, if the end position of the control part is not located at the last chip of an OFDM symbol, one or more padding bits can be added to the control part to construct a new control part, so that the end position of the new control part is located at the last chip of an OFDM symbol.

[0081] In some embodiments, when the chip durations of the data portion and the control portion differ, if the end position of the control portion is not the last chip of an OFDM symbol, a padding bit (i.e., a first padding bit) is added after the control portion. The padding bit continues to be added until it is added to the last chip of the OFDM symbol, and the M value of the padding bit is the same as the M value of the control portion. Here, the padding bit can be 1 or 0. In some embodiments, the padding bit (or the first padding bit) is the same as the bit or level of the last chip in the control portion. For example, if the bit or level of the last chip in the control portion is 1 or high, then the padding bit is 1 or high. In some embodiments, the padding bit is opposite to the bit or level of the last chip in the control portion. For example, if the bit or level of the last chip in the control portion is 1 or high, then the padding bit is 0 or low.

[0082] In some embodiments, where the chip length of the control portion differs from the chip length of the data portion, and the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit following the control portion and a second padding bit following the first padding bit; here, the chip length of the first padding bit is the same as the chip length of the control portion, the chip length of the second padding bit is the same as the chip length of the data portion, the second padding bit includes an odd number of chips, and the data portion is located after the second padding bit.

[0083] In some embodiments, where the chip length of the control portion is different from the chip length of the data portion, and the end position of the control portion is located at the last chip of an OFDM symbol, the signal further includes a second padding bit located after the control portion; here, the chip length of the second padding bit is the same as the chip length of the data portion, the second padding bit includes an odd number of chips, and the data portion is located after the second padding bit.

[0084] In some embodiments, if the chip length of the control portion is different from that of the data portion, and the end position of the control portion is located at the last chip of an OFDM symbol, the first padding bit is not filled.

[0085] In some embodiments, when the chip length of the control portion is the same as the chip length of the data portion, there are no padding bits between the control portion and the data portion.

[0086] In some embodiments, if the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit after the control portion and a second padding bit after the first padding bit; here, the chip length of the first padding bit is the same as the chip length of the control portion, the chip length of the second padding bit is the same as the chip length of the data portion, the second padding bit includes an odd number of chips, and the data portion is located after the second padding bit.

[0087] The first padding bit begins in the first chip after the control section and ends in the last chip of an OFDM symbol. In some embodiments, the first padding bit begins in the first chip after the control section and ends in the last chip of the OFDM symbol containing the last chip of the control section.

[0088] In some embodiments, where the end of the control portion is located at the last chip of an OFDM symbol, the signal further includes a second padding bit following the control portion; here, the chip length of the second padding bit is the same as the chip length of the data portion, the second padding bit comprises an odd number of chips, and the data portion is located after the second padding bit.

[0089] In other words, in order to distinguish the control portion and the data portion at the boundary of an OFDM symbol, special padding bits can be added before the data portion to distinguish the padding bits after the control portion.

[0090] In some embodiments, when the M value (or chip duration) of the data portion differs from that of the control portion, if the end position of the control portion is not the last chip of an OFDM symbol, a first control padding bit (i.e., a first padding bit) is added after the control portion. The first control padding bit continues to be added until it is added to the last chip of the OFDM symbol. The M value of the first control padding bit is the same as the M value of the control portion. A second data padding bit (i.e., a second padding bit) is inserted before the data portion, and the M value of the second data padding bit is the same as the M value of the data portion. Here, the number of second data padding bits is odd. The second data padding bit is 1 or 0, and the second data padding bit starts at the first chip of an OFDM symbol. For example, the second data padding bit is 111, or 1, or 000, or 0.

[0091] In some embodiments, the second padding bits are the same as the bits or levels of the first chip in the data portion. For example, if the bits or levels of the first chip in the data portion are 1 or high, then all the second padding bits are 1 or high. In some embodiments, the second padding bits are opposite to the bits or levels of the first chip in the data portion. For example, if the bits or levels of the first chip in the data portion are 1 or high, then the second padding bits are 0 or low.

[0092] In some embodiments, the second padding bit is the same as the bit or level of the last chip or the first padding bit of the control section. For example, if the last chip or the first padding bit of the control section is 1 or high, then all second padding bits are 1 or high. In some embodiments, the second padding bit is opposite to the bit or level of the last chip or the first padding bit of the control section. For example, if the last chip or the first padding bit of the control section is 1 or high, then the second padding bit is 0 or low.

[0093] In conjunction with the above embodiments, in this disclosure embodiment, the first part and the second part can satisfy at least one of the following (a)-(g):

[0094] (a) The chip length of the first part is greater than or equal to the chip length of the second part;

[0095] (b) The chip length of the first part is an integer multiple of the chip length of the second part;

[0096] (c) The first part occupies an integer number of OFDM symbols;

[0097] (d) The second part occupies an integer number of OFDM symbols;

[0098] (e) The first and second parts together occupy an integer number of OFDM symbols;

[0099] (f) The number of chips in the first part is the same as the number of chips in the second part;

[0100] (g) The number of chips in the first part and the number of chips in the second part are both even numbers greater than 2.

[0101] In other words, by specially designing the sequence of the clock synchronization part, the chip lengths of the control part and the data part are indicated, so that the receiving end can better distinguish and read the information on the control part and the data part.

[0102] For (c) and (d) above, the first part can occupy one OFDM symbol on its own, and the second part can occupy one OFDM symbol on its own.

[0103] For (e) above, the first part can occupy 1 / 2 OFDM symbol, and the second part can occupy 1 / 2 OFDM symbol.

[0104] For (f) above, the first part and the second part can each contain P chips, where P is an even number greater than 2. For example, the P chips are P 1010 interleaved chips (i.e., high and low level interleaved chips).

[0105] Similarly, considering the issue of the multiple relationship between the chip lengths of the control section and the data section in the above embodiments regarding the integrity of information carrying, the multiple between the chip length of the first part and the chip length of the second part can be less than a preset threshold.

[0106] In some embodiments, the first part may be located before the control part, and the second part may be located before the data part. That is, the start indication part precedes the first part of the clock synchronization part, the first part of the clock synchronization part precedes the control part, the control part precedes the second part of the clock synchronization part, and the second part of the clock synchronization part precedes the data part.

[0107] In some embodiments, both the first and second portions of the clock synchronization section consist of an odd number of chips. In some embodiments, if the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit following the control portion. Here, the chip length of the first padding bit is the same as the chip length of the control portion. The second portion of the control portion follows the first padding bit.

[0108] In some embodiments, the first part may precede the second part, or the first part may follow the second part.

[0109] Since the control section precedes the data section, adjusting the order of the first and second sections in CAP can synchronize the order of the control and data sections (distinguishing the CAP section from control and data), or adjust the sequence of the corresponding control section before the control section so that the control section can be identified after the sequence of the corresponding control section is identified (i.e., in CAP, the part indicating control is connected to the control section, and its chip duration is better determined).

[0110] In this embodiment of the disclosure, when the chip length of the first part is equal to the chip length of the second part, the second part can satisfy at least one of the following 1-4:

[0111] 1. The number of chips in the second part is less than the number of chips in the first part;

[0112] 2. All bits in the second part have the same binary value (i.e., all 0s or all 1s);

[0113] 3. All bits in the second part are the same as the last bit in the first part;

[0114] 4. All bits in the second part are the opposite of the last bit in the first part.

[0115] In other words, when the chip length of the control section is the same as that of the data section (i.e., the chip lengths of the first and second parts of the clock synchronization section are the same), the bit sequence of the second part of the clock synchronization section is simplified. Furthermore, since the simplified bit sequence of the second part is a special sequence, it can be distinguished from the subsequent physical reader-to-device channel (PRDCH) transmission section, and the overhead is relatively small.

[0116] Regarding point 3 above, if the second part contains 2 chips, then the voltage levels of these 2 chips are the same as the last voltage level of the first part. For example, the first part is 1010, and the second part is 00. Alternatively, if the second part contains Q chips, then the voltage levels of these Q chips are the same as the last voltage level of the first part. For example, if Q = 3 and the first part is 10101, then the second part is 111.

[0117] Regarding point 4 above, if the second part contains Q chips, then the voltage levels of these Q chips are opposite to the last voltage level of the first part. For example, if Q = 2 and the first part is 1010, then the second part is 11. Alternatively, if the second part contains Q chips, then the voltage levels of these Q chips are opposite to the last voltage level of the first part. For example, if Q = 3 and the first part is 10101, then the second part is 000.

[0118] In some embodiments, after the first node receives a signal from the second node, the first node can execute S202 based on the position of the pilot portion in the signal.

[0119] In S202, the first node determines the position of the control section and / or the position of the data section based on the position of the pilot section, and obtains information about the control section and / or the data section.

[0120] In one implementation, depending on the location of the pilot portion, the first node can perform at least one of the following:

[0121] (a) Determine the location of the control unit and obtain information about the control unit;

[0122] (ii) Determine the location of the data section and obtain information about the data section.

[0123] It should be noted that for the processes in (i) and (ii) above, you can refer to the introduction of reading the information of the control part and the data part based on the chip length of the control part and the data part in the relevant technology, which will not be repeated here.

[0124] Understandably, by reading the clock synchronization portion of the pilot section in the signal, the chip length of the control section and / or the chip length of the data section following the pilot section can be distinguished and identified, thereby obtaining information from the control section and / or the data section. In this way, by designing special signaling or signal sequences in the pilot section of the signal, a reference basis is provided for the subsequent reading of information from the control and data sections, thus matching the data transmission requirements of different communication systems.

[0125] It should be noted that, in order to further simplify the bit sequence of the clock synchronization part and make full use of the information carrying capacity of the control part for control, the clock synchronization part may only include: the first part.

[0126] In some embodiments, where the clock synchronization portion includes only the first portion, the control portion may include indication information for determining the chip length (or M value) of the data portion, and the number of bits corresponding to the indication information of the control portion is determined by the chip length of the first portion (or by the M value of the first portion).

[0127] In other words, CAP indicates the M value of the control section, and the control section indicates the M value of the data section.

[0128] In one implementation, during the process of determining the position of the control section and obtaining the information of the control section based on the position of the pilot section, the first node can determine the information of the control section based on the chip length of the first section.

[0129] Furthermore, during the process of determining the location of the data section and acquiring its information based on the pilot section's location, the first node can determine the set of candidate M-values ​​corresponding to the data section based on the chip length of the first section. It can also determine the indication information in the control section indicating the chip length of the data section based on the number of candidate M-values ​​contained in the set. Next, the first node can determine the chip length of the data section based on the indication information and a preset correspondence, and then determine the data section's information based on the chip length.

[0130] The set of candidate M values ​​corresponding to the data part may include all candidate values ​​in the first preset candidate set that are greater than or equal to the M value corresponding to the control part; or, the set of candidate M values ​​corresponding to the data part may include a preset number of candidate values ​​in the first preset candidate set that are greater than or equal to the M value corresponding to the control part and are adjacent to the M value corresponding to the control part.

[0131] In some embodiments, when the M value of the control section is Y, the M value of the data section can be a value in set A that is greater than or equal to Y. There are N possible M values ​​for the data section, and the number of bits in the control section indicating the chip duration of the data (i.e., the number of bits indicating the chip length of the data section) is ceil(log2(N)). Set A is {1,2,4,6,8,12,16,24,32}.

[0132] For example, if the M value of the control section is 8, and the M value of the data section can be {8, 12, 16, 24, 32}, and N = 5, then the number of bits indicating the chip duration of the data in the control section is 3, where '000' indicates M = 8, '001' indicates M = 12, '010' indicates M = 16, '011' indicates M = 24, and '100' indicates M = 32. The remaining codepoints are reserved. In some embodiments, the correspondence between codepoints and M values ​​can be predefined. In this embodiment, the i-th codepoint indicates the i-th codepoint in the set of possible M values ​​for the data section.

[0133] For example, when the value of M in the control section is Y, the possible values ​​of M in the data section are values ​​in set A that are greater than or equal to Y. There are N possible values ​​of M in the data section, so the number of bits in the control section indicating the chip duration of the data is ceil(log2(N-1)).

[0134] For example, if the M value of the control part is 8, and the M value of the data part can be {8, 12, 16, 24, 32}, and N = 5, then the number of bits indicating the chip duration of the data in the control part is 2, where '00' indicates M = 12, '01' indicates M = 16, '10' indicates M = 24, and '11' indicates M = 32. In this embodiment of the disclosure, the i-th code point indicates the (i+1)-th bit in the set of possible M values ​​for the data part.

[0135] If the M value of the data section is 8 (i.e., the same as the M value of the control section), then the control section does not indicate the chip duration of the data. Similar to the special design in the second part of CAP above, it indicates that the M value of the data section is the same as the M value of the control section.

[0136] For example, when the value of M in the control section is Y, the possible values ​​of M in the data section are K values ​​in set A that are greater than or equal to Y. Since there are K possible values ​​of M in the data section, the number of bits indicating the chip duration of the data in the control section is ceil(log2(K)). In some embodiments, K is a positive integer greater than or equal to 1 and less than or equal to 12. In some embodiments, if the value in set A that is greater than or equal to Y is less than K, then the possible values ​​of M in the data section are values ​​in set A that are greater than or equal to Y.

[0137] For example, when the M value of the control section is Y, the M value of the data section can be any of the four values ​​in set A that are greater than or equal to Y. Since there are four possible M values ​​for the data section, the number of bits used by the control section to indicate the chip duration of the data is 2.

[0138] For example, the M value in the control section is 1, and the M value in the data section can be {1,2,4,6}.

[0139] For example, the M value in the control section is 4, and the M value in the data section can be {4,6,8,12}.

[0140] In some embodiments, when the chip lengths of the control section and the data section are the same, the clock synchronization section may consist only of the first section, and the first section is a first preset mode. Alternatively, when the chip lengths of the control section and the data section are different, the clock synchronization section may consist of both the first section and the second section, and the first section is a second preset mode.

[0141] In some embodiments, the first part of CAP has two patterns. One pattern indicates the existence of a second part (i.e., a second preset pattern), where the first part indicates the chip duration of control and the second part indicates the chip duration of data. The other pattern indicates the absence of a second part (i.e., a first preset pattern), where the chip duration of the control part and the data part are the same, and is indicated by the first part.

[0142] In other words, the receiving end can determine whether a second part exists in the clock synchronization section by identifying the pattern corresponding to the first part, and further determine the chip lengths of the control and data sections. Thus, compared to simplifying the clock synchronization section by shortening the bit sequence of the second part as described above, this embodiment simplifies the clock synchronization section from the perspective of pattern recognition.

[0143] In some embodiments, the clock synchronization portion has multiple patterns. In embodiments of this disclosure, the clock synchronization portion can be one of the following: a clock synchronization portion, a first portion of a clock synchronization portion, or a second portion of a clock synchronization portion.

[0144] For example, the clock synchronization section has multiple patterns. When the M value indicated by the clock synchronization section is a first type of M value, the clock synchronization section uses pattern A; when the M value indicated by the clock synchronization section is a second type of M value, the clock synchronization section uses pattern B. The first type of M value and the second type of M value have different ranges. In some embodiments, the first type of M value is an M value less than 16, and the second type of M value is an M value greater than or equal to 16. In some embodiments, pattern A is 10101, and pattern B is 1110101. Or pattern A is 101, and pattern B is 11101.

[0145] For example, the clock synchronization section has multiple patterns. When the M value indicated by the clock synchronization section is a first type of M value, the clock synchronization section uses pattern A; when the M value indicated by the clock synchronization section is a second type of M value, the clock synchronization section uses pattern B; and when the M value indicated by the clock synchronization section is a third type of M value, the clock synchronization section uses pattern C. The ranges of the first type of M value, the second type of M value, and the third type of M value are different. In some embodiments, the first type of M value is M = 1, the first type of M value is an M value greater than 1 and less than 16, and the second type of M value is an M value greater than or equal to 16. In some embodiments, pattern A is 101, pattern B is 10101, and pattern C is 1110101. Or pattern A is 101, pattern B is 10101, and pattern C is 1010101.

[0146] In some embodiments, the sequence of pattern A is a subset of the sequence of pattern B. The sequence of pattern B is a subset of the sequence of pattern C. For example, pattern A is 101, pattern B is 10101, and pattern C is 1110101. Another example is pattern A being 10101, pattern B being 1010101, and pattern C being 111010101. Yet another example is pattern A being 101, pattern B being 10101, and pattern C being 0010101.

[0147] In some embodiments, the sequence indicating the clock synchronization portion of a smaller M value is a subset of the sequence indicating the clock synchronization portion of a larger M value. For example, the sequence indicating the clock synchronization portion of a smaller M value is 101, and the sequence indicating the clock synchronization portion of a larger M value is 10101.

[0148] In some embodiments, the sequence indicating the clock synchronization portion of a larger M value is formed by adding P 1s or P 0s before the sequence indicating the clock synchronization portion of a smaller M value. For example, the sequence indicating the clock synchronization portion of a larger M value is formed by adding two 1s or two 0s before the sequence indicating the clock synchronization portion of a smaller M value. In some embodiments, P is an even number greater than 1. For example, pattern A is 10101, and pattern B is 1110101. Or pattern A is 10101, and pattern B is 0010101.

[0149] In some embodiments, the first sub-block indicating a clock synchronization portion of M=16, 24, or 32 is a high or low level of a length equal to the chip length of M=8. The second sub-block indicating a clock synchronization portion of M=16, 24, or 32 includes the same sequence. For example, for an indication of M=16, the clock synchronization portion is 110101; for an indication of M=24, the clock synchronization portion is 1110101; and for an indication of M=32, the clock synchronization portion is 11110101.

[0150] In some embodiments, the first sub-block of the clock synchronization portion indicating M=16, 24, or 32 is a high or low level with a length equal to the chip length of M=8.

[0151] In some embodiments, the clock synchronization section has only one pattern, meaning that the pattern is the same regardless of the value of M indicated by the clock synchronization section. For example, all patterns are 10101, or all are 101, or all are 1010101.

[0152] In some embodiments, the pilot section may further include a start indicator part (SIP) for indicating the start of downlink transmission.

[0153] It should be noted that since the start indication section indicates the start of downlink transmission, it needs to be easy to detect and preferably distinguishable from the start of subsequent downlink transmissions to prevent the device from mistaking the data portion of the downlink transmission for the start indication section.

[0154] In this embodiment of the disclosure, the start indication portion includes one or more sub-parts, one of which corresponds to an M value, and the M value of the sub-part is the ratio between the chip length of the sub-part and the length of an OFDM symbol.

[0155] The M value of the sub-part is any candidate value in the second preset candidate set, which is {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12}.

[0156] It should be noted that the M value of the SIP can be different from the M value of the control or data section, and this is used to distinguish them. For example, the M value of the SIP can be one of {3, 5, 7, 9, 10}.

[0157] In some embodiments, the start indication portion may occupy an integer number of OFDM symbols.

[0158] In other words, when a SIP occupies an OFDM symbol, one or more M values ​​of the SIP share the OFDM symbol equally, and the chips of all sub-parts are spliced ​​together to form an OFDM symbol.

[0159] In one implementation, the sub-part can be represented by any of the following:

[0160] “100(3)”, where each bit in 100 corresponds to a chip length level with an M value of 3;

[0161] “10(4)”, where each bit in 10 corresponds to a chip length level with an M value of 4;

[0162] “1000(4)”, where each bit in 1000 corresponds to a chip length level with an M value of 4;

[0163] “110010(6)”, each bit in 110010 corresponds to a chip length level with an M value of 6;

[0164] “101100(6)”, each bit in 101100 corresponds to a chip length level with an M value of 6;

[0165] “11100010(8)”, each bit in 11100010 corresponds to a level with an M value of 8 chip length;

[0166] “10111000(8)”, each bit in 10111000 corresponds to a level with an M value of 8 and a chip length;

[0167] “110000(12)”, each bit in 110000 corresponds to a chip length level with an M value of 12;

[0168] “110010(12)”, each bit in 110010 corresponds to a chip length level with an M value of 12;

[0169] “101100(12)”, each bit in 101100 corresponds to a chip length level with an M value of 12;

[0170] “101100111000(12)”, each bit in 101100111000 corresponds to a chip length level with an M value of 12;

[0171] “111000110010(12)”, each bit in 111000110010 corresponds to a chip length level with an M value of 12;

[0172] “101100111000(6)”, each bit in 101100111000 corresponds to a chip length level with an M value of 6;

[0173] “111000110010(6)”, each bit in 111000110010 corresponds to a chip length level with an M value of 6;

[0174] “010(6)”, where each bit in 010 corresponds to a chip length level with an M value of 6;

[0175] “101(6)”, where each bit in 101 corresponds to a chip length level with an M value of 6;

[0176] “10(2)”, where each bit in 10 corresponds to a chip length of M with a value of 2;

[0177] “10(3)”, where each bit in 10 corresponds to a chip length level with an M value of 3;

[0178] “111000(6)”, each bit in 111000 corresponds to a chip length level with an M value of 6;

[0179] “1010(3)”, where each bit in 1010 corresponds to a chip length level with an M value of 3;

[0180] “1010(6)”, where each bit in 1010 corresponds to a chip length of M with a value of 6.

[0181] In some embodiments, a SIP chip occupies one OFDM symbol. For example, if the M value of the SIP chip is 3, then the SIP sequence can be 101 or 010.

[0182] In some embodiments, if the M value of the SIP chip is 4, then the SIP sequence can be 1000. For example, if the M value of the SIP chip is 6, then the SIP sequence can be 101110 or 101000. In some embodiments, if the M value of the SIP chip is 8, then the SIP sequence can be 10101110 or 10101000 or 10111010 or 10100010. In some embodiments, if the M value of the SIP chip is 12, then the SIP sequence can be 110011100010 or 101011100010 or 101110011000 or 101100011100, etc.

[0183] For example, if the M values ​​of the chips in a SIP are 5 and 10, then the sequence of the SIP is 10(M=10)1010(M=5). This means that the SIP contains two "10"s of M=10 chips and four "1010"s of M=5 chips. Here, the length of the two M=10 chips is equal to the length of one M=5 chip, and together with the four M=5 chips, they form a single OFDM symbol. The M=10 chips can precede or follow the M=5 chips.

[0184] A similar effect can be achieved when the SIP contains two M values.

[0185] In this embodiment of the disclosure, at least two of the sub-parts may have M values ​​that are not divisible by each other, that is, SIP may use two M values ​​that are not divisible by each other.

[0186] In this way, each SIP has a unique M value, which can distinguish it from the subsequent control and / or data sections, meaning it will not appear in the data section either.

[0187] For example, two OFDMs with M=4 and M=6: (1010(4)101010(6)) or (1100(4)11001100(6)). Or two M values ​​that differ significantly (M1 / M2>2), such as M=1, M=4, (10(1)1010(4)), M=2, M=6 (10(2)101010(6)), etc.

[0188] In one implementation, where the start indication portion includes multiple sub-parts, the start indication portion can be represented by any of the following:

[0189] “10(3)10(6)”, each bit in 10 corresponds to a chip length level with an M value of 3, and each bit in 10 corresponds to a chip length level with an M value of 6;

[0190] “10(4)010(6)”, each bit in 10 corresponds to a chip length level with an M value of 4, and each bit in 010 corresponds to a chip length level with an M value of 6;

[0191] “101(6)10(4)”, where each bit in 101 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4;

[0192] “110011010(6)10(4)”, each bit in 110011010 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4.

[0193] “111000110(6)10(4)”, each bit in 111000110 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4.

[0194] “101(6)100100(4)”, each bit in 101 corresponds to a chip length level with an M value of 6, and each bit in 100100 corresponds to a chip length level with an M value of 4.

[0195] In some embodiments, taking M=4,6 as an example, the SIP can be any of the following forms:

[0196] a、10(4)010(6);

[0197] b、10(4)101(6);

[0198] c. 101(6)10(4);

[0199] d、101(6)01(4);

[0200] e, 110011(6)010(6)10(4), and is equivalent to 101(3)010(6)10(4);

[0201] f, 111000(6)110(6)10(4), and is equivalent to 10(2)1(3)0(6)10(4).

[0202] For the above 'a', as shown in Figure 4, the chip corresponding to the '1' in "10" occupies 1 / 4 of the OFDM symbol length (i.e., chip length), the chip corresponding to the '0' in "10" occupies 1 / 4 of the OFDM symbol length, the chip corresponding to the first '0' in "010" occupies 1 / 6 of the OFDM symbol length, the chip corresponding to the '1' in "010" occupies 1 / 6 of the OFDM symbol length, and the chip corresponding to the second '0' in "010" occupies 1 / 6 of the OFDM symbol length. Thus, the chips occupied by "10" and "010" can be concatenated to form a complete OFDM symbol, i.e., 2 × 1 / 4 + 3 × 1 / 6 = 1.

[0203] For e and f above, the order of M corresponding to different bits in SIP can be changed. For example, the chip corresponding to the first "11" of "110011" in e above occupies 1 / 6 of the OFDM symbol length, so they can be integrated into a "1", so that the chip corresponding to "1" occupies 1 / 3 of the OFDM symbol length. Similarly, by performing the above integration on the first "00" and the second "11" of "110011" in e, the equivalent 101(3) can be obtained.

[0204] In some embodiments, taking M=2,6 as an example, the SIP can be any of the following forms:

[0205] 1(2)101(6)=M=6 111101,that is, 111101(6);

[0206] 1(2)010(6)=M=6 111010,that is, 111010(6);

[0207] 101(6)1(2);

[0208] 101(6)0(2);

[0209] 101(6)0(2)10(2);

[0210] 101(6)1(2)10(2);

[0211] 101(6)1(2)01(2).

[0212] In some embodiments, taking M=3,6 as an example, the SIP can be any of the following forms:

[0213] 10(3)10(6);

[0214] 1010(3)1010(6);

[0215] 10(6)0(3)10(6), and is equivalent to 100010(6).

[0216] In some embodiments, with M = 1, 3, the SIP can be any of the following forms:

[0217] 1(1)101(3), and is equivalent to 111 101(3);

[0218] 1(1)010(3), and is equivalent to 111 010(3).

[0219] In some embodiments, with M = 1, 3, 6, the SIP can be any of the following forms:

[0220] 1(1)10(3)10(6), and is equivalent to 111111 111000 10(6);

[0221] 1(1)01(3)01(6), and is equivalent to 111111 000111 01(6);

[0222] 10(6)10(3)0(1);

[0223] 1010(6)1(3)0(1).

[0224] In some embodiments, with M = 1, 2, 6, the SIP can be any of the following forms:

[0225] 1(1)0(2)101(6), and is equivalent to 111111 000101(6);

[0226] 101(6)1(2)0(1), and is equivalent to 101111 000000(6);

[0227] In some embodiments, with M = 1, 4, 6, the SIP can be any of the following forms:

[0228] 1(1)01(4)101(6), and is equivalent to 1111 01(4)101(6);

[0229] 1(1)01(4)010(6), and is equivalent to 1111 01(4)010(6);

[0230] 101(6)01(4)0(1);

[0231] 101(6)10(4)0100(4).

[0232] For the above 1111 01(4)010(6), as shown in Figure 5, the first four "1"s in "111101" occupy a whole OFDM symbol, and the "01" and "010" in "111101" occupy another whole OFDM symbol. That is, 1111 01(4)010(6) occupies two OFDM symbols.

[0233] In some embodiments, the SIP includes one or more sub-sections, each sub-section corresponding to a continuous high-level or low-level length. Different sub-sections may correspond to the same continuous high-level or low-level length, or different continuous high-level or low-level lengths. Each continuous high-level or low-level includes one or more chips.

[0234] In some embodiments, as shown in FIG6, each chip in the SIP corresponds to a chip length of M=6, and the sequence of the SIP is 101110. It can be considered that the SIP includes 3 sub-parts. In the first sub-part (10), the length of each consecutive high / low level is equal to the length of one chip of M=6. In the second sub-part (111), the length of each consecutive high level is equal to the length of 3 chips of M=6. In the third sub-part (0), the length of each consecutive low level is equal to the length of one chip of M=6.

[0235] Similarly, SIP in Figure 6 above can also be represented as 10(6)1(3)0(6).

[0236] In some embodiments, a SIP includes one or more sub-sections, each sub-section corresponding to a continuous high / low level length. A SIP includes at least one of the following sub-sections:

[0237] A high-level and / or low-level signal with a length equal to the chip length M=3;

[0238] A high-level and / or low-level signal with a length equal to the chip length M=6;

[0239] A high-level and / or low-level signal with a length equal to the chip length M=2;

[0240] A high-level and / or low-level signal with a length equal to four M=6 chip lengths;

[0241] A high-level and / or low-level signal with a length equal to three M=8 chip lengths;

[0242] A high-level and / or low-level signal with a length equal to three M=4 chip lengths;

[0243] A high-level and / or low-level signal with a length equal to 5 chips of M=8;

[0244] A high-level and / or low-level signal with a length equal to 7 M=8 chip lengths;

[0245] A high-level and / or low-level signal with a length equal to 5 M=12 chip lengths;

[0246] A high-level and / or low-level signal with a length equal to 7 M=12 chip lengths;

[0247] A high-level and / or low-level signal with a length equal to four M=9 chip lengths;

[0248] A high-level and / or low-level signal with a length equal to 5 chips of M=9;

[0249] A high-level and / or low-level signal with a length equal to 7 chips of M=9;

[0250] A high-level and / or low-level signal with a length equal to two M=9 chip lengths;

[0251] A high-level and / or low-level signal with a length equal to the chip length M=4.

[0252] In some embodiments, the SIP includes a high level and / or a low level with a chip length equal to M=3, and a high level and / or a low level with a chip length equal to M=6.

[0253] In some embodiments, SIP includes a high level and / or a low level with a length equal to 3 chips of M=8, and a high level and / or a low level with a length equal to 1 chip of M=4. For example: SIP=11000111(8), SIP=11001110(8)00111000(8).

[0254] In some embodiments, the sub-parts of the SIP are ordered sequentially according to the length of the consecutive high or low levels of each sub-part. For example, the sub-part with a shorter consecutive high or low level length precedes the sub-part with a longer consecutive high or low level length. For example: SIP = 101100(6)111000(6).

[0255] In some embodiments, the sub-parts of the SIP are ordered sequentially according to the length of their consecutive high or low levels. For example, a sub-part with a shorter consecutive high or low level follows a sub-part with a longer consecutive high or low level. For example: SIP = 111100(6).

[0256] The SIP includes at least one first continuous high level, which includes a high or low level corresponding to a chip length of M=3.

[0257] SIP patterns with M=2, 4, and 6 can refer to SIP patterns with M=4, 8, and 12, meaning the lengths of the high and low levels are the same, but the sequences are different. This is because 1 or 0 for M=2 is equivalent to 11 or 00 for M=4. Alternatively, patterns generated by sequences of M=3, 5, and 9 can be produced using M=6, 10, and 18. For example, 110011 for M=6 is equivalent to 101 for M=3, 1100110011 for M=10 is equivalent to 10101 for M=5, 1100111100 for M=10 is equivalent to 10110 for M=5, 1100110000 for M=10 is equivalent to 10100 for M=5, and 1100111100001100 for M=18 is equivalent to 10110010 for M=9, and so on.

[0258] In some embodiments, a first node (e.g., an A-IoT device) sends a signal to a second node (e.g., a base station), the signal including at least one of the following: a preamble, a midamble, and a postamble.

[0259] The pilot is located at the beginning of the signal, indicating the start of uplink transmission. The middle character is present in the uplink data and is used for SFO (sample frequency offset) estimation and / or channel estimation. The terminator is located at the end of the signal, indicating the end of uplink data transmission.

[0260] In some embodiments, the lengths of the preamble, midamble, and postamble are all 32.

[0261] In some embodiments, the length of both the preamble and postamble is 32. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0262] In some embodiments, the length of the preamble is 64. The length of the postamble is 32. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0263] In some embodiments, the length of the preamble is 64. The length of the postamble is 48. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0264] In some embodiments, the length of the preamble is 48. The length of the postamble is 48. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0265] In some embodiments, the length of the preamble is 48. The length of the postamble is 32. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0266] In some embodiments, the length of the preamble is 48. The length of the postamble is one of the following: {16, 24, 32, 40, 48}. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0267] In some embodiments, the length of the preamble is 64. The length of the postamble is one of the following: {16, 24, 32, 40, 48}. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0268] In some embodiments, the length of the preamble is 32. The length of the postamble is one of the following: {16, 24, 32}. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0269] For example, the length of a preamble and a postamble is 32. The length of a midamble is 16.

[0270] For example, the length of a preamble and a postamble is 32. The length of a midamble is 8.

[0271] In some embodiments, the lengths of the preamble, midamble, and postamble are all 16.

[0272] In some embodiments, the length of both the preamble and postamble is 16. The length of the midamble is one of the following: {4, 8, 12, 16}.

[0273] In some embodiments, the lengths of the preamble, midamble, and postamble are all 16.

[0274] In some embodiments, the length of both the preamble and postamble is 64. The length of the midamble is one of the following: {4, 8, 12, 16, 24, 32}.

[0275] In some embodiments, when the TBS of the uplink data is less than or equal to A, the signal contains a preamble but no midamble or postamble. When the TBS of the uplink data is greater than A and less than or equal to B, the signal contains a preamble and postamble but no midamble. When the TBS of the uplink data is greater than B, the signal contains a preamble, a postamble, and a midamble. In some embodiments, A = 16 or 17, B = 400 or 399. Or A = 16 or 17, B = 200 or 199.

[0276] In some embodiments, a midamble or postamble is inserted every 200 or 199 data bits.

[0277] This disclosure also provides a communication method applied to a second node, as shown in FIG7, which may include S701.

[0278] In S701, the second node sends a signal to the first node.

[0279] The signals transmitted by the second node include at least one of the following: a pilot section, a control section, and a data section. The pilot section includes a clock synchronization section, which is used to indicate the chip length of the control section and / or the chip length of the data section.

[0280] It should be noted that the descriptions of the pilot section, control section, and data section can be found in the above embodiments, and will not be repeated here.

[0281] In some embodiments, if the chip length of the control portion is different from the chip length of the data portion, and the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit located after the control portion, the chip length of the first padding bit being the same as the chip length of the control portion.

[0282] In other words, before transmitting the signal, the transmitting end can determine whether the end position of the control part in the signal is located at the last chip of an OFDM symbol, and if the end position of the control part is not located at the last chip of an OFDM symbol, a first padding bit is added after the control part in the signal.

[0283] In some embodiments, where the chip length of the control portion differs from the chip length of the data portion, and the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit following the control portion and a second padding bit following the first padding bit. The chip length of the first padding bit is the same as the chip length of the control portion, the chip length of the second padding bit is the same as the chip length of the data portion, the second padding bit comprises an odd number of chips, and the data portion is located after the second padding bit.

[0284] In other words, before transmitting the signal, the transmitting end can determine whether the end position of the control part in the signal is located at the last chip of an OFDM symbol. If the end position of the control part is not located at the last chip of an OFDM symbol, a first padding bit is added after the control part in the signal, and a second padding bit is added before the data part.

[0285] The following describes the communication method provided in the above embodiment, taking the interaction between the first node and the second node as an example, as shown in Figure 8, including S801 to S803.

[0286] In S801, the second node sends a signal to the first node.

[0287] In S802, the first node receives signals sent by the second node.

[0288] In S803, the first node determines the position of the control section and / or the position of the data section based on the position of the pilot section, and obtains information about the control section and / or the data section.

[0289] In summary, when considering the coexistence of A-IoT systems and New Radio (NR) systems, the design of the timing acquisition signal in the A-IoT system is the subject of this disclosure. The pilot signal comprises two parts: a start indication part, used by the device to determine the start of downlink transmission; and a clock synchronization part, used by the device to determine the length of a chip in the data or control section.

[0290] It is understood that, in order to achieve the above-mentioned functions, the communication device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the algorithmic steps of the examples described in conjunction with the embodiments of this disclosure, this disclosure can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0291] This disclosure embodiment can divide the communication device into functional modules according to the above method embodiment. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one functional module. The integrated module can be implemented in hardware or software. It should be noted that the module division in this disclosure embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the example of dividing each functional module according to each function.

[0292] Figure 9 is a block diagram of a communication device according to some embodiments. The communication device can be applied to a first node and execute the communication method shown in Figure 2 above, as well as the embodiment on the first node side in Figure 8. As shown in Figure 9, the communication device 900 includes a receiving module 901 and a processing module 902.

[0293] The receiving module 901 is configured to receive signals transmitted by the second node, the signals including at least one of the following: a pilot section, a control section, and a data section. The pilot section includes a clock synchronization section, which indicates the chip length of the control section and / or the chip length of the data section. The processing module 902 is configured to, based on the position of the pilot section, have the first node perform at least one of the following: determine the position of the control section and acquire information about the control section; determine the position of the data section and acquire information about the data section.

[0294] In some embodiments, the clock synchronization section includes a first section and a second section, wherein the chip length of the first section is the same as the chip length of the control section, and the chip length of the second section is the same as the chip length of the data section.

[0295] In some embodiments, the control portion and the data portion satisfy at least one of the following:

[0296] The chip length of the control section is greater than or equal to the chip length of the data section;

[0297] The multiple between the chip length of the control section and the chip length of the data section is less than a preset threshold;

[0298] The chip length of the control section is an integer multiple of the chip length of the data section.

[0299] In some embodiments, the first part and the second part satisfy at least one of the following:

[0300] The length of the first part of the chip is greater than or equal to the length of the second part of the chip;

[0301] The length of the first part of the chip is an integer multiple of the length of the second part of the chip;

[0302] The first part occupies an integer number of OFDM symbols;

[0303] The second part occupies an integer number of OFDM symbols;

[0304] The first and second parts together occupy an integer number of OFDM symbols;

[0305] The number of chips in the first part is the same as the number of chips in the second part;

[0306] The number of chips in the first part and the number of chips in the second part are both even numbers greater than 2.

[0307] In some embodiments, the multiple between the chip length of the first portion and the chip length of the second portion is less than a preset threshold.

[0308] In some embodiments, when the chip length of the first portion is equal to the chip length of the second portion, the second portion satisfies at least one of the following:

[0309] The number of chips in the second part is less than the number of chips in the first part;

[0310] All bits in the second part have the same binary value.

[0311] All bits in the second part are the same as the last bit in the first part;

[0312] All bits in the second part are the opposite of the last bit in the first part.

[0313] In some embodiments, the first part is positioned before the control part, and the second part is positioned before the data part.

[0314] In some embodiments, the clock synchronization portion includes: a first portion, the chip length of which is the same as the chip length of the control portion, the control portion including indication information for determining the chip length of the data portion.

[0315] In some embodiments, the chip length of the control section and the chip length of the data section each correspond to an M value, and the M value is used to indicate the number of chips in an Orthogonal Frequency Division Multiplexing (OFDM) symbol; the processing module 902 is used to determine the information of the control section based on the chip length of the first section; the processing module 902 is used to determine the set of candidate M values ​​corresponding to the data section based on the chip length of the first section; the processing module 902 is also used to determine the indication information indicating the chip length of the data section in the indication information of the control section based on the number of candidate values ​​contained in the set of candidate M values ​​corresponding to the data section; the processing module 902 is also used to determine the chip length of the data section based on the indication information and a preset correspondence; the processing module 902 is also used to determine the information of the data section based on the chip length of the data section.

[0316] In some embodiments, the candidate set of M values ​​corresponding to the data portion includes all candidate values ​​in a first preset candidate set that are greater than or equal to the M value corresponding to the control portion; or...

[0317] The set of candidate M values ​​corresponding to the data part includes a preset number of candidate values ​​that are greater than or equal to the M value corresponding to the control part and are adjacent to the M value corresponding to the control part in the first preset candidate set.

[0318] In some embodiments, the first preset candidate value set is {1, 2, 4, 6, 8, 12, 16, 24, 32}.

[0319] In some embodiments, if the chip length of the control portion is different from the chip length of the data portion, and the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit located after the control portion, the chip length of the first padding bit being the same as the chip length of the control portion.

[0320] In some embodiments, where the chip length of the control portion differs from the chip length of the data portion, and the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit following the control portion and a second padding bit following the first padding bit; or,

[0321] When the chip length of the control section is different from that of the data section, and the end position of the control section is located at the last chip of an OFDM symbol, the signal also includes a second padding bit located after the control section.

[0322] The chip length of the first padding bit is the same as the chip length of the control section, and the chip length of the second padding bit is the same as the chip length of the data section. The second padding bit includes an odd number of chips, and the data section is located after the second padding bit.

[0323] In some embodiments, the pilot section further includes a start indication section for indicating the start of downlink transmission.

[0324] In some embodiments, the start indication portion includes one or more sub-parts, one of which corresponds to an M value, the M value of which is the ratio between the chip length of the sub-part and the length of an OFDM symbol.

[0325] In some embodiments, the M value of the sub-part is any candidate value in a second preset candidate set, which is {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12}.

[0326] In some embodiments, at least two of the multiple sub-parts have M values ​​that are not divisible by each other.

[0327] In some embodiments, at least one of the plurality of sub-parts is represented by any one of the following:

[0328] “100(3)”, where each bit in 100 corresponds to a chip length level with an M value of 3;

[0329] “10(4)”, where each bit in 10 corresponds to a chip length level with an M value of 4;

[0330] “1000(4)”, where each bit in 1000 corresponds to a chip length level with an M value of 4;

[0331] “110010(6)”, each bit in 110010 corresponds to a chip length level with an M value of 6;

[0332] “101100(6)”, each bit in 101100 corresponds to a chip length level with an M value of 6;

[0333] “11100010(8)”, each bit in 11100010 corresponds to a level with an M value of 8 chip length;

[0334] “10111000(8)”, each bit in 10111000 corresponds to a level with an M value of 8 and a chip length;

[0335] “110000(12)”, each bit in 110000 corresponds to a chip length level with an M value of 12;

[0336] “110010(12)”, each bit in 110010 corresponds to a chip length level with an M value of 12;

[0337] “101100(12)”, each bit in 101100 corresponds to a chip length level with an M value of 12;

[0338] “101100111000(12)”, each bit in 101100111000 corresponds to a chip length level with an M value of 12;

[0339] “111000110010(12)”, each bit in 111000110010 corresponds to a chip length level with an M value of 12;

[0340] “010(6)”, where each bit in 010 corresponds to a chip length level with an M value of 6;

[0341] “101(6)”, where each bit in 101 corresponds to a chip length level with an M value of 6;

[0342] “10(2)”, where each bit in 10 corresponds to a chip length of M with a value of 2;

[0343] “10(3)”, where each bit in 10 corresponds to a chip length level with an M value of 3;

[0344] “111000(6)”, each bit in 111000 corresponds to a chip length level with an M value of 6;

[0345] “1010(3)”, where each bit in 1010 corresponds to a chip length level with an M value of 3;

[0346] “1010(6)”, where each bit in 1010 corresponds to a chip length of M with a value of 6.

[0347] In some embodiments, where the start indication portion comprises multiple sub-portions, the start indication portion is represented by any of the following:

[0348] “10(3)10(6)”, each bit in 10 corresponds to a chip length level with an M value of 3, and each bit in 10 corresponds to a chip length level with an M value of 6;

[0349] “10(4)010(6)”, each bit in 10 corresponds to a chip length level with an M value of 4, and each bit in 010 corresponds to a chip length level with an M value of 6;

[0350] “101(6)10(4)”, where each bit in 101 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4;

[0351] “110011010(6)10(4)”, each bit in 110011010 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4.

[0352] “111000110(6)10(4)”, each bit in 111000110 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4.

[0353] “101(6)100100(4)”, each bit in 101 corresponds to a chip length level with an M value of 6, and each bit in 100100 corresponds to a chip length level with an M value of 4.

[0354] In some embodiments, the starting indication portion occupies an integer number of OFDM symbols.

[0355] Figure 10 is a block diagram of another communication device according to some embodiments. The communication device can be applied to a second node and execute the communication method shown in Figure 7 above, as well as the embodiment on the second node side in Figure 8. As shown in Figure 10, the communication device 1000 includes: a transmitting module 1001.

[0356] The transmitting module 1001 is used to transmit signals to the first node. The signals include at least one of the following: a pilot section, a control section, and a data section. The pilot section includes a clock synchronization section, which is used to indicate the chip length of the control section and / or the chip length of the data section.

[0357] In some embodiments, if the chip length of the control portion is different from the chip length of the data portion, and the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit located after the control portion, the chip length of the first padding bit being the same as the chip length of the control portion.

[0358] In some embodiments, when the chip length of the control portion is different from the chip length of the data portion and the end position of the control portion is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit after the control portion and a second padding bit after the first padding bit; or, when the chip length of the control portion is different from the chip length of the data portion and the end position of the control portion is located at the last chip of an OFDM symbol, the signal further includes a second padding bit after the control portion.

[0359] The chip length of the first padding bit is the same as the chip length of the control section, and the chip length of the second padding bit is the same as the chip length of the data section. The second padding bit includes an odd number of chips, and the data section is located after the second padding bit.

[0360] In the case of implementing the functions of the integrated modules described above in hardware, this disclosure provides another block diagram of the communication device involved in the above embodiments. As shown in FIG11, the communication device 1100 includes: a processor 1102 and a bus 1104. In some embodiments, the communication device may further include a memory 1101; in some embodiments, the communication device may further include a communication interface 1103.

[0361] Processor 1102 may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with embodiments of this disclosure. Processor 1102 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with embodiments of this disclosure. Processor 1102 may also be a combination of functions implementing computation, such as a combination of one or more microprocessors, a digital signal processor (DSP), and a microprocessor, etc.

[0362] Communication interface 1103 is used to connect to other devices via a communication network. This communication network can be Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0363] The memory 1101 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0364] In one implementation, the memory 1101 may exist independently of the processor 1102. The memory 1101 can be connected to the processor 1102 via a bus 1104 and is used to store instructions or program code. When the processor 1102 calls and executes the instructions or program code stored in the memory 1101, it can implement the communication method provided in the embodiments of this disclosure.

[0365] In another implementation, memory 1101 can also be integrated with processor 1102.

[0366] Bus 1104 can be an extended industry standard architecture (EISA) bus, etc. Bus 1104 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in Figure 11, but this does not mean that there is only one bus or one type of bus.

[0367] Some embodiments of this disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) storing computer program instructions that, when executed on a computer, cause the computer to perform the communication method as described in any of the above embodiments.

[0368] In some embodiments, the computer-readable storage media described above may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this disclosure may represent one or more devices for storing information and / or other machine-readable storage media. The term "machine-readable storage media" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0369] This disclosure provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the communication method described in any of the above embodiments.

[0370] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A communication method, comprising: The first node receives a signal sent by the second node, the signal including at least one of the following: a pilot section, a control section, and a data section, the pilot section including: a clock synchronization section, the clock synchronization section being used to indicate the chip length of the control section and / or the chip length of the data section; Based on the location of the pilot portion, the first node performs at least one of the following: Determine the location of the control unit and obtain information about the control unit; The location of the data portion is determined, and information about the data portion is obtained.

2. The method according to claim 1, wherein, The clock synchronization section includes a first section and a second section, wherein the chip length of the first section is the same as the chip length of the control section, and the chip length of the second section is the same as the chip length of the data section.

3. The method according to claim 1, wherein, The control section and the data section satisfy at least one of the following: The chip length of the control section is greater than or equal to the chip length of the data section; The multiple between the chip length of the control section and the chip length of the data section is less than a preset threshold. The chip length of the control section is an integer multiple of the chip length of the data section.

4. The method according to claim 2, wherein, The first part and the second part satisfy at least one of the following: The chip length of the first part is greater than or equal to the chip length of the second part; The chip length of the first part is an integer multiple of the chip length of the second part; The first part occupies an integer number of Orthogonal Frequency Division Multiplexing (OFDM) symbols; The second part occupies an integer number of OFDM symbols; The first part and the second part together occupy an integer number of OFDM symbols; The number of chips in the first part is the same as the number of chips in the second part; The number of chips in the first part and the number of chips in the second part are both even numbers greater than 2.

5. The method according to claim 4, wherein, The multiple between the chip length of the first part and the chip length of the second part is less than a preset threshold.

6. The method according to claim 4, wherein, When the chip length of the first portion is equal to the chip length of the second portion, the second portion satisfies at least one of the following: The number of chips in the second part is less than the number of chips in the first part; All bits in the second part have the same binary value; All bits in the second part are the same as the last bit in the first part; All bits in the second part are the opposite of the last bit in the first part.

7. The method according to claim 2, wherein, The first part is located before the control part, and the second part is located before the data part.

8. The method according to claim 1, wherein, The clock synchronization section includes: a first section, wherein the chip length of the first section is the same as the chip length of the control section, and the control section includes indication information for determining the chip length of the data section.

9. The method according to claim 8, wherein, The chip length of the control section and the chip length of the data section each correspond to an M value, and the M value is used to indicate the number of chips in an orthogonal frequency division multiplexing (OFDM) symbol. Based on the position of the pilot section, the first node performs the following steps: determining the position of the control section and obtaining information about the control section. Based on the chip length of the first part, determine the information of the control part; Based on the position of the pilot portion, the first node performs the process of determining the position of the data portion and obtaining information about the data portion, including: Based on the chip length of the first part, determine the set of candidate M values ​​corresponding to the data part; Based on the number of candidate values ​​contained in the candidate M value set corresponding to the data portion, determine the indication information in the indication information of the control portion that indicates the chip length of the data portion; The chip length of the data portion is determined based on the indicated information and the preset correspondence. The information of the data portion is determined based on the chip length of the data portion.

10. The method according to claim 9, wherein, The set of candidate M values ​​corresponding to the data portion includes all candidate values ​​in the first preset candidate set that are greater than or equal to the M value corresponding to the control portion. or, The set of candidate M values ​​corresponding to the data portion includes a preset number of candidate values ​​from the first preset candidate set that are greater than or equal to the M value corresponding to the control portion and are adjacent to the M value corresponding to the control portion.

11. The method according to claim 10, wherein, The first preset candidate value set is {1, 2, 4, 6, 8, 12, 16, 24, 32}.

12. The method according to claim 1, wherein, If the chip length of the control section is different from the chip length of the data section, and the end position of the control section is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit located after the control section, the chip length of the first padding bit being the same as the chip length of the control section.

13. The method according to claim 1, wherein, If the chip length of the control section is different from the chip length of the data section, and the end position of the control section is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit after the control section and a second padding bit after the first padding bit; or, If the chip length of the control section is different from the chip length of the data section, and the end position of the control section is located at the last chip of an OFDM symbol, the signal further includes a second padding bit located after the control section. Wherein, the chip length of the first padding bit is the same as the chip length of the control section, the chip length of the second padding bit is the same as the chip length of the data section, the second padding bit includes an odd number of chips, and the data section is located after the second padding bit.

14. The method according to claim 1, wherein, The pilot section further includes a start indication section, which is used to indicate the start of downlink transmission.

15. The method according to claim 14, wherein, The start indication portion includes one or more sub-parts, one of which corresponds to an M value, wherein the M value of the sub-part is the ratio between the chip length of the sub-part and the length of an OFDM symbol.

16. The method according to claim 15, wherein, The M value of the sub-part is any candidate value in the second preset candidate set, which is {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12}.

17. The method according to claim 15, wherein, The start indication portion includes multiple sub-parts, and at least two of the multiple sub-parts have M values ​​that are not divisible by each other.

18. The method according to claim 15, wherein, The start indication portion includes a plurality of sub-parts, at least one of which is represented by any one of the following: "100(3)", each bit in 100 corresponds to a chip length level with an M value of 3; "10(4)", each bit in 10 corresponds to a chip length level with an M value of 4; "1000(4)", each bit in 1000 corresponds to a chip length level with an M value of 4; "110010(6)", each bit in 110010 corresponds to a chip length level with an M value of 6; "101100(6)", each bit in 101100 corresponds to a chip length level with an M value of 6; "11100010(8)", each bit in 11100010 corresponds to a chip length level with an M value of 8; "10111000(8)", each bit in 10111000 corresponds to a chip length level with an M value of 8; "110000(12)", each bit in 110000 corresponds to a chip length level with an M value of 12; "110010(12)", each bit in 110010 corresponds to a chip length level with an M value of 12; "101100(12)", each bit in 101100 corresponds to a chip length level with an M value of 12; "101100111000(12)", each bit in 101100111000 corresponds to a chip length level with an M value of 12; "111000110010(12)", each bit in 111000110010 corresponds to a chip length level with an M value of 12; "010(6)", each bit in 010 corresponds to a chip length level with an M value of 6; "101(6)", where each bit in 101 corresponds to a chip length level with an M value of 6; "10(2)", each bit in 10 corresponds to a chip length level with an M value of 2; "10(3)", each bit in 10 corresponds to a chip length level with an M value of 3; "111000(6)", each bit in 111000 corresponds to a chip length level with an M value of 6; "1010(3)", each bit in 1010 corresponds to a chip length level with an M value of 3; "1010(6)", each bit in 1010 corresponds to a chip length of M with a value of 6.

19. The method according to claim 15, wherein, When the start indication portion comprises multiple sub-parts, the start indication portion is represented by any of the following: "10(3)10(6)", each bit in 10 corresponds to a chip length level with an M value of 3, and each bit in 10 corresponds to a chip length level with an M value of 6; "10(4)010(6)", each bit in 10 corresponds to a chip length level with an M value of 4, and each bit in 010 corresponds to a chip length level with an M value of 6; "101(6)10(4)", in 101 each bit corresponds to a chip length level with an M value of 6, and in 10 each bit corresponds to a chip length level with an M value of 4; "110011010(6)10(4)", each bit in 110011010 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4; "111000110(6)10(4)", each bit in 111000110 corresponds to a chip length level with an M value of 6, and each bit in 10 corresponds to a chip length level with an M value of 4; "101(6)100100(4)", each bit in 101 corresponds to a chip length level with an M value of 6, and each bit in 100100 corresponds to a chip length level with an M value of 4.

20. The method of claim 14, wherein, The start indication portion occupies an integer number of OFDM symbols.

21. A communication method, comprising: The second node sends a signal to the first node, the signal including at least one of the following: a pilot section, a control section, and a data section, the pilot section including: a clock synchronization section, the clock synchronization section being used to indicate the chip length of the control section and / or the chip length of the data section.

22. The method according to claim 21, wherein, If the chip length of the control section is different from the chip length of the data section, and the end position of the control section is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit located after the control section, the chip length of the first padding bit being the same as the chip length of the control section.

23. The method according to claim 21, wherein, If the chip length of the control section is different from the chip length of the data section, and the end position of the control section is not located at the last chip of an OFDM symbol, the signal further includes a first padding bit after the control section and a second padding bit after the first padding bit; or, If the chip length of the control section is different from the chip length of the data section, and the end position of the control section is located at the last chip of an OFDM symbol, the signal further includes a second padding bit located after the control section. Wherein, the chip length of the first padding bit is the same as the chip length of the control section, the chip length of the second padding bit is the same as the chip length of the data section, the second padding bit includes an odd number of chips, and the data section is located after the second padding bit.

24. A communication device, comprising: Memory and processor; The memory and the processor are coupled; The memory is used to store instructions that can be executed by the processor; When the processor executes the instructions, it performs the method according to any one of claims 1-23.

25. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer instructions that, when executed on a computer, cause the computer to perform the method according to any one of claims 1-23.

26. A computer program product, wherein, The computer program product includes computer program instructions that, when executed, implement the method according to any one of claims 1-23.

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