Optical module

Abstract

An optical module provided by the present disclosure comprises a circuit board, an optical receiver chip, a TIA chip, a signal processing chip, and an MCU. The signal processing chip comprises a channel configuration register. The MCU comprises a control pin, the control pin being electrically connected to the signal processing chip. When the MCU detects for the first time that a clock signal offset recovered by the signal processing chip is lower than a preset threshold during a power-on process of the optical module, the MCU writes a first register value into the channel configuration register by means of the control pin, so as to disable the signal processing chip receiving a photovoltage signal output by the TIA chip. After a preset period of time, a second register value is written into the channel configuration register by means of the control pin, so as to start the signal processing chip receiving the photovoltage signal output by the TIA chip. When the signal processing chip is locked for the first time, the MCU actively intervenes so as to forcibly interrupt a receiving link of the signal processing chip, thereby effectively isolating a signal instability period during the power-on process, such that the signal processing chip is locked back into a more stable parameter.

Description

optical module

[0001] This application claims priority to Chinese Patent Application No. 202511232540.7, filed on August 29, 2025; and to Chinese Patent Application No. 202411570986.6, filed on November 5, 2024; the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of optical communication technology, and in particular to an optical module. Background Technology

[0003] With the development of new business and application models such as cloud computing, mobile internet, and video, the advancement of optical communication technology has become increasingly important. In optical communication technology, optical modules are the tools for converting between photoelectric signals and signals, and are one of the key components in optical communication equipment. Furthermore, with the evolving needs of optical communication technology, the transmission rate of optical modules is constantly increasing. Summary of the Invention

[0004] Some embodiments provide an optical module that ensures that the signal processing chip locks onto a stable signal during power-up.

[0005] Some embodiments provide an optical module comprising:

[0006] Circuit board;

[0007] An optical receiver chip, electrically connected to the circuit board, is used to convert the received optical signal into a photocurrent signal;

[0008] The TIA chip, electrically connected to the optical receiver chip, is used to convert the photocurrent signal into a photovoltage signal and amplify the photovoltage signal; when the photocurrent signal intensity is lower than a preset threshold, the TIA chip detects a LOS state; when the photocurrent signal intensity is higher than the preset threshold, the TIA chip detects that the LOS state has been cleared.

[0009] A signal processing chip is disposed on the surface of the circuit board and electrically connected to the TIA chip to receive the photovoltage signal output by the TIA chip; the signal processing chip includes a channel configuration register, wherein when the register value is a first register value, it indicates that the signal receiving channel of the signal processing chip is closed; when the register value is a second register value, it indicates that the signal receiving channel of the signal processing chip is opened; the signal processing chip is used to acquire signal quality parameters to monitor the input signal quality;

[0010] The MCU includes control pins, which are electrically connected to the signal processing chip and are configured as follows:

[0011] When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-up process of the optical module, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip.

[0012] After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip;

[0013] Alternatively, the MCU is configured as follows:

[0014] When the LOS status reported by the TIA chip is cleared for the first time during the power-on process of the optical module, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip;

[0015] After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip;

[0016] Alternatively, the MCU is configured as follows:

[0017] When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read.

[0018] When the signal quality parameter is lower than the preset quality parameter, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip;

[0019] Then, when the signal quality parameter is higher than the preset quality parameter, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the optical voltage signal output by the TIA chip;

[0020] Alternatively, the MCU is configured as follows:

[0021] When the LOS status reported by the TIA chip is initially read during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read.

[0022] When the signal quality parameter is lower than the preset quality parameter, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip;

[0023] When the signal quality parameter is higher than the preset quality parameter, a second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the optical voltage signal output by the TIA chip;

[0024] The MCU includes a first register for storing a first preset value written by a host computer. This first preset value instructs the MCU to acquire the register value of a target register within the signal processing chip. The target register includes multiple registers, including a channel configuration register. The MCU is configured to: in response to the first preset value in the first register, acquire the register value of the target register and store it in a first protocol area for the host computer to read. The register value includes either the first register value or a second register value; and / or...

[0025] The MCU includes a second register for storing preset debugging commands written by a host computer. These preset debugging commands instruct the signal processing chip to adjust or acquire its parameters. The MCU is configured to: respond to the preset debugging commands in the second register by sending the preset debugging commands to the signal processing chip, causing the signal processing chip to adjust or acquire its parameters based on the preset debugging commands, and feeding back the execution results to the MCU; and receive the execution results fed back by the signal processing chip and store them in the second register, so that the host computer can read the execution results from the second register. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 is a partial structural diagram of an optical communication system provided according to some embodiments of the present disclosure;

[0028] Figure 2 is a partial structural diagram of a host computer provided according to some embodiments of the present disclosure;

[0029] Figure 3 is a structural diagram of an optical module provided according to some embodiments of the present disclosure;

[0030] Figure 4 is an exploded view of an optical module provided according to some embodiments of the present disclosure;

[0031] Figure 5 is a schematic diagram of an optical receiving component structure provided according to some embodiments of the present disclosure;

[0032] Figure 6 is a schematic diagram of the electrical connection between a TIA chip and a signal processing chip according to some embodiments of the present disclosure;

[0033] Figure 7 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure;

[0034] Figure 8 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure;

[0035] Figure 9 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure;

[0036] Figure 10 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure;

[0037] Figure 11 is an internal structural diagram of an optical module provided according to some embodiments of the present disclosure;

[0038] Figure 12 is an internal circuit diagram of an optical module provided according to some embodiments of the present disclosure;

[0039] Figure 13 is a schematic diagram of the structure of an MCU according to some embodiments of the present disclosure;

[0040] Figure 14 is a register value management table provided according to some embodiments of the present disclosure;

[0041] Figure 15 is a schematic diagram of another MCU structure provided according to some embodiments of the present disclosure;

[0042] Figure 16 is a flowchart of a control method provided according to some embodiments of the present disclosure. Detailed Implementation

[0043] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0045] In optical communication technology, to establish information transmission between information processing devices, information is loaded onto light, and the speed of light propagation is used to transmit the information. This light carrying information is called an optical signal. When optical signals are transmitted in optical information transmission equipment, optical power loss can be reduced, enabling long-distance transmission of optical signals. At the same time, the cost of optical information transmission equipment such as optical fibers is lower than that of electrical information transmission equipment such as copper wires. Therefore, optical communication technology can achieve high-speed, long-distance, and low-cost information transmission.

[0046] Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., while optical information transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can only recognize and process electrical signals, while optical communication technology uses optical signals for transmission, requiring optical modules to convert between optical and electrical signals.

[0047] An optical module enables the conversion between optical signals and electrical signals between information processing equipment and optical information transmission equipment. In some embodiments, at least one of the optical signal input or output terminals of the optical module is connected to an optical fiber, and at least one of the electrical signal input or output terminals of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber.

[0048] Since multiple information processing devices can transmit information via electrical signals, at least one of these devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is also referred to as the host computer of the optical module. Furthermore, the optical signal input or output terminal of the optical module is called the optical port, and the electrical signal input or output terminal is called the electrical port.

[0049] Figure 1 is a partial structural diagram of an optical communication system provided according to some embodiments of the present disclosure. As shown in Figure 1, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100 for optical modules, an optical module 200, an optical fiber 101, and a network cable 103, wherein the optical fiber 101 is an optical information transmission device, and the network cable 103 is an electrical information transmission device.

[0050] In some embodiments, one end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can undergo total internal reflection in the optical fiber 101, and the propagation of the optical signal in the direction of total internal reflection can almost maintain the original optical power. The optical signal undergoes multiple total internal reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance information transmission based on low power loss.

[0051] The optical communication system includes one or more optical fibers 101. In some embodiments, the optical fiber 101 is detachably connected to the optical module 200; in some embodiments, the optical fiber 101 is non-detachably connected to the optical module 200.

[0052] The host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor or control the working status of the optical module 200.

[0053] The host computer 100 includes a housing for accommodating the optical module 200, and an optical module interface 102 disposed on the housing. The optical module 200 is inserted into the housing through the optical module interface 102 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0054] The host computer 100 also includes an external power interface that can connect to an electrical signal network. In some embodiments, the external power interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to connect a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103.

[0055] One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the host computer 100, so as to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. In some embodiments, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted in the optical fiber 101 to the remote information processing device 1000.

[0056] In some embodiments, a first optical signal from a remote information processing device 1000 is transmitted through an optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to an optical module 200. The optical module 200 converts the first optical signal into a first electrical signal, and transmits the first electrical signal to a host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to a local information processing device 2000.

[0057] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0058] In addition to optical network terminals, the host computer 100 also includes optical line terminals (OLTs), optical network equipment (ONTs), or data center servers.

[0059] Figure 2 is a partial structural diagram of a host computer according to some embodiments of the present disclosure. To clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 only shows the structure of the host computer 100 related to the optical module 200. As shown in Figure 2, in some embodiments, the host computer 100 further includes a PCB circuit board 105 disposed within a receiving cavity, and a cage 106 disposed on the surface of the PCB circuit board 105; the optical module 200 is inserted into the cage 106 and fixed by the cage 106.

[0060] In some embodiments, a heat sink 107 is provided on the cage 106 to dissipate heat for the optical module; in some embodiments, the heat sink 107 has protruding structures such as fins to increase the heat dissipation area.

[0061] In some embodiments, an electrical connector is provided inside the cage 106, which is configured to connect to the electrical port of the optical module 200.

[0062] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 106 and then diffused through the heat sink 107.

[0063] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, thereby establishing an electrical signal connection between the optical module 200 and the host computer 100.

[0064] In some embodiments, the optical port of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0065] Figure 3 is a structural diagram of an optical module according to some embodiments of the present disclosure, and Figure 4 is an exploded view of an optical module according to some embodiments of the present disclosure. As shown in Figures 3 and 4, in some embodiments, the optical module 200 includes a shell, which includes an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming two openings 204 and 205, one of which is an electrical port and the other is an optical port. In some embodiments, the shell forms an opening that serves as both an electrical port and an optical port.

[0066] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0067] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc. into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the above-mentioned devices.

[0068] The direction of the line connecting the two openings 204 and 205 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200 (right end in Figure 3), and opening 205 is also located at the end of the optical module 200 (left end in Figure 3). Alternatively, opening 204 is located at the end of the optical module 200, while opening 205 is located on the side of the optical module 200.

[0069] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0070] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0071] As shown in Figures 3 and 4, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips. The electronic components and chips are connected according to the circuit design through the circuit traces to achieve functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0072] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into an electrical connector in the cage 106 of the host computer 100.

[0073] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0074] In some embodiments, the circuit board further includes gold fingers formed on its end surface, the gold fingers consisting of a plurality of independent pins.

[0075] In some implementations, the gold fingers 301 are disposed on one side of the surface of the circuit board 300 (e.g., the upper surface shown in Figure 4); in some implementations, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to applications with a large number of pins required.

[0076] In some implementations, the gold fingers of the circuit board extend from the opening 204 and are inserted into the electrical connector of the host computer 100; the circuit board is inserted into the cage 106, and the gold fingers 301 are connected to the electrical connector inside the cage 106. The gold fingers 301 are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0077] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0078] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 106.

[0079] In some embodiments, the optical module includes a light emitting component 400.

[0080] In some embodiments, the optical module includes an optical receiving component 500.

[0081] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold finger 301.

[0082] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0083] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0084] Figure 5 is a schematic diagram of an optical receiving component structure according to some embodiments of the present disclosure. As shown in Figure 5, in some embodiments, the optical receiving component 500 may include an optical receiving chip 510, which is used to convert the received optical signal into a photocurrent signal.

[0085] In some embodiments, the light receiving component 500 may include a TIA chip 520. The TIA chip 520 is electrically connected to the light receiving chip 510 and is used to receive the photocurrent signal output by the light receiving chip 510, convert the photocurrent signal into a photovoltage signal, and amplify the photovoltage signal.

[0086] In some embodiments, a signal processing chip (also known as a DSP) 302 is provided on the surface of the circuit board 300. The signal processing chip 302 is electrically connected to the TIA chip 520. The photovoltage signal amplified by the TIA chip 520 is transmitted to the signal processing chip 302, where the signal processing chip 303 performs signal processing, such as dispersion compensation.

[0087] In some embodiments, a clock and data recovery (CDR) circuit is provided on the surface of the circuit board 300. The CDR circuit can recover high-quality data signals from received distorted electrical signals through a precise clock recovery and data retiming mechanism, thereby improving the stability and accuracy of electrical signal transmission.

[0088] In some embodiments, the CDR circuit may exist independently of the signal processing chip 302 or may be integrated into the signal processing chip 302. For example, if the CDR circuit is integrated into the signal processing chip 302, then the signal processing chip 302 includes both the CDR circuit and the signal processing circuit.

[0089] Figure 6 is a schematic diagram of the electrical connection between a TIA chip and a signal processing chip according to some embodiments of the present disclosure. As shown in Figure 6, in some embodiments, the TIA chip 520 is electrically connected to the signal processing chip 302.

[0090] In some embodiments, the signal processing chip 302 may include a CDR circuit 3021 to recover clock signals and data signals.

[0091] In some embodiments, the signal processing chip 302 may include a signal processing circuit 3022 to further process the recovered data signal.

[0092] In some embodiments, the input terminal of the CDR circuit 3021 is electrically connected to the TIA chip 520, and the output terminal is electrically connected to the signal processing circuit 3022. The CDR circuit 3021 is located between the TIA 520 and the signal processing circuit 3022. The CDR circuit 3021 receives electrical signals from the TIA 520 and extracts clock signals from the transition edges of the electrical signals. Based on the clock signals, the input electrical signals are sampled to generate low-jitter, low-noise data signals. Then, the CDR circuit 3021 outputs the recovered digital signals and clock signals and transmits them to the signal processing circuit 3022 for further data processing.

[0093] In some embodiments, the TIA chip 520 includes a Loss of Signal (LOS) detection circuit to report and resolve LOS status. The LOS detection circuit monitors the signal strength of the input photocurrent signal or the signal strength of the output photovoltage signal and compares it with a preset threshold to report the LOS status and its resolution.

[0094] In some embodiments, the LOS detection circuit includes an LOS pin, which outputs high and low level command signals to indicate the LOS state or LOS state cancellation by controlling the LOS pin. When the LOS detection circuit detects that the intensity of the input photocurrent signal is lower than a preset threshold, the LOS pin outputs a low level command signal to indicate that the current state is LOS, thus realizing LOS state reporting. When the LOS detection circuit detects that the input photocurrent signal is higher than a preset threshold, the LOS pin outputs a high level command signal to indicate that the current state is LOS state cancellation, thus realizing LOS state cancellation reporting.

[0095] In some embodiments, the TIA chip 520 has an internal status register, and one or more specific status register bits are allocated in the register mapping space of the interface. The LOS detection circuit updates the register value of the status register in real time to indicate whether the current state is LOS or LOS is cleared. For example, when the LOS detection circuit detects that the intensity of the input photocurrent signal is lower than a preset threshold, the LOS detection circuit writes a first register value, such as "1", into the status register to indicate that the current state is LOS, thus realizing LOS status reporting. When the LOS detection circuit detects that the intensity of the input photocurrent signal is higher than the preset threshold, the LOS detection circuit writes a second register value, such as "0", into the status register to indicate that the current state is LOS cleared, thus realizing LOS cleared reporting.

[0096] In some embodiments, the TIA chip 520 reports the LOS state being released and begins inputting electrical signals to the signal processing chip 302. When the polling signal arrives at the signal processing chip 302, the CDR circuit 3021 extracts the clock signal from the electrical signal and re-timing the data signal, locking the timing synchronization between the clock signal and the input signal, completing the signal locking. The CDR circuit 3021 reports the locked state, which means that the CDR circuit 3021 has successfully tracked the frequency and phase of the input data signal, and the timing relationship between the recovered local clock signal and the input signal remains stable and synchronized.

[0097] In some embodiments, the CDR circuit 3021 may fail to lock the clock signal frequency and phase, posing a risk of loss of lock (LOL). When the CDR circuit 3021 loses lock, it cannot stably track and lock the clock information in the input data stream, resulting in the inability to extract the correct clock signal from the data, and consequently, the recovered clock signal may be out of sync with the input data or completely lost.

[0098] In some embodiments, the CDR circuit 3021 integrates a phase-locked loop (PLL) state monitoring circuit, which can compare and recover the timing relationship between the clock signal and the input data signal in real time. When the PLL state monitoring circuit detects that the clock signal offset exceeds a preset threshold, the CDR circuit 3021 automatically determines that the state is in a loss-of-lock (LOL) state. When the PLL state monitoring circuit detects that the clock signal offset is below the preset threshold, the CDR circuit 3021 automatically determines that the LOL state is released, i.e., the locked state.

[0099] In some embodiments, the CDR circuit 3021 includes an LOL pin. When the phase-locked loop (PLL) state monitoring circuit detects that the clock signal offset exceeds a preset threshold, the LOL pin of the CDR circuit 3021 outputs a low-level command signal, indicating that the current state is LOL, thus reporting the LOL state. When the PLL state monitoring circuit detects that the clock signal offset is below the preset threshold, the LOL pin of the CDR circuit 3021 outputs a high-level command signal, indicating that the current state is LOL state released, thus reporting the LOL state release.

[0100] In some embodiments, the CDR circuit 3021 has an internal status register, and one or more specific status register bits are allocated in the register mapping space of the interface. The phase-locked loop (PLL) status monitoring circuit updates the register value of the status register in real time to indicate whether the current state is LOL (Loss-Oriented) or LOL state is released. For example, when the PLL status monitoring circuit detects that the clock signal offset exceeds a preset threshold, the PLL status monitoring circuit writes a first register value, such as "1", into the status register to indicate that the current state is LOL, thus reporting the LOL state. When the PLL status monitoring circuit detects that the clock signal offset is below the preset threshold, the PLL status monitoring circuit writes a second register value, such as "0", into the status register to indicate that the current state is LOL state released, thus reporting the LOL state release.

[0101] In some embodiments, when the CDR circuit 3021 is in a locked state for the first time, the signal processing chip 302 establishes a link connection with its preceding and following circuits. For example, when the optical module is powered on, the TIA chip 520 reports the LOS state being released, the CDR circuit 3021 is in a locked state for the first time, and the CDR circuit 3021 reports the LOL state being released, at which point the signal processing chip 302 establishes a link connection with its preceding and following circuits. The initial locking state of the CDR circuit 3021 can serve as a marker for establishing a link connection.

[0102] In some embodiments, when the optical module is powered on, the optical signal input to the optical receiver chip 510 is unstable or of poor quality. This causes the CDR circuit 3021 to lock into operation under poor signal parameters when it first locks in, which in turn causes the entire receiver link to be in a state of high bit error rate. Long-term operation may lead to problems such as link interruption.

[0103] In some embodiments, the surface of the circuit board 300 is provided with an MCU 303.

[0104] In some embodiments, the MCU303 can poll the high / low level status of the LOS pin of the TIA chip 520 or the register value of the internal status register, thereby polling the LOS status or the LOS status being released.

[0105] In some embodiments, the MCU303 can poll the high or low level state of the LOL pin of the CDR circuit 3021 or the register value of the internal status register, thereby polling to read the LOL state or the LOL state being released.

[0106] In some embodiments, the signal processing chip 302 has an internal channel configuration register, in which one or more specific status register bits are allocated in the register mapping space of the interface. By writing different register values ​​into the channel configuration register, the MCU 302 can control the signal processing chip to turn off or on the reception of the TIA chip's output electrical signals.

[0107] In some embodiments, MCU303 may include a control pin, and MCU302 is electrically connected to signal processing chip 302 through the control pin. When MCU303 writes a first register value to the channel configuration register through the control pin, it sends a forced suppression command to the receive channel enable terminal of signal processing chip 302, actively intervening to forcibly interrupt the receive link of signal processing chip, temporarily shutting down signal processing chip 302's reception of the photovoltage signal output by TIA chip 520, and entering a forced suppression state. Exemplarily, in response to the first register value of the channel configuration register, signal processing chip 302 causes the signal receive channel to enter a high-impedance state, thereby shutting down signal processing chip 302's reception of the photovoltage signal output by TIA chip 520.

[0108] In some embodiments, when the MCU302 writes the second register value to the channel configuration register through the control pin, it sends a decompression command to the receive channel enable terminal of the signal processing chip 302 to enable the signal processing chip 302 to receive the photovoltage signal output by the TIA chip 520. Signal reception is restored, and the chip enters the decompression state.

[0109] In some embodiments, during the power-up process of the optical module, when the signal processing chip 302 initially locks, if the MCU 303 detects for the first time that the clock signal offset recovered by the signal processing chip 302 is lower than a preset threshold, the MCU 303 actively and forcibly interrupts the receiving link of the signal processing chip 302 to effectively isolate the period of signal instability. When the signal input is restored, the signal processing chip 302 re-establishes the lock under a stable signal state.

[0110] Figure 7 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure. As shown in Figure 7, in some embodiments, the control of the signal processing chip locking mechanism may include:

[0111] S110: When the clock signal offset recovered by the signal processing chip is detected to be lower than the preset threshold for the first time during the power-up process of the optical module, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip.

[0112] S120: After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip.

[0113] In some embodiments, a delayed triggering mechanism is used to write different register values ​​into the channel configuration register, thereby triggering forced suppression or desuppression of the channel.

[0114] In some embodiments, when the MCU303 detects for the first time during the power-on process of the optical module that the clock signal offset recovered by the signal processing chip 302 is lower than a preset threshold, the signal processing chip 302 is in a unlocked state and locked in an unstable signal state. The MCU303 then writes a first register value into the channel configuration register via a control pin to disable the signal processing chip's reception of the TIA chip's output photovoltage signal. Then, after a preset time, it writes a second register value into the channel configuration register via a control pin to enable the signal processing chip 302 to receive the TIA chip 520's output photovoltage signal. When the signal processing chip 302 is initially locked, a channel suppression-desuppression mechanism is introduced. The MCU 303 actively intervenes to forcibly interrupt the receiving link of the signal processing chip, effectively isolating the unstable signal period during power-on and shielding the unstable optical signal present in the early stage of power-on. When the signal input is restored, the signal processing chip 302 re-establishes the lock in a stable state, creating more stable and optimized clock signal and data signal recovery conditions for the signal processing chip 302. This allows the signal processing chip 302 to re-lock to more stable and optimized parameters, thereby reducing the high bit error rate caused by initial false locking.

[0115] In some embodiments, when the clock signal offset recovered by the signal processing chip 302 is initially detected to be lower than a preset threshold during the power-on process of the optical module, after a first preset time, a first register value is written into the channel configuration register via a control pin to disable the signal processing chip 302's reception of the optical voltage signal output by the TIA chip 520. After a second preset time, a second register value is written into the channel configuration register via a control pin to enable the signal processing chip 302's reception of the optical voltage signal output by the TIA chip 520.

[0116] In some embodiments, writing a first register value into the channel configuration register via the control pin after a first preset time ensures that the signal processing chip 302 is in a stable locked state, rather than a momentary pseudo-locked state. Writing a second register value into the channel configuration register via the control pin after a second preset time ensures effective isolation of the signal instability period during power-on.

[0117] In some embodiments, when the MCU303 detects for the first time during the power-on process of the optical module that the clock signal offset recovered by the signal processing chip 302 is lower than a preset threshold, it sets a first delay time, the delay time of which is a first preset time. At the end of the first delay time, a first register value is written into the channel configuration register to forcibly and temporarily shut down the signal receiving channel. Then, at this time, a second delay time is set, the delay time of which is a second preset time. At the end of the second delay time, a second register value is written into the channel configuration register to restore the signal receiving channel.

[0118] In some embodiments, the start time of the first preset time is when the MCU303 first detects that the clock signal offset recovered by the signal processing chip 302 is lower than a preset threshold, and the start time of the second preset time is the end time of the first preset time.

[0119] In some embodiments, the first preset time ensures that the signal processing chip 302 is in a stable locked state, rather than a momentary pseudo-locked state. The second preset time ensures the time required for the optical signal to fully stabilize after the signal receiving channel is closed. For example, the first preset time can be 100ms, and the second preset time can be 10ms.

[0120] In some embodiments, the first preset time is longer than the second preset time. A longer first preset time ensures that the CDR circuit 3021 is in a stable locked state, rather than a momentary pseudo-locked state. A shorter second preset time compared to the first preset time avoids situations where the signal has stabilized but the delay may not have ended, thereby avoiding unnecessary channel shutdown time, reducing data transmission interruption time, preventing ineffective suppression, and improving the timeliness of desuppression.

[0121] In some embodiments, when the MCU303 detects for the first time during the power-on process of the optical module that the clock signal offset recovered by the signal processing chip 302 is lower than a preset threshold, it generates a first delay signal. In response to the end of the first delay signal, it writes a first register value into the channel configuration register to send a channel forced suppression command to the signal processing chip 302, thus disabling the signal processing chip 302's reception of the TIA chip 520. While writing the first register value, a second delay signal is generated. In response to the end of the second delay signal, it writes a second register value into the channel configuration register to send a channel desuppression command to the signal processing chip 302, thus enabling the signal processing chip 302's reception of the TIA chip 520.

[0122] Figure 8 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure. As shown in Figure 8, in some embodiments, the control of the signal processing chip locking mechanism may include:

[0123] S210: When the LOS status reported by the TIA chip is cleared for the first time during the power-on process of the optical module, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip.

[0124] S220: After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip.

[0125] In some embodiments, when the MCU first reads the LOS status clearance reported by the TIA chip 520 during the power-on process of the optical module, it writes a first register value into the channel configuration register via a control pin to disable the signal processing chip 302's reception of the output photovoltage signal from the TIA chip 520. After a preset time, it writes a second register value into the channel configuration register via a control pin to enable the signal processing chip 302's reception of the output photovoltage signal from the TIA chip 520.

[0126] In some embodiments, when the LOS state reported by the TIA chip 520 is initially read as released during the power-on process of the optical module, after a first preset time, a first register value is written into the channel configuration register via a control pin to disable the signal processing chip 302's reception of the output optical voltage signal from the TIA chip 520; after a second preset time, a second register value is written into the channel configuration register via a control pin to enable the signal processing chip 302's reception of the output optical voltage signal from the TIA chip 520. The first preset time ensures that the TIA chip remains stably in a LOS-free state. The second preset time effectively isolates the period of signal instability during power-on.

[0127] In some embodiments, when the LOS status reported by the TIA chip 520 is read for the first time during the power-on process of the optical module, a channel suppression-desuppression mechanism is introduced. The MCU303 actively intervenes to forcibly interrupt the receiving link of the signal processing chip, effectively isolating the signal instability period during the power-on process and shielding the unstable optical signal that exists in the early stage of power-on.

[0128] In some embodiments, the timing of the MCU first reading the LOS status clearance reported by the TIA chip 520 is earlier than the timing of the MCU 303 first detecting that the clock signal offset recovered by the signal processing chip 302 is lower than a preset threshold during the power-on process of the optical module. By selecting to trigger the action when the LOS status clearance reported by the TIA chip is first read during the power-on process of the optical module, the trigger time is advanced, and the electrical signal received by the signal processing chip from the TIA chip output is a stable electrical signal, thus advancing the lock-in time of the stable electrical signal.

[0129] In some embodiments, a conditional triggering mechanism is used to write different register values ​​into the channel configuration register, thereby triggering forced suppression or desuppression of the channel.

[0130] In some embodiments, the signal processing chip 302 is used to acquire signal quality parameters to monitor the quality of the input signal.

[0131] Figure 9 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure. As shown in Figure 9, in some embodiments, the control of the signal processing chip locking mechanism may include:

[0132] S310: When the clock signal offset recovered by the signal processing chip is lower than the preset threshold for the first time during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read.

[0133] S320: When the signal quality parameters are lower than the preset quality parameters, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip's reception of the TIA chip's output optical voltage signal.

[0134] S330: When the signal quality parameters are higher than the preset quality parameters, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the optical voltage signal output by the TIA chip.

[0135] In some embodiments, when the MCU303 detects for the first time during the power-up process of the optical module that the clock signal offset recovered by the signal processing chip is lower than a preset threshold, the MCU303 reads the signal quality parameters monitored by the signal processing chip 302. When the signal quality parameters are lower than the preset quality parameters, a first register value is written into the channel configuration register to disable the signal processing chip 302's reception of the optical voltage signal output by the TIA chip 520, and the signal receiving channel temporarily enters a forced suppression state. Then, the signal quality parameters are read again. When the signal quality parameters are higher than the preset quality parameters, it indicates that the current signal quality is relatively stable, and a second register value is written into the channel configuration register to enable the signal processing chip 302's reception of the optical voltage signal output by the TIA chip 520, and the signal receiving channel enters a desuppression state. The CDR circuit 3021 is triggered to lock again. The signal quality is quantified by the signal quality parameters, and forced suppression and desuppression are triggered when specific conditions are met. When the signal quality parameters are higher than the preset threshold, the delay may not have ended yet, meaning the signal has stabilized before the delay ends, thus avoiding unnecessary channel shutdown time, reducing data transmission interruption time, avoiding invalid suppression, and improving the timeliness of desuppression.

[0136] In some embodiments, the signal quality parameter can be eye diagram quality.

[0137] In some embodiments, the signal processing chip 302 has an internal eye diagram quality monitoring unit, which can reuse the signal processing capabilities of the signal processing chip 302, such as eye diagram scanning. The input terminal of the eye diagram quality monitoring unit is electrically connected to the output terminal of the TIA chip 520, and the output terminal is electrically connected to the MCU 303, so as to monitor the eye diagram quality of the input signal and output the monitored eye diagram quality parameters to the MCU 303.

[0138] In some embodiments, the eye diagram quality monitoring unit can utilize the eye diagram scanning module built into the signal processing chip 302 to acquire the eye height and eye width of the input signal, thereby calculating the ratio of eye height to eye width to obtain the eye diagram opening. The "eye diagram opening" parameter is used to characterize the eye diagram quality and measure the signal quality input to the signal processing chip 302.

[0139] In some embodiments, the signal processing chip 302 has an eye diagram quality register inside, which is used to store the acquired eye height and eye width, and then obtain the parameter value of eye diagram opening.

[0140] In some embodiments, a conditional triggering mechanism is used to write different register values ​​into the channel configuration register, thereby triggering forced suppression or desuppression of the channel. When the MCU303 detects for the first time during the power-on process of the optical module that the clock signal offset recovered by the signal processing chip is lower than a preset threshold, it reads the parameter value corresponding to the eye opening from the eye diagram quality register. If the parameter value is lower than the preset threshold, it writes a first register value into the channel configuration register to temporarily shut down the signal receiving channel of the signal processing chip 302. Then, it continues to read the parameter value corresponding to the eye opening from the eye diagram quality register. If the parameter value is higher than the preset threshold, it writes a second register value into the channel configuration register to turn on the signal receiving channel of the signal processing chip 302, and the signal receiving channel is restored.

[0141] In some embodiments, the signal quality parameter can be the signal amplitude.

[0142] In some embodiments, the signal processing chip 302 has a signal amplitude monitoring unit inside, which is electrically connected to the TIA chip 520. By measuring the output level of the TIA chip 520, the amplitude of the optical signal can be monitored.

[0143] In some embodiments, the signal processing chip 302 has an internal signal amplitude register for storing the monitored signal amplitude. The MCU 303 can read the monitored signal amplitude parameter value from the signal amplitude register.

[0144] In some embodiments, a conditional triggering mechanism is used to write different register values ​​into the channel configuration register, thereby triggering forced suppression or desuppression of the channel. When the MCU303 detects for the first time during the power-on process of the optical module that the clock signal offset recovered by the signal processing chip is lower than a preset threshold, it reads the signal amplitude parameter value from the signal amplitude register. If the parameter value is lower than the preset threshold, it writes a first register value into the channel configuration register to temporarily shut down the signal receiving channel of the signal processing chip 302. Then, it continues to read the parameter value corresponding to the signal amplitude from the signal amplitude register. If the parameter value is higher than the preset threshold, it writes a second register value into the channel configuration register to turn on the signal receiving channel of the signal processing chip 302, and the signal receiving channel is restored.

[0145] Figure 10 is a schematic diagram of a signal processing chip locking mechanism control according to some embodiments of the present disclosure. As shown in Figure 10, in some embodiments, the control of the signal processing chip locking mechanism may include:

[0146] S410: When the LOS status reported by the TIA chip is cleared for the first time during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read.

[0147] S420: When the signal quality parameters are lower than the preset quality parameters, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip's reception of the TIA chip's output optical voltage signal.

[0148] S430: When the signal quality parameters are higher than the preset quality parameters, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the optical voltage signal output by the TIA chip.

[0149] In some embodiments, when the MCU303 first reads the LOS status release reported by the TIA chip 520 during the power-on process of the optical module, the MCU303 reads the signal quality parameters monitored by the signal processing chip 302. When the signal quality parameters are lower than the preset quality parameters, a first register value is written into the channel configuration register to disable the signal processing chip 302's reception of the optical voltage signal output by the TIA chip 520, and the signal receiving channel temporarily enters a forced suppression state. Then, the signal quality parameters are read again. When the signal quality parameters are higher than the preset quality parameters, it indicates that the current signal quality is relatively stable, and a second register value is written into the channel configuration register to enable the signal processing chip 302's reception of the optical voltage signal output by the TIA chip 520, and the signal receiving channel enters a desuppression state. The CDR circuit 3021 is triggered to lock again. The signal quality is quantified by the signal quality parameters, and forced suppression and desuppression are triggered when specific conditions are met. When the signal quality parameters are higher than the preset threshold, the delay may not have ended yet, that is, the signal has stabilized before the delay ends, thereby avoiding unnecessary channel shutdown time, reducing data transmission interruption time, avoiding invalid suppression, and improving the timeliness of desuppression.

[0150] In some examples, after channel decompression, the TIA chip 520 begins to input a more stable electrical signal to the signal processing chip. The CDR circuit 3021 then performs initial locking based on this more stable signal, creating a more stable initial locking condition for the CDR circuit 3021, allowing it to initially lock onto more stable parameters. By completing channel compression and decompression before the initial locking of the CDR circuit 3021, the initial locking of the CDR circuit 3021 directly applies to a stable signal, thus avoiding misjudgments of link faults caused by the CDR circuit 3021 locking onto an unstable signal.

[0151] In some embodiments, the signal quality parameter can be eye diagram quality.

[0152] In some embodiments, when the MCU first reads the LOS status clearance reported by the TIA chip 520, it reads the parameter value corresponding to the eye opening from the eye diagram quality register. If the parameter value is lower than a preset threshold, it writes a first register value into the channel configuration register to close the signal receiving channel of the signal processing chip 302. Then, it continues to read the parameter value corresponding to the eye opening from the eye diagram quality register. If the parameter value is higher than the preset threshold, it writes a second register value into the channel configuration register to open the signal receiving channel of the signal processing chip 302, and the signal receiving channel is restored.

[0153] In some embodiments, signal quality is quantified by eye diagram quality, and forced suppression and desuppression are triggered when specific conditions are met. When the eye diagram quality is higher than a preset threshold, the delay may not have ended yet, meaning the signal has stabilized before the delay ends. This avoids unnecessary channel shutdown time, reduces data transmission interruption time, avoids ineffective suppression, and improves the timeliness of desuppression.

[0154] In some embodiments, the signal quality parameter can be the signal amplitude.

[0155] In some embodiments, when the MCU first reads the LOS status clearance reported by the TIA chip 520, it reads the parameter value corresponding to the signal amplitude from the signal amplitude register. If the parameter value is lower than a preset threshold, it writes a first register value into the channel configuration register to close the signal receiving channel of the signal processing chip 302. Then, it continues to read the parameter value corresponding to the signal amplitude from the signal amplitude register. If the parameter value is higher than the preset threshold, it writes a second register value into the channel configuration register to restore the signal receiving channel of the signal processing chip 302.

[0156] In some embodiments, a combination of delay-triggered and condition-triggered mechanisms is used to write different register values ​​into the channel configuration register, thereby triggering forced suppression and desuppression of the channel. When the MCU303 detects for the first time during the power-up process of the optical module that the clock signal offset recovered by the signal processing chip is lower than a preset threshold, it writes a first register value into the channel configuration register to disable the signal processing chip 302's reception of the output photovoltage signal from the TIA chip 520. Then, it reads the parameter value corresponding to the eye diagram opening from the eye diagram quality register. If the parameter value is higher than a preset threshold, it writes a second register value into the channel configuration register to enable the signal processing chip 302's reception of the output photovoltage signal from the TIA chip 520.

[0157] In some embodiments, this combination of two mechanisms can also begin when the MCU first reads the LOS status clearance reported by the TIA chip 520. Specifically, when the MCU first reads the LOS status clearance reported by the TIA chip 520, the MCU 303 writes a first register value into the channel configuration register to disable the signal processing chip 302's reception of the TIA chip 520's output photovoltage signal. Then, it reads the parameter value corresponding to the eye diagram opening from the eye diagram quality register. If the parameter value is higher than a preset threshold, it writes a second register value into the channel configuration register to enable the signal processing chip 302's reception of the TIA chip 520's output photovoltage signal.

[0158] In some embodiments, the suppression phase is triggered by a delay. This delay-triggered suppression phase assumes that the signal quality is below a preset threshold, i.e., that the signal quality is unstable, thereby avoiding situations such as misjudgment by the signal instability detector eye diagram. The desuppression phase is triggered by sampling conditions. When the eye diagram quality is above the preset threshold, the delay may not have ended yet, meaning the signal has stabilized before the delay ends. This avoids unnecessary channel closure time, reduces data transmission interruption time, prevents invalid suppression, and improves the timeliness of desuppression.

[0159] In some embodiments, a combination of delay-triggered and condition-triggered mechanisms is used to write different register values ​​into the channel configuration register, thereby triggering forced suppression and desuppression of the channel. When the MCU303 detects for the first time during the power-up process of the optical module that the clock signal offset recovered by the signal processing chip is lower than a preset threshold, it writes a first register value into the channel configuration register to disable the signal processing chip 302's reception of the output photovoltage signal from the TIA chip 520. Then, it reads the parameter value corresponding to the eye diagram opening from the signal amplitude register. If the parameter value is higher than the preset threshold, it writes a second register value into the channel configuration register to enable the signal processing chip 302's reception of the output photovoltage signal from the TIA chip 520.

[0160] Figure 11 is an internal structural diagram of an optical module according to some embodiments of the present disclosure, and Figure 12 is an internal circuit diagram of an optical module according to some embodiments of the present disclosure. In some embodiments, as shown in Figures 11 and 12, an MCU 303 and a DSP 302 are disposed on the upper surface of the circuit board 300. The DSP 302 is disposed on the side of the MCU 303. The MCU 303 is electrically connected to the gold finger 301, and the DSP 302 is electrically connected to the MCU 303. Of course, in some embodiments, the MCU 303 and the DSP 302 are disposed on the lower surface of the circuit board 300, or the MCU 303 and the DSP 302 are disposed on different surfaces of the circuit board 300. The present disclosure does not limit the placement of the MCU 303 and the DSP 302.

[0161] In some embodiments, the DSP 302 can be electrically connected to the optical emitting component 400. The DSP 302 can be used to process electrical signals sent by the host computer and drive the optical emitting component 400 through the processed electrical signals so that the optical emitting component 400 generates optical signals. Alternatively, the DSP 302 can send the processed electrical signals to a driver for driving the optical emitting component 400 so that the driver drives the optical emitting component 400 based on the processed electrical signals.

[0162] In some embodiments, the DSP 302 can be electrically connected to the optical receiver 500. The DSP 302 can be used to process the electrical signals output by the optical receiver 500 and transmit the processed electrical signals to the gold finger 301, so as to transmit them to the host computer through the gold finger 301.

[0163] In some embodiments, the gold finger 301 includes an I2C pin 311, and the MCU 303 is connected to the I2C pin 311. The MCU 303 is connected to a host computer via the I2C pin 311 to establish an I2C communication connection with the host computer, enabling the MCU 303 to receive information from the host computer, such as a first preset value, preset debugging commands, and debugging parameters, based on I2C communication. Additionally, the host computer can obtain information from the MCU 303 based on I2C communication, such as register values ​​and execution results obtained by the MCU 303.

[0164] In some embodiments, when the optical module 200 malfunctions, the host computer needs to obtain the register value of the target register in the DSP 302 in order to perform optical module fault diagnosis and location by utilizing the register values ​​of each register in the target register. The target register in the DSP 302 may include multiple registers, which are key registers within the DSP 302, and the register value of the target register can indicate the operating status of the DSP 302.

[0165] In some examples, the target register in the DSP 302 may include the DSP's host receive (HRX) register, line receive (LRX) register, host transmit (HTX) register, and line transmit (LTX) register. In some examples, the target register in the DSP may include the channel configuration registers mentioned above.

[0166] Of course, the registers in the target register can be selected according to the actual situation. For example, the target register may include 80, 120, 127, 128, or other numbers of registers.

[0167] In some embodiments, when the host computer needs to obtain the register value of a certain register in the DSP 302, the host computer sends a command to the MCU 303 via the I2C pin 311 to read the register value of that register in the DSP 302. This command includes the register address of the register. The MCU 303 receives and parses the command to obtain the register address of the register. Then, the MCU 303 reads the register value of the corresponding register from the DSP 302 based on the register address. The host computer then reads the register value obtained by the MCU 303 from the MCU 303. When the host computer needs to obtain the register values ​​of multiple registers, the host computer will continuously send multiple commands via the I2C pin 311, causing the MCU 303 to respond to these multiple commands sequentially to obtain the register values ​​of multiple registers from the DSP. The MCU 303 will parse and execute the commands multiple times to obtain the register values ​​of the multiple registers.

[0168] In some implementations, when the host computer needs to obtain the register value of the target register in the DSP 302, the host computer sends a first preset value to the MCU 303 via I2C pin 311. The target register corresponds to the first preset value. The first preset value is used to instruct the MCU 303 to obtain the register value of the target register within the DSP 302. When the MCU 303 reads the first preset value, the MCU 303 directly responds to the first preset value to automatically obtain the register value of the target register. For example, the target registers include 32 registers of HRX, 32 registers of LRX, 32 registers of HTX, and / or 31 registers of LTX, etc. The first preset value can be 1, etc. By pre-setting the correspondence between the target register and the first preset value, when the host computer sends different first preset values, the MCU 303 directly responds to the different first preset values ​​to automatically obtain the register values ​​of the different registers. In this way, when the host computer needs to obtain the register values ​​of multiple registers in the DSP 302, the host computer does not need to send multiple commands continuously, and the MCU 303 does not need to parse the commands, obtain the address of the register corresponding to the register value that the host computer needs to obtain from the command, and obtain the register value based on the corresponding register address. This makes it more convenient for the MCU 303 to obtain the register values ​​of multiple registers in the DSP 302, and can save the occupation of MCU 303 resources, thereby enabling the host computer to obtain the register values ​​of multiple registers in the DSP 302 more quickly.

[0169] Figure 7 is a schematic diagram of the structure of an MCU according to some embodiments of the present disclosure. In some embodiments, as shown in Figure 7, the MCU 303 may include a first register 331, which can be used to store a first preset value written by a host computer via I2C pin 311. The host computer can write the first preset value into the first register 331 via I2C pin 311, or the MCU 303 can save the first preset value written by the host computer via I2C pin to the first register 331. The MCU 303 can read the first register 331 periodically or according to a software cycle. When the MCU 303 reads the first preset value, the MCU 303 obtains the register value of the target register and stores it in the first protocol area 332. The host computer can read the first protocol area 332 to obtain the register value stored in the first protocol area 332. The first protocol area 332 may be located inside the first register 331, or it may be located outside the first register 331.

[0170] In some embodiments, when the MCU 303 reads a first preset value, the MCU 303 can map the register value of the target register to the first protocol area 332. For example, the DSP 302 may have a register value management table, which stores the register values ​​of the target register; in response to the first preset value read by the MCU 303, the MCU 303 can map the register value management table to the first protocol area 332. The DSP 302 can periodically update the register value management table.

[0171] In some embodiments, after the MCU 303 stores the register value of the target register into the first protocol area 332, the MCU 303 clears the first preset value in the first register 331 so that the first register 331 can continue to perform subsequent operations. For example, after the MCU 303 maps the register value of the target register to the first protocol area 332, the MCU 303 clears the first preset value in the first register 331.

[0172] In some embodiments, after the MCU 303 clears the first preset value in the first register, the MCU 303 can notify the host computer that it has completed acquiring the register value of the target register, enabling the host computer to read the register value of the target register. For example, the MCU 303 can notify the host computer to read the register value stored in the first protocol area 332. This timely notification to the host computer after the MCU 303 has acquired the register value of the target register facilitates the host computer's timely acquisition of the target register value.

[0173] Figure 8 is a register value management table provided according to some embodiments of the present disclosure. As shown in Figure 8, the register value management table includes the register values ​​of 32 registers of HRX, 32 registers of LRX, 32 registers of HTX, 31 registers of LTX, and the enable bit ENABLE. In response to the first preset value read by MCU 303, MCU 303 maps the register value management table to the first protocol area. When MCU 303 reads the enable bit ENABLE, it indicates that MCU 303 has completed acquiring the register value of the target register.

[0174] In some embodiments, the DSP 302 may periodically obtain the register value of the target register and update the register value management table.

[0175] In some embodiments, when the host computer needs to adjust or obtain the parameters of the DSP 302, it sends a corresponding command to the MCU 303. The MCU 303 receives and parses the command, and calls the corresponding internal function of the DSP 302 based on the parsed command to control the DSP 302 to perform the corresponding action, thereby achieving the purpose of adjusting or obtaining the parameters of the DSP 302. After adjusting or obtaining the parameters of the DSP 302, the MCU 303 stores the result for the host computer to read. For example, the host computer can write the corresponding command to the MCU 303 based on I2C communication. When the host computer needs to adjust or obtain multiple parameters of the DSP 302, the MCU 303 will poll and call multiple functions of the DSP 302, which requires significant MCU resources.

[0176] In some embodiments, when the host computer needs to adjust or obtain the parameters of DSP 302, it sends a preset debugging command to MCU 303. This preset debugging command instructs the host computer to adjust or obtain the parameters of DSP 302 and instructs MCU 303 to send a preset debugging instruction to DSP 302. MCU 303 receives the preset debugging command and sends it to DSP 302, enabling DSP 302 to adjust or obtain its parameters. After adjusting or obtaining its parameters, DSP 302 feeds back the execution result to MCU 303. MCU 303 receives and stores the execution result for the host computer to retrieve. In this way, when the host computer needs to adjust or obtain the parameters of DSP 302, MCU 303 can transmit the preset debugging command for adjusting or obtaining the parameters of DSP 302. For example, it can receive and send the preset debugging command for adjusting or obtaining the parameters of DSP 302 to DSP 302. Compared with the host computer adjusting or obtaining the parameters of DSP 302 in conventional technology, it reduces the operations of MCU 303 such as parsing commands and calling functions, thereby saving the occupation of MCU resources.

[0177] For example, the host computer can write preset debugging commands to the MCU 303 via the I2C pin.

[0178] Figure 9 is a schematic diagram of another MCU structure provided according to some embodiments of the present disclosure. As shown in Figure 9, the MCU 303 may include a second register 333, which can be used to store preset debugging commands. Exemplarily, a host computer can write preset debugging commands into the second register 333 via an I2C pin, or the MCU 303 can store preset debugging commands written by the host computer to the MCU 303 via an I2C pin into the second register 333. In some embodiments, the second register 333 may be the same register as the first register 331, or the second register 333 may be a different register from the first register 331.

[0179] In some embodiments, the preset debug command may include predefined key fields for instructing the adjustment or retrieval of DSP 302 parameters, such as REQUEST CMD, REPLY CMD, etc., for reading DSP 302 API. The preset debug command may include debug parameters, which are parameters used by the DSP 302 to execute the preset debug command. When the MCU 303 reads the preset debug command, it transmits the preset debug command, including the debug parameters, to the DSP 302. The DSP 302 responds to the preset debug command and adjusts its parameters based on the debug parameters, generates an execution result, and feeds the execution result back to the MCU 303. The preset debug command includes debug parameters, facilitating the MCU 303 to send the preset debug command to the DSP 302, enabling the DSP 302 to quickly execute the preset debug command.

[0180] In some embodiments, the second register 333 can be used to store debugging parameters. For example, the host computer can write debugging parameters into the second register 333 via an I2C pin, or the MCU 303 can store the debugging parameters written by the host computer to the MCU 303 via an I2C pin into the second register 333.

[0181] Based on the optical module provided in the above embodiments, a control method is also provided in some embodiments, wherein the execution subject of the control method is an MCU. Figure 10 is a flowchart of a control method provided according to some embodiments of this disclosure. As shown in Figure 10, in some embodiments, the control method may include:

[0182] S100: In response to the first preset value written to the first register, the register value of the target register within the DSP is obtained and stored in the first protocol area for the host computer to read. The first preset value is used to instruct the MCU to obtain the register value of the target register within the DSP, and the target register includes multiple registers.

[0183] In some embodiments, the control method may include:

[0184] S200: In response to a preset debugging command written to the second register, the preset debugging command is sent to the DSP, causing the DSP to adjust or acquire its parameters based on the preset debugging command and feed the execution result back to the MCU. The second register stores the preset debugging command written by the host computer, which instructs the DSP to adjust or acquire its parameters.

[0185] S300: Receive the execution result fed back by the DSP and store it in the second register so that the host computer can read the execution result from the second register.

[0186] In some embodiments, obtaining the register value of the target register in the DSP and storing it in the first protocol area includes: obtaining the register value of the target register in the DSP and mapping it to the first protocol area.

[0187] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An optical module, comprising: Circuit board; An optical receiver chip, electrically connected to the circuit board, is used to convert the received optical signal into a photocurrent signal. The TIA chip, electrically connected to the optical receiver chip, is used to convert the photocurrent signal into a photovoltage signal and amplify the photovoltage signal; when the photocurrent signal intensity is lower than a preset threshold, the TIA chip detects a LOS state; when the photocurrent signal intensity is higher than the preset threshold, the TIA chip detects that the LOS state has been cleared. A signal processing chip, disposed on the surface of the circuit board and electrically connected to the TIA chip, receives the photovoltage signal output by the TIA chip. The signal processing chip includes a channel configuration register. When the register value is a first register value, it indicates that the signal processing chip is disabled from receiving the photovoltage signal output by the TIA chip; when the register value is a second register value, it indicates that the signal processing chip is enabled from receiving the photovoltage signal output by the TIA chip. The signal processing chip is used to acquire signal quality parameters to monitor the input signal quality. The MCU includes control pins, which are electrically connected to the signal processing chip and are configured as follows: When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-up process of the optical module, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip. After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip; Alternatively, the MCU is configured as follows: When the LOS status reported by the TIA chip is cleared for the first time during the power-on process of the optical module, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip; After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip; Alternatively, the MCU is configured as follows: When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read. When the signal quality parameter is lower than the preset quality parameter, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip; Then, when the signal quality parameter is higher than the preset quality parameter, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the optical voltage signal output by the TIA chip; Alternatively, the MCU is configured as follows: When the LOS status reported by the TIA chip is initially read during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read. When the signal quality parameter is lower than the preset quality parameter, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip; When the signal quality parameter is higher than the preset quality parameter, a second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the optical voltage signal output by the TIA chip; The MCU includes a first register for storing a first preset value written by a host computer. This first preset value instructs the MCU to acquire the register value of a target register within the signal processing chip. The target register includes multiple registers, including a channel configuration register. The MCU is configured to: in response to the first preset value in the first register, acquire the register value of the target register and store it in a first protocol area for the host computer to read. The register value includes either the first register value or a second register value; and / or... The MCU includes a second register for storing a preset debugging command written by a host computer. The preset debugging command instructs the signal processing chip to adjust or acquire its parameters. The MCU is configured to: in response to the preset debugging command in the second register, send the preset debugging command to the signal processing chip, causing the signal processing chip to adjust or acquire its parameters based on the preset debugging command, and feed back the execution result to the MCU. The system receives the execution result fed back by the signal processing chip and stores it in the second register, so that the host computer can read the execution result from the second register.

2. The optical module according to claim 1, wherein, The MCU is configured as follows: When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-on process of the optical module, after a first preset time, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip. After a second preset time, a second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip.

3. The optical module according to claim 1, wherein, The signal processing chip has an internal CDR circuit, which includes a phase-locked loop state monitoring circuit and an LOL pin. The CDR circuit is configured as follows: When the phase-locked loop (PLL) state monitoring circuit detects that the clock signal offset exceeds a preset threshold, the LOL pin outputs a low-level command signal; when the PLL state monitoring circuit detects that the clock signal offset is lower than the preset threshold, the LOL pin outputs a high-level command signal. Alternatively, the CDR circuit includes a phase-locked loop state monitoring circuit and a state register; The CDR circuit is configured as follows: When the phase-locked loop (PLL) status monitoring circuit detects a clock signal offset exceeding a preset threshold, it writes a first register value into the status register; when the PLL status monitoring circuit detects a clock signal offset below the preset threshold, it writes a second register value into the status register.

4. The optical module according to claim 1, wherein, The MCU is configured as follows: When the LOS status reported by the TIA chip is cleared for the first time during the power-on process of the optical module, after a first preset time, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip. After a second preset time, a second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip.

5. The optical module according to claim 1, wherein, The TIA chip includes an LOS detection circuit and an LOS pin. The TIA chip is configured as follows: When the LOS detection circuit detects that the intensity of the input photocurrent signal is lower than a preset threshold, the LOS pin outputs a low-level command signal; when the LOS detection circuit detects that the intensity of the input photocurrent signal is higher than the preset threshold, the LOS pin outputs a high-level command signal. Alternatively, the TIA chip may include an LOS detection circuit and a status register. The TIA chip is configured as follows: When the LOS detection circuit detects that the intensity of the input photocurrent signal is lower than a preset threshold, it writes a first register value into the status register; when the LOS detection circuit detects that the intensity of the input photocurrent signal is higher than the preset threshold, it writes a second register value into the status register.

6. The optical module according to claim 1, wherein, A gold finger is formed on the surface of one end of the circuit board, and the gold finger includes an I2C pin; The MCU is mounted on the circuit board; the MCU is connected to the I2C pin; The first register is used to store a first preset value written by the host computer via the I2C pin.

7. The optical module according to claim 1, wherein, When the MCU includes a first register, obtaining the register value of the target register and storing it in the first protocol area includes: mapping the register value of the target register to the first protocol area, wherein the first protocol area is located in the first register.

8. The optical module according to claim 1, wherein, When the MCU includes a first register, the MCU is further configured to: after storing the register value of the target register in the first protocol area, clear the first preset value in the first register; The host computer is notified to read the register values ​​stored in the first protocol area.

9. The optical module according to claim 1, wherein, When the MCU includes a second register, the second register is also used to store debugging parameters written by the host computer. The debugging parameters are parameters used by the signal processing chip to execute the preset debugging command. In response to a preset debugging command written to the second register, the preset debugging command is sent to the signal processing chip, causing the signal processing chip to adjust or acquire its parameters based on the preset debugging command and feed back the execution result to the MCU, including: In response to the preset debugging command written to the second register, the preset debugging command and the debugging parameters are sent to the signal processing chip, so that the signal processing chip adjusts its parameters based on the preset debugging command and the debugging parameters and feeds back the execution result to the MCU.

10. An optical module, comprising: Circuit board; An optical receiver chip, electrically connected to the circuit board, is used to convert the received optical signal into a photocurrent signal. The TIA chip, electrically connected to the optical receiver chip, is used to convert the photocurrent signal into a photovoltage signal and amplify the photovoltage signal; when the photocurrent signal intensity is lower than a preset threshold, the TIA chip detects a LOS state; when the photocurrent signal intensity is higher than the preset threshold, the TIA chip detects that the LOS state has been cleared. A signal processing chip, disposed on the surface of the circuit board and electrically connected to the TIA chip, receives the photovoltage signal output by the TIA chip. The signal processing chip includes a channel configuration register. When the register value is a first register value, it indicates that the signal processing chip is disabled from receiving the photovoltage signal output by the TIA chip; when the register value is a second register value, it indicates that the signal processing chip is enabled from receiving the photovoltage signal output by the TIA chip. The signal processing chip is used to acquire signal quality parameters to monitor the input signal quality. The MCU includes control pins, which are electrically connected to the signal processing chip and are configured as follows: When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-up process of the optical module, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip. After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip; Alternatively, the MCU is configured as follows: When the LOS status reported by the TIA chip is cleared for the first time during the power-on process of the optical module, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip; After a preset time, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip; Alternatively, the MCU is configured as follows: When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read. When the signal quality parameter is lower than the preset quality parameter, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip; Then, when the signal quality parameter is higher than the preset quality parameter, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the optical voltage signal output by the TIA chip; Alternatively, the MCU is configured as follows: When the LOS status reported by the TIA chip is initially read during the power-on process of the optical module, the signal quality parameters monitored by the signal processing chip are read. When the signal quality parameter is lower than the preset quality parameter, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip; When the signal quality parameter is higher than the preset quality parameter, the second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip.

11. The optical module according to claim 10, wherein, The MCU is configured as follows: When the clock signal offset recovered by the signal processing chip is detected to be lower than a preset threshold for the first time during the power-on process of the optical module, after a first preset time, a first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip. After a second preset time, a second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip.

12. The optical module according to claim 10, wherein, The MCU is configured as follows: When the LOS status reported by the TIA chip is cleared for the first time during the power-on process of the optical module, after a first preset time, the first register value is written into the channel configuration register through the control pin to disable the signal processing chip from receiving the optical voltage signal output by the TIA chip. After a second preset time, a second register value is written into the channel configuration register through the control pin to enable the signal processing chip to receive the photovoltage signal output by the TIA chip.

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