Quantum feature map-based classifiers

Abstract

In a general aspect, quantum feature map-based classifiers are presented. In some aspects, a computing system is configured to train a classifier. To train the classifier, training datasets associated with respective classes are obtained. The training datasets are processed to determine representative quantum density operators for the respective classes; and the representative quantum density operators are stored for use by the classifier. Determining a representative quantum density operator for a class includes encoding the training dataset in a quantum logic circuit; obtaining measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit; and determining the representative quantum density operator based on the measurements.

Description

Quantum Feature Map-Based ClassifiersCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 717,420, filed November 7, 2024, entitled "Quantum Machine Learning Systems based on a Density Matrix Classifier.” The above-referenced priority documents are incorporated herein by reference.TECHNICAL FIELD

[0002] The following description relates generally to quantum feature map-based classifiers.BACKGROUND

[0003] Quantum computers can perform computational tasks by storing and processing information within quantum states of quantum systems. For example, qubits (i.e., quantum bits) can be stored in, and represented by, an effective two-level sub-manifold of a quantum coherent physical system. A variety of physical systems have been proposed for quantum computing applications. Examples include superconducting circuits, trapped ions, spin systems, and others.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a block diagram of an example computing environment.

[0005] FIG. 2A is a flow chart showing aspects of an example training process of a quantum feature map-based classifier.

[0006] FIG. 2B is a flow chart showing aspects of an example classification process by operation of the quantum feature map-based classifier trained in the example process shown in FIG. 2A.

[0007] FIG. 3 is a flow chart showing aspects of an example process.

[0008] FIGS. 4A-4C are schematic diagrams showing example quantum logic circuits as part of a quantum feature map-based classifier.

[0009] FIG. 5 is a schematic diagram showing an example quantum processing unit.

[0010] FIG. 6A is a table showing optimized values of model parameters of scikit-learn classifiers.

[0011] FIG. 6B is a plot of F1 scores of simulation results and quantum processor unit (QPU) results from different classification models based on one-to-one encoding of all classical features.

[0012] FIG. 6C is a plot of F1 scores of simulation results and QPU results from different classification models based on one-to-multiple encoding of top three classical features.DETAILED DESCRIPTION

[0013] In some aspects of what is described here, a quantum feature map-based classifier is provided to assign an input sample to one of a plurality of classes based on features extracted from the sample. The quantum feature map-based classifier can be trained using multiple non-overlapping training datasets each associated with a respective class. During the training process, each training dataset can be processed to determine a representative quantum density operator for the respective class by performing a quantum feature mapping process. For example, each training dataset associated with a respective class can be used to parameterize a quantum logic circuit that includes a sequence of quantum logic gates. The parameterized quantum logic circuit can be executed by a quantum processing unit; and measurements of expectation values of quantum states can be obtained. A representative quantum density operator associated with the training dataset can be determined based on the measurements. After the training process is performed on all training datasets, representative quantum density operators associated with the training datasets / classes can be stored for use by a quantum feature map-based classifier.

[0014] In some instances, the quantum logic circuit of the quantum feature mapbased classifier is determined or obtained according to the number of classical features and a range of feature values of data samples in the training dataset. In some instances, the quantum logic circuit includes parametric quantum logic gates which are defined by gate parameters for encoding classical features. In some instances, the quantum logic circuit includes multiple alternating layers of single-qubit rotation gates for encoding data in rotation angles, and layers of two-qubit quantum logic gates for creating entanglement. In some instances, the quantum logic circuit may also include layers offixed non- Clifford quantum logic gates configured to create magic and the layers of two-qubit quantum logic gates can be used for spreading the magic. The quantum logic circuit can be used to translate low-dimensional classical features of data samples in a dataset to high-dimensional features in the Hilbert space. In some implementations, the same quantum logic circuit is used to process all the training datasets.

[0015] In some implementations, the quantum logic circuit may be executed multiple times and multiple quantum observables on the quantum states measured to obtain multiple measured quantum observables. The multiple measured quantum observables can be used to calculate an expectation value of the same quantum observables for the quantum states. In some instances, the quantum logic circuit can be modified and further executed when the process is repeated on measurement of other quantum observables, e.g., first order or higher order Pauli observables (e.g., as shown in operations 302 in the example process 300 shown in FIG. 3).

[0016] In some implementations, after the quantum feature map-based classifier is trained, the classifier can be operated in a classification process for classifying a new test data sample and for determining its classification. For example, a test data sample can be encoded in the same quantum logic circuit used in the training process using the same encoding and feature mapping schemes; the quantum logic circuit encoded with the test data sample can be executed; and measurements of expectation values of quantum observables on quantum states can be obtained. A test quantum density operator associated with the test data sample is determined based on these measurements. This test quantum density operator is then compared to at least one of the training representative quantum density operators obtained during the training process by evaluating a distance metric between the test quantum density operator and the representative training quantum density operators. In certain examples, a classification of the test data sample can be returned based on an evaluation result (e.g., the test data sample is assigned to a class based on the shortest distance). The evaluation of the distance metric may include estimating a Frobenius distance on a quantum computing system.

[0017] In some implementations, the systems and techniques described here can provide technical advantages and improvements. The systems and techniques presented here can achieve high discriminatory power. The systems and techniques canscale linearly with the number of data samples versus a quadratic scaling for the classical benchmark. The systems and techniques presented here do not require iterative training. In some implementations, the number of operations scales linearly with the number of training data samples. The representative quantum density operators can be updated to include new information (e.g., new training data samples or new datasets associated with new classes). The update of the representative quantum density operators is a simple process scaling linearly with the number of new training samples. The systems and techniques presented here are more robust to noise and to scaling in the number of qubits utilized, as compared to algorithms which measure and use bitstrings directly, because of the expectation values which are calculated using the quantum computer. The quantum feature map-based classifier presented here has the potential to outperform standard classical classifiers on datsets that are difficult to classify. The hardness of a classification problem increases with the reduction of a number of classification features with high predictive power, as less information is available to perform the classification. Although this affects both classical and quantum classifiers, the larger expressive power of quantum feature map-based classifiers can help to preserve more information and use it in a more efficient way, especially when this information is shared across multiple qubits. The model is suitable for execution on Noisy Intermediate Scale Quantum (NISQ) devices. In some cases, a combination of these and potentially other advantages and improvements may be obtained.

[0018] FIG. 1 is a block diagram of an example computing environment 100, according to an example embodiment. The example computing environment 100 shown in FIG. 1 includes a computing system 101 and user devices 110A, 110B, 110C. A computing environment may include additional or different features, and the components of a computing environment may operate as described with respect to FIG.1 or in another manner.

[0019] The example computing system 101 includes classical and quantum computing resources and exposes their functionality to the user devices 110A, 110B, 110C (referred to collectively as "user devices 110”). The computing system 101 shown in FIG. 1 includes one or more servers 108, quantum computing systems 103A, 103B, a local network 109, and other resources 107. The computing system 101 may also include one or more user devices (e.g., the user device 110A) as well as other features and components. A computing system may include additional or different features, andthe components of a computing system may operate as described with respect to FIG. 1 or in another manner.

[0020] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computing system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109, or otherwise).

[0021] The user devices 110 shown in FIG. 1 may include one or more classical processors, memory, user interfaces, communication interfaces, and other components. For instance, the user devices 110 may be implemented as laptop computers, desktop computers, smartphones, tablets, or other types of computer devices. In the example shown in FIG. 1, to access computing resources of the computing system 101, the user devices 110 send information (e.g., programs, instructions, commands, requests, input data, etc.) to the servers 108; and in response, the user devices 110 receive information (e.g., application data, output data, prompts, alerts, notifications, results, etc.) from the servers 108. The user devices 110 may access services of the computing system 101 in another manner, and the computing system 101 may expose computing resources in another manner.

[0022] In the example shown in FIG. 1, the local user device 110A operates in a local environment with the servers 108 and other elements of the computing system 101. For instance, the user device 110A may be co-located with (e.g., located within 0.5 to 1 km of) the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, the user device 110A communicates with the servers 108 through a local data connection.

[0023] The local data connection in FIG. 1 is provided by the local network 109. For example, some or all of the servers 108, the user device 110A, the quantum computing systems 103A, 103B, and the other resources 107 may communicate with each other through the local network 109. In some implementations, the local network 109 operates as a communication channel that provides one or more low-latency communication pathways from the server 108 to the quantum computing systems103A, 103B (or to one or more of the elements of the quantum computing systems 103A, 103B). The local network 109 can be implemented, for instance, as a wired or wireless Local Area Network, an Ethernet connection, or another type of wired or wireless connection. The local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements. In some cases, the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.

[0024] In the example shown in FIG. 1, the remote user devices 110B, 110C operate remotely from the servers 108 and other elements of the computing system 101. For instance, the user devices 110B, 110C may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, each of the user devices 110B, 110C communicates with the servers 108 through a remote data connection.

[0025] The remote data connection in FIG. 1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network. In some cases, remote user devices use another type of remote data connection (e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108. The wide area network 115 may include one or more internet servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements. Generally, the computing environment 100 can be accessible to any number of remote user devices.

[0026] The example servers 108 shown in FIG. 1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B, and the other resources 107.

[0027] As shown in FIG. 1, the servers 108 are classical computing resources that include classical processors 111 and memory 112. The servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115, and possibly other channels. In some implementations, the servers 108 may include a host server, an application server, a virtual server, or a combination of these and other types of servers. The servers 108 may include additional or different features and may operate as described with respect to FIG. 1 or in another manner.

[0028] The classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, by way of example, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these. The memory 112 can include, for example, a random-access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium. The memory 112 can include various forms of volatile or non-volatile memory, media, and memory devices, etc.

[0029] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum simulators, or both) as well as classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), applicationspecific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.

[0030] In some implementations, the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution. For example, the servers 108 may send programs to the quantum computing system 103A, the quantum computing system 103B, or any of the other resources 107. The programs may include classical programs, quantum programs, hybridclassical / quantum programs, and may include any type of function, code, data, instruction set, etc.

[0031] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere. In some instances, programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions) that can be executed directly by a computing resource. Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data. For example, a program can include instructions formatted for a quantum computing system, a simulator, a digital microprocessor, co-processor or other classical data processing apparatus, or another type of computing resource.

[0032] In some cases, a program may be expressed in a hardware-independent format. For example, quantum machine instructions may be provided in a quantum instruction language such as Quil, described in the publication "A Practical Quantum Instruction Set Architecture,” arXiv:1608.03355v2, dated Feb. 17, 2017, or another quantum instruction language. For instance, the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or simulators. In some cases, a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, or in another form. In some cases, a program may be expressed in terms of control signals (e.g., pulse sequences, delays, etc.) and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.). In some cases, a program may be expressed in another form or format.

[0033] In some implementations, the servers 108 include one or more compilers that convert programs between formats. For example, the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B. In some cases, a compiler can compile a program to a format that targets a specific quantum resource in the computing system 101. For example, a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to beexecuted by the quantum computing system 103A or the quantum computing system 103B.

[0034] In some cases, a compiler generates a partial binary program that can be updated, for example, based on specific parameters. For instance, if a quantum program is to be executed iteratively on a quantum computing system with varying parameters on each iteration, the compiler may generate the binary program in a format that can be updated with specific parameter values at runtime (e.g., based on feedback from a prior iteration, or otherwise); the parametric update can be performed without further compilation. In some cases, a compiler generates a full binary program that does not need to be updated or otherwise modified for execution.

[0035] In some implementations, the servers 108 generate a schedule for executing programs, allocate computing resources in the computing system 101 according to the schedule, and delegate the programs to the allocated computing resources. The servers 108 can receive, from each computing resource, output data from the execution of each program. Based on the output data, the servers 108 may generate additional programs that are then added to the schedule, output data that is provided back to a user device 110, or perform another type of action.

[0036] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment For example, quantum programs can be formatted as hybrid classical / quantum programs that include instructions for execution by one or more quantum computing resources (e.g., the quantum-based algorithms) and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum virtual machines (QVMs), one or more quantum simulators, or possibly other types of quantum resources. The classical computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized coprocessor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs),application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.

[0037] In some cases, the servers 108 can select the type of computing resource (e.g., quantum or classical) to execute an individual program, or part of a program, in the computing system 101. For example, the servers 108 may select a particular quantum processing unit (QPU) or other computing resource based on availability of the resource, speed of the resource, information or state capacity of the resource, a performance metric (e.g., process fidelity) of the resource, or based on a combination of these and other factors. In some cases, the servers 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance.

[0038] Each of the example quantum computing systems 103 A, 103B shown in FIG. 1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In some implementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in, and represented by, an effective two-level sub-manifold of a quantum coherent physical system. In some instances, quantum logic can be executed in a manner that allows large-scale entanglement within the quantum system. Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the qubits. In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits.

[0039] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between thepair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation.

[0040] In some models, fault- tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, quantum error correcting codes can be deployed to achieve fault-tolerant quantum computation. Other computational regimes may be used; for example, quantum computing systems may operate in non- fault-tolerant regimes. In some implementations, a quantum computing system is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general purpose coherent quantum computing. Other architectures may be used; for example, quantum computing systems may operate in small-scale or non-scalable architectures.

[0041] The example quantum computing system 103A shown in FIG. 1 includes a quantum processing unit 102A and a control system 105A, which controls the operation of the quantum processing unit 102A. Similarly, the example quantum computing system 103B includes a quantum processing unit 102B and a control system 105B, which controls the operation of a quantum processing unit 102B. A quantum computing system may include additional or different features, and the components of a quantum computing system may operate as described with respect to FIG. 1 or in another manner.

[0042] In some instances, all or part of the quantum processing unit 102A functions as a quantum processing unit, a quantum memory, or another type of subsystem. In some examples, the quantum processing unit 102 A includes a superconducting quantum circuit system. The superconducting quantum circuit may include data qubit devices, stabilizer qubit devices, coupler devices, readout devices, and possibly other devices that are used to store and process quantum information. In some cases, multiple data qubit devices are operatively coupled to a single stabilizer check qubit device through respective coupler devices. In some implementations, the quantum processing unit 102A is implemented utilizing aspects designed or generated from the componentsand processes shown in FIGS. 2-4, or in another manner. In certain examples, the qubit devices and the coupler devices are implemented as superconducting quantum circuit devices that include Josephson junctions, for example, in Superconducting QUantum Interference Device (SQUID) loops or other arrangements, and are controlled by radiofrequency signals, microwave signals, and bias signals delivered to the quantum processing unit 102A.

[0043] In some instances, the quantum processing modules can include a superconducting quantum circuit that includes one or more quantum circuit devices. For instance, a superconducting quantum circuit may include qubit devices, readout resonator devices, Josephson junctions, or other quantum circuit devices. In some implementations, quantum circuit devices in a quantum processing unit can be collectively operated to define a single logical qubit. A logical qubit includes a quantum register, for instance multiple physical qubits or qudits, and associated circuitry, that supports physical operations which can be used to detect or correct errors associated with logical states in a quantum algorithm. Physical operations supported by the quantum register associated with a logical qubit may include single-qubit or multi-qubit quantum logic gates and readout mechanisms. Error detection or correction mechanisms associated with a logical qubit may be based on quantum error correction schemes such as the surface code, color code, Bacon- Shor codes, low-density parity check codes (LDPC), some combination of these, or others.

[0044] The quantum processing unit 102A may include, or may be deployed within, a controlled environment. The controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems. In some examples, the components in the quantum processing unit 102A operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise. For example, magnetic shielding can be used to shield the system components from stray magnetic fields, optical shielding can be used to shield the system components from optical noise, thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.

[0045] In some implementations, the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A. The control signals can be configured to encode information inthe qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits. In some examples, the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits. A quantum logic circuit, which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.

[0046] The example control system 105A includes controllers 106A and signal hardware 104A. Similarly, control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a roomtemperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B. In some cases, the control systems 105A, 105B include classical computers, signaling equipment (microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems, or other types of control systems that support operation of the quantum processing units 102A, 102B.

[0047] The control systems 105A, 105B may be implemented as distinct systems that operate independent of each other. In some cases, the control systems 105A, 105B may include one or more shared elements; for example, the control systems 105A, 105B may operate as a single control system that operates both quantum processing units 102A, 102B. Moreover, a single quantum computing system may include multiple quantum processing units, which may operate in the same controlled (e.g., cryogenic) environment or in separate environments.

[0048] The example signal hardware 104A includes components that communicate with the quantum processing unit 102A. The signal hardware 104A may include, for example, waveform generators, amplifiers, digitizers, high-frequency sources, DC sources, AC sources, etc. The signal hardware may include additional or different features and components. In the example shown, components of the signal hardware 104A are adapted to interact with the quantum processing unit 102A. For example, the signal hardware 104A can be configured to operate in a particular frequency range,configured to generate and process signals in a particular format, or the hardware may be adapted in another manner.

[0049] In some instances, one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A. The control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A. For instance, the signal hardware 104A may generate signals to implement quantum logic operations, readout operations, or other types of operations. As an example, the signal hardware 104A may include arbitrary waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radiofrequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices, or other types of components in the quantum processing unit 102A.

[0050] In some instances, the signal hardware 104A receives and processes signals from the quantum processing unit 102A. The received signals can be generated by the execution of a quantum program on the quantum computing system 103 A. For instance, the signal hardware 104A may receive signals from the devices in the quantum processing unit 102A in response to readout or other operations performed by the quantum processing unit 102A. Signals received from the quantum processing unit 102A can be mixed, digitized, filtered, or otherwise processed by the signal hardware 104A to extract information, and the information extracted can be provided to the controllers 106A or handled in another manner. In some examples, the signal hardware 104A may include a digitizer that digitizes electromagnetic waveforms (e.g., microwave or radiofrequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or to other signal hardware components. In some instances, the controllers 106A process the information from the signal hardware 104A and provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102 A.

[0051] In some implementations, the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102A. For example, thesignal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers, and other types of components. In some instances, the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A. In some instances, signal delivery hardware performs preprocessing, signal conditioning, or other operations on readout signals received from the quantum processing unit 102A.

[0052] The example controllers 106A communicate with the signal hardware 104A to control the operation of the quantum computing system 103A. The controllers 106A may include classical computing hardware that directly interfaces with components of the signal hardware 104A. The example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems. The classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or other types of data processing apparatus. The memory may include any type of volatile or non-volatile memory or another type of computer storage medium. The controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels. The controllers 106A may include additional or different features and components.

[0053] In some implementations, the controllers 106A include memory or other components that store quantum state information, for example, based on qubit readout operations performed by the quantum computing system 103A. For instance, the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in one or more of the controllers 106A. In some cases, the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.

[0054] In some implementations, the controllers 106A include memory or other components that store a quantum program containing quantum machine instructionsfor execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.

[0055] In some instances, the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes. For example, the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals. In some cases, the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a single execution of the quantum program, and a collection of bitstrings from multiple shots may be analyzed to compute quantum state probabilities.

[0056] In some implementations, the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above. For example, the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical / quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.

[0057] The other quantum computing system 103B and its components (e.g., the quantum processing unit 102B, the signal hardware 104B, and controllers 106B) can be implemented as described above with respect to the quantum computing system 103 A;in some cases, the quantum computing system 103B and its components may be implemented or may operate in another manner.

[0058] In some implementations, the quantum computing systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation. For example, the computing system 101 may include both an adiabatic quantum computing system and a gate-based quantum computing system. As another example, the computing system 101 may include a superconducting circuit-based quantum computing system and an ion trap-based quantum computing system. In such cases, the computing system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations.

[0059] In some instances, one or more components of the computing system 101 shown in FIG. 1 are configured to perform the operations of the example processes shown in FIGS. 2A-2B, 3, or another process. For example, one or more classical processors (e.g., the classical processors 111 in the servers 108 and the controller 106 in the control system 105 in the example computing system 101 shown in FIG. 1) can be configured to pre-process received datasets associated with respective classes to determine a number of features and a range of feature values; train a quantum feature map-based classifier; and use the classifier to determine a classification of test data samples. The computing system 101 can compile the quantum logic circuit into a sequence of native gates that can be executed on a quantum processing unit 102. The compiled sequences can be executed on the quantum processing unit 102 to encode datapoints from datasets into quantum states and obtain measured quantum states. The measured quantum states can be processed to determine representative quantum density operators for respective datasets / classes. The representative quantum density operators can then be stored (e.g., in a classical memory, or a quantum computer) for use by a classifier 114.

[0060] The classifier 114 can be implemented using classical or quantum computing hardware, software, or combinations thereof. In some implementations, a classifier 114 includes one or more classical processors, which execute instructions stored in memory to cause a quantum processing unit 102 to perform quantum logic operations, process measurement results, and generate a corresponding classification output. The classicalprocessors may perform numerical operations, apply model parameters, evaluate decision boundaries, or produce the classification result. The classifier 114 may include classical software executed by classical computing hardware and quantum programs (including logic circuits) that are executed by the quantum processing units. The classifier 114 may be communicably connected to other components in the computing system 101, e.g., with the servers 108 and with the quantum computing system 103. In some instances, the classifier 114 maybe implemented as part of the server 108 or the control system 105. In some instances, the classifier 114 can be trained according to the operation shown in FIG. 2A or in another manner; and can be operated to perform a classification process according to the operations shown in FIG. 2B or in another manner.

[0061] FIG. 2A is a flow chart showing aspects of an example training process 200. The example training process 200 can be performed, by operation of a computing system (e.g., the quantum computing system 103 in FIG. 1), to train a quantum feature map-based classifier. The quantum feature map-based classifier can be trained by processing multiple training datasets associated with respective classes; determining representative quantum density operators associated with the training datasets; and storing the representative quantum density operators for use by the quantum feature map-based classifier. In some implementations, a classifier is a computational module configured to assign a data sample to one or more predefined categories. In some embodiments, the classifier is implemented on one or more classical processors, which execute instructions stored in memory to cause a quantum processing unit to perform quantum logic operations, process measurement results, and generate a corresponding classification output. The classical processor may perform numerical operations, apply model parameters, evaluate decision boundaries, or produce the classification result. In some instances, the example training process 200 is a supervised learning process. The example process 200 may include additional or different operations, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 200 can be combined, iterated or otherwise repeated, or performed in another manner.

[0062] At 202, a group of training datasets of N non-overlapping datasets (classes) C1,..., CNis obtained. For example, let 풟 be a group of datasets consisting of training data samples belonging to N non-overlapping training datasets (classes) C1,..., CNEach training data sample in a training dataset, x ∈ 풟, can be represented as a vector of classical features, x: = (x1,..., xm)T, where m is the number of classical features, or the dimensionality of the training dataset. Each training data sample x in a training dataset is an m-dimensional vector of real-valued classical features. In some instances, the training data sample x may include discrete or categorical variables. In some instances, the training datasets are received by the computing system 101 from the user device 110 via the wide area network 115 as shown in FIG. 1. In some implementations, all training data samples in the training datasets are represented in the same format. In some instances, the training datasets may be received from other devices.

[0063] At 204, each training dataset is processed to determine a corresponding representative quantum density operator. In some implementations, a quantum feature map can be performed to map a vector of classical features or a selected subset of classical features of a training data sample into quantum states. In some implementations, a quantum logic circuit is constructed and executed. In some instances, a quantum logic circuit for quantum feature mapping may include at least one layer of single-qubit quantum logic gates, and at least one layer of multi-qubit quantum logic gates. In some instances, single-qubit T gates can be used in the quantum logic circuit to increase quantum magic. In some instances, the quantum logic circuit includes parametric quantum logic gates with gate parameters configured to encode each training data sample. For example, a quantum logic circuit for quantum feature mapping may include multiple layers of single-qubit rotation gates with rotation angles as gate parameters for encoding the vectors of the classical features of training data samples; and multiple layers of multi-qubit quantum logic gates configured to create entanglement. In some instances, the quantum logic circuit may be implemented as the quantum logic circuits 400, 410, 420 shown in FIGS. 4A-4C or in another manner.

[0064] In some implementations, a quantum logic circuit is used to efficiently encode data samples with relatively low-dimensional classical features into extremely highdimensional quantum states, thus creating a quantum feature map. In this case allquantum states are initialized as |0⟩, and the initial state is |ψ0⟩ = |0⟩ ⊗ ··· ⊗ |0⟩ ≡ |0⟩⊗n. The vector of classical features, x, or a subset of the classical features can be mapped into a set of gate parameters of the quantum logic circuit. In some instances, an angle encoding method is used, where the classical features are mapped to rotation angles of single-qubit quantum logic gates of the quantum logic circuit In some instances, different schemes to map the classical features of data samples to parameters of the quantum logic circuit may be used. For example, amplitude encoding, basis encoding, reuploading encoding, or other types of encoding schemes can be used to map classical features onto quantum states. In certain instances, classical features can be encoded on parameters of the multi-qubit quantum logic gates, parameters on both the single-qubit quantum logic gates and the multi-qubit quantum logic gates, or in another manner. The final state,thus can encode the data samples in a dataset in the high-dimensional Hilbert space. In some instances, the quantum logic circuit can provide more expressive power than equivalent classical models when only a polynomial number of parameters is allowed.

[0065] A quantum feature map <p is defined as a function that maps data samples x into operators <p(x) of a Hilbert space J~C. The quantum feature map <p is realized on a computing system (e.g., the computing system 101 in FIG. 1) via a unitary transformation U(x) applied to initial states |0) = 0⊗n:φ(x): = U(x)|0⟩⟨0|U(x)†≡ |x⟩⟨x|. [2]

[0066] The quantum state |x⟩: = U(x)|0⟩ is a pure quantum state encoding the data sample x. When the quantum feature map φ is specified on n qubits, then the dimension of the Hilbert space ℋ of linear operators is 4n= 2n× 2n.

[0067] In some instances, quantum features produced from the execution of the quantum feature map can then be used to construct respective quantum density operators corresponding to respective datasets and thus classes. For each class Ci⊂ 풟, i = 1,...,N, a representative quantum density operator can be defined as an equally weighted statistical ensemble of all data samples in Cpwhere [C denotes the cardinality of Ciand the sum goes over all data samples xk, k = 1, ..., [Ci] in class

[0068] As shown in FIG. 2A, operation 204 includes sub-operations 212 during which a quantum logic circuit is parameterized based on the training dataset; suboperation 214 during which quantum features are obtained by executing the quantum logic circuit; and sub-operation 216 during which quantum states are measured.

[0069] At 212, a quantum logic circuit is parameterized based on the training dataset. In some implementations, a quantum logic circuit is configured to implement the unitary transformation U (x) applied to n qubits. In some implementations, all n-qubits are initialized to their ground states 0⊗n. In some instances, the quantum logic circuit may be constructed based on the training datasets and the quantum computing hardware. In some instances, a quantum logic circuit may be defined by the depth and shape of the quantum logic circuit, the number of layers of the single-qubit quantum logic gates and multi-qubit quantum logic gates in the quantum logic circuit, the number of qubits on which the quantum logic circuit is applied, types of quantum logic gates, the ansatz (e.g., manner the quantum logic gates are connected together), measurement basis, features in the high-dimensional Hilbert space, and other parameters. In some instances, the quantum logic circuit may be deep enough to distribute the entanglement but not too deep to cause decoherence.

[0070] In some implementations, the quantum logic circuit may include single-qubit quantum logic gates, two-qubit quantum logic gates, or other multi-qubit quantum logic gates applied on a number of qubits. In some implementations, layers of the single qubit quantum logic gates in the quantum logic circuit are data encoding layers (e.g., 404A, 404B, 404C in FIGS. 4A-4B); and layers of the multi-qubit quantum logic gates are entanglement-creating layers (e.g., 406A, 406B, 406C in FIGS. 4A-4B). In some implementations, layers of single-qubit T gates in the quantum logic circuit are magic creation layers (e.g., 422A, 422B, 422C in FIG. 4C). In some implementations, the number of qubits where the quantum logic circuit is applied is determined by the number of classical features that represent different aspects or attributes of the data samples, or dimensionality of the data samples in the dataset In some instances, the number of classical features of data samples in the dataset can be determined by implementing feature selection and extraction techniques. In some instances, thenumber (n) of qubit devices (e.g., quantum registers) where the quantum logic circuit for performing quantum feature mapping is applied may be equal to the number of classical features. In other words, each classical feature of data samples in a dataset is mapped to a quantum state of a qubit device (e.g., one-to-one mapping). An example quantum logic circuit that can be used in a one-to-one mapping is shown in FIG. 4A. In certain instances, the number of classical features may be different from the number of qubit devices. In this case, two or more classical features of data samples may be selected and mapped to a quantum state of a single qubit device (multiple-to-one mapping). In some instances, one classical feature may map to multiple qubit devices (one-to-multiple mapping). In some instances, the datasets in the training dataset may include different number of classical features. In this case, classical features may be selected (e.g., most important classical features) from different datasets; and only a subset of classical features may be used to represent the dataset In certain examples, a selected classical feature can be mapped to a respective qubit (e.g., one-to-one mapping). In some examples, a selected classical feature can be mapped to two or more qubits (e.g., one-to-multiple mapping). An example quantum logic circuit that can be used in a one-to- multiple mapping is shown in FIG. 4B.

[0071] In some implementations, the quantum logic circuit is configured to efficiently encode a data sample defined by relatively low-dimensional classical features into extremely high-dimensional quantum states, thus realising a quantum feature map. For example, all quantum states of qubit devices may be intialised as |0), and the initial state is |ψ0⟩ = |0) ® ••• ® |0) = |0⟩⊗n. The vector of classical features, x, can be mapped into a set of gate parameters of the quantum logic circuits 400, 410, 420. For example, as shown in FIGS. 4A-4C, the single-qubit quantum logic gates in the quantum logic circuit include parametric single-qubit rotation gates, the vectors of classical features can be mapped onto rotation angles of the parametric single-qubit rotation gates, e.g., an angle encoding method. In this case, parameterizing the quantum logic circuit includes parameterizing the single-qubit rotation gates. When the parametric quantum logic gates include other parameters according to the encoding scheme, the quantum logic gates can be parameterized accordingly. In some implementations, quantum logic gates in a quantum logic circuit can be parameterized by determining values of the parameters of the quantum logic gates based on one or more classical features of the training data sample. For example, the single-qubit rotation gates can beparameterized based on all the classical features by determining the rotation angles for one or more of the single-qubit rotation gates. For another example, a subset of the classical features can be selected, and the selected subset of classical features can be used to parameterize the quantum logic gates. The final state, |ψf⟩, thus encodes the classical data sample and the subsequent sample classification is performed in the high-dimensional Hilbert space.

[0072] In some instances, a single-qubit X-rotation gate can be expressed as the unitary operator matrixcos(0 / 2) — isin(0 / 2)] [4]— isin(0 / 2) cos(0 / 2) ]'In some instances, a single-qubit Y-rotation gate can be expressed as the unitary operator matrixDFR> [cos(0 / 2) -sin(0 / 2)] [5]Y[sin(0 / 2) cos(0 / 2) ]'In some instances, a single-qubit Z- rotation gate can be expressed as the unitary operator matrixn > [exp(-i0 / 2) 0 1 [6]W~ [ o exp(i© / 2)]’

[0073] In some instances, other schemes to encode the classical features of the data to parameters of the quantum logic circuit may be used. For example, amplitude encoding, basis encoding, reuploading encoding, or other types of encoding schemes can be used to map classical features onto quantum states. In certain instances, classical features can be encoded on parameters of the multi-qubit quantum logic gates, parameters on both the single-qubit quantum logic gates and the multi-qubit quantum logic gates, or in another manner. The output quantum states, |ψf⟩, thus can encode the classical data samples in the input dataset and the subsequent machine learning problem can be performed in the high-dimensional Hilbert space. In some instances, the quantum logic circuit can provide more expressive power than equivalent classical models when only a polynomial number of parameters is allowed.

[0074] In some instances, the number of layers of the single-qubit quantum logic gates and multi-qubit quantum logic gates can be defined by the amount of entanglement required, the amount of magic (non-Cliffordness) required, the fidelity ofthe single-qubit and multi-qubit gates used in the quantum logic circuit, the topology of the quantum device, the native gates available on the quantum device, and whether data re-upload techniques are required, or in another manner.

[0075] For example, the depth and number of layers, and the gates used within the quantum logic circuit may be varied. For example, a multi-qubit quantum logic gate to obtain entanglement may include a controlled-Z (CZ) gate, an imaginary SWAP (iSWAP) gate, a controlled-NOT (CNOT) gate, a controlled-phase (CPHASE) gate, or another multi-qubit quantum logic gate.

[0076] In some instances, the CZ gate can be represented by the unitary operator matrix

[0077] In some instances, the iSWAP gate can be represented by the unitary operator matrix

[0078] In some instances, the CNOT gate can be represented by the unitary operator matrix

[0079] In some instances, the CPHASE gate can be represented by the unitary operator matrix

[0080] In some instances, circuit shape can be determined in order to best match the qubit topology of the quantum processing unit, e.g., connectivity of qubit devices.Features in the high-dimensional Hilbert space used may be Pauli observables of first order, or of first and second order. In some examples, other Pauli observables may beselected as features; or completely different features may also be utilized. In some instances, utilizing expectation values of Pauli observables as features results in an algorithm that is impacted less by readout errors or noises. This makes it more robust than algorithms which require measurement of specific bitstring values (e.g. the |0) state). In some instances, this results in improved speed and improved scaling with number of qubits.

[0081] In some implementations, a number of classical features of the data samples are determined, e.g., by using feature extraction techniques or Random Fourier transforms. A range of feature values for each classical feature of the data samples in the dataset is calculated. The quantum logic circuit is determined according to the number of classical features and the range of feature values. For example, the number of layers of the single-qubit quantum logic gates and the number of qubits to which the quantum logic circuit is applied are determined. In some instances, when the quantum logic circuit includes parametric single-qubit rotation gates, rotation angle values of the single-qubit rotation gates are determined according to the number of layers of the single-qubit quantum logic gates and the number of qubits to which the quantum logic circuit is applied.

[0082] In some instances, feature encoding is performed using the angle encoding scheme. Each classical feature xt, i = 1,..., m of a data sample x: = (xp..., xm)Tis encoded into the corresponding rotation angle - the adjustable parameter of a singlequbit quantum gate. Each single-qubit quantum logic gate operator (mathematically, a 2 x 2 unitary matrix) can be seen as a rotation of the qubit state (a point on the unit sphere called the Bloch sphere) around some axis. In practice, and without loss of generality, rotations may be around the x, y, and z axis (with z-basis being the computational basis). Any point on the Bloch sphere can be reached from any other point on the Bloch sphere by just two rotations around any two orthogonal axes.

[0083] In some instances, prior to executing the parametrized quantum logic circuit, the data samples can be pre-processed by standardizing the classical features according to the range of feature values. Given the dataset C with the total number of data samples equal to the dataset cardinality [C], for each data sample xfe, k = 1,..., [C], the mapping of the classical feature x to the corresponding rotation angle 6 may be performed as follows:where a is the range parameter.

[0084] In some instances, before mapping a classical feature into a rotation angle of a single qubit rotation gate, the classical feature can be pre-processed to modify (e.g. even out) its distribution. If values of a classical feature is distributed more or less evenly, the mapping scheme shown in equation (11) above works well without any preprocessing. In instances where the values of a classical feature are concentrated around the minimum or the maximum values, the distribution can be streched up from the minimum or down from the maximum in order to enhance the discriminatory power of a quantum feature map. Such reconfiguration of the distribution is an attempt to reach as many regions of the Hilbert space as possible and increase the distance between different data samples. In some instances, an example feature pre-processing rule may include• If median — min < (max — min) Then x -> xY, y =1 3• If - (max — min) < median — min < - (max — min) Then x -> xY, y = 1.3• If median — min > - (max — min) Then

[0085] At 214, measurements are obtained. In some instances, the parameterized quantum logic circuit is executed on the qubits by operation of a quantum processing unit, e.g., the quantum processing unit (e.g., the quantum processing unit 102 in FIG. 1) and the classical processors (e.g., the control system 104, the classical processors 111 or other classical computing resources in FIG. 1). In some instances, the parameterized quantum logic circuit may be converted, translated, or otherwise compiled into a native gate sequence which can be directly executed on a quantum processing unit. The native gate sequence may include parametric single-qubit quantum logic gate. In some instances, the native gate sequence may include non-parametric quantum logic gates.

[0086] In some instances, the data samples may be pre-processed in another manner. For example, the data samples from multiple datasets may be split into multiple datasets and data samples from different datasets may be resampled and interleaved together. Standardizing the feature values is usually done based on the datafrom all the datasets (e.g., all classes), or based on external information which determines the maximum and minimum value of each classical feature. In some implementations, quantum features <p(xfe) for each data sample in class|xk⟩, k = 1,..., [Ci] in each class Ci, i = 1, N are obtained. In some instances, the quantum features can be constructed via the transformation given by equation (2) using the unitary transformation U (xfe). In particular, during operation 214, quantum states are measured. After the execution of the parameterized quantum logic circuit, the quantum states are measured by operation of the quantum processing unit. During the measurement, the quantum states of the qubits are collapsed to one of their respective basis states (|0) or |1⟩).

[0087] The final quantum state,is obtained after the execution of the parameterized quantum logic circuit - a sequence of quantum logic gates (linear unitary operators [ / ) controlled by parameters Θ1,..., Θm- to the initial quantum state, |ψ0⟩:f} = UmQm~)... C / 2(02)C / i(0i)|i o> U2)

[0088] In some instances, readout error mitigation techniques can be applied.Readout error mitigation can be used to reduce the errors which occur during the measurement of the quantum state of a qubit For example, randomized readout error mitigation can be implemented on the quantum computer hardware / software stack.

[0089] The multiple measured quantum states can be used to calculate expectation values of quantum observables for the quantum states. In some instances, an Approximate Quantum State technique can be used for estimating Pauli (or other) expectations. The Approximate Quantum State technique enables estimation of numerous Pauli expectation values using a fixed set of bitstring samples obtained from a quantum computer. In some implementations, an approximate quantum state technique allows calculation of the expectation value of multiple quantum observables from a fixed set of measurements. In some instances, 1000 shots per data sample are used. This enables the possibility of scaling linearly with the number of data samples. In some instances, calculating expectation values of Pauli observables as features in the high-dimensional Hilbert space can make the process or algorithm less affected by readout errors. This makes it more robust than algorithms which require measurement of specific bitstring values. This results in improved speed and improved scaling with number of qubits. In some instances, other techniques can be used to estimate Pauliexpectations. In some instances, classical shadow techniques can be used. In some instances, the operation 216 may include sub-operations. For example, the operation 216 may be implemented as the example process 300 shown in FIG. 3 or in another manner.

[0090] Operations 212 and 214 can be repeated to execute the parameterized quantum logic circuit and measure the quantum observable on the quantum states along the same computational basis multiple times to obtain multiple measurements. In some instances, operations 212, 214 may be repeated to obtain a modified parameterized quantum logic circuit; execute the modified parameterized quantum logic circuit; and measure different quantum observables on the quantum states (e.g., along a different computational basis). For example, the operations 212, 214 in the example process 220 may be repeated on different computational basis to obtain multiple sets of expectation values as shown in the example process 300 in FIG. 3 or in another manner. The modified parameterized quantum logic circuit can be executed multiple times and measured multiple times to obtain multiple measurements. The multiple measurements can be used to calculate expectation values of different quantum observables on the quantum states. In some instances, quantum observables correspond to measurements along specific axes of the Bloch sphere (e.g., different measurement bases), such as the Pauli Matrices.

[0091] At 216, a representative quantum density operator p, associated with the class Ci, i = 1,..., IV is determined. In some implementations, for each training data sample in a class, a corresponding quantum density operator is determined based on the measurement of the quantum observables. After determining all the corresponding quantum density operators of all the training data samples in a class, the representative quantum density operator for that class can be determined. In some implementations, the representative quantum density operator p, is defined as an equally weighted statistical ensemble of all samples in C, as defined in equation (3). In some instances, the quantum density operator may include a density matrix, a reduced form of a density matrix, or another type of quantum density operator. A quantum density operator and the projectors |x)(x| that form them are all vectors in the space J-Coof linear operators on J-C (note that projectors - the "measurement" operators - are linear but not unitary operators). Multiprocessing and multithreading parallel processing techniques are usedto speed up the classical calculations. In some instances, a density matrix includes the average expectation values of all Pauli values across the dataset, e.g., as described in the example process 300 shown in FIG. 3 or in another manner. In some implementations, operations 202, 204 in the training process 200 are repeated on all the classes to determine corresponding representative quantum density operators associated to the respective classes in the training dataset

[0092] At 206, the representative quantum density operators associated with the respective classes are stored. In some instances, the representative quantum density operators can be stored in a classical memory device as part of the classical computing system or in another manner. In some embodiments, a classical memory device is provided to store the representative quantum density operators generated by or received from one or more classical processing units of the classical computing system. The classical memory may comprise volatile memory (e.g., SRAM, DRAM) and / or nonvolatile memory (e.g., Flash, MRAM), organized in addressable locations that store the representative quantum density operators as binary words of fixed or configurable width (e.g., 8, 16, 32, or 64 bits). In some instances, the representative quantum density operators can be stored in a database. In some implementations, the database can associate the representative quantum density operators with respective identifiers of the respective classes. In some implementations, the database is configured to associate the representative quantum density operators with respective labels, each label can be represented by a corresponding identifier. In some instances, the identifier may be a numerical value, token, or other machine-readable representation that uniquely designates a classification category. During operation, the quantum feature map-based classifier can process a test data sample and output a label identifier indicating the predicted class. The label identifiers may be stored in memory and referenced by downstream modules to enable consistent interpretation, routing, or further processing of the classification results.

[0093] In some instances, the stored representative quantum density operators can be accessed by a quantum feature map-based classifier during a classification process (e.g., the example process 220 shown in FIG. 2B or in another manner) to determine a classification of a test data sample. In some instances, the operations 202, 204, 206 shown in FIG. 2A can be repeated to determine multiple sets of representative quantumdensity operators. Each set of representative quantum density operators is obtained using and associated with a specific quantum feature mapping configuration, for example, using a specific quantum logic circuit, a specific encoding scheme, a specific feature mapping scheme, a specific measurement scheme, a specific form of quantum density operator, etc. In some instances, each set of representative quantum density operators may be constructed using the same training dataset For example, in response to different feature mapping schemes used during the training process, multiple sets of representative quantum density operators may be constructed storing representative quantum density operators obtained by executing the same quantum logic circuit using respective feature mapping schemes during the operations shown in the example process 200 in FIG. 2 A.

[0094] In some implementations, the stored representative quantum density operators can be updated when a new training data sample belonging to a known and previously trained dataset / class is obtained. The new training data sample can be processed using a quantum feature mapping process under the same quantum feature mapping configuration that is initially used to generate the stored representative quantum density operators. For example, if a training dataset associated with a class i has k data samples, then each expectation value in the representative quantum density operator is calculated as an average over the values obtained from k data samples in the class i. For example, a representative quantum density operator of the class i can be defined as an average quantum density operatoris the representative quantum density operator of the class, ρijis the quantum density operator associated with a data sample k in the dataset associated with the class i, and k is the total number of data samples in the dataset. Therefore, kρi=p[- Given a new data sample in the same class i, the average is updated to be taken over the individual expectations from all k + 1 data samples. Therefore, the updated representative quantum density operator associated to the class can be defined as:In some instances, the representative quantum density operator stored in the storage system can be updated in another manner.

[0095] In some implementations, data stored in the storage system is updated when a new dataset associated with a new class CN+1is received. For example, the training process 200 shown in FIG. 2A can be executed by executing a quantum logic circuit and using a feature mapping scheme associated with the plurality of representative quantum density operators to obtain a new representative quantum density operator associated with the new dataset The storage system can be updated by storing the new representative quantum density operator as a new entry. In some instances, for the same dataset in the same class, the storage system may include multiple sets of representative quantum density operators determined using different quantum logic circuits, different encoding schemes, different feature mapping schemes, or different measurement schemes. In this case, when a new dataset is received, multiple representative quantum density operators based on the different quantum logic circuits, different encoding schemes, different feature mapping schemes, or different measurement schemes may be determined.

[0096] In some instances, the training datasets include training data samples in the form of quantum states instead of classical vectors of real numbers. In this case, the operations in the example process 200 can be used to process input quantum states of respective classes and to determine representative quantum density operators for the respective classes. For example, an input data sample including a quantum state can be generated from a quantum sensor device (e.g., a gravitometer, a magnetic field sensor, or another type of quantum sensor device) or another quantum computer system. The computing system for executing the example process 200 can directly receive the quantum states or via mechanisms using entanglement. In this case, the sub-operation 212 may become optional, where a quantum logic circuit is not required to encode the input quantum state. The input quantum states after being received by the computing system can be processed following the sub-operation 216 to determine a representative quantum density operator associated with the class.

[0097] In some instances, the received input quantum states may be processed by a quantum logic circuit. For example, a non-parametric quantum logic circuit for processing the input quantum states may include an H gate or an HS† gate for the purpose of rotating into the different measurement bases. In some instances, a quantum logic circuit (e.g., non-parametric or parametric) which may include a series of quantum logic gates can be used to pre-process the input quantum states moving states from different classes further apart, and in some instances to increase magic (e.g., T gates) and thus, generalization. In certain implementations, a quantum logic circuit for receiving the input quantum states as input quantum states can be used for other purposes. In some implementations, the quantum logic circuit for processing the input quantum states may also be parametric. In this case, gate parameters of the parametric quantum logic circuit can be configured to improve and optimize classification results. In some instances, the parameter values may be optimized and obtained by performing a classical machine learning process; and the optimized parameter values determined from the classical machine learning process can be communicated back to the computing system to update the parameter values of the quantum logic circuit during the training process. The quantum observables can be measured during sub-operations 214 after executing the quantum logic circuit; and a representative quantum density operator associated with the class can be obtained during sub-operation 216.

[0098] FIG. 2B is a flow chart showing aspects of an example process 220 for performing a classification process using a quantum feature map-based classifier to classify a test data sample. In some instances, the quantum feature map-based classifier is trained according to the operations in the example process 200 shown in FIG. 2A or in another manner. The example process 220 is used to evaluate a test data sample by constructing a quantum feature map that encodes the test data sample into quantum states by executing a quantum logic circuit on a quantum processing unit (e.g., the quantum computing system 103 in FIG. 1); determining a test quantum density operator (e.g., a complete form, a reduced form, or a partial view of a density matrix) derived from the measurements of expectation values of the quantum observables on the quantum states associated with the test data sample; and determining the test quantum density operator which can be used to compare with the representative quantum density operators in the storage system to determine a classification of the test data sample. The example process 220 may include additional or differentoperations, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 220 can be combined, iterated or otherwise repeated, or performed in another manner.

[0099] In some instances, operations 222, 226 in the example process 220 may be implemented as the respective operations 202, 206 in the example process 200. The plurality of representative quantum density operators can be obtained during operation 224 by the classifier. As shown in FIG. 2B, operation 226 used to process the test data sample includes sub-operation 232 during which a quantum logic circuit is parameterized based on the test data sample; sub-operation 234 during which measurements of expectation values of quantum observables on quantum states generated during the execution of the quantum logic circuit are obtained; and suboperation 236 during which the test quantum density operators associated with the test data sample is determined. In some instances, the test data sample may be obtained from a quantum process (e.g. a quantum sensor device or a quantum computer system) and already be represented as a quantum state. Sub-operation 232 may then require no further (or minimal) additional quantum logic circuits to be applied and may become optional. In some instances, the sub-operations 232, 234, 236 may be implemented as the sub-operations 212, 214, 216 in the example process 200 shown in FIG. 2A. In some implementations, once the database is selected, the same quantum logic circuit, the same encoding scheme, the same feature mapping scheme, the same measurement scheme, and the same form of quantum density operator used in the training process 200 to obtain the selected database are used in the classification process 220. The example process 220 includes additional operations 228, 230 for evaluating distances and determining a classification of the test data sample.

[0100] At 228, distances between the test quantum density operator and each of the respective quantum density operators in the storage system are evaluated. In some instances, the closeness of any two classes, and Cj, can be defined as a distance between the corresponding representative quantum density operators and pj of a training dataset and the test data sample. In some instances, the test quantum density operator and the respective quantum density operator used for determining the distance are obtained using the same quantum feature map (e.g., the same quantumlogic circuit, the same encoding scheme, the same feature mapping scheme, the same measurement scheme, etc.).

[0101] In some instances, the distance may be a Jensen- Shannon distance, a Bures distance, a Hellinger distance, a Frobenius distance, or another distance. In some instances, other metrics can be used to evaluate the distance, including the the trace distance, the geometric distance, or other metrics. In some instances, other criteria may be used to determine the classification of the test data sample based on the distances. In some implementations, a Jensen- Shannon distance between two quantum density operators is defined as:where S(ρ) = −Tr(ρlnρ) is the von Neumann entropy.

[0102] In some instances, a Bures distance between two quantum density operators is defined as:dB(ρi, ρj) =, (16)where F(ρi,ρj) = (Tr√(√ρiρj√ρi))2is the fidelity of two quantum states.

[0103] In some instances, a Hellinger distance between two quantum density operators is defined as:

[0104] In some instances, a Frobenius distance between two quantum density operators is defined as:

[0105] In some implementations, the Frobenius distance can be efficiently estimated on a quantum computing system. Consider the space of linear operators ℋOwith dimension DO= D2= (2n)2acting in the Hilbert space ℋ of a quantum system with dimension D = 2n. A distance squared d2between two Hermitian operators p and q can be derived from a linear product (·,·) defined in ℋOd2(p,q) = ‖ p − q ‖2= (p − q, p − q). (19)

[0106] If {Bi} is a complete orthonormal set in ℋO, then p and q can be expressed as vectors in ℂDwith components pi: = (Bi, p) and qi: = (Bi, q) respectively. The Pauli operators:corresponding to the j-th single-qubit identity and Pauli operators, are an orthogonal set with the choice of linear product(L, M) = Tr[L†M], (21) which induces the Frobenius norm. The distance squared d2can be expressed as the Euclidean distance in ℂD.with column vectors

[0107] Fixing the normalisation of the operators {Vi}, e.g., by choosing Bi= Vi / √D and p and q representing two quantum density operators, the elements piand qibecome real numbers that can be expressed asand therefore

[0108] The Frobenius distance as defined in equation (18) can be written as a Euclidean distance between vectors of expectation values of Paulis

[0109] The complete basis set of operators Vtconsists of 4" elements. This makes working with the complete basis set impractical or even impossible for large n. In some instances, a subset of L operators Vtfrom the full set can be selected to approximate thesum on the expectation values of all Pauli operators with the sum on the subset of L Pauli operators:

[0110] For example, L can be the set of all first order Pauli operators. In some instances, the higher order tensor products of Pauli operators can be ignored since their expectation values tend to make negligibly small contribution.

[0111] Thus, the Frobenius distance estimator can be defined as

[0112] If the subspace of ℋOspanned by the L Pauli operators is considered, then

[0113] In some instances, the expression shown in equation (29) can be used as the exact Frobenius distance with a quantum feature map that does not map to the full quantum density matrix, but to vectors of components of the full quantum density matrix on a Pauli basis.

[0114] The smaller the dF(p, q) value is, the higher similarity between the two datasets is. For example, when the dF(p, q) = 0, the two representative quantum density operators are identical and the test data sample has the same classification as the training dataset For example, when the dF(p, q) < dth, where dthis a predefined threshold value, the test data sample is close enough to the training dataset (e.g., representing the same class). On the other hand, when dF(p, q) > dth, the test data may be considered different from the training dataset. In some instances, the dF(p, qi) for respective training datasets can be determined and a minimal value of the dF(p, q^) can be obtained. When the minimal value of dF(p, q^) is equal to or less than the threshold value, the test data sample and the training dataset are considered having the same classification. In some instances, the threshold is determined by splitting a data set into subsets and calculating distances between the subsets. This provides statistics on the distances obtained for samples from the same distribution. In certain examples, thethreshold can be set based on these statistics. In some instances, the threshold may be set as a specified number of standard deviations away from the mean. In some instances, the threshold may be set using a convergence analysis and the central limit theorem. For example, one approach is a χ2-like test, where for n samples, if the statistics n|c|2is higher than the quantile of order 1 − α the hypothesis that the test data sample has the same classification as the training dataset can be rejected. In some instances, the threshold may be determined in another manner.

[0115] At 230, a classification result is returned. For example, the classification result may be returned to the user device from the computing system. In some instances, the classification result includes a quantitative or qualitative evaluation of the distances, e.g., the distances / similarity / closeness between the test data sample and each of the training datasets, whether or not the test data sample belongs to a class, etc.

[0116] FIG. 3 is a flow chart showing aspects of an example process 300 for determining a representative quantum density operator of a dataset In some instances, the example process 300 may be used in the example training and classification processes 200, 220 as the operations 214, 234 to obtain measurements of expectation values of quantum states. In some implementations, the example process 300 can be used to process a training dataset or a test data sample. In certain examples, the example process 300 maybe used to process other dataset for another process (e.g., updating a database containing representative quantum density operators). The example process 300 may be executed by operation of a quantum computing system (e.g., the quantum computing system 103 in FIG. 1). The example process 300 may include additional or different operations, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 300 can be combined, iterated or otherwise repeated, or performed in another manner.

[0117] At 302, measurements of expectation values of observables of quantum states are obtained. The quantum states are generated by executing a quantum logic circuit on the quantum computing system. The quantum logic circuit may be implemented as the example quantum logic circuit 400, 410, 420 shown in FIGS. 4A-4C or in another manner. As shown in FIG. 3, operation 302 includes suboperations 312, 314, 316, and 318.

[0118] At 312, for each data sample i = 1,...,m in a dataset, the quantum logic circuit is executed for N times; after each execution of the quantum logic circuit, Pauli Zfeis measured on all qubits, where k = 1,..., [C], When the Pauli Zkis measured as state |0), a value of + 1 is recorded; and when the Pauli Zkis measured as state |1), a value of -1 is recorded. An expectation value Zkis calculated as an average value of the recorded Zkacross all quantum logic circuit executions.

[0119] At 314, for each data sample i = 1,the quantum logic circuit is modified by placing a H gate on all qubits before measurement; the modified quantum logic circuit is executed N times; after each execution of the modified quantum logic circuit, Pauli Xkis measured on all qubits k = 1,..., [C], When the Pauli Xkis measured as state |0), a value of + 1 is recorded; and when the Pauli Xkis measured as state |1), a value of -1 is recorded. An expectation value Xkis calculated as an average value of recorded Xkacross all the modified quantum logic circuit executions.

[0120] At 316, for each data sample i = 1,the quantum logic circuit is modifed by placing HS† gates on all qubits before measurement; the modified quantum logic circuit is executed N times; after each execution of the modified quantum logic circuit, Pauli Ykis measured on all qubits k = 1,..., [C], When the Pauli Ykis measured as state |0), a value of + 1 is recorded; and when the Pauli Ykis measured as state |1), a value of -1 is recorded. An expectation value YkAis calculated as an average value of recorded Ykacross all the modified quantum logic circuit executions.

[0121] At 318, for each data sample i = 1,the quantum logic circuit is modifed by placing either H or HS† gates on a selected subset of qubits before measurement; the modified quantum logic circuit is executed N times; after each execution of the modified quantum logic circuit, multiple datasets of expectation values associated with distinct measurement bases for qubits, for example, either Pauli X or Pauli Y or Pauli Z are measured on the subset of qubits. (The value +1 is recorded if we measure state |0) and the value —1 is recorded if we measure state 11)). If gate H was placed on the qubit k before measurement and gates HS† were placed on the qubit l before measurement, Xkand Ylcan be measured; the expectation value XkYlAis then calculated as an average value of the product XkYlof recorded values of Xkand Ylacross all the modified quantum logic circuit executions.

[0122] At 304, the average expectation values across all data samples in the dataset are calculated. Without loss of generality, for a circuit with n qubits, assume that 3n second-order Paulis (i.e., the same number as all first order Paulis) are measured. An array with a dimension of m x 6n containing expectation values of first and second order Paulis for the dataset is obtained. For every column of these arrays, the average expectation values across all data samples in the dataset are calculated using:

[0123] In some implementations, the representative quantum density operator associated with the dataset is a 6n-dimensional column vector that is obtained:

[0124] In some implementations, given the representation of a quantum density operator A asand given the representation of a quantum density operator B asthen the column vector of differences is calculated asand an estimate of the Frobenius distance is calculated as

[0125] FIGS. 4A-4C are schematic diagrams showing example quantum logic circuits 400, 410, 420. In some implementations, each of the example quantum logic circuits 400, 410, 420 corresponds to part of a computing program for training a quantum feature map-based classifier. Each of the example quantum logic circuits 400, 410, 420 includes unitary operations applied to qubits defined by qubit devices of a quantum processing unit (e.g., the quantum processing unit 102 in FIG. 1). In some implementations, each of the example quantum logic circuits 400, 410, 420 includesunitary operations applied to qubits defined by qubit devices in a quantum processing unit with the connectivity graph representation 500 shown in FIG. 5. In some implementations, each of the example quantum logic circuits 400, 410, 420 may be executed on a superconducting quantum processing unit (e.g., the example superconducting quantum processing unit 102A in FIG. 1) or other superconducting quantum processing unit or other quantum processor modalities. Each of the quantum logic circuits 400, 410, 420 is configured to implement a quantum feature mapping process. In other words, the quantum logic circuits 400, 410, 420, when executed, can map classical features of each data sample from a dataset into corresponding quantum states.

[0126] As shown in FIG. 4A, the example quantum logic circuit 400 includes a sequence of alternating sets of single-qubit rotation gates 404 and two-qubit iSWAP gates 406 applied on 9 qubits 412. Specifically, the quantum logic circuit 400 includes a set of Hadamard gates, H, applied on the 9 qubits at a first time step t1, a first set of single-qubit rotation gates 404A on the y basis, Ry(0), applied on the 9 qubits at a second time step t2, each of which is configured to apply a specific phase rotation to a qubit around the Y axis of the Bloch sphere. The quantum logic circuit 400 includes a first set of two-qubit iSWAP gates 406A at a third time step t3. The quantum logic circuit 400 includes a second set of single-qubit rotation gates 404B on the X basis, Rx(0), applied on the 9 qubits at a fourth time step t4, each of which is configured to apply a specific phase rotation to a qubit around the X axis of the Bloch sphere. The quantum logic circuit 400 includes a second set of two-qubit iSWAP gates 406B at a fourth time step t4. The quantum logic circuit 400 includes a third set of single-qubit rotation gates 404C on the Y basis, Ry(0), applied on the 9 qubits at a sixth time step t6, each of which is configured to apply a specific phase rotation to a qubit around the Y axis of the Bloch sphere. The quantum logic circuit 400 includes a third set of two-qubit iSWAP gates 406C at a seventh time step t7.

[0127] In some instances, a Hadamard gate can be expressed by the unitary operator matrix

[0128] As shown in FIG. 4B, the example quantum logic circuit 410 includes a sequence of alternating sets of single-qubit rotation gates 414 and two-qubit iSWAP gates 406 applied on nine qubits 412. Specifically, the quantum logic circuit 410 includes a set of Hadamard gates, H, applied on the nine qubits at a first time stepa first set of single-qubit rotation gates 414A applied on the nine qubits, at a second time step t2. The first set of single-qubit rotation gates 414A includes a subset of single-qubit rotation gates on the y basis, Ry(0), applied on six of the nine qubits (e.g., 412-1, 412-2, 412-3, 412-7, 412-8, 412-9) each of which is configured to apply a specific phase rotation to a qubit around the Y axis of the Bloch sphere. The first set of single-qubit rotation gates 414A further includes a subset of single-qubit rotation gates on the x basis, Rx(0), applied on three of the nine qubits (e.g., 412-4, 412-5, 412-6), each of which is configured to apply a specific phase rotation to a qubit around the X axis of the Bloch sphere. The quantum logic circuit 410 includes a first set of two-qubit iSWAP gates 406A at a third time step t3. The quantum logic circuit 410 includes a second set of single-qubit rotation gates 414B applied on the 9 qubits at a fourth time step t4. The second set of single-qubit rotation gates 414B includes a subset of single-qubit rotation gates on the x basis, Rx(0), applied on six of the nine qubits (e.g., 412-1, 412-2, 412-3, 412-7, 412-8, 412-9) each of which is configured to apply a specific phase rotation to a qubit around the X axis of the Bloch sphere. The second set of single-qubit rotation gates 414B includes a subset of single-qubit rotation gates on the y basis, Ry(0), applied on three of the nine qubits (e.g., 412-4, 412-5, 412-6), each of which is configured to apply a specific phase rotation to a qubit around the Y axis of the Bloch sphere. The quantum logic circuit 410 includes a second set of two-qubit iSWAP gates 406B at a fifth time step t5. The quantum logic circuit 410 includes a third set of single-qubit rotation gates 414C applied on the 9 qubits at a sixth time step t6. The third set of single-qubit rotation gates 414C includes a subset of single-qubit rotation gates on the y basis, Ry(0), applied on six of the nine qubits (e.g., 412-1, 412-2, 412-3, 412-7, 412-8, 412-9) each of which is configured to apply a specific phase rotation to a qubit around the Y axis of the Bloch sphere. The third set of single-qubit rotation gates 414C further includes a subset of single-qubit rotation gates on the x basis, Rx(0), applied on three of the nine qubits (e.g., 412-4, 412-5, 412-6), each of which is configured to apply a specific phase rotation to a qubit around the X axis of the Bloch sphere. Finally, the quantum logic circuit 410 includes a third set of two-qubit iSWAP gates 406C at a seventh time step t7.

[0129] Each of the first, second and third sets of two-qubit iSWAP gate 406A, 406B, 406C in the example quantum logic circuits 400, 410 is configured to create entanglement between qubit pairs. Each of the first, second and third sets of two-qubit iSWAP gates 406A, 406B, 406C is further divided into sub-operations performed during sub-intervals. For example, each of the first, second and third datasets of two-qubit iSWAP gates 406A, 406B, 406C includes a first set of two-qubit iSWAP gates at a first sub-interval to create entanglement between qubit 412-1 and qubit412-2, and between qubit 412-4 and qubit 412-9; a second set of two-qubit iSWAP gates at a second subinterval to create entanglement between qubit 412-5 and qubit 412-7, and between qubit 412-8 and qubit 412-9; a third set of two-qubit iSWAP gates at a third sub-interval to create entanglement between qubit 412-1 and qubit 412-6, and between qubit 412-7 and qubit 412-8; a fourth set of two-qubit iSWAP gates at a fourth sub-interval to create entanglement between qubit 412-3 and qubit 412-5, and between qubit 412-6 and qubit 412-7; a fifth set of two-qubit iSWAP gates at a fifth sub-interval to create entanglement between qubit 412-1 and qubit 412-5; a sixth set of two-qubit iSWAP gates at a sixth sub-interval to create entanglement between qubit 412-3 and qubit412-4, and between qubit 412-5 and qubit 412-9; and a seventh set of two-qubit iSWAP gates at a seventh sub-interval to create entanglement between qubit 412-2 and qubit 412-3.

[0130] As shown in FIG. 4A, classical features of a data sample in a dataset can be encoded through one-qubit rotation operations which are rotations of the individual quantum states around the X or Y axes. Each data sample can be represented by a vector of nine classical features, and each classical feature is encoded into the corresponding rotation angle. The quantum logic circuit 400 is applied on nine qubits and includes three data encoding layers. This specifies the feature mapping scheme where each qubit device encodes one feature (e.g., one-to-one mapping between feature and qubit) and all rotation angles are defined on the interval [0, n / 4] according to equation (11), where a = 1 / 4 and, 9 E [0, TT / 4], V i,k.

[0131] As shown in FIG. 4B, a subset of classical features may be selected based on a criterion such as feature importance which ranks features in terms of their relative predictive power. In some implementations, feature importance may be implemented via a Random Forest classifier, a SHapley Additive exPlanations (SHAP) analysis, or a Principal Component Analysis (PCA). Instead of mapping all classical features in a datasample, a subset of classical features can be selected and the selected subset of classical features can be mapped to one or more qubits through single-qubit rotation operations which are rotations of the individual quantum states around the X or Y axes. For example, when each data sample can be represented by a vector of nine classical features, three top classical features can be selected and each can be mapped into the corresponding rotation angles of single-qubit rotation gates applied to one or more qubits. This specifies a feature mapping scheme where multiple qubits are used to encode the same selected classical feature (e.g., one-to-multiple mapping between feature and qubit) and all rotation angles are defined on the interval [0, n / 4] according to equation (11), where a = 1 / 4 and, 6 G [0, TT / 4], V i, k. In particuar, a first selected classical feature of a data sample can be encoded in rotation angles of single-qubit rotation gates applied on qubits 412-1, 412-2, 412-3; a second selected classical feature of the data sample can be encoded in rotation angles of single-qubit rotation gates applied on qubits 412-4, 412-5, 412-6; and a third selected classical feature of the data sample can be encoded in rotation angles of single-qubit rotation gates applied on qubits 412-7, 412-8, 412-9. In some implementations, the quantum logic circuit 410 is configured to perform a multi-qubit feature mapping of data samples.

[0132] In some implementations, final quantum states of the qubits 412 are measured. The example quantum logic circuit 400 may include a set of measurements, each of which is configured to extract classical information from the qubits 412 causing collapsing of the superposition of a qubit 412 into a respective definite output represented by a classical bit (0 or 1). The measurement produces a classical bitstring, which is a data sample from the probability distribution encoded in the final quantum state (each quantum state encodes a probability distribution).

[0133] As shown in FIGS. 4A-4B, each of the quantum logic circuit 400, 410 includes three layers of two-qubit iSWAP gates 406 creating entanglement; alternating with three layers of single-qubit Rx, and Rygates 404 performing repeated data encoding. The quantum logic circuit 400, 410 can be configured to ensure that data samples in datasets are not concentrated in any one region of the system’s Hilbert space. In some instances, a quantum logic circuit may include a different number of layers of singlequbit rotation gates and two-qubit iSWAP gates. For another example, the three layers of the single-qubit rotation gates may be organized in another order. In some instances,the quantum logic circuit may include other types of parametric quantum logic gates, and the features can be encoded into gate parameters of the quantum logic circuits in another manner. In some instances, other multi- qubit gates different from the iSWAP gate may be used. For another example, the sub-operations of the two-qubit iSWAP gates may be organized in a different order.

[0134] As shown in FIG.4C, the example quantum logic circuit 420 includes three layers of first subsets of quantum logic gates 422 A, 422 B, 422 C. Each of the first subsets of quantum logic gates 422A, 422B, 422C includes fixed non-Clifford quantum logic gates. A fixed quantum logic gate is non-parametric, which means that the quantum logic gate is predetermined and is not parameterized by a variable. As such, each time the fixed quantum logic gate is applied during an execution of the quantum logic circuit, the fixed quantum logic gate remains the same regardless of input parameters or other variables. Each quantum logic gate in the first subset 422 A, 422 B, 422 C maybe a singlequbit, a two-qubit, or a multi- qubit quantum logic gate. In some implementations, each quantum logic gate of the first subset 422A, 422B, 422C is configured to create magic. The quantum logic gate in the first subset 422 A, 422B, 422C can introduce the nonstabilizer nature of quantum state or operations that cannot be generated using Clifford gates alone. In some implementations, the quantum logic gates in the first subset 422 A, 422B, 422C create magic by transforming stabilizer states into non-stabilizer ("magic”) states. In some instances, magic is a measure of non-Cliffordness of the transformation. In some implementations, each quantum logic gate in the first subset 422A, 422B, 422C is a single-qubit T gate. In some instances, each quantum logic gate in the first subset 422A, 422B, 422C may include a multi-qubit fixed non-Clifford quantum logic gate configured to create magic states. For example, the multi-qubit fixed non-Clifford quantum logic gate may be a controlled-T gate. In some implementations, prior to the application of the first subset 422A, 422B, 422C of quantum logic gates, the quantum logic circuit 420 includes a set of Hadamard gates prior to the application of the first subset 422A, 422B, 422C of quantum logic gates.

[0135] In some implementations, each fixed non-Clifford quantum logic gate in the first subset 422 A, 422 B, 422 C is a single-qubit T gate. The single-qubit T gate can apply a π / 4 phase rotation to the |1⟩ state and can be represented by the unitary operator matrixThe single-qubit T gate can create a property known as "magic” in a quantum state. For example, when a T gate is applied to a superposition state like |+) = (|0) + |1)) / V2, the result is a qubit having a magic state:In some instances, each quantum logic gate in the first subset 422 A, 422B, 422C may include a multi-qubit fixed non-Clifford quantum logic gate configured to create magic states. For example, the multi-qubit fixed non-Clifford quantum logic gate may be a controlled-T gate. In some instances, each fixed non-Clifford quantum logic gate in the first subset 422A, 422B, 422 C may include other types of quantum logic gates. In some implementations, the quantum logic circuit 420 includes a set of Hadamard gates (e.g., the subset 402 shown in FIGS. 4A-4B) prior to the application of the first subset 422 A, 422B, 422C of quantum logic gates.

[0136] As shown in FIG. 4C, the example quantum logic circuit 420 includes three layers of second subsets 424A, 424B, 424C of quantum logic gates that can be used to encode data samples from the input dataset into quantum states, translating lowdimensional classical features of data samples to high-dimensional magic-enhanced quantum features in the Hilbert space. In some instances, the quantum logic circuit 420 is determined or obtained according to the number of classical features and a range of classical feature values of the data samples in the dataset In some instances, each of the second subsets 424A, 424B, 424C of quantum logic gates which is applied to a number of qubits defined by qubit devices in a quantum computing system includes parametric quantum logic gates which are defined by gate parameters. In some implementations, examples of multi-qubit quantum logic gate that can be used to spread magic between qubits include the controlled-Z (CZ) gate, the imaginary SWAP (iSWAP) gate, the controlled-NOT (CNOT) gate, the controlled-phase (CPHASE) gate, and other multi-qubit quantum logic gates.

[0137] FIG. 5 is a schematic diagram showing an example connectivity graph representation 500 of a quantum processing unit. In some instances, the quantum processing unit may be part of a quantum computing system which may be communicably connected to other subsystems or components of the quantum computing system. The connectivity graph representation 500 of a quantum processingunit includes a device array in which each node 502 corresponds to a qubit device and each edge 504 corresponds to a coupler device or another mechanism that enables controlled interaction between two qubit devices. The connectivity graph representation 500 is an abstract representation of which qubit devices can directly interact with one another, which may not represent a literal physical layout depending on the quantum hardware platforms that are used to realize the logical connectivity in physical space.

[0138] The term "coupler device,” as used herein, broadly refers to any physical element or operational mechanism that mediates or enables / disables a tunable or controllable coupling between qubit devices, which may vary depending on the underlying quantum hardware technology. In superconducting quantum circuits, the coupler device can include an electrical element, such as a Josephson junction-based circuit, a tunable resonator, or a variable inductive or capacitive network disposed between adjacent qubit devices to selectively control their coupling strength. In trapped-ion systems, the coupler device may correspond to a control operation that activates spin-motion coupling through laser pulses, whereby collective vibrational modes serve as an effective coupling channel. In neutral-atom systems, the coupler device may be implemented as a laser-induced Rydberg interaction between atoms positioned within a blockade radius, the interaction being tunable through optical detuning or atomic spacing. In photonic systems, the coupler device may correspond to a reconfigurable optical element, such as a variable beam splitter or phase shifter, that controls interference between optical modes. In semiconductor spin-qubit systems, the coupler device may be realized through an electrically controlled tunneling barrier or exchange region that mediates spin-spin interaction between neighboring quantum dots. Thus, while the connectivity graph representation 400 illustrates edges 404 as coupler devices for conceptual clarity, the physical realization of a coupler device may encompass a dedicated hardware element, a dynamically controlled field, or an interaction operation specific to the qubit implementation technology.

[0139] As shown in FIG. 5, the connectivity graph representation 500 includes nine nodes 502, e.g., 502-1, 502-2, 502-3, 502-4, 502-5, 502-6, 502-7, 502-8, 502-9 representing nine qubit devices, and twelve edges 504, e.g., 504-1, 504-2, 504-3, 404-4, 504-5, 504-6, 504-7, 504-8, 504-9, 504-10, 504-11, 504-12 representing twelve couplerdevices. Each edge 504 is connected between two nodes 502. Qubit devices (nodes) can be coupled to each other if they share a common coupler device (edge). The quantum processing unit may include additional devices, including additional qubit devices, readout resonators, or other quantum circuit devices.

[0140] In some instances, the quantum processing unit is a superconducting quantum processing unit which includes superconducting quantum circuit devices arranged in a two-dimensional or three-dimensional lattice structure. The connectivity graph representation 500 can represent a physical layout of the quantum circuit devices in the superconducting quantum processing unit In this case, the superconducting quantum circuit devices are arranged in a rectilinear (e.g., rectangular, or square) array that extends in two spatial dimensions (e.g., in the plane of the page). In some implementations, the devices can be arranged in another type of ordered array. In some instances, the rectilinear array also extends in a third spatial dimension (e.g., in / out of the page), for example, to form a cubic array or another type of three-dimensional array.

[0141] Quantum states (e.g., qubits) of respective qubit devices can be manipulated by control signals, or read by readout signals, generated by a control system of the quantum computing system. The qubit devices can be controlled individually, for example, by delivering control signals to the respective qubit devices. In some cases, a set of neighboring quantum circuit devices (e.g., the qubit devices and the coupler device) are controlled jointly by delivering control signals to the set. In some cases, readout devices can detect the states of the qubit devices, for example, by interacting directly with the respective qubit devices.

[0142] In some instances, a qubit device may be a superconducting tunable-frequency qubit device such as a flux-tunable transmon device, a flux qubit device, a capacitively shunted flux qubit device, a flatsonium device, a fluxonium device, or another type of superconducting qubit device. In some implementations, a flux-tunable transmon device includes a superconducting circuit loop (e.g., a SQUID loop), which can receive a magnetic flux that tunes the transition frequency of the tunable-frequency qubit device. As an example, the superconducting circuit loop may include two Josephson junctions connected in parallel, and the tunable-frequency qubit device may also include a shunt capacitor in parallel with the two Josephson junctions. For another example, the superconducting circuit loop may include three Josephson junctions, asingle Josephson junction, and a linear indicator in parallel, or another loop. In some implementations, the transition frequency of the tunable-frequency qubit device may be defined at least in part by Josephson energies of the two Josephson junctions, a capacitance of the shunt capacitor, and a magnetic flux threading the superconducting circuit loop.

[0143] In some examples, the transition frequency of a qubit device is not tunable by application of a bias field and is independent of magnetic flux experienced by the qubit device. For instance, a fixed-frequency qubit device may have a fixed transition frequency that is defined by an electronic circuit of the qubit device. As an example, a fixed-frequency qubit device (e.g., a fixed- frequency transmon qubit device) may be implemented without a SQUID loop. In some examples, the fixed- frequency qubit device includes one Josephson junction and a shunt capacitor, and the transition frequency of the fixed-frequency qubit device is defined at least in part by a Josephson energy of the Josephson junction and a capacitance of the shunt capacitor, which is independent of a magnetic flux experienced by the fixed-frequency qubit device.

[0144] In some implementations, a superconducting circuit loops in a tunable-frequency qubit device can receive a magnetic flux Φ(t) that controls the transition frequency of the tunable-frequency qubit device. In this case, the tunable-frequency qubit device is a flux tunable quantum circuit device, and the superconducting quantum processing unit is a flux tunable quantum processing unit. Manipulating the magnetic flux Φ(t) through the superconducting circuit loop can increase or decrease the transition frequencies of the example tunable-frequency qubit device. In this example, the magnetic flux Φ(t) through the superconducting circuit loop can be modified in order to tune the transition frequencies of the tunable-frequency qubit device. In some cases, inductors or other types of flux bias elements as part of control lines carrying the control signals are coupled to superconducting circuit loops of respective tunable-frequency qubit devices by respective mutual inductances, and the magnetic flux Φ(t) through the superconducting circuit loops can be controlled by the current through the flux bias element

[0145] In some implementations, the tunability of the qubit devices, in the superconducting quantum processing unit allows pairs of qubit devices to be selectively coupled on-demand to perform multi-qubit quantum logic gates, to entangle pairs ofqubits defined by pairs of qubit devices, or to perform other types of control operations. The qubit devices can have a high "on / off” ratio, which refers to the ratio of the effective coupling strength provided by control of the tunable-frequency coupler device. In some implementations, the coupler devices, when activated or deactivated, can enable or disable coupling between two neighboring qubit devices, respectively.

[0146] In the superconducting quantum processing unit, the coupler devices may be implemented by transmon qubit devices, flux qubit devices, flatsonium qubit devices, fluxonium qubit devices, or other types of tunable-frequency qubit devices. In some implementations, the coupler device is a tunable-frequency coupler device. In certain examples, a tunable-frequency coupler device may include a superconducting circuit loop (e.g., a SQUID loop), which can receive a coupler flux bias that tunes the transition frequency of the tunable-frequency coupler device. In some instances, a tunable-frequency coupler device includes two coupler electrodes; the two Josephson junctions of the tunable-frequency coupler device are connected in parallel between the two coupler electrodes; the shunt capacitor is caused by the two coupler electrodes. In this case, the tunable-frequency coupler device is a tunable-frequency "floating” coupler device. In some implementations, the coupler devices may be implemented as the tunable "grounded” coupler device. In some implementations, the coupler devices may be implemented as a fixed-frequency coupler device (e.g., a capacitor).

[0147] In some instances, information is encoded in the qubit devices in the superconducting quantum processing unit, and the information can be processed by operation of the qubit devices. For instance, input information can be encoded in the computational states or computational subspaces defined by some or all of the qubit devices in the quantum processing unit The information can be processed, for example, by applying a quantum algorithm or other operations to the input information. The quantum algorithm may be decomposed as quantum logic gates or instruction sets that are performed by the qubit devices and coupler devices over a series of clock cycles. For instance, a quantum algorithm may be executed by a combination of single-qubit quantum logic gates and two-qubit quantum logic gates. In some cases, information is processed in another manner. Processing the information encoded in the qubit devices can produce output information that can be extracted from the qubit devices. The output information can be extracted, for example, by performing state tomography orindividual readout operations. In some instances, the output information is extracted over multiple clock cycles or in parallel with the processing operations.

[0148] In some aspects of operation, a control system can communicate control signals to the qubit devices in the quantum processing unit The control signals can be configured to modulate, increase, decrease, or otherwise manipulate the transition frequencies of the qubit devices (e.g., when the qubit devices are tunable-frequency qubit devices). In some implementations, a control signal includes a flux bias control signal that varies a magnetic flux experienced by a superconducting tunable-frequency qubit device of a superconducting quantum processing unit. In trapped-ion systems, control signals are realized as laser beams or radio-frequency fields that excite motional sidebands or drive spin transitions, with amplitude, phase, and detuning parameters determining the effective gate operations. Neutral-atom systems employ optical-tweezer and laser-excitation control signals, where tightly focused optical beams position and address individual atoms and modulate Rydberg excitation for two-qubit interactions. Photonic quantum systems use optical control signals such as phaseshifter voltages, electro-optic modulators, or pump lasers to generate and manipulate photonic qubits or entanglement Spin-based quantum devices, including semiconductor quantum dots and color centers, utilize electrical gate voltages, magnetic or microwave fields, and optical pulses to control spin initialization, manipulation, and readout. Accordingly, the control circuitry of a quantum processing unit may generate and coordinate different types of electrical, magnetic, or optical control signals depending on the qubit implementation technology, each providing the required temporal, spectral, and spatial precision for reliable quantum operations.

[0149] In some instances, a control signal can dynamically tune the transition frequency of the tunable-frequency qubit device to enable interactions between qubits, typically by bringing them into resonance or near-resonance to activate a coupling mechanism, such as cross- resonance, iSWAP, or CZ (controlled- Z) gates. In some instances, a control signal may include a modulation signal that is configured to modulate a transition frequency of a tunable-frequency qubit device at a certain modulation frequency and a certain modulation amplitude.

[0150] In some instances, control signals can be communicated to the coupler devices to generate interactions between the coupler device and the neighboring qubitdevices. In some cases, the control signals can generate an interaction between two qubit devices that are mediated by the coupler device. In some implementations, the control signals are configured to generate interactions that perform quantum logic gates on the qubits defined by the qubit devices. For example, in some cases, one or more of the control signals generate an interaction that applies a two-qubit quantum logic gate to a pair of qubits defined by two of the qubit devices coupled through a coupler device in the quantum processing unit. A control signal may be a current signal, a voltage signal, or another type of electrical signal which can be used to control a control line, for example with a flux bias element, to modulate a flux bias control signal so as to modulate a magnetic flux and generate a modulated magnetic flux (e.g., a modulated flux bias). In this case, the control signals activate two- qubit quantum logic gates by modulating a transition frequency of a qubit device, and / or tuning a transition frequency of the coupler device.

[0151] In some instances, a control system associated with the quantum processing unit can identify a quantum logic gate to be applied to a pair of qubits in the quantum processing unit The pair of qubits includes, for example, a first qubit defined by the qubit device 502-1 and a second qubit defined by the qubit device 502-2 in the qubit device array through the coupler device 504-1. The control signal can be configured to turn on the coupler device 504-1 (e.g., when the coupler device is a tunable- frequency coupler device) to enable the coupling between the qubit devices 502-1 and 502-2. The control signal can be further configured to perform a control operation (e.g., two-qubit quantum logic gate) on the qubit devices 502-1 and 502-2. At the same time, control signals maybe communicated to qubit devices 504-2, 504-12 to disable the coupling between qubit devices 502-2 and 502-3 as well as the coupling between qubit devices 502-1 and 502-5 when the two-qubit quantum logic gate is applied to qubits defined by qubit devices 502-1 and 502-2. The control system can perform the quantum logic gate by communicating the control signal to a control line that is coupled to the coupler device in the quantum processing unit. In some implementations, the control signal can be further configured to perform a calibration process to determine device parameters and control parameters for activating the quantum logic gate; for enabling and disabling the coupling between the two qubit devices, and for other control operations.

[0152] Values of the control parameters of the control signal can be selected to achieve a specified multi-qubit quantum logic gate. In some systems, applying the two-qubit quantum logic gate to the pair of qubits defined by a pair of tunable-frequency qubit devices may include applying any quantum logic gate from the XY family of gates, the controlled-phase family of gates, the iSWAP family of gates, or another family of gates. In some cases, applying the two-qubit quantum logic gate to the pair of qubits includes applying a controlled-phase gate (e.g., a controlled-Z gate) to the pair of qubits. In some cases, applying the two-qubit quantum logic gate to the pair of qubits includes applying a Bell-Rabi gate, a square-root-of-Bell-Rabi gate, or another two-photon gate to the pair of qubits.

[0153] In some implementations, the control system, or another type of system associated with the quantum computing system, determines the values of the control parameters for applying two-qubit quantum logic gates in the quantum processing unit For example, the values of the control parameters for the control signal may be determined by a gate calibration process defined in software, firmware, or hardware or a combination thereof. In some cases, the control system executes a gate calibration process when the superconducting quantum processing unit is first installed for use in the quantum computing system, and the gate calibration process may be repeated at other times (e.g., as needed, periodically, according to a calibration schedule, etc.). For instance, a gate calibration module may execute a calibration process that obtains values of device parameters of the qubit devices and the coupler devices in the superconducting quantum processing unit. For example, the device parameters include a range of qubit operating frequency and anharmonicity of the qubit devices (e.g., when the qubit devices 502 are tunable-frequency qubit devices), an operating frequency and anharmonicity of the qubit devices (e.g., when the qubit devices 502 are fixed- frequency qubit devices), and a coupling between the qubit devices and the tunable-frequency coupler devices, or another parameter.

[0154] In some instances, the values of the device parameters are used to determine the values of the control parameters for the control signal. In some implementations, the control parameters for the control signal may include the relative duration, relative phase, gate-activating amplitudes and time durations in an asymmetric bipolar flux pulse, flux modulation frequency, flux modulation amplitude, or another parameter.When the qubit devices are tunable-frequency qubit devices, the control signal with the determined parameters can be applied to one or more of the qubit devices to bring the qubit devices on resonance with each other.

[0155] In some implementations, a coupler bias control signal communicated to the tunable-frequency coupler device is configured to tune the transition frequency of the tunable-frequency coupler device. The transition frequency of the tunable-frequency coupler device can be changed from a parking frequency at which the coupling is turned off (e.g., zero coupling and idling condition) to a gate-activating frequency when the coupling is turned on for implementing a multi-qubit quantum logic gate that maximizes the coupling or the fidelity. In some implementations, a tunable- frequency coupler device is configured to dynamically modify the coupling strength between qubit devices, e.g., from an effective zero coupling during idling to large coupling for a fast two-qubit gate.

[0156] The systems and techniques presented in the present application are applied on a training dataset containing 214 data samples (This is the Glass Identification Dataset from B. German, Glass Identification, UCI Machine Learning Repository, 1987). Each data sample represent a glass sample, described by nine features (i.e., Refractive Index, Sodium, Magnesium, Aluminium, Silicon, Potassium, Calcium, Barium, and Iron). All 214 data samples in the dataset can be divided into four datasets with four classes (i.e., Window, Container, Tableware, and Headlamp); and each data sample has a known class label. The dataset is heavily imbalanced, which makes it harder to find the right balance between precision and recall and prompts us to choose the Fl score with 'macro' averaging across classes as the preferred metric. Table 1 shows a distribution of data samples in the dataset by classes.Table 1

[0157] Feature importance analysis is conducted using a random forest classifier. The ranking of the nine features in terms of their relative predictive power is shown in Table 2 below.Table 2

[0158] A first quantum feature map-based classifier was trained on all nine features according to the operations described in the example process 220 shown in FIG. 2B using the quantum logic circuit 400 shown in FIG. 4A. A second quantum feature mapbased classifier was trained on the top three features (i.e., Mg, Ba, and Al) according to the operations described in the example process 220 shown in FIG. 2B using the quantum logic circuit 410 shown in FIG. 4B. The first and second quantum feature mapbased classifiers are separately trained using a quantum simulator and a 9-qubit superconducting quantum processing unit Different quantum density operators can be obtained when different quantum logic circuits are used.

[0159] For comparison, four standard classical classifiers which are widely used in data science applications, including multi-layer perceptron (MLP), random forest (RF), support vector machine (SVM), and logistic regression (LR), are also performed on the same dataset MLP is a feedforward neural network trained through the backpropagation of error with gradient descent RF is an ensemble learning model that builds a strong classifier through the aggregation of predictions made by several individual weak classifiers (decision trees) trained in parallel on a random dataset of the data. SVM perform classification using the kernel trick to implicitly map their inputs into highdimensional feature spaces where linear classification can be performed more easily. LR is, arguably, the most basic and simple model consisting of mapping a linear combination of features into the interval [0, 1] (which can be interpreted as probability) with the help of a logistic function. The scikit-learn implementation of these classical classifiers were used with the set of optimised parameters shown in FIG. 6A.

[0160] Similar to the feature standardisation for the quantum feature map-based classifier, where all classical features are mapped to the same rotation angle interval [0, απ] as described in Equation (11) above, classical classifiers such as MLP, SVM and LR also work with standardized features. The scikit-learn StandardScaler class is used to standardize features by removing their mean values and scaling them to unit variance.

[0161] FIGS. 6B-6C are plots 610, 620 showing Fl score results for the classical benchmarks and the quantum feature map-based classifier executed on a quantum simulator (DMC (sim)) and on a superconducting quantum processing unit (DMC (QPU)). The results based on the quantum feature map-based classifier using the superconducting quantum processing unit were obtained using the approximation based on the first order Pauli expectation values (DMC (QPU: approximation). The results based on the quantum feature map-based classifier using a quantum simulator were obtained using both the first order Paulis approximation shown in Equation (29) and the exact formula shown in Equation (18) (DMC(sim: approximation) and DMC (sim: exact))

[0162] All Fl scores are out-of-sample. The scikit-learn test- train-split class was used to generate ten random 80:20 splits into training and test data samples. The optimal value of the range parameter a was found to be 0.2 through a simple gridsearch method. In some implementations, a can be selected to maximize a measure of magic.

[0163] As shown in FIGS. 6B-6C, the dots indicate the mean values and the error bars indicate the uncertainty in Fl scores (+1 standard deviation). The nine features scenario with one-to-one mapping (e.g., each classical feature is mapped to a qubit) has a higher average Fl score across all classifiers (shown in FIG. 6B) in comparison with those obtained using the one-to-multiple mapping (three top classical features are used and each classical feature is mapped to three qubits) (shown in FIG. 6C). This is not surprising since nine features contain significantly more information as per the feature importance analysis presented in Table 2.

[0164] As shown in FIG. 6B, DMC (sim) performs comparable with or equivalent to the classical benchmarks on the nine features scenario. At the same time it ranks above all the classical benchmarks on the top three features scenario with triple qubit feature encoding (FIG. 6C), where the mean DMC Fl score is almost a full one standard deviation above the mean Fl scores of all the classical classifiers. This is caused by the expressive power of the quantum feature map and ability of the quantum feature mapbased classifier presented here to preserve more valuable information. While it may not be clearly visible when we work with all nine features, dealing with the reduced set of features puts more pressure on the classifiers (in terms of limited available predictive information) and suppresses performance of the classical models more than the quantum feature map-based classifier.

[0165] As shown in FIGS. 6B-6C, Fl scores obtained by performing the quantum feature map-based classifier on the superconducing quantum processing unit are noisier than the results obtained on a quantum simulator and show lower average Fl scores. However, even with the noise present in the superconducting quantum processing unit, the performance of the quantum feature map-based classifier using a superconducting quantum processing unit is comparable with or equivalent to those obtained from the classical classifiers on the three top feature scenario.

[0166] Some of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Some of the subject matterdescribed in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data-processing apparatus. A computer storage medium can be, or can be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Moreover, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media.

[0167] Some of the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0168] In a general aspect, quantum feature map-based classifiers are presented.

[0169] In a first example, a computing system includes a quantum processing unit; and one or more classical processors. The one or more classical processors are configured to obtain a plurality of training datasets associated with respective classes; process the plurality of training datasets to determine representative quantum density operators for the respective classes; and store the representative quantum density operators for use by a classifier. Determining a representative quantum density operator for a class includes parameterizing a quantum logic circuit based on the training dataset associated with the class, the quantum logic circuit comprising at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates; obtaining measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit; and based on the measurements, determining the representative quantum density operator for the class.

[0170] Implementations of the first example may include one or more of the following features. Each training dataset includes a plurality of training data samples. Each training data sample includes a plurality of classical features. Parameterizing the quantum logic circuit includes parameterizing a plurality of quantum logic gates based on the plurality of classical features. Each training dataset includes a plurality oftraining data samples. Each training data sample includes a plurality of classical features, and parameterizing the quantum logic circuit includes selecting a subset of the plurality of classical features; and parameterizing a plurality of quantum logic gates based on the selected subset of the plurality of classical features.

[0171] Implementations of the first example may include one or more of the following features. Each training dataset includes a plurality of training data samples, and determining the representative quantum density operator for a class includes determining a plurality of quantum density operators based on the plurality of training data samples; and averaging the plurality of quantum density operators.

[0172] Implementations of the first example may include one or more of the following features. Each training dataset includes a plurality of training data samples. Each training data sample includes classical features. Parameterizing the quantum logic circuit includes calculating a number of the classical features of the training data samples and a range of feature values; and standardizing the classical features according to the range of feature values. The expectation values include multiple subsets of expectation values associated with distinct measurement bases for qubits in the parameterized quantum logic circuit

[0173] Implementations of the first example may include one or more of the following features. The one or more classical processors are configured to update the representative quantum density operators, and updating a representative quantum density operator associated with a class includes obtaining a new training data sample associated with the class; processing the new training data sample to determine a new quantum density operator associated with the new training data sample; updating the representative quantum density operator associated with the class based on the new quantum density operator; and storing the updated representative quantum density operator for use by the classifier.

[0174] Implementations of the first example may include one or more of the following features. The one or more classical processors are configured to update the representative quantum density operators, and updating the representative quantum density operators includes obtaining a new training dataset associated with a new class; processing the new training dataset to determine a new representative quantumdensity operator for the new class; and storing the new representative quantum density operator for use by the classifier.

[0175] Implementations of the first example may include one or more of the following features. Each representative quantum density operator includes one of a density matrix; or a reduced form of a density matrix. The single-qubit quantum logic gates include single-qubit rotation gates, and parameterizing the quantum logic circuit includes determining rotation angles for one or more of the single-qubit rotation gates. Storing the representative quantum density operators for use by the classifier includes storing the representative quantum density operators in a database that associates the representative quantum density operators with respective identifiers of the classes.

[0176] In a second example, a computing method includes by operation of a one or more classical processors, obtaining a plurality of training datasets associated with respective classes; processing the plurality of training datasets to determine representative quantum density operators for the respective classes; and storing the representative quantum density operators for use by the classifier. Determining a representative quantum density operator for a class includes parameterizing a quantum logic circuit based on the training dataset associated with the class, the quantum logic circuit including at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates; obtaining measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on a quantum processing unit; and based on the measurements, determining a representative quantum density operator associated with the training dataset.

[0177] Implementations of the second example may include one or more of the following features. Each training dataset includes a plurality of training data samples. Each training data sample includes a plurality of classical features. Parameterizing the quantum logic circuit includes parameterizing a plurality of quantum logic gates based on the plurality of classical features. Each training dataset includes a plurality of training data samples. Each training data sample includes a plurality of classical features. Parameterizing the quantum logic circuit includes selecting a subset of the plurality of classical features; and parameterizing a plurality of quantum logic gates based on the selected subset of the plurality of classical features.

[0178] Implementations of the second example may include one or more of the following features. Each training dataset includes a plurality of training data samples, and determining the representative quantum density operator for a class includes determining a plurality of quantum density operators based on the plurality of training data samples; and averaging the plurality of quantum density operators.

[0179] Implementations of the second example may include one or more of the following features. Each training dataset includes a plurality of training data samples. Each training data sample includes classical features. Parameterizing the quantum logic circuit includes calculating a number of the classical features of the training data samples and a range of feature values; and standardizing the classical features according to the range of feature values. The expectation values include multiple subsets of expectation values associated with distinct measurement bases for qubits in the parameterized quantum logic circuit

[0180] Implementations of the second example may include one or more of the following features. The one or more classical processors are configured to update the representative quantum density operators, and updating a representative quantum density operator associated with a class includes obtaining a new training data sample associated with the class; processing the new training data sample to determine a new quantum density operator associated with the new training data sample; updating the representative quantum density operator associated with the class based on the new quantum density operator; and storing the updated representative quantum density operator for use by the classifier.

[0181] Implementations of the second example may include one or more of the following features. The one or more classical processors are configured to update the representative quantum density operators, and updating the representative quantum density operators includes obtaining a new training dataset associated with a new class; processing the new training dataset to determine a new representative quantum density operator for the new class; and storing the new representative quantum density operator for use by the classifier.

[0182] Implementations of the second example may include one or more of the following features. Each representative quantum density operator includes one of a density matrix; or a reduced form of a density matrix. The single-qubit quantum logicgates include single-qubit rotation gates, and parameterizing the quantum logic circuit includes determining rotation angles for one or more of the single-qubit rotation gates. Storing the representative quantum density operators for use by the classifier includes storing the representative quantum density operators in a database that associates the representative quantum density operators with respective identifiers of the classes.

[0183] In a third example, a computing system includes a quantum processing unit; and one or more classical processors. The one or more classical processors includes a classifier. The classifier is configured to obtain a test data sample; obtain a plurality of representative quantum density operators associated with respective classes; process the test data sample to determine a test quantum density operator for the test data sample; determine a classification of the test data sample based on an evaluation of distances between the test quantum density operator and the plurality of representative quantum density operators; and return the classification of the test data sample. Determining the test quantum density operator for the test data sample includes parameterizing a quantum logic circuit based on the test data sample, the quantum logic circuit comprising at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates; obtaining measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit; and based on the measurements, determining the test quantum density operator associated with the test data sample.

[0184] Implementations of the third example may include one or more of the following features. The distance is a Frobenius distance, and evaluating the distances includes determining the Frobenius distance between the test quantum density operator and each representative quantum density operator using an approximate quantum state technique. Determining the test quantum density operator for the test data sample includes obtaining multiple measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit multiple times.

[0185] Implementations of the third example may include one or more of the following features. The one or more classical processors are further configured to train the classifier, and training the classifier includes obtaining a plurality of trainingdatasets associated with the respective classes; and processing the plurality of training datasets to determine the plurality of representative quantum density operators for the respective classes. Determining the plurality of representative quantum density operators for the respective classes includes determining an average quantum density operator for each of the classes. The test data sample includes a plurality of classical features, and parameterizing the quantum logic circuit includes parameterizing a plurality of quantum logic gates based on the plurality of classical features. Determining the classification of the test data sample includes identifying a particular class of the respective classes, and returning the classification includes returning an identifier associated with the particular class.

[0186] Implementations of the third example may include one or more of the following features. The test quantum density operator includes one of: a density matrix; or a reduced form of a density matrix. The single-qubit quantum logic gates include single-qubit rotation gates, and parameterizing the quantum logic circuit includes determining rotation angles for one or more of the single-qubit rotation gates. The computing system includes a database that associates the representative quantum density operators with respective identifiers of the classes.

[0187] In a fourth example, a computing method includes, by operation of a one or more classical processors, obtaining a test data sample; obtaining a plurality of representative quantum density operators associated with a plurality of classes; processing the test data sample to determine a test quantum density operator for the test data sample; determining a classification of the test data sample based on an evaluation of distances between the test quantum density operator and the plurality of representative quantum density operators; and returning the classification of the test data sample. Determining the test quantum density operator for the test data sample includes parameterizing a quantum logic circuit based on the test data sample, the quantum logic circuit including at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates; obtaining measurements of expectation values of quantum observables on quantum states generated by causing a quantum processing unit to execute the parameterized quantum logic circuit; and based on the measurements, determining the test quantum density operator associated with the test data sample.

[0188] Implementations of the fourth example may include one or more of the following features. The distance is a Frobenius distance, and evaluating the distances includes determining the Frobenius distance between the test quantum density operator and each representative quantum density operator using an approximate quantum state technique. Determining the test quantum density operator for the test data sample includes obtaining multiple measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit multiple times.

[0189] Implementations of the fourth example may include one or more of the following features. The one or more classical processors are further configured to train the classifier, and training the classifier includes obtaining a plurality of training datasets associated with the respective classes; and processing the plurality of training datasets to determine the plurality of representative quantum density operators for the respective classes. Determining the plurality of representative quantum density operators for the respective classes includes determining an average quantum density operator for each of the classes. The test data sample includes a plurality of classical features, and parameterizing the quantum logic circuit includes parameterizing a plurality of quantum logic gates based on the plurality of classical features. Determining the classification of the test data sample includes identifying a particular class of the respective classes, and returning the classification includes returning an identifier associated with the particular class.

[0190] Implementations of the fourth example may include one or more of the following features. The test quantum density operator includes one of a density matrix; or a reduced form of a density matrix. The single-qubit quantum logic gates include single-qubit rotation gates, and parameterizing the quantum logic circuit includes determining rotation angles for one or more of the single-qubit rotation gates. The computing method further includes accessing a database that associates the representative quantum density operators with respective identifiers of the classes.

[0191] While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separateimplementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

[0192] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[0193] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

CLAIMSWhat is claimed is:

1. A computing system comprising:a quantum processing unit; andone or more classical processors configured to:obtain a plurality of training datasets associated with respective classes; process the plurality of training datasets to determine representative quantum density operators for the respective classes, wherein determining a representative quantum density operator for a class comprises:parameterizing a quantum logic circuit based on the training dataset associated with the class, the quantum logic circuit comprising at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates;obtaining measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit; andbased on the measurements, determining the representative quantum density operator for the class; andstore the representative quantum density operators for use by a classifier.

2. The computing system of claim 1, wherein each training dataset comprises a plurality of training data samples, each training data sample comprises a plurality of classical features, and parameterizing the quantum logic circuit comprises parameterizing a plurality of quantum logic gates based on the plurality of classical features.

3. The computing system of claim 1, wherein each training dataset comprises a plurality of training data samples, each training data sample comprises a plurality of classical features, and parameterizing the quantum logic circuit comprises:selecting a subset of the plurality of classical features; andparameterizing a plurality of quantum logic gates based on the selected subset of the plurality of classical features.

4. The computing system of claim 1, wherein each training dataset comprises a plurality of training data samples, and determining the representative quantum densityoperator for a class comprises:determining a plurality of quantum density operators based on the plurality of training data samples; andaveraging the plurality of quantum density operators.

5. The computing system of claim 1, wherein each training dataset comprises a plurality of training data samples, each training data sample comprises classical features, and parameterizing the quantum logic circuit comprises:calculating a number of the classical features of the training data samples and a range of feature values; andstandardizing the classical features according to the range of feature values.

6. The computing system of claim 1, wherein the expectation values comprise multiple subsets of expectation values associated with distinct measurement bases for qubits in the parameterized quantum logic circuit.

7. The computing system of claim 1, wherein the one or more classical processors are configured to update the representative quantum density operators, and updating a representative quantum density operator associated with a class comprises:obtaining a new training data sample associated with the class; processing the new training data sample to determine a new quantum density operator associated with the new training data sample;updating the representative quantum density operator associated with the class based on the new quantum density operator; andstoring the updated representative quantum density operator for use by the classifier.

8. The computing system of claim 1, wherein the one or more classical processors are configured to update the representative quantum density operators, and updating the representative quantum density operators comprises:obtaining a new training dataset associated with a new class;processing the new training dataset to determine a new representative quantum density operator for the new class; andstoring the new representative quantum density operator for use by the classifier.

9. The computing system of any one of claims 1 through 8, wherein each representative quantum density operator comprises one of:a density matrix; ora reduced form of a density matrix.

10. The computing system of any one of claims 1 through 8, wherein the single-qubit quantum logic gates comprise single-qubit rotation gates, and parameterizing the quantum logic circuit comprises determining rotation angles for one or more of the single-qubit rotation gates.

11. The computing system of any one of claims 1 through 8, wherein storing the representative quantum density operators for use by the classifier comprises storing the representative quantum density operators in a database that associates the representative quantum density operators with respective identifiers of the classes.

12. A computing method comprising, by operation of a one or more classical processors:obtaining a plurality of training datasets associated with respective classes; processing the plurality of training datasets to determine representative quantum density operators for the respective classes, wherein determining a representative quantum density operator for a class comprises:parameterizing a quantum logic circuit based on the training dataset associated with the class, the quantum logic circuit comprising at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates;obtaining measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on a quantum processing unit; andbased on the measurements, determining a representative quantum density operator associated with the training dataset; andstoring the representative quantum density operators for use by the classifier.

13. The method of claim 12, wherein each training dataset comprises a plurality of training data samples, each training data sample comprises a plurality of classical features, and parameterizing the quantum logic circuit comprises parameterizing a plurality of quantum logic gates based on the plurality of classical features.

14. The method of claim 12, wherein each training dataset comprises a plurality of training data samples, each training data sample comprises a plurality of classical features, and parameterizing the quantum logic circuit comprises:selecting a subset of the plurality of classical features; andparameterizing a plurality of quantum logic gates based on the selected subset of the plurality of classical features.

15. The method of claim 12, wherein each training dataset comprises a plurality of training data samples, and determining the representative quantum density operator for a class comprises:determining a plurality of quantum density operators based on the plurality of training data samples; andaveraging the plurality of quantum density operators.

16. The method of claim 12, wherein each training dataset comprises a plurality of training data samples, each training data sample comprises classical features, and parameterizing the quantum logic circuit comprises:calculating a number of the classical features of the training data samples and a range of feature values; andstandardizing the classical features according to the range of feature values.

17. The method of claim 12, wherein the expectation values comprise multiple subsets of expectation values associated with distinct measurement bases for qubits in the parameterized quantum logic circuit18. The method of claim 12, wherein the one or more classical processors are configured to update the representative quantum density operators, and updating a representative quantum density operator associated with a class comprises:obtaining a new training data sample associated with the class;processing the new training data sample to determine a new quantum density operator associated with the new training data sample;updating the representative quantum density operator associated with the class based on the new quantum density operator; andstoring the updated representative quantum density operator for use by the classifier.

19. The method of claim 12, wherein the one or more classical processors are configured to update the representative quantum density operators, and updating the representative quantum density operators comprises:obtaining a new training dataset associated with a new class;processing the new training dataset to determine a new representative quantumdensity operator for the new class; andstoring the new representative quantum density operator for use by the classifier.

20. The method of any one of claims 12- 19, wherein each representative quantum density operator comprises one of:a density matrix; ora reduced form of a density matrix.

21. The method of any one of claims 12- 19, wherein the single-qubit quantum logic gates comprise single-qubit rotation gates, and parameterizing the quantum logic circuit comprises determining rotation angles for one or more of the single-qubit rotation gates.

22. The method of any one of claims 12- 19, wherein storing the representative quantum density operators for use by the classifier comprises storing the representative quantum density operators in a database that associates the representative quantum density operators with respective identifiers of the classes.

23. A computing system comprising:a quantum processing unit; andone or more classical processors comprising a classifier configured to:obtain a test data sample;obtain a plurality of representative quantum density operators associated with respective classes;process the test data sample to determine a test quantum density operator for the test data sample, wherein determining the test quantum density operator for the test data sample comprises:parameterizing a quantum logic circuit based on the test data sample, the quantum logic circuit comprising at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates;obtaining measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit; andbased on the measurements, determining the test quantum density operator associated with the test data sample;determine a classification of the test data sample based on an evaluationof distances between the test quantum density operator and the plurality of representative quantum density operators; andreturn the classification of the test data sample.

24. The computing system of claim 23, wherein the distance is a Frobenius distance, and evaluating the distances comprises:determining the Frobenius distance between the test quantum density operator and each representative quantum density operator using an approximate quantum state technique.

25. The computing system of claim 23, wherein determining the test quantum density operator for the test data sample comprises:obtaining multiple measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit multiple times.

26. The computing system of claim 23, wherein the one or more classical processors are further configured to train the classifier, and training the classifier comprises: obtaining a plurality of training datasets associated with the respective classes; andprocessing the plurality of training datasets to determine the plurality of representative quantum density operators for the respective classes.

27. The computing system of claim 26, wherein determining the plurality of representative quantum density operators for the respective classes comprises determining an average quantum density operator for each of the classes.

28. The computing system of claim 27, wherein the test data sample comprises a plurality of classical features, and parameterizing the quantum logic circuit comprises parameterizing a plurality of quantum logic gates based on the plurality of classical features.

29. The computing system of claim 28, wherein determining the classification of the test data sample comprises identifying a particular class of the respective classes, and returning the classification comprises returning an identifier associated with the particular class.

30. The computing system of any one of claims 23 - 29, wherein the test quantum density operator comprises one of:a density matrix; ora reduced form of a density matrix.

31. The computing system of any one of claims 23 - 29, wherein the single-qubit quantum logic gates comprise single-qubit rotation gates, and parameterizing the quantum logic circuit comprises determining rotation angles for one or more of the single-qubit rotation gates.

32. The computing system of any one of claims 23 - 29, comprising a database that associates the representative quantum density operators with respective identifiers of the classes.

33. A computing method comprising, by operation of a one or more classical processors:obtaining a test data sample;obtaining a plurality of representative quantum density operators associated with a plurality of classes;processing the test data sample to determine a test quantum density operator for the test data sample, wherein determining the test quantum density operator for the test data sample comprises:parameterizing a quantum logic circuit based on the test data sample, the quantum logic circuit comprising at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates;obtaining measurements of expectation values of quantum observables on quantum states generated by causing a quantum processing unit to execute the parameterized quantum logic circuit; andbased on the measurements, determining the test quantum density operator associated with the test data sample;determining a classification of the test data sample based on an evaluation of distances between the test quantum density operator and the plurality of representative quantum density operators; andreturning the classification of the test data sample.

34. The computing method of claim 33, wherein the distance is a Frobenius distance, and evaluating the distances comprises:determining the Frobenius distance between the test quantum density operatorand each representative quantum density operator using an approximate quantum state technique.

35. The computing method of claim 33, wherein determining the test quantum density operator for the test data sample comprises:obtaining multiple measurements of expectation values of quantum observables on quantum states generated by executing the parameterized quantum logic circuit on the quantum processing unit multiple times.

36. The computing method of claim 33, wherein the one or more classical processors are further configured to train the classifier, and training the classifier comprises: obtaining a plurality of training datasets associated with the respective classes; andprocessing the plurality of training datasets to determine the plurality of representative quantum density operators for the respective classes.

37. The computing method of claim 36, wherein determining the plurality of representative quantum density operators for the respective classes comprises determining an average quantum density operator for each of the classes.

38. The computing method of claim 37, wherein the test data sample comprises a plurality of classical features, and parameterizing the quantum logic circuit comprises parameterizing a plurality of quantum logic gates based on the plurality of classical features.

39. The computing method of claim 38, wherein determining the classification of the test data sample comprises identifying a particular class of the respective classes, and returning the classification comprises returning an identifier associated with the particular class.

40. The computing method of any one of claims 33 - 39, wherein the test quantum density operator comprises one of:a density matrix; ora reduced form of a density matrix.

41. The computing method of any one of claims 33 - 39, wherein the single-qubit quantum logic gates comprise single-qubit rotation gates, and parameterizing the quantum logic circuit comprises determining rotation angles for one or more of the single-qubit rotation gates.

42. The computing method of any one of claims 33 - 39, comprising accessing a database that associates the representative quantum density operators with respective identifiers of the classes.

Images