Aperture delay calibration circuit and method for multi-channel analog-to-digital converter

Abstract

The present invention relates to the technical field of integrated circuits. Disclosed are an aperture delay calibration circuit and method for a multi-channel analog-to-digital converter. The calibration circuit comprises: a configurable delay circuit, a sample-and-hold circuit, an analog-to-digital conversion circuit, and an aperture delay calculation circuit. When aperture delay calibration is performed on a chip, an input signal and a sampling clock signal are externally applied to each channel of the multi-channel analog-to-digital converter, and are converted into a digital code by means of the analog-to-digital conversion circuit after passing through the sample-and-hold circuit, the digital code is outputted to the aperture delay calculation circuit to calculate a delay configuration word, and the delay configuration word is inputted to the configurable delay circuit to compensate for the aperture delay. The method of the present invention converts an inter-channel aperture delay deviation measurement problem into an inter-channel analog-to-digital conversion output result deviation, and performs multi-chip simultaneous calibration without the need for additional circuits. By adding the aperture delay calculation circuit inside the chip, the aperture delay is automatically calibrated inside the chip, thereby lowering the requirements on a test device, reducing the test time and costs, and improving the test efficiency.

Description

Calibration circuit and method for aperture delay of multi-channel analog-to-digital converter Technical Field

[0001] This invention relates to the field of analog-to-digital conversion and calibration technology, and in particular to a calibration circuit and method for aperture delay of a multi-channel analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as a bridge between the physical and digital worlds, and are widely used in fields such as industrial monitoring and power transmission. ADCs are driven by an external clock to sample and convert input signals. Due to signal transmission delays, the sampled and held input signal of an ADC is typically delayed compared to the ideal input signal.

[0003] In synchronous sampling or direct I / Q demodulation applications, the aperture delays of two or more ADCs must be well matched to ensure that input signals of the same phase are sampled. Aperture delay mismatch between converters can introduce errors into rapidly rotating signals. Traditional aperture delay calibration typically uses a high-speed oscilloscope to measure the phase difference between the sampling clock and the sampled input signal to obtain the calibration result, which suffers from long testing times and high testing costs. Furthermore, traditional aperture delay calibration requires a host computer to control the chip and write calibration configuration words, making the testing process complex and cumbersome. Moreover, traditional aperture delay calibration methods cannot achieve simultaneous calibration of multiple chips. Summary of the Invention

[0004] The problem this invention aims to solve is the aperture delay mismatch between different channels in traditional multi-channel analog-to-digital converters. This invention proposes a calibration circuit and method for the aperture delay of multi-channel analog-to-digital converters, which can be used for simultaneous calibration of multiple chips and greatly improves testing efficiency.

[0005] The present invention adopts the following technical solution: a calibration circuit for aperture delay of a multi-channel analog-to-digital converter, comprising: a configurable delay circuit, a sample-and-hold circuit, an analog-to-digital conversion circuit, and an aperture delay calculation circuit;

[0006] The input signal and sampling clock signal are applied to each channel of the multi-channel analog-to-digital converter. The sampling clock signal is input to the sample-and-hold circuit after passing through a configurable delay circuit. The input signal is directly input to the sample-and-hold circuit, sampled and held by the sample-and-hold circuit, and then input to the analog-to-digital converter to be converted into a digital encoding result. The digital encoding result converted by each channel is output to the aperture delay calculation circuit to calculate the encoding deviation and delay configuration word. The aperture delay is compensated by the configurable delay circuit. The configurable delay circuit inputs the compensation result back to the sample-and-hold circuit. After multiple iterations, the aperture delay calibration of the multi-channel analog-to-digital converter is automatically completed.

[0007] Preferably, the input signal is a ramp signal or a sine wave signal, and the higher the frequency of the input signal, the higher the calibration accuracy.

[0008] Preferably, the configurable delay circuit sets up multiple levels of buffers, each level of buffer is controlled by a switch, and the sampling clock signal passes through multiple levels of buffers in sequence to generate different delay signals.

[0009] Preferably, the configurable delay circuit also includes a decoder. The aperture delay calculation circuit calculates the delay configuration word for each channel, inputs it into the corresponding decoder, and after decoding by the decoder, controls the closing of one switch of the configurable delay circuit, outputting one delay signal as a delay sampling clock to the sample-and-hold circuit.

[0010] Preferably, the aperture delay calculation circuit includes an up-and-down counter and a threshold comparator. The up-and-down counter automatically calculates the encoding deviation of the conversion results of each input channel, and the threshold comparator compares the deviation result with a preset threshold.

[0011] Preferably, the aperture delay calibration of the multi-channel analog-to-digital converter is completed when the encoding deviation is zero or less than a preset threshold.

[0012] The technical solution of the present invention also includes: a calibration method for the aperture delay of a multi-channel analog-to-digital converter, comprising the following steps:

[0013] S1. When the host computer issues a command to perform aperture delay calibration on the chip, the input signal and sampling clock signal are applied to each channel of the multi-channel analog-to-digital converter respectively. The multi-channel analog-to-digital converter performs analog-to-digital conversion on the input signal to obtain the digital encoding result of each channel.

[0014] S2. Due to the inconsistent aperture delay of the analog-to-digital converters in multiple channels, there is a deviation in the conversion results of the analog-to-digital converters in multiple channels. The digital encoding results after conversion of each channel are output to the aperture delay calculation circuit to calculate the deviation of the conversion results between each channel.

[0015] S3. The aperture delay calculation circuit determines the relationship between the aperture delays of each channel based on the deviation of the conversion results between each channel, and calculates the delay configuration word of the configurable delay circuit.

[0016] S4. The configurable delay circuit compensates for the aperture delay according to the delay configuration word, thereby reducing the aperture delay mismatch between multiple channels.

[0017] S5. Repeat steps S1 to S4. After multiple iterations, determine whether to continue aperture delay calibration. Calibration is complete when the conversion result deviation of each channel is less than the preset threshold.

[0018] Preferably, in step S1, the input signal is calculated based on the input signal range of the multi-channel analog-to-digital converter and the aperture delay mismatch time between channels, as shown in the following formula: Where f represents the input signal frequency, t represents time, and V FS V represents the peak-to-peak value of the input signal. IN (t) represents the applied input signal value.

[0019] Preferably, in step S3, the aperture delay calculation circuit calculates the encoding deviation between the digital encoding results obtained from each channel conversion, using the following method: Where Δt represents the aperture delay difference between channels, V IN (t+Δt), V IN (t) represents the sampled voltage at times t and t+Δt, respectively. D represents the rate of change of the input signal, and D represents the difference in output encoding between different channels of the analog-to-digital converter due to the aperture delay difference. IN (t+Δt)]、D[V IN [(t)] represent the output encoding of different channel analog-to-digital converters.

[0020] Preferably, in step S3, the method for calculating the delay configuration word is as follows: set the initial value of the aperture delay configuration word of each channel to zero, and during the calibration process, increment the delay configuration word of the channel with the smallest aperture delay by 1 until the difference in aperture delay between channels is less than the threshold, then the calibration ends.

[0021] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0022] 1. The present invention provides a calibration circuit and method for aperture delay of a multi-channel analog-to-digital converter, which transforms the problem of measuring aperture delay deviation between channels into deviation of analog-to-digital conversion output results between channels. It eliminates the need for high-precision testing equipment to measure the phase difference between the sampling clock and the sampling input signal, thereby reducing the requirements for testing equipment without the need for additional circuitry.

[0023] 2. This invention achieves automatic internal calibration of aperture delay by incorporating an aperture delay calculation circuit, reducing testing time and cost. Aperture delay calibration of the chip only requires an external input signal and sampling clock signal, allowing for convenient simultaneous calibration of multiple chips and significantly improving testing efficiency. Attached Figure Description

[0024] Figure 1 is a block diagram of the calibration circuit structure for the aperture delay of the multi-channel analog-to-digital converter of the present invention;

[0025] Figure 2 is a block diagram of the configurable delay circuit structure of the present invention;

[0026] Figure 3 is a flowchart of the calibration method for aperture delay of the multi-channel analog-to-digital converter of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the application will be further described in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in this invention. All non-innovative embodiments based on these embodiments by other researchers in the art are within the protection scope of this invention. Furthermore, the step numbers in the embodiments of this invention are only set for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0028] In one embodiment of the present invention, a calibration circuit for aperture delay of a multi-channel analog-to-digital converter, as shown in FIG1, includes: a configurable delay circuit, a sample-and-hold circuit, an analog-to-digital conversion circuit, and an aperture delay calculation circuit.

[0029] The input signal and the sampling clock signal are applied to each channel of the multi-channel analog-to-digital converter. The sampling clock signal is input to the sample-and-hold circuit after passing through a configurable delay circuit. The input signal is directly input to the sample-and-hold circuit, sampled and held by the sample-and-hold circuit, and then input to the analog-to-digital converter circuit, which converts it into a digital encoding result.

[0030] Due to inconsistent aperture delays, the conversion results of multiple channel analog-to-digital converters deviate. The digital encoding results after conversion of each channel are output to the aperture delay calculation circuit. The configuration word of the configurable delay circuit is obtained based on the deviation between the conversion results, and the conversion result is output to the configurable delay circuit.

[0031] The configurable delay circuit compensates for the aperture delay based on the encoding deviation and the delay configuration word, and inputs the compensation result into the sample-and-hold circuit to reduce the aperture delay mismatch between multiple channels.

[0032] After multiple iterations, when the conversion result deviation of the multi-channel converter is less than the preset threshold, the aperture delay of the multi-channel analog-to-digital converter is automatically calibrated.

[0033] Preferably, in this embodiment, a configurable delay circuit is provided, as shown in Figure 2. The configurable delay circuit is provided with multiple levels of buffers. Each level of buffer is controlled by a switch. The sampling clock signal generates different delay signals after passing through multiple levels of buffers. The aperture delay calculation circuit calculates the delay configuration word of each channel. After the delay configuration word is decoded by the decoder, it controls the closing of a switch and outputs a delay signal as a delay sampling clock to the sample-and-hold circuit.

[0034] Preferably, in this embodiment, the aperture delay calculation circuit consists of a simple up-and-down counter and a threshold comparator. The digital encoding results of each channel are input to the aperture delay calculation circuit. The up-and-down counter automatically calculates the encoding deviation of the input conversion results of each channel. The threshold comparator compares the deviation result with a preset threshold. This design does not require control from a host computer and occupies a small chip area. When the encoding deviation is zero or less than the preset threshold, the aperture delay calibration of the multi-channel analog-to-digital converter is completed.

[0035] Furthermore, this embodiment, based on the aforementioned multi-channel analog-to-digital converter aperture delay calibration circuit, achieves automatic aperture delay calibration within the chip, as shown in Figure 3, including the following steps:

[0036] S1. When the host computer issues a command to perform aperture delay calibration on the chip, the input signal and sampling clock signal are applied to each channel of the multi-channel analog-to-digital converter respectively. The multi-channel analog-to-digital converter performs analog-to-digital conversion on the input signal to obtain the digital encoding result of each channel.

[0037] S2. Due to the inconsistent aperture delay of the analog-to-digital converters in multiple channels, there is a deviation in the conversion results of the analog-to-digital converters in multiple channels. The digital encoding results after conversion of each channel are output to the aperture delay calculation circuit to calculate the deviation of the conversion results between each channel.

[0038] S3. The aperture delay calculation circuit determines the relationship between the aperture delays of each channel based on the deviation of the conversion results between each channel, and calculates the delay configuration word of the configurable delay circuit.

[0039] S4. The configurable delay circuit compensates for the aperture delay based on the delay configuration word and the sampling clock, reducing the aperture delay mismatch between multiple channels.

[0040] S5. Repeat steps S1 to S4. After multiple iterations, determine whether to continue aperture delay calibration. Calibration is complete when the conversion result deviation of each channel is less than the preset threshold.

[0041] In step S1, the input signal is calculated based on the input signal range of the multi-channel analog-to-digital converter and the aperture delay mismatch time between channels. Taking a 16-bit multi-channel analog-to-digital converter as an example, the input signal range is -10V to 10V. Assuming the aperture delay mismatch between channels is 2ns, the applied input signal is: V IN (t) = 10*sin(2πft)

[0042] It should be noted that in this embodiment, the input signal can be a ramp signal or a sine signal. Within the bandwidth of the sample and hold circuit, and provided that no dynamic setup error occurs, the higher the frequency of the input signal, the higher the calibration accuracy.

[0043] In step S2, the aperture delay mismatch between the channels of the multi-channel analog-to-digital converter causes the input signals sampled by the ADCs of different channels to be different, which in turn produces a deviation in the digital output results.

[0044] The aperture delay calculation circuit calculates the encoding deviation between the digital encoding results obtained from the conversion of each channel, as follows: D = D[V] IN (t+Δt)]-D[V IN (t)]

[0045] The digital output encoding deviation is greatest when the input signal passes through the midpoint. The maximum encoding deviation is: 3.14mV / ns * 2ns = 6.28mV = 20LSB

[0046] The aperture delay is compensated based on the output encoding deviation. When the output encoding deviation is zero or less than the threshold, the calibration is considered complete. In this embodiment, the aperture delay deviation can be calibrated to a minimum of 100ps.

[0047] In summary, this invention proposes an aperture delay calibration circuit and method for multi-channel analog-to-digital converters (ADCs). It transforms the problem of measuring aperture delay deviation between channels into measuring the deviation of the ADC output results between channels. This eliminates the need for high-precision testing equipment to measure the phase difference between the sampling clock and the sampling input signal, reducing the requirements for testing equipment without the need for additional circuitry. Furthermore, by incorporating an aperture delay calculation circuit within the chip, automatic aperture delay calibration is achieved within the chip, reducing testing time and cost. Aperture delay calibration of the chip only requires externally applied input and sampling clock signals, thus facilitating simultaneous calibration of multiple chips and significantly improving testing efficiency.

[0048] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A calibration circuit for aperture delay of a multi-channel analog-to-digital converter, characterized in that, include: Configurable delay circuit, sample and hold circuit, analog-to-digital conversion circuit, and aperture delay calculation circuit; The input signal and sampling clock signal are applied to each channel of the multi-channel analog-to-digital converter. The sampling clock signal is input to the sample-and-hold circuit after passing through a configurable delay circuit. The input signal is directly input to the sample-and-hold circuit, sampled and held by the sample-and-hold circuit, and then input to the analog-to-digital converter to be converted into a digital encoding result. The digital encoding results converted by each channel are output to the aperture delay calculation circuit to calculate the encoding deviation and delay configuration word. The aperture delay is compensated by the configurable delay circuit. The aperture delay calculation circuit includes an up-and-down counter and a threshold comparator. The up-and-down counter automatically calculates the encoding deviation of the conversion results of each input channel, and the threshold comparator compares the deviation result with a preset threshold. The configurable delay circuit inputs the compensation result into the backsample and hold circuit, and automatically completes the calibration of the aperture delay of the multi-channel analog-to-digital converter after multiple iterations.

2. The calibration circuit for the aperture delay of a multi-channel analog-to-digital converter according to claim 1, characterized in that, The input signal is a ramp signal or a sine wave signal; the higher the frequency of the input signal, the higher the calibration accuracy.

3. The calibration circuit for the aperture delay of a multi-channel analog-to-digital converter according to claim 1, characterized in that, The configurable delay circuit is equipped with multiple buffers, each of which is controlled by a switch. The sampling clock signal passes through the multiple buffers in sequence to generate different delay signals.

4. The calibration circuit for the aperture delay of a multi-channel analog-to-digital converter according to claim 3, characterized in that, The configurable delay circuit also includes a decoder. The aperture delay calculation circuit calculates the delay configuration word for each channel, inputs it into the corresponding decoder, and after decoding by the decoder, controls the closing of one switch of the configurable delay circuit, outputting one delay signal as a delay sampling clock to the sample-and-hold circuit.

5. The calibration circuit for the aperture delay of a multi-channel analog-to-digital converter according to claim 4, characterized in that, When the encoding deviation is zero or less than a preset threshold, the aperture delay calibration of the multi-channel analog-to-digital converter is completed.

6. A calibration method for the aperture delay of a multi-channel analog-to-digital converter, applied to the calibration circuit described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1. When the host computer issues a command to perform aperture delay calibration on the chip, the input signal and sampling clock signal are applied to each channel of the multi-channel analog-to-digital converter respectively. The multi-channel analog-to-digital converter performs analog-to-digital conversion on the input signal to obtain the digital encoding result of each channel. S2. Due to the inconsistent aperture delay of the analog-to-digital converters in multiple channels, there is a deviation in the conversion results of the analog-to-digital converters in multiple channels. The digital encoding results after conversion of each channel are output to the aperture delay calculation circuit to calculate the deviation of the conversion results between each channel. S3. The aperture delay calculation circuit determines the relationship between the aperture delays of each channel based on the deviation of the conversion results between each channel, and calculates the delay configuration word of the configurable delay circuit. S4. The configurable delay circuit compensates for the aperture delay according to the delay configuration word, thereby reducing the aperture delay mismatch between multiple channels. S5. Repeat steps S1 to S4. After multiple iterations, determine whether to continue aperture delay calibration. Calibration is complete when the conversion result deviation of each channel is less than the preset threshold.

7. The calibration method for aperture delay of a multi-channel analog-to-digital converter according to claim 6, characterized in that, The input signal is calculated based on the input signal range of the multi-channel analog-to-digital converter and the aperture delay mismatch time between channels, as shown in the following formula: Where f represents the input signal frequency, t represents time, and V FS V represents the peak-to-peak value of the input signal. IN (t) represents the applied input signal value.

8. The calibration method for aperture delay of a multi-channel analog-to-digital converter according to claim 7, characterized in that, The aperture delay calculation circuit calculates the encoding deviation between the digital encoding results obtained from each channel conversion, using the following method: Where Δt represents the aperture delay difference between channels, V IN (t+Δt), V IN (t) represents the sampled voltage at times t and t+Δt, respectively. D represents the rate of change of the input signal, and D represents the difference in output encoding between different channels of the analog-to-digital converter due to the aperture delay difference. IN (t+Δt)]、D[V IN [(t)] represent the output encoding of different channel analog-to-digital converters.

9. The calibration method for aperture delay of a multi-channel analog-to-digital converter according to claim 8, characterized in that, In step S3, the delay configuration word is calculated. The initial value of the aperture delay configuration word of each channel is zero. During the calibration process, the delay configuration word of the channel with the smallest aperture delay is incremented by 1 until the difference in aperture delay between channels is less than the threshold, and then the calibration ends.

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