Data access method, storage drive, and storage medium controller

Abstract

The present application relates to the technical field of storage, and discloses a data access method, a storage drive, and a storage medium controller. The method comprises: when an access instruction of a storage medium controller is switched from a first access instruction (an access object of the first access instruction being a first storage chip) to a second access instruction (an access object of the second access instruction being a second storage chip), first initializing a second interface circuit before accessing the second storage chip, and accessing the second storage chip only after the initialization is completed. Since the second interface circuit has been restored to an initial state before receiving the second access instruction, no error will occur, and data from the storage medium controller can be processed normally, so that the second access instruction can be executed normally, and the second storage chip can be accessed normally.

Description

Data access methods, storage drives, and storage media controllers

[0001] This application claims priority to Chinese Patent Application No. 202411629629.2, filed on November 13, 2024, entitled "Data Access Method, Storage Driver and Storage Medium Controller", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of storage technology, and in particular to a data access method, a storage driver, and a storage media controller. Background Technology

[0003] With the development of big data analytics, the Internet of Things (IoT), and other technologies, data has become a core element driving technological progress. Especially with the advent of 5G, the amount of data generated and the demand for data storage have increased dramatically, creating a huge demand for high-capacity solid-state drives (SSDs).

[0004] In some current SSDs, there is an SSD controller, multiple multiplexers (MUX), and multiple NAND flash memory chips. Each MUX is connected to the interface circuits of the SSD controller and two NAND flash memory chips. The MUX selects one of the two connected NAND flash memory chips to access data in response to the access command of the SSD controller. For example, it selects one of the two NAND flash memory chips to transmit the access command to the interface circuit of one of the NAND flash memory chips.

[0005] When an SSD controller executes an access command, it sends a strobe signal and input / output signals carrying the access command to the MUX. Based on the strobe signal, the MUX selects and activates the interface circuit of the NAND flash memory chip requested by the access command, enabling the transmission of the input / output signals between the SSD controller and the requested NAND flash memory chip. When executing two access commands for different NAND flash memory chips, the SSD controller controls the strobe signal to toggle. Based on the toggle of the strobe signal, the MUX switches the SSD controller's input / output signals between the interface circuits of the different NAND flash memory chips. This causes the previously executed access command to affect the execution of the subsequent access command, leading to errors in the execution of the subsequent access command and preventing its normal execution. Summary of the Invention

[0006] This application provides a data access method, a storage driver, and a storage media controller, which can prevent earlier access instructions in the storage driver from affecting the execution of subsequent access instructions. The technical solution is as follows:

[0007] Firstly, a data access method is provided. This method is applied to a storage drive, which includes a storage medium controller, a first storage chip, and a second storage chip. The storage drive can be an SSD, the storage medium controller can be an SSD controller, and the first and second storage chips can be different storage chips. Each storage chip contains interface circuitry and storage circuitry. The storage circuitry provides physical storage space for recording data. Different storage chips have different interface circuitry, and the storage chips communicate with the storage medium controller via their interface circuitry. The storage chips are, for example, flash memory chips or phase-change RAM (PCM) chips. Taking a flash memory chip as an example, the storage circuitry is, for example, a flash memory die or a flash memory package, such as a package composed of multiple dies. The interface circuits in the first and second storage chips are respectively referred to as the first interface circuit and the second interface circuit; that is, the first interface circuit is located in the first storage chip and communicates with the storage medium controller, and the second interface circuit is located in the second storage chip and communicates with the storage medium controller. The storage media controller accesses the storage chip by transmitting access commands to the interface circuitry of the storage chip. These access commands originate externally to the storage driver (e.g., the central processing unit (CPU) of the computer where the storage driver resides) or are generated by the storage driver itself. The access command requesting access to the first storage chip is called the first access command, and the access command requesting access to the second storage chip is called the second access command.

[0008] The method can be executed by a storage medium controller, and includes: the storage medium controller transmitting a first access instruction to a first interface circuit to access a first storage chip; when the access instruction of the storage medium controller to access the storage chip changes from the first access instruction to a second access instruction, the storage medium controller switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit; before accessing the second storage chip via the second access instruction, the storage medium controller initializes the second interface circuit; after initialization, the storage medium controller transmits a second access instruction to the second interface circuit to access the second storage chip.

[0009] When the storage medium controller switches from accessing the first storage chip to accessing the second storage chip, direct access to the second storage chip may result in errors (e.g., the second storage chip not responding). One reason for this error is that the interface circuit switching transmits the first access command remaining on the communication channel between the storage controller and the first interface circuit to the second interface circuit, causing a change in the state of the second interface circuit (uninitialized state). The existence of this state triggers an error in the second storage chip when accessing it.

[0010] Based on the method provided in the first aspect, when the access instruction of the storage medium controller switches from a first access instruction (the access object of the first access instruction is the first storage chip) to a second access instruction (the access object of the second access instruction is the second storage chip), the second interface circuit is initialized before accessing the second storage chip. Access to the second storage chip only occurs after initialization is complete. Since the second interface circuit has been restored to its initialized state before receiving the second access instruction, it will not malfunction and can normally process data from the storage medium controller, enabling the second access instruction to be executed normally and the second storage chip to be accessed normally.

[0011] In one possible implementation, the memory driver further includes a selection circuit; the memory media controller sends a chip strobe signal to the selection circuit to switch the interface circuit for accessing the memory chip from a first interface circuit to a second interface circuit. The memory media controller, through the selection circuit, sends an initialization signal to the second interface circuit to initialize it. Specifically, the chip strobe signal triggers the selection circuit to switch the interface circuit for accessing the memory chip from the first interface circuit to the second interface circuit, and the initialization signal indicates that the interface circuit should be initialized.

[0012] Based on the above possible implementation methods, the selection circuit can switch the interface circuit for the storage medium controller to access the storage chip between different storage chips in the storage driver, so that the storage medium controller accesses one storage chip at a time, thereby achieving load isolation.

[0013] In one possible implementation, the timing of sending the chip strobe signal and the initialization signal can be determined based on the transmission delay of the chip strobe signal and the initialization signal in the selection circuit. For example, the method further includes: if the transmission delay of the chip strobe signal in the selection circuit is greater than the transmission delay of the initialization signal in the selection circuit, the storage medium controller sends the chip strobe signal to the selection circuit, and after a first duration, sends the initialization signal to the selection circuit; or, if the transmission delay of the chip strobe signal in the selection circuit is less than the transmission delay of the initialization signal in the selection circuit, the storage medium controller sends the initialization signal to the selection circuit, and after a first duration, sends the chip strobe signal to the selection circuit. Wherein, the first duration is the difference between the transmission delays of the chip strobe signal and the initialization signal in the selection circuit.

[0014] When the selection circuit sends a strobe signal to the second interface circuit based on the chip strobe signal, based on the above possible implementation methods, the initialization signal and the strobe signal generated by the selection circuit based on the chip strobe signal reach the second memory chip at the same time, so as to avoid problems such as signal sampling misalignment and data access errors on the second memory chip side.

[0015] In one possible implementation, the initialization of the second interface circuit includes any one of the following: performing a reset operation on the second interface circuit to set the second interface circuit to an initialized state; or performing a pseudo-read / write operation on the second memory chip to restore the second interface circuit to an initialized state; or performing a read operation on the second memory chip to restore the second interface circuit to an initialized state.

[0016] Based on the above possible implementation methods, multiple optional implementation methods are provided for the initialization of the interface circuit to adapt to different application scenarios.

[0017] In one possible implementation, the memory driver further includes a selection circuit. The second access instruction is carried by an access signal. Based on this, the memory medium controller sends a chip strobe signal and an access signal to the selection circuit, so as to trigger the selection circuit to transmit the access signal to the second interface circuit through the chip strobe signal, thereby realizing the transmission of the second access instruction to the second interface circuit.

[0018] In one possible implementation, the storage medium controller sends a chip strobe signal and an access signal to the selection circuit by: if the transmission delay of the chip strobe signal in the selection circuit is greater than the transmission delay of the access signal in the selection circuit, first sending the chip strobe signal to the selection circuit, and then sending the access signal to the selection circuit after a second time interval; or, if the transmission delay of the chip strobe signal in the selection circuit is less than the transmission delay of the access signal in the selection circuit, first sending the access signal to the selection circuit, and then sending the chip strobe signal to the selection circuit after a second time interval. The second time interval is the difference between the transmission delays of the chip strobe signal and the access signal in the selection circuit.

[0019] When the selection circuit sends a gating signal to the second interface circuit based on the chip gating signal, based on the above possible implementation methods, the access signal and the gating signal generated by the selection circuit based on the chip gating signal reach the second memory chip at the same time, so as to avoid problems such as signal sampling misalignment and data access error on the second memory chip side.

[0020] In one possible implementation, after the storage medium controller transmits the second access instruction to the second interface circuit, the method further includes: when the access instruction for the storage medium controller to access the storage chip changes from the second access instruction to the first access instruction, the storage medium controller switches the interface circuit for accessing the storage chip from the second interface circuit to the first interface circuit; before accessing the first storage chip, the storage medium controller initializes the first interface circuit; after initialization, the storage medium controller transmits the first access instruction to the first interface circuit to access the first storage chip.

[0021] When the storage medium controller switches back from accessing the second storage chip to accessing the first storage chip, direct access to the first storage chip may result in errors (such as the first storage chip not responding). One reason for this error is that the storage medium controller's previous access to the first storage chip caused a change in the interface circuit state (a non-initialized state). The existence of this state causes the first storage chip to malfunction upon subsequent access.

[0022] Based on the above possible implementations, when the access instruction of the storage medium controller switches from the second access instruction back to the first access instruction, the first interface circuit is initialized before accessing the first storage chip. Access to the first storage chip only occurs after initialization is complete. Since the first interface circuit has been restored to its initialized state before receiving the first access instruction, it will not malfunction and can process data from the storage controller normally, enabling the first access instruction to be executed correctly and the first storage chip to be accessed normally.

[0023] Secondly, a storage driver is provided, the storage driver comprising:

[0024] The first memory chip includes a first interface circuit, a first control circuit, and a storage circuit for recording data.

[0025] The second memory chip includes a second interface circuit, a second control circuit, and a storage circuit for recording data.

[0026] A storage medium controller is used to transmit a first access command to a first interface circuit to access the first storage chip;

[0027] The storage medium controller is also used to switch the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit when the access instruction for the storage medium controller to access the storage chip is switched from the first access instruction to the second access instruction.

[0028] The storage medium controller is also used to transmit an initialization signal to the second interface circuit before accessing the second storage chip. The initialization signal indicates that the interface circuit in the storage chip should be initialized.

[0029] The second control circuit is used to initialize the second interface circuit based on the initialization signal;

[0030] The storage medium controller is also used to transmit a second access command to the second interface circuit after initialization is complete, so as to access the second storage chip.

[0031] In one possible implementation, the control chip is also used to implement the method steps performed by the storage medium controller in any of the alternative methods provided in the first aspect above.

[0032] Thirdly, a storage medium controller is provided for performing the method provided in the first aspect or any alternative manner of the first aspect.

[0033] Fourthly, a storage medium controller is provided, which includes a control chip and a selection circuit connected to the control chip. The selection circuit provides connection between the control chip and a first interface circuit in a first storage chip and a second interface circuit in a second storage chip. The first and second storage chips also include storage circuits for recording data.

[0034] The control chip is used to send the first access command to the selection circuit;

[0035] The selection circuit is used to transmit a first access command to the first interface circuit to access the first memory chip;

[0036] The control chip is also used to send a chip strobe signal to the selection circuit when the access instruction of the storage medium controller to access the storage chip is switched from the first access instruction to the second access instruction. The chip strobe signal indicates that the second storage chip is selected from the multiple connected storage chips to be turned on.

[0037] The selection circuit is also used to switch the interface circuit for the storage medium controller to access the storage chip from the first interface circuit to the second interface circuit based on the chip selection signal.

[0038] The control chip is also used to initialize the second interface circuit through a selection circuit before accessing the second memory chip, and after initialization, to transmit a second access command to the second interface circuit to access the second memory chip.

[0039] In one possible implementation, the control chip is also used to implement the method steps performed by the storage medium controller in any of the alternative methods provided in the first aspect above.

[0040] Fifthly, a storage medium controller is provided, the storage medium controller including a control chip for performing the method provided as described in the first aspect or any alternative to the first aspect.

[0041] A sixth aspect provides a computer-readable storage medium storing at least one piece of program code, which is read by a control chip in a storage medium controller to cause the storage medium controller to perform the method provided in the first aspect or any alternative method of the first aspect.

[0042] In a seventh aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a control chip in a storage medium controller reading the program code from the computer-readable storage medium, the control chip executing the program code, causing the storage medium controller to perform the method provided in the first aspect or any alternative method of the first aspect. Attached Figure Description

[0043] Figure 1 is a schematic diagram of a storage driver provided in an embodiment of this application;

[0044] Figure 2 is a schematic diagram of another storage driver provided in an embodiment of this application;

[0045] Figure 3 is a schematic diagram of the connection relationship on a single channel in a storage driver provided in an embodiment of this application;

[0046] Figure 4 is a switching control logic diagram of a selection circuit provided in an embodiment of this application;

[0047] Figure 5 is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0048] Figure 6 is a flowchart of a data access process on a single channel provided in an embodiment of this application;

[0049] Figure 7 is a flowchart of a data access method provided in an embodiment of this application;

[0050] Figure 8 is a flowchart of another data access method provided in an embodiment of this application;

[0051] Figure 9 is a flowchart of another data access method provided in an embodiment of this application;

[0052] Figure 10 is a schematic diagram of the switching of a memory chip in a fault scenario provided by an embodiment of this application;

[0053] Figure 11 is a schematic diagram of the structure of a storage medium controller provided in an embodiment of this application. Detailed Implementation

[0054] In traditional solid-state drives (SSDs), the SSD controller communicates with multiple NAND flash memory chips via multiple ONFI channels. Each open NAND flash interface (ONFI) channel connects to one NAND flash memory chip, and each NAND flash memory chip includes multiple NAND flash dies. Due to the limitation of the data transfer rate of a single channel, the number of NAND flash dies in a NAND flash memory chip connected to an ONFI channel cannot be increased indefinitely. Therefore, when expanding the storage capacity of an SSD using a traditional SSD controller, it is usually necessary to passively wait for the storage capacity of a single die to increase, making it difficult to increase the storage capacity of the SSD. Therefore, there is an urgent need for a storage device that can expand storage capacity while ensuring the data transfer rate of a single channel.

[0055] Based on this, this application provides a storage driver for storing data. The storage driver can be any type of storage device that enables the storage media controller to communicate with the storage chip (such as a NAND flash memory chip) through a communication channel, such as an SSD or other types of storage device.

[0056] Figure 1 is a schematic diagram of a storage driver provided in an embodiment of this application. As shown in Figure 1, the storage driver 100 includes a storage medium controller 11, N selection circuits 12, and N*M storage chips 13. Each selection circuit 12 is connected to the storage medium controller 11 and the M storage chips 13, respectively. Different selection circuits 12 are connected to different storage chips 13, and N and M are both integers greater than or equal to 1.

[0057] Each memory chip 13 is used to store data. The structure of each memory chip 13 is similar. The structure of the memory chip will be introduced below with reference to Figure 2, taking one memory chip 13 as an example.

[0058] As shown in Figure 2, the memory chip 13 includes multiple memory circuits 131. Each memory circuit 131 provides physical storage space for recording data. For example, the memory circuit 131 includes NAND cells, and each cell can record one or more bits of data. The memory chip 13 can be a NAND flash memory chip, and the memory circuits 131 can be NAND flash memory dies. As shown in Figure 3, each memory chip 13 includes 32 NAND flash memory dies, but the number of NAND flash memory dies is not limited to 32. Here, the embodiments of this application do not limit the number of memory circuits 131 in the memory chip 13.

[0059] The memory chip 13 also includes an interface circuit 132 and a control circuit 133. The interface circuit 132 is, for example, a NAND flash interface (NFI), and the protocol used by the interface circuit 132 is, for example, the ONFI standard protocol. The interface circuit 132 serves as the external communication interface for the memory chip 13, providing a connection between the storage media controller 11 and the memory chip 13 for communication. For example, the interface circuit 132 is connected to the storage media controller 11 through a selection circuit 12, and communicates with the storage media controller 11 through the selection circuit 12. The connection method between the interface circuit 132 and the selection circuit 12 will be described below and will not be repeated here.

[0060] The control circuit 133 is connected to the interface circuit 132 and multiple storage circuits 131 within the memory chip 13. For example, the control circuit 133 connects to T*P storage circuits 131 through T media channels, with P storage circuits 131 connected to each media channel. That is, every P storage circuits 131 are located in one media channel, where T is an integer greater than 1 and P is an integer greater than or equal to 1. As shown in Figure 3, in the memory chip 13, P is 4 and T is 8, meaning one memory chip 13 includes 32 NAND flash memory chips and 4 media channels, with 8 NAND flash memory chips located in one media channel.

[0061] The control circuit 133 is used to obtain instructions from the storage medium controller 11 from the interface circuit 132, and manage the connected storage circuit 131 according to the instructions from the storage medium controller 11. The control circuit 133 can be a programmable electronic component, such as a central processing unit (CPU), data processing unit (DPU), graphics processing unit (GPU), or embedded neural network processing unit (NPU). Here, the type of control circuit 133 is not limited in this embodiment.

[0062] The storage medium controller 11 manages the various storage chips 13 in the storage drive 100. The storage medium controller 11 can be a programmable electronic component, such as a processing chip like a CPU, DPU, GPU, or NPU. In this embodiment, the type of storage medium controller 11 is not limited.

[0063] As shown in Figure 3, the storage media controller 11 can also communicate with a host other than the storage drive 100, for example, via an M.2 interface or a Serial Advanced Technology Attachment (SATA) interface. The M.2 interface is also known as the Next Generation Form Factor (NGFF) interface. The communication protocol between the storage media controller 11 and the host may include bus protocols such as Peripheral Component Interconnect Express (PCIE), Serial Attached Internet Small Computer System Interface (SAS), or Serial Advanced Technology Attachment (SATA). The host can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, server, or any other suitable electronic device capable of connecting to the storage drive 100.

[0064] N represents the number of selection circuits 12 and the number of communication channels in the storage driver 100. A communication channel refers to the signal transmission link between the storage medium controller 11 and the storage chip 13. Taking the storage circuit 131 as a NAND flash memory chip as an example, the communication channel can be an ONFI channel. N can be 16 or other values. In the storage driver 100, different selection circuits 12 correspond to different communication channels. The storage chip 13 connected to each selection circuit 12 is the storage chip 13 on the corresponding communication channel. Thus, through N selection circuits 12, N*M storage chips 13 in the storage driver 100 can be divided into N communication channels. M is the number of storage chips 13 on the same communication channel. M can be 2 or greater than 2. Here, the values ​​of N and M are not limited in this embodiment.

[0065] The storage medium controller 11 accesses the storage chip 13 by transmitting access commands to the interface circuit 132 in the storage chip 13. The access command from the storage medium controller 11 can be an access request sent by the host, or any one of multiple access commands generated based on the host's access request. These multiple access commands are used to complete the access request. The access command includes a target storage address and indicates that access should be performed on the target storage address. The access method can be writing data or reading data. When the access method is writing data, the access command is a write command; when the access method is reading data, the access command is a read command. When the storage medium controller 11 accesses the storage chip 13, it can read and write data in the storage circuit 131 through the interface circuit 132.

[0066] The storage medium controller 11 is used to transmit an access command to the target interface circuit via the target selection circuit in response to any access command, so as to access the target storage chip. The access command requests access to a specific storage chip 13, the target storage chip is the storage chip 13 requested by the access command, the target interface circuit is the interface circuit 132 of the target storage chip, and the target interface circuit is the interface circuit for the storage medium controller 11 to access the storage chip in response to the access command. The target selection circuit is the selection circuit 12 connected to the target storage chip.

[0067] For example, the storage medium controller 11 is used to send a chip strobe signal and an access signal to the target selection circuit in response to the access command. The chip strobe signal indicates the selection of a target storage chip from the connected M storage chips 13. The chip strobe signal is a strobe signal, which can be a chip select (SE) signal or a chip enable (CE) signal. The access signal carries the access command and can be a data (DQ) signal carrying the access command.

[0068] The target selection circuit receives chip strobe signals and access signals. Based on the chip strobe signals, it sets the target interface circuit of the target memory chip among the M connected memory chips 13 as the interface circuit for the storage medium controller 11 to access the memory chip, and transmits access signals to the target interface circuit to access the target memory chip. Therefore, the chip strobe signals trigger the target selection circuit to transmit access signals to the target interface circuit.

[0069] The control circuit 133 in the target memory chip is used to obtain an access signal from the target interface circuit and access the storage circuit 131 in the target memory chip based on the access signal to complete the access to the target memory chip.

[0070] In a traditional SSD, one ONFI channel corresponds to one NAND flash memory chip (i.e., one storage chip 13). However, when the storage driver 100 is an SSD, the storage chip 13 is a NAND flash memory chip, and the communication channel is an ONFI channel, the selection circuit 12 allows one ONFI channel to correspond to more NAND flash memory chips (e.g., M chips). Therefore, compared to a traditional SSD, the storage driver 100 provided in this application increases the number of NAND flash memory chips on a single ONFI channel, thereby increasing the storage capacity of a single ONFI channel. Specifically, it can increase the storage capacity of a single ONFI channel by M times, thereby increasing the overall storage capacity of the SSD and achieving capacity expansion. Furthermore, when accessing a NAND flash memory chip, the storage medium controller 11 sends a chip strobe signal to the corresponding selection circuit 12 to indicate the NAND flash memory chip to be accessed. The selection circuit 12 then selects the NAND flash memory chip from its connected NAND flash memory chips based on the chip strobe signal for data access. Therefore, the storage medium controller 11 actually accesses a portion of the NAND flash memory chips on a single channel, reducing the actual load on a single channel and ensuring the data transfer rate of a single channel. Thus, the storage driver 100 can meet expansion requirements while ensuring the data transfer rate of a single channel.

[0071] In the storage driver 100, each selection circuit 12 is connected to the storage medium controller 11 and the corresponding M storage chips 13 in a similar manner. Next, taking any selection circuit 12 as an example, the connection between this selection circuit 12 and the storage medium controller 11 and the corresponding M storage chips 13 will be described in (1) and (2) below.

[0072] (1) The selection circuit 12 is connected to the storage medium controller 11 via the first bus 14.

[0073] For example, the storage drive 100 also includes N channel interface circuits 15, which provide connections between the storage medium controller 11 and communication channels. Each channel interface circuit 15 corresponds to one communication channel, and different channel interface circuits 15 correspond to different communication channels. The storage medium controller 11 is connected to the N channel interface circuits 15, and each channel interface circuit 15 is connected to a selection circuit 12 via a first bus 14, thereby setting the selection circuit 12 on the corresponding communication channel.

[0074] Taking the storage driver 100 shown in Figure 3 as an example, assuming the storage chip 13 is a NAND flash memory chip, the communication channel in Figure 3 is called a NAND channel (CH). Assuming N is 16, there are 16 NAND channels, namely CH0 to CH15, each corresponding to a channel interface circuit 15. For simplicity, in Figure 3, the channel interface circuits 15 corresponding to CH1 to CH15 are simplified to one interface circuit 151 as an example. The selection circuits 12 on CH1 to CH15 are not shown. CH1 to CH15 are represented by a single line, and CH[i:i+1] is used to represent CHi, where i is an integer greater than or equal to 0 and less than or equal to N-1. In Figure 3, taking CH0 as an example, the connection relationship between the storage medium controller 11, the selection circuit 12, and the storage chip 13 on CH0 is shown in detail. For example, the storage medium controller 11 is connected to the channel interface circuit 15 corresponding to CH0. The channel interface circuit 15 is connected to a selection circuit 12 through a first bus 14. The selection circuit 12 is connected to M storage chips through M second buses 16, so that the channel interface circuit 15, the first bus 14, the selection circuit 12 and the M second buses 16 form CH0.

[0075] The first bus 14 is a bus between the storage medium controller 11 and the selection circuit 12, used to transmit signals between the storage medium controller 11 and the selection circuit 12. The first bus 14 includes a first strobe bus 141, which is the strobe bus within the first bus 14 used to transmit the strobe signal (referred to as the first strobe signal) of the storage medium controller 11. There are multiple first strobe signals, which can be either CE or SE signals. Taking the connection relationship on CH0 in Figure 3 and the connection relationship on a single channel in the storage driver 100 shown in Figure 4 as examples, the first strobe bus 141 includes multiple first strobe signal lines, each used to transmit one first strobe signal from the storage medium controller 11. Taking the CE signal as an example, the first strobe bus 141 includes four first strobe signal lines, used to transmit CE0, CE1, CE2, and CE3 signals respectively, but the number of first strobe signal lines and the number of first strobe signals are not limited to four.

[0076] Multiple first strobe signals include chip strobe signals, medium strobe signals, and enable signals. The first strobe signal line that transmits the chip strobe signal is called the chip strobe signal line, the first strobe signal line that transmits the medium strobe signal is called the chip strobe signal line, and the first strobe signal line that transmits the enable signal is called the group enable signal line.

[0077] The chip strobe signal indicates the selection of one memory chip 13 from the M connected memory chips 13 for activation. The selected memory chip 13 is the target memory chip. The number of chip strobe signals can be the square root of M, and each chip strobe signal is transmitted through a chip strobe signal line. For example, if M is 2, the number of chip strobe signals is 1. Different values ​​of the chip strobe signal indicate the selection of different memory chips 13. When the number of M is greater than 2, there are multiple chip strobe signals, each with a value of 0 or 1. There are multiple combinations of values ​​for these multiple chip strobe signals, and each combination indicates the selection of one memory chip 13 from the M connected memory chips 13. Different combinations of values ​​indicate the selection of a different memory chip 13. Taking Figures 3 and 4 as examples, assume that the selection circuit connects two memory chips, namely memory chip 0 and memory chip 1, as shown in Figure 5. Assume that multiple first selection signals include signals CE0 to CE3, where signal CE2 is the chip selection signal, as shown in box 51. When signal CE2 is 0, it indicates that memory chip 0 is selected to be turned on from the two connected memory chips 13. When signal CE2 is 1, it indicates that memory chip 1 is selected to be turned on from the two connected memory chips 13.

[0078] There are multiple media strobe signals, each transmitted through a media strobe signal line. These multiple media strobe signals indicate the selection of one media channel (i.e., the target media channel) from among the M connected memory chips. Each first strobe signal has a value of 0 or 1, and there are multiple combinations of values ​​for the multiple media strobe signals. Each value combination corresponds to one memory chip 13 and one media channel within that memory chip 13, indicating the selection of the corresponding media channel within that memory chip 13. Taking memory chips 0 and 1 connected in the circuit selection circuit in Figures 3 and 4 as an example, as shown in Figure 5, assume that the multiple first strobe signals include signals CE0 to CE3, where signals CE0 to CE2 are all media strobe signals, and both memory chips 0 and 1 include media channels 0 to 3. In box 52, the four possible combinations of values ​​for signals CE0 to CE2 respectively indicate a medium channel in memory chip 0 indicated by signal CE2. For example, the combination of values ​​{0,0,0} indicates that medium channel 0 in memory chip 0 is selected to be turned on, the combination of values ​​{0,0,1} indicates that medium channel 1 in memory chip 0 is selected to be turned on, and so on. In box 53, the four possible combinations of values ​​for signals CE0 to CE2 respectively indicate a medium channel in memory chip 1 indicated by signal CE2. For example, the combination of values ​​{1,0,0} indicates that medium channel 0 in memory chip 1, the combination of values ​​{1,0,1} indicates that medium channel 1 in memory chip 1, and so on.

[0079] The enable signal is used to enable the selection circuit 12. Taking Figure 5 as an example, assume that the multiple first strobe signals include signals CE0 to CE3. Signal CE3 is the enable signal. When signal CE3 is 0, it means that selection circuit 12 is enabled. When signal CE3 is 1 (not shown in Figure 5), it means that selection circuit 12 is not enabled.

[0080] Traditional SSDs transmit multiple strobe signals, including CE0 to CE3, through their ONFI channels. In traditional SSDs, CE0 to CE3 are used to indicate the selection of one media channel from multiple media channels within a NAND flash memory chip. In this embodiment, CE0 to CE3 are used as the first strobe signal, and their definitions are redefined. For example, CE0 to CE2 are used as media strobe signals, indicating the selected memory chip and media channel. CE2 is also multiplexed as a chip strobe signal, indicating the selected memory chip. CE3 is used as the enable signal for selection circuit 12. This eliminates the need to add pins to the channel interface circuit (such as channel interface circuit 15) of the traditional SSD's ONFI channel to transmit the chip strobe signal and enable signal.

[0081] In other embodiments, the CE0 to CE3 signals in the ONFI channel of a conventional SSD are used as media strobe signals. The channel interface circuit of the ONFI channel in a conventional SSD transmits chip strobe signals and enable signals to the selection circuit through additional pins.

[0082] As shown in Figures 3 and 4, the first bus 14 also includes a first input / output bus 142. The first input / output bus 142 is the input / output bus within the first bus 14, used to transmit input / output signals. Input / output signals are bidirectional signals used for data access. These signals carry instructions from the storage medium controller 11 and / or the host, such as access instructions, reset instructions, pseudo-read / write instructions, or other types of instructions. For example, the input / output signals include a DQ signal, which carries instructions. During a read operation, the DQ signal also carries data read from the storage chip 13. The input / output signals also include auxiliary control signals, which assist the control circuit 133 in the storage chip 13 in parsing instructions from the DQ signal. These auxiliary control signals include a data strobe (DQS) signal, read enable (RE), write enable (WE), and other signals. For example, as shown in Figure 3, the input / output signals are 12-bit non-volatile (NV) double data rate (DDR) signals. In this application, the embodiments do not limit the input and output signals.

[0083] (2) The selection circuit 12 is connected to the interface circuit 132 of the M memory chips 13 via the M second buses 16.

[0084] Different second buses 16 are connected to the interface circuits 132 of different memory chips 13. The second bus 16 is a bus between the selection circuit 12 and the interface circuit 132 of the memory chip 13, used to transmit signals between the memory chip 13 and the interface circuit 132 of the memory chip 13.

[0085] As shown in Figures 2 and 4, the second bus 16 includes a second strobe bus 161, which is the strobe bus in the second bus 16 used to transmit strobe signals (referred to as second strobe signals) of the selection circuit. There are multiple second strobe signals, each corresponding to a medium channel in the memory chip 13. Different second strobe signals correspond to different medium channels, and each second strobe signal indicates whether the corresponding medium channel is turned on. For example, a second strobe signal of 1 indicates that the corresponding medium channel is turned on, and a second strobe signal of 0 indicates that the corresponding medium channel is not turned on. For ease of description, in this embodiment, if any second strobe signal indicates that the corresponding medium channel is turned on, then the second strobe signal is called a valid strobe signal; if the second strobe signal indicates that the corresponding medium channel is not turned on, then the second strobe signal is called an invalid strobe signal.

[0086] The second strobe bus 161 includes T second strobe signal lines. Each second strobe signal line is used to transmit a second strobe signal. Each second strobe signal line corresponds to one of the T media channels of the memory chip 13. Different second strobe signal lines correspond to different media channels, so that the second strobe signal transmitted in each second strobe signal line corresponds to a media channel.

[0087] Taking the CE signal as the second strobe signal as an example, as shown in Figures 3 and 4, assuming M is 2, the selection circuit 12 connects to two memory chips 13, namely memory chip 0 and memory chip 1. The second strobe bus 161 connected to memory chip 0 includes four second strobe signal lines, used to transmit four second strobe signals: CE0', CE1', CE2', and CE3'. These four second strobe signals correspond to one medium channel in memory chip 0. The second strobe bus 161 connected to memory chip 1 also includes four second strobe signal lines, used to transmit four second strobe signals: CE4', CE5', CE6', and CE7'. These four second strobe signals correspond to one medium channel in memory chip 1. Each medium channel in memory chip 0 and memory chip 1 has eight NAND flash dies; therefore, each CE signal from CE0' to CE7' corresponds to eight NAND flash dies.

[0088] The second bus 16 also includes a second input / output bus 162, which is the input / output bus within the second bus 16. It is used to transmit input / output signals of the storage medium controller 11 between the selection circuit 12 and the storage chip 13. The second input / output bus 162 has the same structure as the first input / output bus 142. As shown in Figure 4, the second input / output bus 162 and the first input / output bus 142 transmit the same input / output signals. The input / output signals transmitted in the second input / output bus 162 will not be described in detail here.

[0089] To distinguish the input / output signals transmitted by different second input / output buses 162 in different second buses 16, on CH0 shown in Figure 3, DDR_0 represents the input / output signal transmitted by the second input / output bus 162 in one second bus 16, and DDR_1 represents the input / output signal transmitted by the second input / output bus 162 in another second bus 16. However, it should be understood that the first input / output bus 142 and the second input / output bus 162 connected by the same selection circuit 12 transmit the same input / output signal.

[0090] Taking the selection circuit 12 as an example of a target selection circuit, the storage medium controller 11 sends input / output signals to the target selection circuit via the first input / output bus 142 and sends multiple first gating signals to the target selection circuit via the first gating bus in response to an access command. The target selection interface circuit receives the input / output signals and the multiple first gating signals. Based on the chip gating signal among the multiple first gating signals, the target selection circuit sends input / output signals to the target interface circuit and sends a valid gating signal corresponding to the target medium channel to the target circuit based on the multiple medium gating signals among the multiple first gating signals.

[0091] The structure and control logic of each selection circuit 12 in the storage driver 100 are similar. Next, taking a selection circuit 12 as an example, the structure and control logic of the selection circuit 12 will be introduced in conjunction with the following (3).

[0092] (3) Select circuit 12

[0093] As shown in Figures 3 and 4, the selection circuit 12 includes a chip selector 121. The chip selector 121 is connected to the storage medium controller 11 and M storage chips. For example, the chip selector 121 is connected to the control component 11 via a first input / output bus 142 and a chip selection signal line in the first selection signal bus 141, and is connected to the interface circuits 132 of the M storage chips 13 via M second input / output buses 162. Different second input / output buses 162 are connected to the interface circuits 132 of different storage chips 13. As shown in Figures 3 and 4, the chip selector 121 connects to two storage chips 13 via two second input / output buses 162.

[0094] Chip selector 121 can be a data selector (multiplexer, MUX). The MUX can be an f:g MUX, where f is the number of select (SEL) input interfaces of the MUX, the chip strobe signal is the select input signal of the MUX, each select input interface is connected to a chip strobe signal line to receive a chip strobe signal from the connected component signal line, and g is the number of output interfaces of the MUX. Each output interface is connected to the interface circuit 132 of a memory chip 13 through a second input / output bus 162. In this embodiment, f equals the number of chip strobe signals of the storage medium controller 11, and g equals the number M of memory chips 13 connected to the selection circuit 12. In Figures 3 and 4, chip selector 121 is a 1:2 MUX.

[0095] The selection circuit 12 also includes a media selector 122, which is connected to the storage media controller 11 and the M storage chips. For example, the media selector 122 is connected to the storage media controller 11 via a first gating bus 141, and to the interface circuits 132 of the M storage chips 13 via M second gating buses 161. Different second gating buses 161 are connected to the interface circuits 132 of different storage chips 13. The second input / output bus 162 and the second gating bus 161 connected to the same storage chip 13 belong to the same second bus 16. The first gating bus 141 connected to the selection circuit 12 and the first input / output bus 142 connected to the chip selector 121 belong to the same first bus 14.

[0096] Taking the selection circuit 12 as an example, based on the connection method between the chip selector 121, the media selector 122, the control component 11, and the M memory chips 13, the functions of the chip selector 121 and the media selector 122 are described as follows.

[0097] Chip selector 121 is used to receive a chip strobe signal from a connected chip strobe signal line and to receive input / output signals from a connected first input / output bus 142. Chip selector 121 is also used to transmit access signals to the interface circuit 132 of the target memory chip based on the chip strobe signal. For example, based on the chip strobe signal, chip selector 121 selects one of the M connected memory chips 13 (i.e., the target memory chip) and connects its interface circuit 132 (i.e., the target interface circuit) to the storage medium controller 11, transmitting the received input / output signals to the target interface circuit. For instance, the first input / output bus 142 can be connected to the second input / output bus 162 (i.e., the target input / output bus) corresponding to the target memory chip, thereby connecting the storage medium controller 11 to the interface circuit 132 (i.e., the target interface circuit), making the target interface circuit the interface circuit 132 for the storage medium controller 11 to access the memory chip, allowing the input / output signals in the first input / output bus 142 to be transmitted to the target input / output bus, and the input / output signals to be transmitted to the target interface circuit through the target input / output bus.

[0098] The media selector 122 is used to receive multiple first gating signals from the connected first gating bus 141, and based on the multiple media gating signals among the multiple first gating signals, transmit a valid gating signal corresponding to the target media channel to the target interface circuit. For example, as shown in Figures 3 and 4, the media selector 122 can be a decoder. The media selector 122 is also used to decode the multiple media gating signals to obtain multiple second gating signals. These multiple second gating signals correspond to one media channel among the M memory chips 13. The second gating signal corresponding to the target media channel among the multiple second gating signals is a valid gating signal, and the second gating signal corresponding to the media channel other than the target media channel is an invalid gating signal.

[0099] Taking multiple second strobe signals, including signals CE0' to CE7', as an example, the media selector 122 is a 3-to-8 decoder. The truth table of the media selector 122 is shown in Table 1 below. The media selector 122 can decode multiple media strobe signals, such as signals CE0 to CE2, into corresponding value combinations of signals CE0' to CE7' according to this truth table, thereby selecting and activating the media channel corresponding to the valid strobe signal among signals CE0' to CE7'. When any signal among signals CE0' to CE7' takes a value of 0, the signal is a valid strobe signal; when the signal takes a value of 1, the signal is an invalid strobe signal.

[0100] Table 1

[0101] The media selector 122 generates M*P second strobe signals, with each group consisting of P second strobe signals. The media channels corresponding to the second strobe signals in the same group are located in the same memory chip, so that each group of second strobe signals corresponds to one memory chip 13, and different groups of second strobe signals correspond to different memory chips 13. Taking Table 1 as an example, signals CE0' to CE3' form one group of second strobe signals, corresponding to memory chip 0, and signals CE4' to CE7' form another group of second strobe signals, corresponding to memory chip 1.

[0102] The media selector 122 is also used to send a corresponding set of second strobe signals to the interface circuits 132 of the M memory chips 13 via the connected M second strobe buses 161. Taking Figures 3 and 4 as examples, the CE0' to CE3' signals are sent to the interface circuit 132 of memory chip 0 via the second strobe bus 161 corresponding to memory chip 0, and the CE4' to CE7' signals are sent to the interface circuit 132 of memory chip 1 via the second strobe bus 161 corresponding to memory chip 1.

[0103] When accessing the target memory chip, the storage media controller 11 outputs a primary media selection signal to the media selector 122. The media selector 122 outputs multiple secondary strobe signals, which are secondary media strobe signals. Of these secondary strobe signals, only the secondary strobe signal corresponding to the target media channel is valid; the others are invalid. Thus, the target selection circuit transmits the valid strobe signal to the target interface circuit via the media selector 122 and the access signal to the target interface circuit via the chip selector 121. This allows the control circuit 133 in the target memory chip to access the memory circuit 131 on the target media channel based on the access signal and the valid strobe signal.

[0104] Taking one of the M memory chips 13 connected to the target selection circuit as an example, the interface circuit 132 in memory chip 13 receives multiple second strobe signals from the connected second strobe bus 161 and receives input / output signals from the storage medium controller 11 from the connected second input / output bus 162. It then sends input / output signals and these multiple second strobe signals to the control circuit 133 in the memory chip 13. Each second strobe signal corresponds to a media channel in the memory chip 13. The control circuit 133 receives the input / output signals and the multiple second strobe signals, and accesses the storage circuit 131 in the memory chip 13 based on these signals. For example, if a valid strobe signal is among the received multiple second strobe signals, the control circuit 133 selects the medium channel corresponding to the valid strobe signal from the connected multiple medium channels and accesses the storage circuit 131 on the activated medium channel based on the access signal in the input / output signals. In this case, the storage chip 13 is the target storage chip, the interface circuit 132 in the storage chip 13 is the target interface circuit, and the medium channel corresponding to the valid strobe signal is the target medium channel. If no valid strobe signal is among the received multiple second strobe signals, the control circuit 133 ignores the received input / output signals, and the input / output signals are invalid signals, and the storage chip 13 is not the target storage chip.

[0105] Chip selector 121 switches the input / output signals of storage medium controller 11 among M storage chips based on changes in the chip selection signal. Taking Figure 4 as an example, in response to an access command requesting access to storage chip 0, storage medium controller 11 outputs a CE2 signal with a value of 0 to chip selector 121, triggering chip selector 121 to transmit its input / output signals to storage chip 0. Subsequently, when executing an access command requesting access to storage chip 1, storage medium controller 11 outputs a CE2 signal with a value of 1 to chip selector 121, triggering chip selector 121 to switch its input / output signals to storage chip 1. By switching the input / output signals of storage medium controller 11 among different storage chips 13 in the same communication channel, single-channel load isolation can be achieved, and storage medium controller 11 can access one storage chip 13 at a time, thus ensuring the data transmission rate of the communication channel where storage chip 13 is located. When the media selector 122 is a decoder, it can decode the media strobe signal of the storage media controller 11 into more second strobe signals, thereby using more second strobe signals to manage more storage chips 13, realizing single-channel capacity expansion, and thus increasing the overall storage capacity of the storage drive.

[0106] The media selector 122 is also connected to the storage media controller 11 via an enable signal line. The media selector 122 is also used to enable based on the enable signal transmitted in the enable signal line. As shown in Figures 3 and 4, the enable signal is the CE3 signal. If the received CE3 signal is 0, the media selector 122 is enabled; if the received CE3 signal is 1, the media selector 122 is disabled.

[0107] Optionally, chip selector 121 is connected to storage medium controller 11 via an enable signal line. Chip selector 121 is also used to enable based on the enable signal transmitted in the enable signal line. This allows chip selector 121 and media selector 122 to be in the same enabled state. Chip selector 121 and media selector 122 in the same selection circuit 12 share the same enable signal, which avoids adding additional pins in the channel interface circuit 15 to provide enable signals for chip selector 121 and media selector 122 respectively.

[0108] In the storage drive 100, the signals from the storage media controller 11 are interconnected with the storage chip 13 via the selection circuit 12. Taking Figure 6 as an example, assuming the storage drive 100 is an SSD, the storage media controller 11 is the SSD's master controller (i.e., the SSD controller), the chip selector 121 in the selection circuit 12 is a 1:2 data selector MUX_1:2, the media selector 122 in the selection circuit 12 is a decoder, and the storage chip 13 is a NAND flash memory chip. The NAND flash memory chip includes 32 NAND flash dies, with every 16 NAND flash dies connected to the same wire bonding (WB), where WB is a media channel. Assuming access to the NAND flash memory chip on the communication channel N (CHn), the input / output signals used to carry access commands are represented as M_2 signals (finger). The master controller sends a chip strobe signal and an M_2 finger to the MUX_1:2 on CHn, and the MUX_1:2 sends an M_2 finger to the NAND flash memory chip indicated by the chip strobe signal. Furthermore, the main controller sends multiple media strobe signals to the decoder on CHn. The decoder decodes these signals into multiple sets of second strobe signals and sends one set of second strobe signals to each NAND flash memory chip on CHn. Each set of second strobe signals includes multiple second strobe signals, and each set corresponds to a WB (Wave Block) in a NAND flash memory chip. When any NAND flash memory chip on CHn receives a set of second strobe signals containing a valid strobe signal, it accesses the NAND flash memory die on the WB corresponding to the valid strobe signal.

[0109] As can be seen from the above description, any selection circuit 12 in the storage driver 100 is used to select one of the multiple (i.e. M) storage chips 13 connected to it from the interface circuit of the storage chip 13 based on the selection signal of the storage medium controller 11.

[0110] Next, based on the storage driver 100 described above, and referring to Figure 7, taking the execution of an access instruction by the storage medium controller 11 in the storage driver 100 as an example, the selection logic of the selection circuit 12 and the access process of the storage chip 13 will be described. This process includes the following steps:

[0111] 701. In response to the first access instruction, the storage medium controller 11 sends a first access signal, a first chip strobe signal, and a first medium strobe signal to the first selection circuit.

[0112] Here, the first access instruction refers to any access instruction requesting access to the first memory chip. The target memory address in the first access instruction is called the first memory address, which is the memory address requested by the first access instruction. The medium channel connected to the memory circuit 131 to which the first memory address belongs is the first medium channel, which is the target medium channel for this access. The memory chip 13 to which the memory circuit 131 to which the first memory address belongs is the first memory chip, which is the target memory chip for this access. The first selection circuit is the selection circuit connected to the first memory chip, which is the target selection circuit used for this access.

[0113] The first access signal is an access signal used to carry the first access instruction. The first chip strobe signal is a chip strobe signal among multiple first strobe signals. The first chip strobe signal indicates that the first memory chip is selected from the multiple (e.g., M) connected memory chips. There are multiple first media strobe signals, which indicate that the first media channel of the first memory chip is selected from the M connected memory chips. Taking Figures 3 and 4 as examples, assuming that the first memory chip is memory chip 0 and the first media channel is media channel 0 in memory chip 13, then the first selection circuit is the selection circuit 12 connected to memory chip 0. According to the switching control logic diagram of the selection circuit shown in Figure 5, the first chip strobe signal is the CE2 signal with a value of 0, and the multiple first media selection signals are the CE1 to CE2 signals with values ​​of {0,0,1}.

[0114] In response to the first access command, the storage medium controller 11 sends multiple first strobe signals and first input / output signals to the first selection circuit, thereby sending a first access signal, a first chip strobe signal, and a first media strobe signal to the first selection circuit. At this time, the multiple first strobe signals include the first chip strobe signal and multiple first media strobe signals, and these multiple first strobe signals also include an enable signal, such as the CE3 signal with a value of 0. The first input / output signals are the input / output signals sent by the storage medium controller 11 in response to the first access command, and the first input / output signals include the first access signal.

[0115] The storage medium controller 11 can send multiple first strobe signals to the first selection circuit by sending multiple first strobe signals to the first strobe bus 141 connected to the first selection circuit, and send first input / output signals to the first input / output bus 142 connected to the first selection circuit.

[0116] The above description uses the example of simultaneously sending a first access signal and a first chip strobe signal to the first selection circuit. In other embodiments, when the transmission delay of the first chip strobe signal in the first selection circuit (referred to as the first transmission delay) is different from the transmission delay of the first access signal in the first selection circuit (referred to as the second transmission delay), if the first transmission delay is greater than the second transmission delay, the storage medium controller 11, in response to the first access command, first executes the step of sending the first chip strobe signal to the first selection circuit (i.e., sending multiple first strobe signals to the first selection circuit), and after a third duration, executes the step of sending the first access signal to the first selection circuit (i.e., sending the first input / output signal to the first selection circuit), where the third duration is the difference between the transmission delays of the first access signal and the first chip strobe signal in the first selection circuit. Alternatively, if the first transmission delay is less than the second transmission delay, the storage medium controller 11, in response to the first access command, first executes the step of sending the first access signal to the first selection circuit, and then executes the step of sending the first chip strobe signal to the first selection circuit. By sending the first access signal and the first chip strobe signal in this way, the first access signal and multiple second strobe signals (described below) generated based on the first chip strobe signal can reach the first memory chip simultaneously, so as to avoid problems such as signal sampling misalignment and data access errors on the first memory chip side.

[0117] Since the first chip strobe signal is a multiplexed first medium strobe signal, the first transmission delay is the time from when the first selection circuit receives the first medium strobe signal to when it outputs the second strobe signal generated based on the first medium strobe signal; that is, the transmission delay of the first strobe signal in the first selection circuit. The second transmission delay is the time from when the first selection circuit receives the first input / output signal to when it outputs the first input / output signal; that is, the transmission delay of the first input / output signal in the first selection circuit.

[0118] 702. The first selection circuit receives a first access signal, a first chip gating signal, and a first medium gating signal, and sends a first access signal and a valid gating signal corresponding to the first medium channel to the first interface circuit based on the first chip gating signal and the first medium gating signal.

[0119] The first interface circuit is the interface circuit 132 in the first memory chip, that is, the interface circuit (i.e., the target interface circuit) of the memory chip accessed by the storage medium controller 11 in response to the first access command. The valid strobe signal is the second strobe signal corresponding to the first medium channel.

[0120] The chip selector 121 in the first selection circuit receives a first input / output signal and a first component selection signal from the connected first input / output bus 142. Based on the first component selection signal, the chip selector 121 sends a first input / output signal to the first interface circuit to achieve the sending of a first access signal to the first interface circuit. For example, based on the first component selection signal, the chip selector 121 selects the interface circuit 132 (i.e., the first interface circuit) of the first memory chip from the connected M memory chips 13 and connects it to the storage medium controller 11, transmitting the received first input / output signal to the first interface circuit. This process can be referred to as the following process above: Based on the chip selection signal, the chip selector 121 selects the interface circuit 132 (i.e., the target interface circuit) of the target memory chip from the connected M memory chips 13 and connects it to the storage medium controller 11, transmitting the received input / output signal to the target interface circuit.

[0121] For example, assuming the first component selection signal is the CE2 signal with a value of 0, according to the switching control logic diagram shown in Figure 5, the chip selector 121 sends a first input / output signal to the interface circuit of the memory chip 0. For example, it sends the first input / output signal to the second input / output bus 162 connected to the memory chip 0, so that the first input / output signal is transmitted to the interface circuit of the memory chip 0.

[0122] The media selector 122 in the first selection circuit receives multiple first strobe signals. Based on the first media strobe signal among the multiple first strobe signals, it sends a valid strobe signal corresponding to the first media channel to the first memory chip. Taking the media selector 122 as a decoder as an example, the media selector 122 decodes the multiple first media strobe signals to obtain multiple second strobe signals. These multiple second strobe signals correspond to one media channel of each of the M memory chips 13. Among these multiple second strobe signals, the second strobe signal corresponding to the first media channel is the valid strobe signal, and the other second strobe signals are invalid strobe signals. The media selector 122 sends a set of second strobe signals corresponding to the multiple second strobe signals to the interface circuit 132 of the M memory chips 13. For example, it sends a corresponding set of second strobe signals to each connected second strobe bus, so that the set of second strobe signals is transmitted to the interface circuit 132 connected to the second strobe bus.

[0123] Taking multiple first media selection signals, including the combination of values ​​{0,0,1} as CE0 to CE2, as an example, the media selector 122 decodes the CE0 to CE2 signals into the combination of values ​​{0,1,1,1,1,1,1,1} as shown in Table 1. The CE0' signal has a value of 0, which is a valid selection signal, indicating that the corresponding media channel 0 is turned on. The CE1' to CE7' signals all have values ​​of 1, which are invalid selection signals. The media selector 122 sends the CE0' to CE3' signals to the second selection bus 161 connected to the memory chip 0, and sends the CE4' to CE7 signals to the second selection bus 161 connected to the memory chip 1.

[0124] 703. The first interface circuit in the first memory chip receives a first access signal and a valid strobe signal corresponding to the first medium channel. The control circuit 133 in the first memory chip accesses the first memory chip based on the first access signal and the valid strobe signal.

[0125] The first storage circuit is the storage circuit 131 to which the first storage address belongs in the first storage chip.

[0126] When accessing the first memory chip, data can be read and written in the memory circuit 131 of the first memory chip through the first interface circuit. For example, the first interface circuit receives a first input / output signal and multiple second strobe signals, and sends the first input / output signal and multiple second strobe signals to a first control circuit, which is the control circuit 133 in the first memory chip. Based on the valid strobe signal among the multiple second strobe signals, the first control circuit activates the first medium channel in the first memory chip. The first access direction in the first input / output signal is parsed to derive a first access instruction. Based on the first memory address in the first access instruction, the first memory circuit on the first medium channel is accessed (e.g., data is read or written in the first memory circuit).

[0127] For the other memory chips connected to the first selection circuit besides the first memory chip, the interface circuits 132 of the other memory chips also receive multiple second strobe signals and send the received multiple second strobe signals to their respective connected control circuits 133. Since the second strobe signals received by the interface circuits 132 of the other memory chips are all invalid strobe signals, the control circuits 133 of the other memory chips ignore the multiple second strobe signals and do not access the memory circuits in their respective memory chips.

[0128] The method provided in this application embodiment involves the storage medium controller 11 in the storage driver 100 sending an access signal and multiple strobe signals to the selection circuit 12 in response to an access command. The selection circuit 12 then sends an access signal from among the multiple connected storage chips 13 to the storage chip 13 that the access command requests access to, based on the multiple strobe signals, so as to access the storage chip 13.

[0129] When the storage medium controller executes an access instruction requesting access to different storage chips 13 on the same communication channel, the storage medium controller 11 controls the chip strobe signal on the communication channel to flip (i.e., the chip strobe signal changes), thereby triggering the chip selector 121 in the selection circuit on the communication channel to switch the input / output signals of the storage medium controller 11 among the M storage chips. In this application, signal flipping refers to the flipping of the signal value state, for example, the signal value changes from 0 to 1, or the signal value changes from 1 to 0. Signal flipping can be manifested as the signal changing from a high level to a low level or from a low level to a high level.

[0130] For a given access instruction to be executed, if this access instruction requests access to a different memory chip 13 on a communication channel than the previously executed access instruction, the storage medium controller 11 controls the chip selector 121 (e.g., MUX) in the target selection circuit (e.g., the first selection circuit) via a chip strobe signal. This switches the interface circuit of the memory chip accessed by the storage medium controller 11 from the interface circuit requested by the previously executed access instruction to the interface circuit of the memory chip requested by this access instruction. This achieves strobe control over the input and output signals of the storage medium controller 11, resulting in a transmission delay in the input and output signals at the chip selector 121. The maximum transmission delay can reach 10–100 ns, but relevant standards define that the transmission delay of input and output signals should be less than 10 ns. The chip selector 121 switches the input and output signals between different memory chip 13 interface circuits according to the toggling of the chip strobe signal. For example, when the chip strobe signal is 0, the chip selector 121 sends input / output signals to the interface circuit of memory chip 0. When the chip strobe signal changes from 0 to 1, the interface circuit for accessing the memory chip by the storage medium controller 11 is switched from the interface circuit 132 of memory chip 0 to the interface circuit 132 of memory chip 1, thereby switching the input / output signals of the storage medium controller 11 to the interface circuit 132 of memory chip 1. Due to this characteristic, when the storage medium controller 11 executes two access instructions to access different memory chips 13 (such as NAND flash memory chips) on the same communication channel, the chip selector 121 switches the input / output signals between different memory chips 13 based on the toggling of the chip strobe signal. This causes the previously executed access instruction to affect the execution of the subsequent access instruction, resulting in an error in the execution of the subsequent access instruction.

[0131] For example, when the storage medium controller 11 executes an access instruction 0 requesting access to the storage chip 0, the storage medium controller 11 sends a chip strobe signal (such as the CE2 signal) with a value of 0 to the chip selector 121 connected to the storage chip 0, triggering the chip selector 121 to transmit an input / output signal 0 carrying the access instruction 0 to the storage chip 0. If, during the transmission of the input / output signal 0, the storage medium controller 11 executes an access instruction 1 requesting access to the storage chip 1, the storage medium controller 11 sends a chip strobe signal with a value of 1 and a signal carrying the access instruction 0 to the chip selector 121. The input / output signal of access instruction 1, with a chip strobe signal of value 1, triggers chip selector 121 to switch the input / output signal of storage medium controller 11 to the interface circuit of storage chip 1. This causes the remaining input / output signal 0 and input / output signal 1 to be sent together to the interface circuit of storage chip 1. The remaining input / output signal 0 will cause timing errors in the input / output signals on the interface circuit of storage chip 1, leading the control circuit of storage chip 1 to mistakenly identify the remaining input / output signal 0 as input / output signal 1, resulting in an access error for access instruction 1 and an error in the execution of access instruction 1. Therefore, when storage medium controller 11 executes two access instructions consecutively, and the two access instructions request access to different storage chips 13, the execution of the first access instruction will affect the execution of the second access instruction, which may cause the execution of the second access instruction to fail.

[0132] Based on this, this application provides another data access method, which is applied to any of the storage drives 100 described above. The storage drive 100 includes a storage medium controller 11, a first storage chip, and a second storage chip. The second storage chip and the first storage chip are located on the same communication channel and connected to the same selection circuit (i.e., the first selection circuit). Each of the first and second storage chips includes an interface circuit 132 and a storage circuit 131 for recording data. This method is executed by the storage medium controller 11 in the storage drive 100, as shown in FIG8, and includes the following steps.

[0133] 801. The storage medium controller 11 transmits a first access command to the first interface circuit to access the first storage chip, wherein the first interface circuit is located in the first storage chip and communicates with the storage medium controller 11.

[0134] The first interface circuit and the first access instruction are described in the embodiment shown in Figure 7. This step 801 can be implemented by the above steps 701 to 703, and will not be described again here.

[0135] 802. When the access instruction of the storage medium controller 11 to access the storage chip 13 is switched from the first access instruction to the second access instruction, the storage medium controller 11 switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, wherein the second interface circuit is located in the second storage chip and communicates with the storage medium controller 11.

[0136] The second interface circuit is the interface circuit 132 in the second memory chip, which is the interface circuit (i.e., the target interface circuit) through which the storage medium controller 11 accesses the memory chip in response to the second access instruction. The second access instruction is an access instruction requesting access to the second memory chip. The first access instruction and the second access instruction can be adjacent access instructions with consecutive execution order. The first access instruction is executed through the above step 801. The first access instruction and the second access instruction request access to different memory chips on the same communication channel. The second memory chip is the chip requested by the second access instruction.

[0137] The target memory address in the second access instruction is called the second memory address, meaning the second access instruction indicates that the second memory address should be accessed. The medium channel connected to the memory circuit 131 to which the second memory address belongs is called the second medium channel, which is the target medium channel obtained in this access. The memory chip 13 to which the memory circuit 131 to which the second memory address belongs is called the second memory chip, which is the memory chip accessed in this access. Both the second memory chip and the first memory chip are connected to the first selection circuit, which is the selection circuit 12 used in this access.

[0138] The interface circuit for accessing the memory chip refers to the interface circuit through which the storage medium controller 11 accesses the memory chip. It is the interface circuit of the memory chip requested by the access instruction to be executed. For example, when executing the first access instruction, the first interface circuit is the interface circuit for the storage medium controller 11 to access the memory chip, and when executing the second access instruction, the second interface circuit is the interface circuit for the storage medium controller 11 to access the memory chip.

[0139] During the transmission of the first access instruction through the first interface circuit, the storage medium controller 11 sends a first input / output signal to the first selection circuit. According to relevant technical standards, after the storage medium controller completes the action of sending the first input / output signal, it begins to execute the next access instruction (i.e., the second access instruction). When executing the second access instruction, the access instruction for accessing the storage chip 13 is switched from the first access instruction to the second access instruction.

[0140] Before executing the second access instruction, the storage medium controller 11 switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, so as to avoid switching the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit when executing the second access instruction.

[0141] The interface circuit switching process can be as follows: the storage medium controller 11 sends a second chip strobe signal to the first selection circuit. This second chip strobe signal triggers the first selection circuit to switch the interface circuit for the storage medium controller 11 to access the storage chip from the first interface circuit to the second interface circuit. The second chip strobe signal indicates the selection of the second storage chip from among the connected multiple (e.g., M) storage chips. Taking Figures 3 and 4 as examples, assuming the first storage chip is storage chip 0 and the second storage chip is storage chip 1, according to the switching control logic diagram of the selection circuit shown in Figure 5, the second chip strobe signal is the CE signal 2 with a value of 1.

[0142] For example, the storage medium controller 11 sends multiple first strobe signals to the first selection circuit (the sending method can be referred to step 701 above). At this time, the multiple first strobe signals include a second chip strobe signal and multiple second media strobe signals. The second chip strobe signal and the multiple second media strobe signals are determined based on the second access instruction. The second chip strobe signal is the chip strobe signal among the multiple first strobe signals, and the second chip strobe signal is used to indicate the selection of a second storage chip to be turned on from the multiple (e.g., M) connected storage chips. The second media strobe signal is the media strobe signal among the multiple first strobe signals, and the multiple second media strobe signals indicate the selection of a second media channel in the second storage chip to be turned on from the M connected storage chips. Taking Figures 3 and 4 as examples, assuming that the second storage chip is storage chip 1 and the second media channel is media channel 0 in storage chip 1, according to the switching control logic diagram of the selection circuit shown in Figure 5, the second chip strobe signal is the CE2 signal with a value of 1, and the multiple second media strobe signals are the CE1 to CE2 signals with values ​​of {1,0,0}. The enable signal among the multiple first strobe signals is the CE3 signal with a value of 0.

[0143] The chip selector 121 in the first selection circuit receives a second chip selection signal from a plurality of first selection signals. Based on the second chip selection signal, the interface circuit for the storage medium controller 11 to access the storage chip is switched from the first interface circuit to the second interface circuit. For example, based on the second chip selection signal, the first input / output bus 142 connected to the first selection circuit is connected to the second input / output bus 162 corresponding to the second storage chip.

[0144] The media selector 122 in the first selection circuit receives multiple first strobe signals and generates multiple second strobe signals based on multiple second media strobe signals among the multiple first strobe signals. Taking the multiple second media strobe signals including the combination of values ​​{1,0,0} as signals CE0 to CE2 as an example, the media selector 122 decodes the signals CE0 to CE2 into signals CE0' to CE7' with the combination of values ​​{1,1,1,1,0,1,1,1} according to the truth table shown in Table 1. The value of the CE4' signal is 0, which is a valid strobe signal, indicating that the corresponding media channel 0 is turned on. The values ​​of the CE1' to CE7' signals are all 1, which are invalid strobe signals. After generating multiple second strobe signals, the media selector 122 sends the corresponding multiple second strobe signals (i.e., a set of second strobe signals) to each interface circuit 132 connected to the first selection circuit. This process has been described above and will not be repeated here.

[0145] Since the storage medium controller 11 does not send input / output signals to the first selection circuit at this time, the chip selector 121 in the first selection circuit will not send input / output signals to each interface circuit 132 connected to it. Thus, each interface circuit 132 connected to the first selection circuit only receives the second strobe signal and does not receive the input / output signal. Therefore, the control circuit 133 connected to each interface circuit 132 can ignore the second strobe signal it receives.

[0146] When the storage medium controller switches from accessing the first storage chip to accessing the second storage chip, direct access to the second storage chip may result in errors (e.g., the second storage chip becoming unresponsive). One reason for this error is that the interface circuit switching transmits the residual first access command from the communication channel between the storage medium controller and the first interface circuit to the second interface circuit. This causes a change in the state of the second interface circuit (a non-initialized state). The existence of this state triggers an error in the second storage chip when accessing it. For example, due to this state, subsequent second access commands sent to the second interface circuit cannot be correctly recognized, thus preventing the control circuit in the second storage chip from executing the second access command, resulting in an error in accessing the second storage chip.

[0147] Based on this, in the application, after the storage medium controller 11 switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, it first initializes the second interface circuit through the following step 803 to restore the second interface circuit to the initialization state. After the initialization is completed, it accesses the second storage chip through the following step 804.

[0148] 803. Before accessing the second memory chip, the storage medium controller 11 initializes the second interface circuit.

[0149] In this context, "before accessing the second memory chip" refers to the process of accessing the second memory chip via the second access instruction, i.e., before transmitting the second access instruction to the second interface circuit. Initializing the second interface circuit aims to restore it to its initial state.

[0150] Initializing the second interface circuit includes any of the following: resetting the second interface circuit to set it to an initialized state; or performing a dummy read / write operation on the second memory chip, restoring the second interface circuit to its initialized state during the dummy read / write operation; or performing a read operation on the second memory chip, restoring the second interface circuit to its initialized state during the read operation. The dummy read / write operation includes either a dummy read or a dummy write operation. Dummy read / write operations are special control operations performed based on the operating characteristics of NAND flash memory chips. They are not true data reading or writing operations, but rather operations performed to meet the time period or signal synchronization requirements of the internal workflow of the NAND flash memory chip. A read operation is a data reading operation from the NAND flash memory chip.

[0151] The storage medium controller 11 sends an initialization command to the second storage chip through a first selection circuit to implement step 803. The initialization command instructs the target interface circuit to be initialized. This initialization command can be a reset command, which instructs the interface circuit 132 of the storage chip 13 to be reset. Alternatively, the initialization command can be a pseudo-read / write command, which instructs the storage chip 13 to perform a pseudo-read / write operation. Or, the initialization command can be a read command, which instructs the storage circuit in the storage chip to perform a read operation. The storage address for the read operation can be the second storage address in the second access command, i.e., a read operation is performed on the storage address requested by the second access command. The initialization command includes an instruction type identifier, which indicates the instruction type. Different types of initialization commands are indicated by different instruction type identifiers. For example, the instruction type identifiers for the reset command, pseudo-read / write command, and read command are FF, 0031, and 70, respectively.

[0152] The storage medium controller 11 sends an initialization signal to the second interface circuit through the first selection circuit to send an initialization command to the second storage chip. The initialization signal is used to carry the initialization command and indicates that the interface circuit 132 of the storage chip is initialized. The initialization signal can be a DQ signal carrying the initialization command.

[0153] For example, the storage medium controller 11 sends an initialization signal to the first selection circuit in response to an initialization command. For instance, it sends a third input / output signal to the first input / output bus 142 connected to the first selection circuit; this third input / output signal is an input / output signal that includes the initialization signal. The chip selector 121 in the first selection circuit receives the third input / output signal. Since the chip selector 121 has switched the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit in step 802, the chip selector 121 sends the received initialization signal to the second interface circuit; for example, it sends the third input / output signal to the second input / output bus 162 corresponding to the second storage chip.

[0154] In other embodiments, in step 803, the storage medium controller 11 sends an initialization signal to the first selection circuit in response to the initialization command, and sends multiple first strobe signals to the first selection circuit (the sending method can be referred to step 701 above). In this case, the multiple first strobe signals include a second chip strobe signal and multiple second medium strobe signals. The chip selector 121 in the first selection circuit receives the initialization signal and the second chip strobe signal from the multiple first strobe signals, and sends the received initialization signal to the second interface circuit based on the second chip strobe signal. The medium selector 122 in the first selection circuit receives the multiple first strobe signals, generates multiple second strobe signals based on the multiple second medium strobe signals from the multiple first strobe signals, and sends the corresponding multiple second strobe signals to each interface circuit 132 connected to the first selection circuit.

[0155] The above description uses the example of executing step 802 first and then step 803. In other embodiments, steps 802 and 803 may be executed simultaneously. For example, before accessing the second memory chip via the second access instruction (i.e., before executing the second access instruction), the storage medium controller 11 performs the steps of sending a second chip strobe signal to the first selection circuit and sending an initialization signal to the first selection circuit.

[0156] When the transmission delay of the second chip strobe signal in the first selection circuit (referred to as the third transmission delay) differs from the transmission delay of the initialization signal in the first selection circuit (referred to as the fourth transmission delay), if the third transmission delay is greater than the fourth transmission delay, the storage medium controller 11, in response to the initialization command, first executes the step of sending the second chip strobe signal to the first selection circuit (i.e., sending multiple first strobe signals to the first selection circuit), and after a first duration, executes the step of sending the second access signal to the first selection circuit (i.e., sending the third input / output signal to the first selection circuit), where the first duration is the difference between the transmission delays of the second chip strobe signal and the initialization signal in the first selection circuit. Alternatively, if the third transmission delay is less than the fourth transmission delay, the storage medium controller 11, in response to the initialization command, first executes the step of sending the initialization signal to the first selection circuit, and after a first duration, executes the step of sending the second chip strobe signal to the first selection circuit. By sending the initialization signal and the second chip strobe signal in this manner, the initialization signal and the multiple second strobe signals generated based on the second chip strobe signal can reach the second storage chip simultaneously, thus avoiding problems such as signal sampling misalignment and data access errors on the second storage chip side.

[0157] Since the second chip strobe signal is also multiplexed as a medium strobe signal for multiple first strobe signals, the third transmission delay is the time from when the first selection circuit receives the multiple first strobe signals to when it outputs the second strobe signal generated based on the multiple first strobe signals; that is, the transmission delay of the first strobe signal in the first selection circuit. The second transmission delay is the time from when the first selection circuit receives the third input / output signal to when it outputs the third input / output signal; that is, the transmission delay of the third input / output signal in the first selection circuit.

[0158] Following steps 802 and 803 above, the second interface circuit in the second memory chip receives a third input / output signal and a plurality of second strobe signals, among which a valid strobe signal corresponds to the second medium channel. The second interface circuit sends the third input / output signal and the plurality of second strobe signals to the control circuit 133 in the second memory chip. Based on the initialization signal in the third input / output signal, the control circuit 133 parses the initialization instruction and initializes the second interface circuit based on the initialization instruction.

[0159] For example, if the initialization instruction is a reset instruction, the control circuit 133 ignores the valid strobe signal and performs a reset operation on the second interface circuit to set the second interface circuit to the initialization state.

[0160] If the initialization instruction is a pseudo-read / write instruction, the control circuit 133 ignores the valid strobe signal and performs a pseudo-read / write operation on the storage circuit 131 in the second storage chip. During the pseudo-read / write operation, the second interface circuit is restored to the initialization state. For example, during the pseudo-read / write operation, the storage medium controller 11 sends DQS / DQ signals to the second interface circuit multiple times through the first selection circuit. The multiple DQS / DQ signals are flipped, causing the timing circuit control logic of the second interface circuit to jump out of the error state before the switch, and the state machine is restored to the default / initial state. The second interface circuit is restored to the high impedance or input state, thereby restoring the second interface circuit to the initialization state.

[0161] If the initialization command is a read command, the control circuit 133 activates the second medium channel corresponding to the valid strobe signal, performing a read operation on the storage circuit 131 on the second medium channel. During the read operation, the second interface circuit is restored to its initialization state. For example, during the read operation, the storage medium controller 11 sends DQS / DQ signals multiple times to the second interface circuit through the first selection circuit. These multiple DQS / DQ signals flip, causing the timing circuit control logic of the second interface circuit to jump out of the error state before the switch, restoring the state machine to the default / initial state. The second interface circuit then returns to a high-impedance or input state, thus restoring the second interface circuit to its initialization state. After the read operation is completed, the control circuit 133 returns the read data to the storage medium controller 11 through the second interface circuit and the first selection circuit. Since the purpose of this read operation is to initialize the second interface circuit, not to read data, the storage medium controller 11 ignores the data read by the control circuit 133 based on this read operation.

[0162] During the transmission of the first access command through the first interface circuit, the storage medium controller 11 sends a first input / output signal to the first selection circuit. According to relevant technical standards, after the storage medium controller 11 completes the action of sending the first input / output signal, it executes the next access command (i.e., the second access command). When executing the second access command, the storage medium controller 11 switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, and transmits the second access command through the second interface circuit to access the second storage chip. If, during the switch from the first interface circuit to the second interface circuit, there are remaining first input / output signals in the first input / output bus between the first selection circuit and the storage medium controller 11, these remaining first input / output signals are transmitted to the second interface circuit. This causes a timing error in the input / output signals on the second interface circuit, resulting in the control circuit in the second storage chip misidentifying the input / output signals carrying the second access command subsequently received by the second interface circuit, thus leading to an error in the execution of the second access command. In this embodiment, before executing the second access instruction, the interface circuit for the storage medium controller 11 to access the storage chip is switched from the first interface circuit to the second interface circuit (i.e., step 802). Even if there are remaining first input / output signals transmitted to the second interface circuit after the interface circuit switch, the remaining first input / output signals on the first interface circuit can be eliminated by initializing the second interface circuit (i.e., step 803), so that the timing of the input / output signals of the first interface circuit is restored to the initial state. After initialization, when executing the second access instruction (i.e., step 804), the remaining first input / output signals after the interface circuit switch can be prevented from affecting the execution of the second access instruction, so that the second access instruction can be executed normally.

[0163] 804. After initialization, the storage medium controller 11 transmits a second access command to the second interface circuit to access the second storage chip.

[0164] For example, in response to the second access instruction, the storage medium controller 11 sends a second access signal, a second chip strobe signal, and a second medium strobe signal to the first selection circuit. The second access signal is an access signal used to carry the second access instruction. The second chip strobe signal and the second medium strobe signal have been described in step 802 above and will not be repeated here.

[0165] For example, in response to the second access instruction, the storage medium controller 11 sends a second input / output signal and a plurality of first strobe signals to the first selection circuit. The plurality of first strobe signals include a second chip strobe signal and a plurality of second medium strobe signals. The second chip strobe signal is the chip strobe signal among the plurality of first strobe signals. The second chip strobe signal also includes an enable signal, which is a CE3 signal with a value of 0.

[0166] The second input / output signal can be sent to the first selection circuit by sending the second input / output signal to the first input / output bus 142 connected to the first selection circuit. The method of sending multiple first strobe signals to the first selection circuit has been described above and will not be repeated here.

[0167] The first selection circuit receives the second access signal, the second chip strobe signal, and the second medium strobe signal. Based on the second chip strobe signal and the second medium strobe signal, it sends the second access signal and a valid strobe signal corresponding to the second medium channel to the second interface circuit. This process is the same as step 702. The second interface circuit receives the second access signal and the valid strobe signal corresponding to the second medium channel. The control circuit 133 (i.e., the second control circuit) in the second memory chip accesses the second memory medium based on the second access signal and the valid strobe signal. This process is the same as step 703.

[0168] The above explanation uses the simultaneous transmission of the second access signal and the second chip strobe signal to the first selection circuit as an example. In other cases, if the transmission delay of the second chip strobe signal to the first selection circuit (i.e., the third transmission delay) is greater than the transmission delay of the second access signal to the first selection circuit (referred to as the fifth transmission delay), and if the third transmission delay is greater than the fifth transmission delay, the storage medium controller 11, in response to the second access command, first executes the step of sending the second chip strobe signal to the first selection circuit, and after a second duration, executes the step of sending the second access signal to the first selection circuit. The second duration is the difference between the transmission delays of the second chip strobe signal and the second access signal to the first selection circuit. Alternatively, if the third transmission delay is less than the fifth transmission delay, the storage medium controller 11, in response to the second access command, first executes the step of sending the second access signal to the first selection circuit, and after a second duration, executes the step of sending the second chip strobe signal to the first selection circuit. By sending the second access signal and the second chip gating signal in this way, the second access signal and multiple second gating signals generated based on the second chip gating signal can reach the second memory chip simultaneously, so as to avoid problems such as signal sampling misalignment and data access errors on the second memory chip side.

[0169] It should be understood that the fifth transmission delay is the time between the first selection circuit receiving the second input / output signal and the first selection circuit outputting the second input / output signal, i.e., the transmission delay of the second input / output signal in the first selection circuit.

[0170] The method provided in this application, when the access instruction of the storage medium controller switches from a first access instruction (the access object of the first access instruction is the first storage chip) to a second access instruction (the access object of the second access instruction is the second storage chip), initializes the second interface circuit before accessing the second storage chip, and only accesses the second storage chip after initialization is complete. Since the second interface circuit has been restored to its initial state before receiving the second access instruction, it will not malfunction and can normally process data from the storage medium controller, enabling the second access instruction to be executed normally and the second storage chip to be accessed normally.

[0171] In other embodiments, the storage medium controller 11 may not initialize the second interface circuit before executing the second access instruction, but instead execute the second access instruction after the first access instruction has been completely transmitted to the first interface circuit. For example, FIG9 shows a flowchart of another data access method provided by this application. This method is applied to any of the storage drivers 100 described above. The storage driver 100 includes a storage medium controller 11, a first storage chip, and a second storage chip. The second storage chip and the first storage chip are located on the same communication channel and connected to the same selection circuit (i.e., the first selection circuit). Each of the first and second storage chips includes an interface circuit 132 and a storage circuit 131 for recording data. The method is executed by the storage medium controller 11 in the storage driver 100 and includes the following steps.

[0172] 901. The storage medium controller 11 transmits a first access command to the first interface circuit to access the first storage chip, wherein the first interface circuit is located in the first storage chip and communicates with the storage medium controller 11.

[0173] Step 901 is the same as step 801 above, and will not be repeated here.

[0174] 902. After the first access command is fully transmitted to the first interface circuit, the storage medium controller 11 switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, and transmits the second access command to the second interface circuit to access the second storage chip. The second interface circuit is located in the second storage chip and communicates with the storage medium controller 11.

[0175] The transmission time of the first access instruction in the communication channel where the first selection circuit is located is called the target duration. In other words, the target duration is the time it takes for the first access instruction to be completely transmitted from the storage medium controller 11 through the first selection circuit to the first interface circuit. It can also be understood as the time it takes for the first input / output signal to be completely transmitted from the storage medium controller 11 through the first selection circuit to the first interface circuit.

[0176] In step 901, after the storage medium controller 11 starts transmitting the first access signal to the first interface circuit, after a target duration, the first access signal is fully transmitted to the first interface circuit through the communication channel where the first selection circuit is located. The storage medium controller 11 then switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, and transmits the second access command through the second interface circuit to access the second storage chip.

[0177] The process by which the storage medium controller 11 switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, and transmits the second access command through the second interface circuit to access the second storage chip, can be as follows: In response to the second access command, the storage medium controller 11 sends a second access signal, a second chip strobe signal, and a second media strobe signal to the first selection circuit. The first selection circuit receives the second access signal, the second chip strobe signal, and the second media strobe signal. Based on the second chip strobe signal, it switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, sends a first access signal to the second interface circuit, and sends a valid strobe signal corresponding to the second media channel to the second interface circuit based on the second media strobe signal. This process is similar to step 702. The second interface circuit receives the second access signal and the valid strobe signal corresponding to the second media channel. The control circuit 133 in the second storage chip accesses the second storage circuit based on the second access signal and the valid strobe signal. This process is similar to step 703.

[0178] Generally, according to relevant technical standards, the timing parameters of the input and output signals of the memory 11 are configured in the control circuit 133 of the memory chip. For example, tRPSTH and tCHZ, the values ​​of tRPSTH and tCHZ meet the requirements of relevant technical standards. tRPSTH refers to the holding time of the RE signal in the input / output signals after the medium strobe signal for an access instruction changes from low to high (i.e., its value changes from 0 to 1). tCHZ refers to the holding time of the DQS signal in the input / output signals after the medium strobe signal for an access instruction changes from low to high. When the input / output signals for a certain access instruction meet the configured RPSTH and tCHZ, it indicates that the access instruction carried by that input / output signal has been completely transmitted to the memory chip.

[0179] Compared to traditional SSDs, the selection circuit 12 is a new component added to the communication channel. The values ​​of tRPSTH and tCHZ required by existing relevant technical standards do not take into account the transmission delay brought by the selection circuit 12, such as the transmission delay of input and output signals in the selection circuit 12 and the transmission delay brought by the switching interface circuit for input and output signals. If, during the execution of the first access instruction, the storage medium controller 11 transmits the first input / output signal to the first interface circuit according to the tRPSTH and tCHZ requirements of existing relevant technical standards, the media gating signal (such as the CE2 signal) multiplexed as the chip gating signal among the multiple first gating signals will flip during the timing of tRPSTH and tCH. This causes the chip selector 121 (such as MUX) in the first selection circuit to prematurely switch the interface circuit for the storage medium controller 11 to access the storage chip from the first interface circuit to the second interface circuit. This switches the remaining timing of the first input / output signal (the timing of tRPSTH and tCHZ) to the second interface circuit, resulting in the timing of the first input / output signal from the first storage chip not being completed, and tRPSTH and tCHZ not meeting the requirements. Furthermore, these remaining timings will affect the timing of the input / output signals on the second interface circuit, causing subsequent input / output signals carrying the second access instruction on the second interface circuit to be misidentified, thus affecting the execution of the second access instruction.

[0180] In the embodiment shown in Figure 8 above, the second interface circuit is initialized in advance before the second access instruction is executed, so as to eliminate the remaining timing of the first input and output signals on the second interface circuit and avoid subsequent impact on the recognition and execution of the second access instruction.

[0181] In the embodiment shown in Figure 9, if the tRPSTH and tCHZ configured in the first memory chip meet the requirements of existing relevant technical standards, the storage medium controller 11 switches the interface circuit after fully transmitting the first access command to the first interface circuit. This causes the first input / output signal received on the first memory chip to not meet the tRPSTH and tCHZ requirements of existing relevant technical standards. The control circuit in the first memory chip identifies that the first input / output signal is incorrect. That is, the first memory chip does not support the following capability of the storage medium controller 11: after fully transmitting the first access command to the first interface circuit, switching the interface circuit for accessing the memory chip from the first interface circuit to the second interface circuit. Based on this, for the embodiment shown in Figure 9, the values ​​of tRPSTH and tCHZ configured in each memory chip 13 can be modified (e.g., appropriately reducing the values ​​of tRPSTH and tCHZ) so that each memory chip 13 can support the capability of the storage medium controller 11 using the modified tRPSTH and tCHZ, so that the first memory chip and the second memory chip can execute the relevant steps in the embodiment of Figure 9.

[0182] The method provided in the embodiment shown in Figure 9, for a first access instruction and a second access instruction requesting access to different memory chips, after the first access instruction is completely transmitted to the first interface circuit, switches the interface circuit for accessing the memory chip from the first interface circuit to the second interface circuit. This prevents the remaining first access instruction from being transmitted to the second interface circuit, and avoids the remaining first access instruction affecting the second access instruction on the second interface circuit when the second access instruction is subsequently transmitted through the second interface circuit. This ensures that the second access instruction on the second interface circuit can be executed normally in the second memory chip, and that the second memory chip can be accessed normally.

[0183] When the access instruction from the storage medium controller 11 to the storage chip 13 changes from a first access instruction to a second access instruction, the storage medium controller 11 switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit. This causes a portion of the first access instruction (such as the remaining timing of the first input / output signals) to be switched to the second interface circuit. The first interface circuit remains in a high-impedance state (uninitialized state) for receiving the first access instruction and cannot return to the initialized state. Subsequently, when the storage medium controller 11 switches back to accessing the first storage chip from the second storage chip, the storage medium controller 11 sends a new access instruction to the first interface circuit. Because the first interface circuit is in a high-impedance state (uninitialized state) at this time, the new access instruction is misidentified and misexecuted, thus triggering an access error when accessing the first storage chip again. Therefore, the storage medium controller 11's previous access to the first storage chip caused a change in the state of the first interface circuit (uninitialized state), and the existence of this state causes an error to be triggered when accessing the first storage chip again.

[0184] Based on this, before accessing the first memory chip in response to a new access command, the storage medium controller 11 can first initialize the first interface circuit, and then access the first memory chip after the initialization is complete. For example, after the storage medium controller 11 transmits the second access command to the second interface circuit (step 804 or step 902), the data access method provided in this application further includes the following steps A1 to A3.

[0185] Step A1: When the access instruction of the storage medium controller 11 to access the storage chip is switched from the second access instruction to the first access instruction, the storage medium controller 11 switches the interface circuit for accessing the storage chip from the second interface circuit to the first interface circuit.

[0186] In this step A1, the first access instruction requests access to the first memory chip. The first access instruction in this step A1 and the first access instruction in step 801 (or step 901) above can be the same access instruction or different access instructions.

[0187] Step A1 is similar to step 802 above, except that in step A1, the storage medium controller 11 sends a first chip strobe signal to the first selection circuit, triggering the first selection circuit to switch the interface circuit for accessing the storage chip from the second interface circuit to the first interface circuit. For example, the storage medium controller 11 sends multiple first strobe signals to the first selection circuit, where the chip strobe signal among these multiple first strobe signals is the first chip strobe signal, and multiple media strobe signals among these multiple first strobe signals are the first media strobe signals.

[0188] Step A2: Before accessing the first memory chip, the storage medium controller 11 initializes the first interface circuit.

[0189] In this step A2, the same principle applies as step 803 above. The difference is that in this step A2, when an initialization signal is sent to the first selection circuit in response to the initialization instruction, and multiple first strobe signals are sent to the first selection circuit, the chip strobe signal among the multiple first strobe signals is the first chip strobe signal, and the multiple medium strobe signals among the multiple first strobe signals are the first medium strobe signals.

[0190] Step A3: After initialization is complete, the storage medium controller 11 transmits a first access command to the first interface circuit to access the first storage chip.

[0191] The method by which the storage medium controller 11 transmits a first access command to the first interface circuit to access the first storage chip can be achieved through the above steps 701 to 703, and will not be described again here.

[0192] Steps A1 to A3 above involve initializing the first interface circuit before accessing the first memory chip when the access instruction of the storage medium controller switches from the second access instruction back to the first access instruction. Access to the first memory chip only occurs after initialization is complete. Since the first interface circuit has been restored to its initialized state before receiving the first access instruction, it will not malfunction and can process data from the storage medium controller normally, allowing the first access instruction to be executed correctly and the first memory chip to be accessed normally. For example, if the first interface circuit receives the first access instruction in its initialized state, the control circuit 133 in the first memory chip can correctly identify the first access instruction received on the first interface circuit and access the storage circuit 131 in the first memory chip based on the first access instruction, thereby enabling the first access instruction to be executed normally and the first memory chip to be accessed normally.

[0193] The storage drive 100 uses the selection circuit 12 to achieve greater capacity and higher performance. However, the larger storage capacity places more stringent requirements on the fault management of the entire storage drive 100. In addition to using the selection circuit 12 to achieve greater capacity and higher performance, it is also necessary to achieve more refined management and isolation of faults in the storage circuit 131 in the storage drive 100 to prevent the spread of faults.

[0194] For example, during the operation of the storage drive 100, the storage media controller 11 can not only perform normal read and write operations on the storage chips 13, but also periodically check the status of each storage chip 13. If any storage chip 13 is detected to be in a faulty state, the storage media controller 11 isolates the faulty storage chip 13 through the chip selector 121 connected to that storage chip 13. For example, when accessing the faulty storage chip 13 again later, the storage media controller 11 no longer sends a chip selection signal indicating the storage chip 13 to the chip selector 121, but instead sends a chip selection signal indicating other storage chips 13 on the corresponding channel to access other storage chips 13, which are storage chips 13 in a normal state. Taking Figure 10 as an example, assuming that the storage media controller 11 detects that storage chip 1 on a certain communication channel is in a faulty state and storage chip 0 is in a normal state, if the access command to be executed requests access to storage chip 0, the storage media controller 11 accesses storage chip 0 through its connected MUX to execute the access command.

[0195] The fault state of memory chip 13 indicates a malfunction in the memory chip. This malfunction can be caused by a fault in the interface circuit 132, the storage medium controller 11, or the storage circuit 131 within memory chip 13. A fault in interface circuit 132 could be due to its inability to receive signals, a fault in storage medium controller 11 could be due to its inability to function properly, or a fault in storage circuit 131 could be due to its inability to access the storage circuit. For example, an abnormality within storage circuit 131 or an open circuit in the data line (e.g., WB) used to connect to storage circuit 131 within memory chip 13 can both cause a malfunction in storage circuit 131. In some embodiments, the storage medium controller 11 may also detect the temperature of storage circuit 131; if the temperature of a storage circuit 131 exceeds a threshold, a malfunction is determined in that storage circuit 131. This application does not limit the causes and types of malfunctions in storage circuit 131.

[0196] By comprehensively considering the states of the interface circuit 132, control circuit 133, and storage circuit 131 of the storage chip 13, it is possible to determine whether the storage chip 13 is faulty, thus enabling more refined fault management. Isolating faulty storage chips can prevent the fault from spreading further, such as causing more storage circuits 132 to fail.

[0197] The chip selector 121 in the selection circuit 12 can divide the physical capacity of the entire storage circuit 131 into N parts. Each part of the physical capacity includes the storage capacity of N storage chips 13. These N storage chips 13 are connected to different selection circuits 12. Each part of the physical capacity can be used as a virtual independent storage drive 100, thereby virtualizing the storage drive 100 into N independent storage drives, thus realizing a redundant array of independent disks (RAID). The storage media controller 11 can control the N virtual independent storage drives at the granularity of a virtual independent storage drive.

[0198] In some embodiments, the storage driver 100 may also include other components that can be connected to the storage media controller 11, as shown in FIG2. Other components include a power-down protection module, a sensor module, a serial peripheral interface (SPI), and a cache, wherein the cache may include DDR memory, such as 10 4x16 gigabyte (GB) DDR or 10 4x32GB DDR.

[0199] In other embodiments, the selection circuit 12 may also be encapsulated within the storage medium controller 11. Taking the storage medium controller 11 shown in FIG11 as an example, as shown in FIG11, the storage medium controller 11 includes a control chip 111 and N selection circuits 12. Each selection circuit 12 provides a connection between the control chip 111 and the interface circuits 132 of M storage chips 13. For example, each selection circuit 12 is connected to the control chip 12 via a first bus 14. This connection method can refer to the method of selecting the circuit 12 to be connected to the storage medium controller 11 via the first bus 14 described in (1) above, and will not be repeated here. Each selection circuit 12 is connected to the interface circuits 132 of the M storage chips 13 via M second buses 16. This connection method can refer to (2) described in (2) above, and will not be repeated here.

[0200] The control chip 111 can be a programmable electronic component, such as a CPU, DPU, GPU, or NPU processing chip. Here, the type of control chip 111 is not limited in this embodiment. The control chip 111 is used to implement the method steps executed by the storage medium controller 11 in the above-described data access method embodiments.

[0201] In the storage driver 100, storage chips 13 on the same communication channel can be packaged on the same storage circuit board, storage chips 13 on different communication channels can be packaged on different storage circuit boards, or storage chips 13 on multiple communication channels can be packaged on the same storage circuit board. Taking a die-on-board (DOB) storage circuit board as an example, as shown in Figure 3, storage chips 13 on two communication channels are packaged into the same DOB. Here, DOB refers to a packaging form in which bare dies are directly placed on a functional printed circuit board or substrate-like PCB (SLP).

[0202] The storage medium controller 11 can be packaged on a separate circuit board, which is called the storage medium control board. The channel interface circuit 15 connected to the storage medium controller 11 can also be packaged on the storage medium control board. Each selection circuit 12 can be packaged on a separate circuit board, which is called the selection circuit board. That is, there are N selection circuit boards in the storage driver 100, and these N selection circuit boards, the storage medium control board, and the storage circuit boards are different circuit boards. In some embodiments, the N selection circuits 12 can also be packaged on the same circuit board as the storage medium controller 11 to form a new storage medium control board. Alternatively, the selection circuit 12 on the same communication channel and M memory chips 13 can be packaged on the same circuit board to form a new storage circuit board. For example, the storage driver 100 includes a storage medium control board and N storage circuit boards, each storage circuit board corresponding to a communication channel, and each storage circuit board including a selection circuit 12 and M memory chips 13.

[0203] In an exemplary embodiment, a storage medium controller is also provided, which is applied in any of the storage drives 100 described above. The storage medium controller includes a control chip for executing at least one piece of program code to implement the method steps performed by the storage medium controller 11 in the various method embodiments described above, thereby causing the storage medium controller to perform the method steps performed by the storage medium controller 11 in the various method embodiments described above.

[0204] The at least one piece of program code may be microcode, which can be stored in the cache of the control chip, so that the control chip reads and executes the at least one piece of program code from the cache to implement the method steps executed by the storage medium controller 11 in the above method embodiments.

[0205] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code, which can be executed by a control chip in the storage medium controller to complete the method steps performed by the storage medium controller 11 in the various method embodiments described above. This computer-readable storage medium is a non-transitory computer-readable storage medium, such as a read-only memory (ROM) or random access memory (RAM).

[0206] In an exemplary embodiment, a computer program product or computer program is also provided, which includes program code and computer instructions stored in a computer-readable storage medium. A control chip in the storage medium controller reads the program code from the computer-readable storage medium and executes the program code, causing the storage medium controller to perform the method steps performed by the storage medium controller 11 in the above-described method embodiments.

[0207] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0208] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0209] All information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the access instructions involved in this application were obtained under fully authorized conditions.

[0210] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0211] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data access method, characterized by, The method is applied to a storage drive, the storage drive including a storage medium controller, a first storage chip, and a second storage chip, each storage chip including interface circuitry and storage circuitry for recording data, the method comprising: The storage medium controller transmits a first access command to the first interface circuit to access the first storage chip, wherein the first interface circuit is located in the first storage chip and communicates with the storage medium controller. When the access instruction of the storage medium controller to access the storage chip is switched from the first access instruction to the second access instruction, the storage medium controller switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, wherein the second interface circuit is located in the second storage chip and communicates with the storage medium controller. Before accessing the second memory chip, the storage medium controller initializes the second interface circuit. After the initialization is completed, the storage medium controller transmits the second access command to the second interface circuit to access the second storage chip.

2. The method of claim 1, wherein, The storage driver also includes a selection circuit; The storage medium controller switches the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit, including: The storage medium controller sends a chip strobe signal to the selection circuit, and the chip strobe signal is used to trigger the selection circuit to switch the interface circuit for the storage medium controller to access the storage chip from the first interface circuit to the second interface circuit. The initialization of the second interface circuit by the storage medium controller includes: The storage medium controller sends an initialization signal to the second interface circuit through the selection circuit, the initialization signal indicating that the interface circuit should be initialized.

3. The method of claim 2, wherein, The method further includes: If the transmission delay of the chip strobe signal in the selection circuit is greater than the transmission delay of the initialization signal in the selection circuit, the storage medium controller sends the chip strobe signal to the selection circuit, and after a first duration, sends the initialization signal to the selection circuit again. The first duration is the difference between the transmission delays of the chip strobe signal and the initialization signal in the selection circuit; or... If the transmission delay of the chip strobe signal in the selection circuit is less than the transmission delay of the initialization signal in the selection circuit, the storage medium controller sends the initialization signal to the selection circuit, and after the first duration, sends the chip strobe signal to the selection circuit again.

4. The method according to any one of claims 1-3, characterized in that, The initialization of the second interface circuit includes any of the following: Perform a reset operation on the second interface circuit to set it to the initialization state; or, Perform pseudo-read / write operations on the second memory chip to restore the second interface circuit to its initial state; or, A read operation is performed on the second memory chip to restore the second interface circuit to its initial state.

5. The method according to any one of claims 1-4, characterized in that, The storage driver also includes a selection circuit; Before the storage medium controller transmits the second access instruction to the second interface circuit, the method further includes: The storage medium controller sends a chip strobe signal and an access signal to the selection circuit. The chip strobe signal is used to trigger the selection circuit to transmit the access signal to the second interface circuit. The access signal is used to carry the second access instruction.

6. The method of claim 5, wherein, The storage medium controller sends chip strobe signals and access signals to the selection circuit, including: If the transmission delay of the chip strobe signal in the selection circuit is greater than the transmission delay of the access signal in the selection circuit, the storage medium controller sends the chip strobe signal to the selection circuit, and after a second time interval, sends the access signal to the selection circuit again. The second time interval is the difference between the transmission delays of the chip strobe signal and the access signal in the selection circuit; or... If the transmission delay of the chip strobe signal in the selection circuit is less than the transmission delay of the access signal in the selection circuit, the storage medium controller sends the access signal to the selection circuit, and after the second duration, sends the chip strobe signal to the selection circuit again.

7. The method of claim 1, wherein, After the first access instruction is fully transmitted to the first interface circuit, the storage medium controller then performs the step of switching the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit.

8. The method according to any one of claims 1-7, characterized in that, After the storage medium controller transmits the second access command to the second interface circuit, the method further includes: When the access instruction of the storage medium controller to access the storage chip is switched from the second access instruction to the first access instruction, the storage medium controller switches the interface circuit for accessing the storage chip from the second interface circuit to the first interface circuit. Before accessing the first memory chip, the storage medium controller initializes the first interface circuit. After the initialization is completed, the storage medium controller transmits the first access command to the first interface circuit to access the first storage chip.

9. A storage drive, comprising: The storage drive includes: The first memory chip includes a first interface circuit, a first control circuit, and a storage circuit for recording data. The second storage chip includes a second interface circuit, a second control circuit, and a storage circuit for recording data. A storage medium controller is used to transmit a first access command to the first interface circuit to access the first storage chip; The storage medium controller is further configured to switch the interface circuit for accessing the storage chip from the first interface circuit to the second interface circuit when the access instruction for accessing the storage chip by the storage medium controller is switched from the first access instruction to the second access instruction. The storage medium controller is further configured to transmit an initialization signal to the second interface circuit before accessing the second storage chip, the initialization signal indicating that the interface circuit in the storage chip is initialized; The second control circuit is used to initialize the second interface circuit based on the initialization signal; The storage medium controller is further configured to transmit the second access instruction to the second interface circuit after the initialization is completed, so as to access the second storage chip.

10. The storage drive of claim 9, wherein, The initialization of the second interface circuit is used for any of the following: Perform a reset operation on the second interface circuit to set it to the initialization state; or, Perform pseudo-read / write operations on the second memory chip to restore the second interface circuit to its initial state; or, A read operation is performed on the second memory chip to restore the second interface circuit to its initial state.

11. A storage media controller, characterized by, The storage medium controller is used for: A first access command is transmitted to a first interface circuit to access a first memory chip, wherein the first interface circuit is located in the first memory chip and communicates with the storage medium controller, and the first memory chip further includes a storage circuit for recording data. When the access instruction of the storage medium controller to access the storage chip is switched from the first access instruction to the second access instruction, the interface circuit of the storage medium controller to access the storage chip is switched from the first interface circuit to the second interface circuit. The second interface circuit is located in the second storage chip and communicates with the storage medium controller. The second storage chip also includes a storage circuit for recording data. The second interface circuit is initialized before accessing the second memory chip; After the initialization is completed, the second access command is transmitted to the second interface circuit to access the second memory chip.

12. The storage media controller of claim 11, wherein, The initialization of the second interface circuit includes any of the following: Perform a reset operation on the second interface circuit to set it to the initialization state; or, Perform pseudo-read / write operations on the second memory chip to restore the second interface circuit to its initial state; or, A read operation is performed on the second memory chip to restore the second interface circuit to its initial state.

13. A storage media controller, characterized by The storage medium controller includes: The selection circuit provides a connection between the control chip and the first interface circuit in the first memory chip and the second interface circuit in the second memory chip. The first memory chip and the second memory chip also include a storage circuit for recording data. The control chip is used to send a first access command to the selection circuit; The selection circuit is used to transmit the first access instruction to the first interface circuit to access the first memory chip. The control chip is also used to send a chip strobe signal to the selection circuit when the access instruction of the storage medium controller to access the storage chip is switched from the first access instruction to the second access instruction. The chip strobe signal indicates that the second storage chip is selected and turned on from the multiple connected storage chips. The selection circuit is also used to switch the interface circuit for the storage medium controller to access the storage chip from the first interface circuit to the second interface circuit based on the chip selection signal. The control chip is further configured to initialize the second interface circuit through the selection circuit before accessing the second memory chip, and after the initialization is completed, transmit the second access command to the second interface circuit to access the second memory chip.

14. The storage media controller of claim 13, wherein, The initialization of the second interface circuit includes any of the following: Perform a reset operation on the second interface circuit to set it to the initialization state; or, Perform pseudo-read / write operations on the second memory chip to restore the second interface circuit to its initial state; or, A read operation is performed on the second memory chip to restore the second interface circuit to its initial state.

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