Time-division concurrency method, apparatus, computer device, storage medium, and computer program product

Abstract

The present application provides a time-division concurrency method, an apparatus, a computer device, a storage medium, and a computer program product. The method comprises: sending a chip select signal to target slave devices in a single-wire receiving mode, and switching the target slave devices to a bidirectional mode; acquiring target driving rates of the target slave devices; determining an actual distribution rate on the basis of the target driving rates of the target slave devices and the number of the target slave devices; and sequentially sending data frames to corresponding target slave devices on the basis of the actual distribution rate, so as to complete parallel driving of pixel chips corresponding to the target slave devices. In the present application, a master device having an MCU chip select function is used to implement bidirectional communication with slave devices, so as to work in conjunction with the slave devices to complete switching between a single-wire receiving mode configuration function and a bidirectional mode configuration function, thereby implementing concurrent communication of data streams.

Description

Time-sharing concurrency methods, devices, computer equipment, storage media, and computer program products

[0001] This application claims priority to Chinese Patent Application No. 202411648840.9, filed on November 18, 2024, entitled "Time-sharing Concurrency Method, Apparatus, Computer Equipment and Storage Medium", the contents of which are incorporated herein by reference in part. Technical Field

[0002] This application relates to the field of multi-channel concurrent communication technology, and in particular to a time-sharing concurrent method, apparatus, computer equipment, storage medium and computer program product. Background Technology

[0003] A surface light source lamp composed of multiple pixel point light sources can display colored patterns and animations. In order to display the image clearly, a sufficient number of controllable light sources are needed to realize the pixel pattern.

[0004] As multi-pixel light curtains gradually move from outdoor to indoor lighting, more refined application functions are needed. MCUs, with their richer hardware peripherals, lower power consumption, and lower cost, can well meet these business requirements. However, MCUs typically have limited cores, usually single-core or dual-core, and cannot directly implement multi-channel concurrent operations. Summary of the Invention

[0005] This application proposes a time-sharing concurrency method, apparatus, computer device, storage medium, and computer program product. It uses a master device with MCU chip select function to realize bidirectional communication with a slave device, thereby enabling the slave device to switch between single-line reception and bidirectional mode configuration functions to achieve concurrent communication of data streams.

[0006] On the one hand, embodiments of this application provide a time-sharing concurrency method, including:

[0007] Send a chip select signal to the target slave device in single-wire receive mode to switch the target slave device to bidirectional mode;

[0008] Obtain the target drive rate of the target slave device;

[0009] The actual distribution rate is determined based on the target drive rate of the target slave device and the number of the target slave devices;

[0010] Based on the actual distribution rate, data frames are sequentially sent to the corresponding target slave devices to complete the parallel driving of the pixel chips corresponding to the target slave devices.

[0011] In one possible implementation, the control method is applied to a time-sharing concurrent system, including a master device and multiple groups of slave devices, wherein the master device connects to the corresponding groups of slave devices by controlling multiple groups of peripheral buses.

[0012] In one possible implementation, the master device has at least a first DMA controller, and the slave device has at least a second DMA controller and a third DMA controller. The step of sending a chip select signal to the target slave device in single-wire receive mode to switch the target slave device to bidirectional mode includes:

[0013] Obtain the target device's address information;

[0014] Based on the address information, a communication connection is established between the master device and the target slave device through the first DMA controller and the second DMA controller to receive the response signal from the target slave device.

[0015] In one possible implementation, the parallel driving of the pixel chip corresponding to the target slave device includes:

[0016] Under the condition that the target switches from device to bidirectional mode,

[0017] The third DMA controller establishes a single-line communication between the target slave device and its corresponding pixel chip to enable parallel driving of multiple pixel chips.

[0018] In one possible implementation, the central controller of the slave device is configured with at least a synchronous communication peripheral channel and an asynchronous communication peripheral channel, and the central controller switches the corresponding channels through the third DMA controller to complete the driving process of pixel chips with different requirements.

[0019] In one possible implementation, determining the actual distribution rate based on the target drive rate of the target slave device and the number of the target slave devices includes:

[0020] The actual distribution rate after rate boosting is obtained by multiplying the target drive rate of the target slave device by the number of target slave devices.

[0021] In one possible implementation, the step of sequentially sending data frames to the corresponding target slave devices based on the actual distribution rate includes:

[0022] Data frames are sent sequentially to different target slave devices based on the interval time corresponding to the actual distribution rate.

[0023] The data frames are processed concurrently by all the target slave devices within the time period corresponding to the target drive rate.

[0024] On one hand, embodiments of this application provide a time-sharing concurrency device, including:

[0025] Processing unit: used to send a chip select signal to the target slave device in single-wire receive mode and switch the target slave device to bidirectional mode;

[0026] Acquisition unit: used to acquire the target drive rate of the target slave device;

[0027] The actual distribution rate is determined based on the target drive rate of the target slave device and the number of the target slave devices;

[0028] The processing unit is further configured to sequentially send data frames to the corresponding target slave devices based on the actual distribution rate, thereby completing the parallel driving of the pixel chip corresponding to the target slave device.

[0029] On one hand, embodiments of this application provide a computer device, including: a storage device and a processor;

[0030] A memory, wherein one or more computer programs are stored;

[0031] A processor is used to load one or more computer programs to implement the time-sharing concurrency method described above.

[0032] On one hand, embodiments of this application provide a computer-readable storage medium storing a computer program adapted to be loaded by a processor and executed as described above for time-sharing concurrency.

[0033] On one hand, embodiments of this application provide a computer program product, including computer instructions stored in a computer-readable storage medium. The processor of a computer device reads and executes the computer instructions from the computer-readable storage medium, enabling the computer device to execute the aforementioned time-sharing concurrency method.

[0034] In this embodiment, a chip select signal is first sent to the target slave device in single-line receiving mode to switch the target slave device to bidirectional mode; then, the target drive rate of the target slave device is obtained; and the actual distribution rate is determined based on the target drive rate of the target slave device and the number of target slave devices; finally, data frames are sequentially sent to the corresponding target slave devices based on the actual distribution rate to complete the parallel driving of the pixel chip corresponding to the target slave device. Thus, the MCU of the master device in this application is configured with a DMA-enabled communication peripheral channel, and the SCU of the slave device has at least two DMA-enabled communication peripheral channels. One side of the SCU is used to cooperate with the MCU to configure the chip select mode corresponding to the DMA function, realizing high-speed communication between the master device and multiple slave devices, and the other side of the SCU with a DMA-enabled communication peripheral channel realizes time-division concurrent data flow. Attached Figure Description

[0035] To more clearly illustrate the technical solutions and advantages in the embodiments or conventional technologies of this specification, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 is a flowchart illustrating a time-sharing concurrency method provided in an embodiment of this specification;

[0037] Figure 2 is an architecture diagram of the time-sharing concurrent system provided in the embodiments of this specification;

[0038] Figure 3 is a schematic diagram of the communication method of the time-sharing concurrent system provided in the embodiments of this specification;

[0039] Figure 4 is a schematic diagram illustrating the principle of demand-driven rate implementation using a time-sharing concurrency approach provided in the embodiments of this specification;

[0040] Figure 5 is a schematic diagram of the communication connection between the master MCU and the slave SCU provided in the embodiments of this specification;

[0041] Figure 6 is a schematic diagram of the communication process between the master MCU and the slave SCU provided in the embodiment of this specification;

[0042] Figure 7 is a schematic diagram of a time-sharing concurrent device provided in an embodiment of this specification. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0044] As shown in Figure 1, this application provides a time-sharing concurrency method, including:

[0045] S100: Send a chip select signal to the target slave device in single-wire receiving mode to switch the target slave device to bidirectional mode;

[0046] It should be noted that in traditional technology, the method of implementing multi-pixel concurrent control through FPGA is both costly and power-consuming. Using MCU to implement multi-channel concurrent services can solve the above problems, but MCU cores are usually limited, generally single-core or dual-core, and cannot directly implement multi-channel concurrent services.

[0047] The control method in this application is based on a time-sharing concurrent system. The system includes a master device and multiple groups of slave devices. The master device connects to its corresponding group of slave devices through multiple peripheral buses, thereby realizing multi-channel concurrent communication through the MCU. This enables high-speed data refresh and ensures the smoothness of pixel patterns or animations.

[0048] Specifically, the system includes the following components:

[0049] The main MCU has at least one DMA-enabled SPI communication peripheral, enabling high-speed SPI communication with multiple sub-SCUs. The main MCU has a first DMA controller and its corresponding SPI communication peripheral.

[0050] As shown in Figure 2, in this embodiment, the main MCU is equipped with two sets of first DMA controllers and two sets of corresponding SPI communication peripherals. The main MCU realizes the sorting function of the two sets of SPI communication peripherals to the external sub-SCU through the corresponding first DMA controllers and their matching SPI communication peripherals.

[0051] Each sub-SCU has at least two DMA-enabled SPI communication peripherals. One SPI communication peripheral can achieve SPI communication at the same rate as the master MCU, and the other SPI communication peripheral is used to simultaneously drive single-wire communication pixel chips. The slave device has at least a second DMA controller and a third DMA controller, each with its corresponding SPI communication peripheral.

[0052] In the embodiments of this application, the third DMA controller is also configured with a UART communication peripheral, which can switch between the corresponding SPI communication peripheral or UART communication peripheral according to the different required rates of driving different types of pixel chips.

[0053] In one implementation, step S100, sending a chip select signal to a target slave device in single-wire receive mode to switch the target slave device to bidirectional mode, includes:

[0054] Obtain the target device's address information;

[0055] Based on the address information, a communication connection is established between the master device and the target slave device through the first DMA controller and the second DMA controller to receive the response signal from the target slave device.

[0056] Specifically, the sub-SCU can switch between MISO and MOSI functions to change the communication method between the sub-SCU and the main MCU, as shown in Figures 3 and 6. The communication process is as follows:

[0057] When the master device pre-sends target data to the target slave device, it sends a chip select signal to enable the target slave device, and other slave devices that also have corresponding configurations with the master device switch to the off state at a preset time point;

[0058] After receiving the chip select signal from the device, the target switches from one-way receive mode to two-way receive mode.

[0059] The master device sends target data to the target slave device;

[0060] After receiving the target data from the device, it sends a response signal;

[0061] After receiving the response signal, the master device sends a shutdown signal;

[0062] When the target receives a shutdown signal from the device, it changes its bidirectional mode to unidirectional reception mode.

[0063] S200: Obtain the target drive rate of the target slave device;

[0064] S300: Determine the actual distribution rate based on the target drive rate of the target slave device and the number of the target slave devices;

[0065] In one implementation, step S300, determining the actual distribution rate based on the target drive rate of the target slave device and the number of target slave devices, includes:

[0066] The actual distribution rate after rate boosting is obtained by multiplying the target drive rate of the target slave device by the number of target slave devices.

[0067] Specifically, the time-sharing concurrency principle in this application is illustrated by the following example:

[0068] When driving a pixel chip with a rate of 800Kbps, assuming the data stream transmission time is T1, when driving n such chips, since the CPU can only execute sequentially, it theoretically takes T1*n time. This results in an overall actual rate of 800kbps / n, which does not actually achieve a lossless pixel refresh effect.

[0069] To achieve lossless refresh of multiple pixel chips simultaneously, an FPGA is typically used, which is equivalent to multiple CPUs executing outputs at the same time.

[0070] This application achieves time-sharing concurrency by increasing the overall data transmission rate to 800kbps*n while maintaining the overall data transmission time at T1, thereby using DMA+SPI peripherals.

[0071] In other words, since a large amount of data needs to be transmitted, if peripherals are not used, the CPU will always be involved in the transmission process. A large number of interrupt operations will cause a heavy CPU load and cannot guarantee the correctness of data frame transmission.

[0072] Meanwhile, in specific application scenarios, the MCU also has the development capabilities for protocols such as WIFI and Bluetooth, making it more suitable for application in the smart home field compared to FPGA. S400: Based on the actual distribution rate, data frames are sequentially sent to the corresponding target slave devices to complete the parallel driving of the pixel chips corresponding to the target slave devices.

[0073] In one implementation, sending data frames sequentially to the corresponding target slave devices based on the actual distribution rate includes:

[0074] Data frames are sent sequentially to different target slave devices based on the interval time corresponding to the actual distribution rate.

[0075] The data frames are processed concurrently by all the target slave devices within the time period corresponding to the target drive rate.

[0076] In one implementation, parallel driving of the pixel chip corresponding to the target slave device includes:

[0077] Under the condition that the target switches from device to bidirectional mode,

[0078] The third DMA controller establishes a single-line communication between the target slave device and its corresponding pixel chip to enable parallel driving of multiple pixel chips.

[0079] In this application, the sub-SCU has two DMA-enabled SPI communication peripherals, which enable the sub-SCU to achieve SPI communication at the same rate as the main MCU through one SPI communication peripheral, while driving the pixel chip with a single-wire communication connection through the other SPI communication peripheral, thereby driving the pixel chip to refresh the current pixel display at a matching rate.

[0080] In one implementation, the central controller of the device is configured with at least a synchronous communication peripheral channel and an asynchronous communication peripheral channel. The central controller switches the corresponding channels through the third DMA controller to complete the driving process of pixel chips with different requirements.

[0081] Specifically, the third DMA controller of the sub-SCU is configured with switchable SPI peripheral interface and UART peripheral interface, determined according to the interface of the load such as the pixel chip. In some other embodiments, the implementation of the sub-SCU with a peripheral interface having the corresponding communication method is selected according to the type of load interface, all of which are within the protection scope of this application.

[0082] With a DMA controller configured, peripherals can send DMA requests to the CPU through the DMA controller. After the CPU responds to these requests, the DMA controller takes over the control of the bus and directly transfers data between memory and I / O devices, reducing CPU intervention and improving data transfer efficiency.

[0083] Referring to Figure 7, which is a schematic diagram of a time-sharing concurrency device provided in an embodiment of this application, the time-sharing concurrency device 700 may specifically include:

[0084] Processing unit 701: Used to send a chip select signal to a target slave device in single-wire receive mode, and switch the target slave device to bidirectional mode;

[0085] Acquisition unit 702: used to acquire the target drive rate of the target slave device;

[0086] The actual distribution rate is determined based on the target drive rate of the target slave device and the number of the target slave devices;

[0087] The processing unit 701 is further configured to send data frames sequentially to the corresponding target slave devices based on the actual distribution rate, thereby completing the parallel driving of the pixel chip corresponding to the target slave device.

[0088] An embodiment of this application provides a computer device, including: a storage device and a processor;

[0089] A memory, wherein one or more computer programs are stored;

[0090] A processor is used to load one or more computer programs to implement the multi-channel pixel time-division concurrent control method in this application.

[0091] Furthermore, it should be noted that this application embodiment also provides a computer storage medium, which stores a computer program, and the computer program includes program instructions. When the processor executes the above program instructions, it can execute the methods in the corresponding embodiments described above. Therefore, it will not be described again here.

[0092] For technical details not disclosed in the embodiments of the computer storage medium involved in this application, please refer to the description of the method embodiments of this application. As an example, program instructions may be deployed on a computer device, or executed on multiple computer devices located in one location, or executed on multiple computer devices distributed in multiple locations and interconnected through a communication network.

[0093] According to one aspect of this application, embodiments of this application also provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, enabling the computer device to perform the methods described in the preceding embodiments; therefore, further details will not be provided here.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data processing device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0096] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A time-division concurrency method, wherein, include: Send a chip select signal to the target slave device in single-wire receive mode to switch the target slave device to bidirectional mode; Obtain the target drive rate of the target slave device; The actual distribution rate is determined based on the target drive rate of the target slave device and the number of the target slave devices; Based on the actual distribution rate, data frames are sequentially sent to the corresponding target slave devices to complete the parallel driving of the pixel chips corresponding to the target slave devices.

2. The time-division concurrency method of claim 1, wherein, The control method is applied to a time-sharing concurrent system, which includes a master device and multiple groups of slave devices. The master device connects to the corresponding groups of slave devices by controlling multiple peripheral buses.

3. The time-division concurrency method of claim 2, wherein, The master device is provided with at least a first DMA controller, and the slave device is provided with at least a second DMA controller and a third DMA controller. The step of sending a chip select signal to the target slave device in single-wire receive mode to switch the target slave device to bidirectional mode includes: Obtain the target device's address information; Based on the address information, a communication connection is established between the master device and the target slave device through the first DMA controller and the second DMA controller to receive the response signal from the target slave device.

4. The time-division concurrency method of claim 3, wherein, The parallel driving of the pixel chip corresponding to the target slave device includes: Under the condition that the target switches from device to bidirectional mode, The third DMA controller establishes a single-line communication between the target slave device and its corresponding pixel chip to enable parallel driving of multiple pixel chips.

5. The time-division concurrency method of claim 4, wherein, The central controller of the slave device is configured with at least synchronous communication peripheral channels and asynchronous communication peripheral channels. The central controller switches the corresponding channels through the third DMA controller to complete the driving process of pixel chips with different requirements.

6. The time-sliced concurrency method of claim 1, wherein, The step of determining the actual distribution rate based on the target drive rate of the target slave device and the number of target slave devices includes: The actual distribution rate after rate boosting is obtained by multiplying the target drive rate of the target slave device by the number of target slave devices.

7. The time-division concurrency method of claim 6, wherein, The step of sequentially sending data frames to the corresponding target slave devices based on the actual distribution rate includes: Data frames are sent sequentially to different target slave devices based on the interval time corresponding to the actual distribution rate. The data frames are processed concurrently by all the target slave devices within the time period corresponding to the target drive rate.

8. A time-division concurrency apparatus, wherein, include: Processing unit: used to send a chip select signal to the target slave device in single-wire receive mode and switch the target slave device to bidirectional mode; Acquisition unit: used to acquire the target drive rate of the target slave device; The actual distribution rate is determined based on the target drive rate of the target slave device and the number of the target slave devices; The processing unit is further configured to sequentially send data frames to the corresponding target slave devices based on the actual distribution rate, thereby completing the parallel driving of the pixel chip corresponding to the target slave device.

9. A computer device, wherein, include: Storage devices and processors; A memory, wherein one or more computer programs are stored; A processor for loading one or more computer programs to implement the time-sharing concurrency method as described in any one of claims 1-7.

10. A computer readable storage medium, wherein, The computer readable storage medium stores a computer program, and the computer program is suitable for being loaded and executed by the processor to perform the time-sharing concurrent method according to any one of claims 1-7.

11. A computer program product, wherein, The computer readable storage medium stores computer instructions, and the processor of the computer device reads the computer instructions from the computer readable storage medium and executes, so that the computer device can perform the time-sharing concurrent method according to any one of claims 1-7.

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