Apparatus and method for communication having read address offset
By configuring the register address offset and response range for the MIPI module, the readback contention problem among multiple modules on the MIPI bus is resolved, improving communication efficiency and testing convenience.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SHANGHAI VANCHIP ELECTRONICS TECH CO LTD
- Filing Date
- 2025-11-04
- Publication Date
- 2026-05-28
AI Technical Summary
Under the same MIPI bus and USID, multiple MIPI modules compete for bus access, resulting in readback contention, which leads to wasted readback functionality and low communication efficiency.
By configuring register address bias and register address response range for each sub-chip, the register address access ranges of each sub-chip do not conflict with each other. When the MIPI master chip sends a MIPI read instruction, the sub-chip determines whether to respond based on the register address information, bias, and response range, and controls the bus to output the value of the corresponding register.
This solves the readback contention problem of multiple MIPI modules under the same MIPI bus and USID, reduces communication time, retains the readback capability of each sub-chip, and facilitates comprehensive testing and debugging.
Smart Images
Figure CN2025132370_28052026_PF_FP_ABST
Abstract
Description
Communication device and method with read address bias Technical Field
[0001] This invention relates to the field of MIPI communication technology, and in particular to a communication device and method with read address bias. Background Technology
[0002] Currently, RFFE (RF Front End Interface) chips are becoming increasingly integrated, with a single USID (Unique Slave ID, a unique ID number for each RFFE sub-chip on the same MIPI bus) often encompassing multiple RFFE functional components. However, during chip design, for placement and routing or die reuse considerations, logic circuits may be distributed across different chips, each with complete MIPI functionality. This improves communication speed and makes testing easier and more comprehensive. However, MIPI is a half-duplex protocol with readback functionality. In scenarios where multiple MIPI modules reside on the same MIPI bus and USID, bus preemption during readback can occur. For scenarios with multiple MIPI modules sharing the same USID on a single bus, related technologies typically only retain the readback capability of the master module, disabling or eliminating the readback capability of sub-modules via GPIO, resulting in wasted readback functionality for the sub-modules.
[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to address the technical problem in the prior art where multiple MIPI modules under the same MIPI bus and USID compete for the MIPI bus during readback, resulting in bus contention. This invention provides a communication device and method with read address bias. This invention can effectively solve the readback contention problem of multiple MIPI modules under the same MIPI bus and USID, and can effectively preserve the readback capability of each sub-chip while reducing communication time, making it easier for comprehensive testing and debugging.
[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: a communication device with read address bias, comprising a MIPI master control chip and at least two sub-chips connected to the MIPI master control chip via a bus, each of the sub-chips being provided with a MIPI module, and each of the MIPI modules of the sub-chips on the same bus being configured with a register address bias and a register address response range, so that the register address access ranges of the sub-chips connected to the same bus do not conflict with each other;
[0006] The MIPI master control chip is configured to send a MIPI read instruction to the MIPI module, the MIPI read instruction including register address information;
[0007] The MIPI module is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range. If so, it controls the bus and outputs the value of the corresponding register.
[0008] Optionally, the sub-chips connected on the same bus are connected in parallel.
[0009] Optionally, the register address access ranges of the various sub-chips connected on the same bus do not conflict with each other, including:
[0010] The address space formed by the register address access ranges of all the sub-chips connected to the same bus is contiguous relative to the MIPI master control chip.
[0011] Optionally, the bus includes clock signal lines and data signal lines;
[0012] The MIPI module includes a main logic control unit and a cache unit. The main logic control unit and the cache unit are connected through a first internal signal line, a second internal signal line, and a third internal signal line. The main logic control unit is connected to the MIPI master control chip through the clock signal line, and the cache unit is connected to the MIPI master control chip through the data signal line.
[0013] When the signal on the first internal signal line is low, the MIPI module operates in the instruction receiving state. At this time, the buffer unit is configured to receive the MIPI read instruction sent by the MIPI master control chip, and send the MIPI read instruction to the main logic control unit through the second internal signal line. The main logic control unit is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address bias, and the register address response range. If so, the signal on the first internal signal line is set to high, so that the MIPI module operates in the data readback state.
[0014] When the MIPI module is operating in the data readback state, the main logic control unit is configured to send the value of the corresponding register to the cache unit through the third internal signal line; the cache unit is configured to operate in the push-pull output state to send the value of the corresponding register to the MIPI master control chip; the main logic control unit is also used to set the signal on the first internal signal line to a low level after not responding to the MIPI read instruction or after completing the MIPI read instruction, so that the MIPI module operates in the instruction receiving state.
[0015] Optionally, the register address information includes the register start address and the number of readback registers. The MIPI module is configured to: calculate the current internal read address based on the register start address, the number of readback registers, the register address offset, and the current readback count; and determine whether the current internal read address is within the register address response range. If so, control the bus and output the value of the register corresponding to the current internal read address.
[0016] Optionally, the MIPI module is configured to determine whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip. If so, it determines whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range.
[0017] Optionally, the MIPI module is configured to, after determining whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range, further include: determining whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip; if so, responding to the MIPI read instruction.
[0018] Optionally, the sub-chip includes an RF front-end interface chip.
[0019] To achieve the above objectives, the present invention also provides a communication method for the communication apparatus with read address bias described in any of the preceding claims, the communication method comprising:
[0020] The MIPI master control chip sends a MIPI read instruction to the MIPI module, and the MIPI read instruction includes register address information.
[0021] The MIPI module determines whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range. If so, it controls the bus and outputs the value of the corresponding register.
[0022] Optionally, the communication method further includes:
[0023] Update the register address bias and / or the register address response range online.
[0024] Compared with the prior art, the communication device and method with read address bias provided by the present invention have the following advantages:
[0025] The present invention provides a communication device with read address bias, comprising a MIPI master control chip and at least two sub-chips connected to the MIPI master control chip via a bus. Each sub-chip is equipped with a MIPI module. The MIPI modules of each sub-chip on the same bus are configured with a register address bias and a register address response range, so that the register address access ranges of the sub-chips connected to the same bus do not conflict with each other. The MIPI master control chip is configured to send a MIPI read instruction to the MIPI module, the MIPI read instruction including register address information. The MIPI module is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address bias, and the register address response range. If so, it controls the bus and outputs the value of the corresponding register. Therefore, the communication device with read address bias provided by the present invention has a register address bias and a register address response range configured on the MIPI modules of each sub-chip connected to the same bus, and can ensure that the register address access ranges of each sub-chip connected to the same bus do not conflict with each other. Thus, it can effectively solve the readback contention problem of multiple MIPI modules under the same MIPI bus and USID, and can effectively preserve the readback capability of each sub-chip while reducing communication time, making it easier to conduct comprehensive testing and debugging.
[0026] Since the communication method provided by this invention belongs to the same inventive concept as the communication device with read address bias provided by this invention, the communication method provided by this invention has at least all the advantages of the communication device with read address bias provided by this invention. For details on the beneficial effects of the communication method provided by this invention, please refer to the above description of the beneficial effects of the communication device with read address bias provided by this invention, which will not be repeated here. Attached Figure Description
[0027] Figure 1 is a schematic diagram of the overall structure of the communication device with read address bias provided in Embodiment 1 of the present invention;
[0028] Figure 2 is a schematic diagram of the first application scenario of the communication device with read address bias provided by the present invention;
[0029] Figure 3 is a schematic diagram of a second application scenario of the communication device with read address bias provided by the present invention;
[0030] Figure 4 is a schematic diagram of the structure of the MIPI module of the communication device with read address bias provided by the present invention;
[0031] Figure 5 is a timing example diagram of the communication device with read address bias provided by the present invention when executing the MIPI read instruction;
[0032] Figure 6 is a timing example diagram of the communication device with read address bias provided by the present invention when executing the MIPI read instruction;
[0033] Figure 7 is a flowchart illustrating the execution of MIPI write instructions by the MIPI module of the communication device with read address bias provided by the present invention.
[0034] Figure 8 is a schematic diagram of the overall flow of the communication method provided in Embodiment 2 of the present invention;
[0035] The reference numerals in the attached diagram are as follows: MIPI main control chip - 100; sub-chips - 210, 220, 230, 240, 250; MIPI modules - 211, 221, 231, 241, 251; main logic control unit - 2111, cache unit - 2112; clock signal lines - SCLK, SCLK1, SCLK2; data signal lines - SDATA, SDATA1, SDATA2; first internal signal line - SDATA_OEN, second internal signal line - SDATA_I, third internal signal line - SDATA_O. Detailed Implementation
[0036] The following detailed description, in conjunction with the accompanying drawings, provides a further detailed account of the communication device and method with read address bias proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read the content disclosed in the specification. They are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same objectives as this invention, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it need not be discussed further in subsequent figures. Furthermore, if the methods described herein involve a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, some of the described steps may be omitted and / or other steps not described herein may be added to the method.
[0037] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.
[0038] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.
[0039] The core idea of this invention is to provide a communication device and method with read address bias. This invention can effectively solve the readback contention problem of multiple MIPI modules under the same MIPI bus and USID. It can reduce communication time while well preserving the readback capability of each sub-chip, and is more convenient for comprehensive testing and debugging.
[0040] Example 1
[0041] To achieve the above-mentioned idea, this embodiment provides a communication device with read address bias. For example, please refer to Figure 1, which is a schematic diagram of the overall structure of the communication device with read address bias provided in Embodiment 1 of the present invention. As can be seen from Figure 1, the communication device with read address bias provided in this embodiment includes a MIPI master control chip 100 and at least two sub-chips (three sub-chips 210, 220, and 230 are shown in Figure 1) connected to the MIPI master control chip 100 via a bus. Each of the sub-chips 210, 220, and 230 is respectively provided with MIPI modules 211, 221, and 231. The MIPI modules 211, 221, and 231 of each of the sub-chips 210, 220, and 230 on the same bus are configured with register address bias and register address response range, so that the register address access ranges of the sub-chips 210, 220, and 230 connected to the same bus do not conflict with each other. Specifically, the MIPI master control chip 100 is configured to send MIPI read instructions to the MIPI modules 211, 221 and 231, the MIPI read instructions including register address information; the MIPI modules 211, 221 and 231 are configured to determine whether to respond to the MIPI read instructions based on the register address information, the register address offset and the register address response range, and if so, control the bus and output the value of the corresponding register.
[0042] Therefore, the communication device with read address bias provided by the present invention has register address bias and register address response range configured on the MIPI modules 211, 221 and 231 of each of the sub-chips 210, 220 and 230 connected to the same bus, and can ensure that the register address access ranges of each of the sub-chips 210, 220 and 230 connected to the same bus do not conflict with each other. Thus, it can effectively solve the readback contention problem of multiple MIPI modules 211, 221 and 231 under the same MIPI bus and USID, and can effectively preserve the readback capability of each sub-chip 210, 221 and 230 while reducing communication time, making it easier for comprehensive testing and debugging.
[0043] It should be noted that, as those skilled in the art will understand, the MIPI modules 211, 221, and 231, in addition to the functions described herein, also possess all the functions required by the MIPI protocol. Furthermore, the MIPI read instruction in this document is a register read instruction. For more detailed information on MIPI instructions and the MIPI protocol, please refer to relevant materials known to those skilled in the art; due to space limitations, this document will not elaborate on them. Additionally, it should be understood that the fact that the three sub-chips 210, 220, and 230 are located on the same bus is merely illustrative and not a limitation of the invention; the invention does not limit the number of sub-chips.
[0044] For example, unless otherwise specified, the sub-chips 210, 220, and 230 in the various embodiments herein are assumed to be radio frequency front-end interface chips. However, it is obvious to those skilled in the art that the present invention does not impose excessive limitations on the specific types of the sub-chips 210, 220, and 230. The sub-chips 210, 220, and 230 can also be chips other than radio frequency front-end interface chips. For example, the sub-chips 210, 220, and 230 can be, but are not limited to, video decoding chips, display interface chips, and common-mode filter chips. Further, the bus is a MIPI bus, and the MIPI master control chip 100 is a device that controls the system MIPI signal bus. The present invention does not impose excessive limitations on the MIPI master control chip 100. For example, the MIPI master control chip 100 can be an RFIC (radio frequency integrated circuit) in a mobile phone system.
[0045] Preferably, in some exemplary embodiments, please continue to refer to FIG1, as can be seen from FIG1, the sub-chips 210, 220 and 230 connected on the same bus are connected in parallel. Thus, the present invention can not only effectively avoid excessive wiring, but also simplify the control complexity of communication and interaction between the MIPI modules 211, 221 and 231 and the respective sub-chips 210, 220 and 230.
[0046] It should be understood that the communication device with read address bias provided by the present invention does not impose excessive limitations on its application scenarios. For example, in some embodiments, please refer to Figure 2, which is a schematic diagram of a first application scenario of the communication device with read address bias provided by the present invention. As can be seen from Figure 2, in this application scenario, multiple sub-chips 210, 220, and 230 located on the same bus can be integrated into the same highly integrated chip. Furthermore, in other embodiments, please refer to Figure 3, which is a schematic diagram of a second application scenario of the communication device with read address bias provided by the present invention. As can be seen from Figure 3, in this application scenario, multiple sub-chips 210, 220, and 230 located on the same bus can be integrated with multiple sub-chips 240 and 250 located on another bus into the same highly integrated chip, wherein sub-chip 210 is located on both buses.
[0047] Next, the MIPI modules 211, 221, and 231 of each of the sub-chips 210, 220, and 230 on the same bus are configured with register address bias and register address response range, so that the register address access ranges of each of the sub-chips 210, 220, and 230 connected to the same bus do not conflict with each other, as explained below:
[0048] First, the register address offset is the offset value of the address built into each of the MIPI modules 211, 221, and 231, and the register address offsets of each MIPI module 211, 221, and 231 located on the same bus are different. Second, the register address response range can be understood as the register addressing space of the sub-chips 210, 220, and 230 where the MIPI modules 211, 221, and 231 are located. Third, taking the sub-chip 210 in Figure 1 as an example, if its register address offset is a, and its internal read address addressing space is d to e, then relative to the MIPI master control chip 100, the register address access range of the sub-chip 210 is (a+d) to (a+e). When the MIPI module 211 receives the register address d in the MIPI read instruction, it calculates da to obtain the internal read address c, and then determines whether c is within its register address response range. That is, the MIPI module 211 will only respond to the MIPI read instruction if c ≥ d and c ≤ e (in other words, d ≥ (a + d) and d ≤ (a + e)). More specifically, taking Figure 1 as an example, if the register address offset of sub-chip 210 is 0x00 and the register address response range is 0x00 to 0x3F, in order to avoid the register address access range of sub-chips 220 and 230 conflicting with the register address access range of sub-chip 210, then the register address offset of sub-chip 220 should be greater than 0x3F. For example, the register address offset of sub-chip 220 is 0x40 and the register address response range is 0x00 to 0x3F. Similarly, the register address offset of sub-chip 230 should be greater than 0x7F. For example, the register address offset of sub-chip 230 is 0x8A and the register address response range is 0x0A to 0x3F. In this scenario, when the register address of the MIPI read command sent by the MIPI master control chip 100 is 0x00 to 0x3F, the MIPI module 211 of the sub-chip 210 will respond to the command; when the register address of the MIPI read command sent by the MIPI master control chip 100 is 0x40 to 0x7F, the MIPI module 221 of the sub-chip 220 will respond to the command; and when the register address of the MIPI read command sent by the MIPI master control chip 100 is 0x8A to 0xBF, the MIPI module 231 of the sub-chip 230 will respond to the command.
[0049] It should be understood that, for the various sub-chips 210, 220, and 230 located on the same bus, the present invention does not impose excessive limitations on their register address offsets and read address response ranges. The register address offsets and read address response ranges of the various sub-chips 210, 220, and 230 can be the same or different. However, the register address access ranges of the various sub-chips 210, 220, and 230 obtained from the register address offsets and read address response ranges must not conflict with each other. To ensure that the register address access ranges of the various sub-chips 210, 220, and 230 are unique relative to the MIPI master control chip 100, it is preferable that the register address offsets of the various sub-chips 210, 220, and 230 are different.
[0050] Preferably, in some exemplary embodiments, the register address access ranges of the various sub-chips 210, 220, and 230 connected on the same bus do not conflict with each other, including:
[0051] Relative to the MIPI master control chip 100, the address space formed by the register address access ranges of all the sub-chips 210, 220, and 230 connected to the same bus is contiguous. Therefore, the communication device with read address bias provided by this invention simplifies the readback control logic of the MIPI master control chip 100 and each MIPI module 211, 221, and 231.
[0052] For example, as illustrated above: sub-chip 210 has a register address bias of 0x00 and a register address response range of 0x00 to 0x3F; sub-chip 220 has a register address bias of 0x40 and a register address response range of 0x00 to 0x3F; and sub-chip 230 has a register address bias of 0x8A and a register address response range of 0x00 to 0x35. In this scenario, the address space formed by sub-chips 210 and 220 is contiguous, while the address space formed by sub-chips 220 and 230 is discontinuous. However, if the register address bias of sub-chip 230 is 0x80 and the register address response range is 0x00 to 0x3F, then the address space formed by sub-chips 210, 220, and 230 is contiguous.
[0053] Preferably, in some exemplary embodiments, please continue to refer to FIG1. As can be seen from FIG1, the bus includes a clock signal line SCLK and a data signal line SDATA, and the MIPI modules 211, 221 and 231 output the values of the corresponding registers through the data signal line SDATA.
[0054] Preferably, in some exemplary embodiments, please continue to refer to Figures 1 and 4, where Figure 4 is a structural schematic diagram of the MIPI module of the communication device with read address bias provided by the present invention. As can be seen from Figures 1 and 4, the bus includes a clock signal line SCLK and a data signal line SDATA. For ease of understanding and explanation, MIPI module 221 is used as an example here. The structures of MIPI module 221 and MIPI module 231 are similar to those of MIPI module 221, and will not be described in detail here. As can be seen from Figure 4, the MIPI module 211 includes a main logic control unit 2111 and a cache unit 2112. The main logic control unit 2111 and the cache unit 2112 are connected through a first internal signal line SDATA_OEN, a second internal signal line SDATA_I, and a third internal signal line SDATA_O. The main logic control unit 2111 is connected to the MIPI master control chip 100 through the clock signal line SCLK, and the cache unit 2112 is connected to the MIPI master control chip 100 through the data signal line SDATA.
[0055] Specifically, when the signal on the first internal signal line SDATA_OEN is low, the MIPI module 211 operates in the instruction receiving state (i.e., at this time, the port of the buffer unit 2112 connected to the data signal line SDATA is in a high-impedance state). At this time, the buffer unit 2112 is configured to receive the MIPI read instruction sent by the MIPI master control chip, and send the MIPI read instruction to the main logic control unit 2111 through the second internal signal line SDATA_I. The main logic control unit 2111 is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address bias, and the register address response range. If so, the signal on the first internal signal line SDATA_OEN is set to high, so that the MIPI module 211 operates in the data readback state.
[0056] When the MIPI module 211 is in the data readback state, the main logic control unit 2111 is configured to send the value of the corresponding register to the cache unit 2112 through the third internal signal line SDATA_O; the cache unit 2112 is configured to work in the push-pull output state to send the value of the corresponding register to the MIPI main control chip 100.
[0057] The main logic control unit 2111 is further configured to set the signal on the first internal signal line SDATA_OEN to a low level after not responding to the MIPI read instruction or after completing the MIPI read instruction, so that the MIPI module 211 operates in the instruction receiving state.
[0058] Therefore, the communication device with read address bias provided by the present invention adopts a modular design of main logic control unit 2111 and cache unit 2112, which is simple in logic and easy to implement.
[0059] It should be noted that, as those skilled in the art will understand, the communication device with read address bias provided by the present invention does not limit the communication method between the main logic control unit 2111 and the cache unit 2112. For example, in some other exemplary embodiments, the main logic control unit 2111 and the cache unit 2112 may also be connected through other I / O interfaces, which are not limited herein.
[0060] Preferably, in some exemplary embodiments, the register address information includes the register start address and the number of readback registers. The MIPI modules 211, 221, and 231 are configured to: calculate the current internal read address based on the register start address, the number of readback registers, the register address offset, and the current readback count; and determine whether the current internal read address is within the register address response range. If so, control the bus and output the value of the register corresponding to the current internal read address. Therefore, the communication device with read address offset provided by this invention ensures that the MIPI modules 211, 221, and 231 will only occupy the bus to send back data when the register address information in the MIPI read instruction is within their offset register address range. By reasonably setting the register address offset of each MIPI module 211, 221, and 231, it can be guaranteed that only one MIPI module 211, 221, or 231 occupies the bus at any given time, thus effectively solving the readback contention problem.
[0061] Preferably, in some exemplary embodiments, the MIPI modules 211, 221, and 231 are configured to determine whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chips 210, 220, and 230. If so, they determine whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range. Therefore, the communication device with read address offset provided by the present invention, by determining whether to respond to the MIPI read instruction based on the register address after determining a USID match during readback operations, can further improve communication efficiency.
[0062] For example, referring to Figures 1 and 4, and also referring to Figure 5, Figure 5 is a flowchart illustrating the execution of a MIPI write instruction by the MIPI module of the communication device with read address bias provided by the present invention. As can be seen from Figure 5, in this example, the flow of the MIPI module 211 writing the instruction is roughly as follows:
[0063] SA1: After determining the start signal (SSC, Sequence Start Condition) of the received MIPI instruction, all MIPI data packets start from SSC. SSC is a specific combination of clock signal and data signal (clock signal line SCLK is kept low and a high-level pulse appears on data signal line SDATA). Then, step SA2 is executed.
[0064] SA2: After determining that the USID corresponding to the MIPI instruction matches the USID of the sub-chip 210, if it is determined that the instruction is a read instruction (i.e., the MIPI read instruction in this document), if yes, proceed to step SA3; if no, process the instruction and return to step SA1.
[0065] SA3: Extract the register address information from the MIPI read instruction to obtain the register start address and the number of registers to be read back; subtract the register address offset configured in the MIPI module 211 from the register start address information to obtain the current internal read address, and reset the current number of read back to 0;
[0066] SA4: Determine whether the current internal read address is within the register address response range configured in the MIPI module 211. If yes, pull the first internal signal line SDATA_OEN high and output the value of the register corresponding to the current internal read address to the buffer unit 2112 through the third internal signal line SDATA_O, so that the buffer unit 2112 outputs the value of the register to the MIPI module 211 through the data signal line SDATA. If no, pull the first internal signal line SDATA_OEN low, so that the buffer unit 2112 enters the data receiving state.
[0067] SA5: Determine whether the MIPI read instruction has ended. If not, increment the current internal read address and return to step SA4. If yes, execute step SA6.
[0068] For example, increment the current read count by 1, determine whether the current read count is greater than or equal to the read register count, if not, the MIPI read instruction has not ended, increment the current internal read address, and return to step SA4; if yes, the MIPI read instruction ends, and step SA6 is executed.
[0069] SA6: Pull the first internal signal line SDATA_OEN low, so that the buffer unit 2112 enters the data receiving state, and return to step SA1.
[0070] Please refer to Figure 6, which is a timing example diagram of the communication device with read address bias provided by the present invention when executing the MIPI read instruction. A further example is as follows: In the scenario described earlier, where the register address bias of sub-chip 210 is 0x00 and the register address response range is 0x00~0x3F, the register address bias of sub-chip 220 is 0x40 and the register address response range is 0x00~0x3F, and the register address bias of sub-chip 230 is 0x80 and the register address access range is 00x00~0x3F, the register address information read by the MIPI master control chip 100 is read address 1 (e.g., register start address 0x2F and read back register number 3), read address 2 (e.g., register start address 0x5A and read back register number 10), and read address 3 (e.g., register start address 0x9D and read back register number 8). As can be seen from Figure 6, the MIPI master control chip 100 and the three sub-chips 210, 220, and 230 alternately control the data signal line SDATA.
[0071] Additionally, it should be noted that, as those skilled in the art will understand, the communication device with read address bias provided by the present invention does not impose excessive limitations on the execution of MIPI write instructions. For example, please refer to Figure 7, which is a timing example diagram of the communication device with read address bias provided by the present invention executing MIPI read instructions. As shown in Figure 7, in some exemplary embodiments, when executing MIPI write instructions, all MIPI modules 211, 221, and 231 can respond to the MIPI write instructions and update their corresponding internal registers according to information such as register addresses and register values in the command.
[0072] It should be noted that, as those skilled in the art will understand, the above examples are merely exemplary illustrations of preferred embodiments of the present invention. For instance, in some exemplary embodiments, the MIPI modules 211, 221, and 231 are configured to, after determining whether to respond to the MIPI read instruction based on the register address information, the register address bias, and the register address response range, further include: determining whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chips 210, 220, and 230; if so, responding to the MIPI read instruction.
[0073] Example 2
[0074] This embodiment provides a communication method for use in the communication device with read address bias described in any embodiment of Example 1. For example, please refer to Figure 8, which is a schematic flowchart of the communication method provided in this embodiment. As can be seen from Figure 8, the communication method provided in this embodiment includes:
[0075] S100: The MIPI master control chip 100 sends a MIPI read instruction to the MIPI modules 211, 221 and 231, the MIPI read instruction including register address information;
[0076] S200: The MIPI modules 211, 221 and 231 determine whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range. If so, they control the bus and output the value of the corresponding register.
[0077] Since the communication method provided by this invention belongs to the same inventive concept as the communication device with read address bias provided by this invention, the communication method provided by this invention has at least all the advantages of the communication device with read address bias provided by this invention. For details on the beneficial effects of the communication method provided by this invention, please refer to the above description of the beneficial effects of the communication device with read address bias provided by this invention, which will not be repeated here.
[0078] Since the communication method provided by this invention is based on the same principle as the communication device with read address bias provided by this invention, for any part of the communication method provided in this embodiment not mentioned, please refer to the relevant description in Embodiment 1 for an adaptive understanding.
[0079] Preferably, in some exemplary embodiments, the communication method further includes: updating the register address bias and / or the register address response range online. Therefore, the communication method provided by the present invention, by updating the register address bias and / or the register address response range online, enables the present invention to better adapt to different application scenarios. Different application scenarios include, but are not limited to, the addition of sub-chips.
[0080] It should be noted that those skilled in the art should understand that this invention does not limit the specific method of updating the register address bias and / or the register address response range. For example, in some embodiments, the register address bias and / or the register address response range can be updated via GPIO; in other embodiments, the register address bias and / or the register address response range can be updated via register writing; and in still other embodiments, the register address bias and / or the register address response range can be updated via Efuse programming.
[0081] Compared with the prior art, the communication device and method with read address bias provided by the present invention have the following advantages:
[0082] The communication device with read address bias provided by the present invention configures register address bias and register address response range on the MIPI modules of each sub-chip connected to the same bus, and enables the register address access ranges of each sub-chip connected to the same bus to not conflict with each other. Thus, it can effectively solve the readback contention problem of multiple MIPI modules under the same MIPI bus and USID, and can effectively preserve the readback capability of each sub-chip while reducing communication time, making it easier to conduct comprehensive testing and debugging.
[0083] Since the communication method provided by this invention belongs to the same inventive concept as the communication device with read address bias provided by this invention, the communication method provided by this invention has at least all the advantages of the communication device with read address bias provided by this invention. For details on the beneficial effects of the communication method provided by this invention, please refer to the above description of the beneficial effects of the communication device with read address bias provided by this invention, which will not be repeated here.
[0084] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.
[0085] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0086] The above description is merely a preferred embodiment of the communication device and method with read address bias provided by the present invention, and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.
Claims
1. A communication device with read address bias, characterized in that, It includes a MIPI master control chip and at least two sub-chips connected to the MIPI master control chip via a bus. Each sub-chip is equipped with a MIPI module. The MIPI modules of each sub-chip on the same bus are configured with register address bias and register address response range, so that the register address access ranges of each sub-chip connected to the same bus do not conflict with each other. The MIPI master control chip is configured to send a MIPI read instruction to the MIPI module, the MIPI read instruction including register address information; The MIPI module is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range. If so, it controls the bus and outputs the value of the corresponding register.
2. The communication device according to claim 1, characterized in that, The sub-chips connected on the same bus are connected in parallel.
3. The communication device according to claim 1, characterized in that, The register address access ranges of the various sub-chips connected to the same bus do not conflict with each other, including: The address space formed by the register address access ranges of all the sub-chips connected to the same bus is contiguous relative to the MIPI master control chip.
4. The communication device according to claim 1, characterized in that, The bus includes clock signal lines and data signal lines; The MIPI module includes a main logic control unit and a cache unit. The main logic control unit and the cache unit are connected through a first internal signal line, a second internal signal line, and a third internal signal line. The main logic control unit is connected to the MIPI master control chip through the clock signal line, and the cache unit is connected to the MIPI master control chip through the data signal line. When the signal on the first internal signal line is low, the MIPI module operates in the instruction receiving state. At this time, the buffer unit is configured to receive the MIPI read instruction sent by the MIPI master control chip, and send the MIPI read instruction to the main logic control unit through the second internal signal line. The main logic control unit is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address bias, and the register address response range. If so, the signal on the first internal signal line is set to high, so that the MIPI module operates in the data readback state. When the MIPI module is operating in the data readback state, the main logic control unit is configured to send the value of the corresponding register to the cache unit through the third internal signal line; the cache unit is configured to operate in the push-pull output state to send the value of the corresponding register to the MIPI master control chip; the main logic control unit is also used to set the signal on the first internal signal line to a low level after not responding to the MIPI read instruction or after completing the MIPI read instruction, so that the MIPI module operates in the instruction receiving state.
5. The communication device according to claim 1, characterized in that, The register address information includes the register start address and the number of readback registers. The MIPI module is configured to: calculate the current internal read address based on the register start address, the number of readback registers, the register address offset, and the current readback count; and determine whether the current internal read address is within the register address response range. If so, control the bus and output the value of the register corresponding to the current internal read address.
6. The communication device according to claim 1, characterized in that, The MIPI module is configured to determine whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip. If so, it determines whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range.
7. The communication device according to claim 1, characterized in that, The MIPI module is configured to, after determining whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range, further include: determining whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip; if so, responding to the MIPI read instruction.
8. The communication device according to claim 1, characterized in that, The sub-chip includes an RF front-end interface chip.
9. The communication device according to claim 1, characterized in that, The communication device is configured to allow online updates of the register address bias and / or the register address response range.
10. The communication device according to claim 9, characterized in that, The register address bias and / or the register address response range are updated online by at least one of the following methods: GPIO, register writing, or Efuse programming.
11. A communication method, characterized in that, For a communication apparatus with read address bias as described in any one of claims 1 to 10, the communication method includes: The MIPI master control chip sends a MIPI read instruction to the MIPI module, and the MIPI read instruction includes register address information. The MIPI module determines whether to respond to the MIPI read instruction based on the register address information, the register address offset, and the register address response range. If so, it controls the bus and outputs the value of the corresponding register.
12. The communication method according to claim 11, characterized in that, The communication method further includes: Update the register address bias and / or the register address response range online.