Optoelectronic device, method for operating an optoelectronic device and method for manufacturing the same

Abstract

The invention concerns an optoelectronic device, in particular microLED, comprising a semiconductor layer stack (2) of at least a first layer (3) of a first conductivity type, a second layer (4), and an active region (5) comprising at least one quantum well arranged between the first and the second layer and being configured to emit light of a first wavelength. The second layer comprises a central region (7a) of a second conductivity type as well as a lateral region (7b) of the first conductivity type which is adjacent to the active region (5) and laterally surrounds at least portions of the central region. The semiconductor layer stack (2) further comprises a top surface, a bottom surface (11b) opposite the top surface and a side surface (11c) extending from the bottom surface into the direction of the top surface and extending through at least the first layer, the active region and the lateral region of the second layer. The optoelectronic device further comprises a first contact layer (8) electrically contacting the first layer and a second contact layer (9) electrically contacting the central region of the second layer but being electrically isolated from the lateral region of the second layer.

Description

[0001] 2024PF00929

[0002] OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

[0003] The present application claims priority from German patent application DE 10 2024 134 287 . 0 filed on November 21 , 2024 , the disclosure of which is incorporated by way for reference in its entirety .

[0004] The present invention concerns an optoelectronic device , in particular pLED, as well as well as a method for manufacturing the same .

[0005] BACKGROUND pLEDs are optoelectronic devices that comprise a lateral dimension in the range from a few hundred nm to about 40 pm. Such devices provide a variety of different applications , including but not limited to VR / AR applications as well as displays .

[0006] In order to increase the external quantum efficiency ( EQE ) of for example pLEDs , or more general light emitting nanostructures , one can engineer the geometry, shape and surroundings (passivation, reflective mirror , ...) of the pLEDs in a way that the light extraction efficiency (LEE ) in a specific solid angle is maximized . Apart from the LEE the internal quantum efficiency ( IQE ) is as important , where a main loss factor originates from non-radiative recombination (NRR) of charge carriers within the pLED .

[0007] In particular pLEDs based on an InGaAlP material system suffer from decreasing performance with smaller size . A reason for this efficiency drop can be NRR of inj ected charge carriers at etched surfaces . For example , etching is a common and standard process for pixel definition ( etching through the active region and physical separation of individual pixels ) , that introduces damage to the surface and underlying layers dependent on the specific process and parameters used . Damage in this case means the creation of defect centres in the crystal lattice of the etched structure . Defects created on the surface of the active region - which is exposed during and after pixel definition - act as non-radiative recombination channels which reduce the IQE of the pLED leading to a bad overall performance . This effect 2024PF00929 is particularly pronounced for the InGaAlP material system due to its high charge carrier diffusion length and surface recombination velocities , as well as Fermi level pinning at the semiconductor surface . Especially for small pixels such as for the case of pLEDs with a high surf ace-to-volume ratio , in particular a high ratio of the exposed active region surface on the pixel' s sidewall vs . the total active region volume , this is a maj or challenge .

[0008] To reduce non-radiative recombination at the edges of a pLED, a possible approach is a passivation of the pLED surface by, e . g . , dielectrics . However, by this the performance cannot be improved significantly and in a desired way . A further approach to reduce non-radiative recombination at the side surfaces of a pLED is to keep the charge carriers away from the side surfaces which comprise the non-radiative recombination centres . This can for example be done by quantum well intermixing the active regions in areas along the side surfaces of the pLED by means of which a respective dopant is diffused into the active region causing the bandgap of the active region along the side surfaces to enlarge due to intermixing processes . By this , charge carriers can be kept away from the side surfaces which comprise the non-radiative recombination centres . However , such an approach is limited for pLED sizes larger than several micrometres , as the intermixing resolution is insufficient for pLEDs in the micrometre size .

[0009] Another approach is a so-called epitaxial regrowth . After a first epitaxially growth step, including the active region, the epitaxially grown layers and in particular the active region are structured and locally etched away . Using this approach, structured active regions in the micrometre range are possible . Then, a second epitaxially growth step is conducted over the whole structure , leading to an overgrowth of the non-etched islands as well as the etched regions . By this , some of the defects at the etched surface are passivated due to the similarity of the materials comprised in the active region and the regrown layers . Furthermore , like in the intermixing approach, charge carriers are blocked by high energy barriers to prevent diffusion to the pixel side surfaces . Still , the interface between the regrowth layer and the etched surfaces remains critical and can cause 2024PF00929 significant nonradiative recombination and efficiency losses within the pLEDs . In addition, leakage currents can occur, causing further efficiency losses .

[0010] A further problem of current designs of pLEDs relates to their switching speed which at least for some applications of pLEDs can be desirably high . The switching speed is mainly limited by the respective on and off time , also referred to as rise and fall time . While lasers reach several 100 MHz to GHz corresponding to rise and fall times in the range of several tens of ps , conventional lighting diodes are much slower within a few 100 kHz or ]is in switching speed . The slow switching speed can thereby in particular be caused by the carrier lifetime in the active region, as the charge carriers still populate the active region even if the power is switched off . This can in particular be the case for material systems such as nitrides which suffer from intrinsically long lifetimes of the charge carriers ( small electronhole overlap due to polarization fields , ...) .

[0011] Several approaches have been taken to improve the switching speed . Those were mainly directed at reducing the carrier lifetime , for instance by deliberately introducing impurities into the active region . Those impurities act as non-radiative recombination centres . As the overall carrier lifetime is a combination of radiative recombination and non-radiative recombination, one can increase one recombination (here the non-radiative recombination ) path at the cost of the other . This will , on the one hand, practically shorten the "afterglow" of light after switching off the lighting diode thereby reducing the off- switching time . A shorter carrier lifetime may also bring a faster ON- switching, due to the increased rate of carrier density build up in the active region . However, shortening the carrier lifetime by increasing the non-radiative recombination rate comes with a reduction in the internal quantum efficiency ( IQE ) and hence an overall efficiency loss whereas trying to improve the efficiency of the pLEDs by reducing the effect of nonradiative recombination, this is mostly on the cost of the switching speed and switching of the pLEDs becomes slower . 2024PF00929

[0012] An alternative approach is the design of an elaborative driving schemes including current spikes at the start of the pulse or reverse biases to speed up the light decay . However, such an approach requires a complex driver design requiring a larger footprint and driving the costs .

[0013] It is thus an obj ect of the present application to provide an optoelectronic device which overcomes at least some of the aforementioned aspects , as well as to provide a method for manufacturing such an optoelectronic device .

[0014] SUMMARY OF THE INVENTION

[0015] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0016] This invention targets to change the band energy / prof ile within the active region close to etched side surfaces of the active region to create a potential barrier such that one charge carrier type ( electrons or holes , depending on the chosen layer conductivities ) can be kept away from the side surfaces which comprise the non-radiative recombination centres . To do this , a lateral region of one of the semiconductor layers with a different conductivity type , between which the active region is arranged, and which is adj acent to the side surfaces of the active region is removed and replaced by the material of the semiconductor layer with the corresponding other conductivity type . As a result , the electrostatic potential ( and hence the band profile ) within the active region will change in the vicinity of the removed and replaced material creating a barrier close to etched side surfaces of the active region for a lateral transport of the charge carriers . Further a contact layer, via which a potential can be applied to the remaining central region of the semiconductor layer whose lateral region has been removed and replaced, is electrically isolated from the lateral region at least when operating the optoelectronic device in an ON-state . This in combination allows for mostly a vertical electron and hole transport through the active region as no or almost 2024PF00929 no current flows through the removed and replaced lateral region of the respective semiconductor layer but through its remaining central region and causes a reduction of non-radiative recombination at the etched side surfaces .

[0017] Further in some aspects the invention targets to decrease the switchoff times of such an optoelectronic device by creating a quasi-ohmic electron current leakage path, so that the current flowing through the pn-j unction in the central region drops very quickly when switching off the optoelectronic device . To do this , when switching off the optoelectronic device a potential can actively be applied to the lateral region that causes a charge carrier sweep from the central region to the lateral region . This way, the carrier concentration in the central part of the active region, and hence the emitted light , will decay much faster .

[0018] Advantages that may result from the proposed concept can be that smaller pLEDs are possible as the lateral region can be defined by photolithographic processes and can therefore be smaller / more accurate compared to for example a process like quantum well intermixing . In addition to this , the design allows more freedom in the doping and alloy composition of the semiconductor material in the lateral region without impacting the performance of the light emitting portion of the optoelectronic device , as no vertical current flows through the material in the lateral region . Since there is no vertical current flow in material in the lateral region, potential traps at the interfaces of the material in the lateral region should have no negative impact such that these cause less NRR in the active region, thus providing a better brightness of the optoelectronic device due to a better IQE .

[0019] According to a first aspect , an optoelectronic device , in particular pLED, comprising a semiconductor layer stack is provided . The semiconductor layer stack comprises at least a first layer of a first conductivity type , a second layer as well as an active region comprising at least one quantum well arranged between the first and the second layer . The active region is thereby configured to emit light of a first wavelength . In particular the active region of the semiconductor layer 2024PF00929 stack comprises at least one quantum well , however the active region can also comprise a multi quantum well structure comprising several quantum wells .

[0020] The second layer is designed to comprise a central region of a second conductivity type different to the first conductivity type as well as a lateral region of the first conductivity type which is adj acent to the active region and laterally surrounds at least portions of the central region . The lateral region can thereby extend throughout the whole thickness of the second layer and enclose the central region completely in lateral direction or the lateral region can extend through only part of the thickness of the second layer being arranged adj acent to the active region and enclose the central region in lateral direction in this part of the thickness of the second layer .

[0021] The semiconductor layer stack comprises a top surface , a bottom surface opposite the top surface and a side surface extending from the bottom surface into the direction of the top surface . The side surface thereby in particular comprises at least the first layer, the active region and the lateral region of the second layer . For example , the side surface can result from a step of structuring the semiconductor layer stack thereby removing a portion of the semiconductor layer stack and remaining another portion of the semiconductor layer stack . The side surface can be a therefrom resulting side surface of the remained portion . In particular the side surface can result of an etching step for structuring the semiconductor layer stack resulting in an etched side surface extending at least through the first layer, the active region and the lateral region of the second layer .

[0022] The optoelectronic device further comprises a first contact layer electrically contacting the first layer and a second contact layer electrically contacting the central region of the second layer but being electrically isolated from the lateral region of the second layer . The first and second contact layer can thereby of the same material system as the semiconductor layer stack but can also be contact layers comprising a metal and / or a transparent conductive oxide (TCO ) such as for example indium tin oxide ( ITO ) . By means of the first and 2024PF00929 second contact layer a first and a second potential can be applied to the optoelectronic device to operate the optoelectronic device in a desired manner .

[0023] By means of the term "quantum well" a potential well with discrete energy values is to be understood . One of the simplest quantum well systems can be constructed by inserting a thin layer of one type of semiconductor material between two layers of another with a different bandgap . An example can be two layers of for example InGaAlP with a large bandgap surrounding a thin layer of InGaP with a smaller bandgap . Since the bandgap of the contained material is lower than the surrounding InGaAlP, a quantum well (potential well ) is created in the InGaP region . This change in band energy across the structure can be seen as a change in the potential that a carrier would feel , therefore low energy carriers can be trapped in these wells . Within the quantum well , there are discrete energy eigenstates that carriers can have . For example , an electron in the conduction band can have lower energy within the well than it could have in the InGaAlP region of this structure . Consequently, an electron in the conduction band with low energy can be trapped within the quantum well . Similarly, holes in the valence band can also be trapped in the top of potential wells created in the valence band .

[0024] According to some aspects , the semiconductor layer stack is of an InGaAlP or InGaAlAs material system. For example , the semiconductor layer stack can be of an Al and / or In containing semiconductor material system . For example , the semiconductor layer stack can be of a material system comprising Indium ( In) and Aluminium (Al ) and Gallium ( Ga ) and Arsenide (As ) and / or Phosphide ( P ) . The semiconductor layer stack can however be also of any other semiconductor material system .

[0025] According to some aspects , the active region comprises a multi quantum well structure . The quantum wells can thereby be substantially equal in size and / or composition, can however also vary between each other . The at least two quantum wells can for example comprise a substantially equal effective bandgap and can in particular be configured to emit 2024PF00929 light of a substantially equal wavelength . According to some aspects , the active region can comprise or be formed of a bulk active region . According to some aspects , the doping differences between the central and lateral regions of the second layer causes a difference in the electrostatic potential ( and hence in the band bending ) of the active region, creating a potential barrier for the lateral transport of one carrier type towards the side surface . In particular the active region comprises a different electrostatic potential adj acent to the lateral region of the second layer than adj acent to the central region of the second layer . Together with the second contact layer , via which a potential can be applied to the central region of the second layer , and which is electrically isolated from the lateral region of the second layer at least when operating the optoelectronic device in an ON-state , this allows for mostly a vertical electron and hole transport through the active region as no or almost no current flows through the lateral region of the second layer but through its remaining central region and causes a reduction of non-radiative recombination at the side surface of the active region .

[0026] According to some aspects , the side surface extends from the bottom surface into the direction of the top surface through the first layer , the active region, the lateral region of the second layer and at least a portion of the central region of the second layer . In particular for the case that the lateral region extends through only part of the thickness of the second layer the side surface may also comprise a portion of central region of the second layer that is arranged on the lateral region of the second layer on a side opposite the active region .

[0027] According to some aspects , the semiconductor layer stack comprises a sacrificial quantum well arranged adj acent to the active region between the active region and the second layer . The sacrificial quantum well thereby comprises a larger effective bandgap than the at least one quantum well of the active region .

[0028] By means of the term "effective" bandgap , the bandgap of the respective quantum well , layer, or sublayer in terms of the energy difference between the lowest electron and hole bound states ( sometimes called 2024PF00929 ground states ) is to be understood . The effective bandgap can for example be determined by the bulk bandgap of the material of the quantum well and the potential profile of the quantum well ( depth, thickness , composition gradings , ...) . For example , in a thinner quantum well , the ground states shift to higher energies above the bottom of the well potential and thus the "effective bandgap" increases .

[0029] By means of the term "sacrificial" quantum well a quantum well is to be understood that is conf igured / designed to not cause any carrier recombination when using the optoelectronic device as intended . This means that the sacrificial quantum well is conf igured / designed to not cause radiative nor non radiative recombination . In particular the sacrificial quantum well can comprise a different material composition than QWs of the active region so that their effective bandgap is larger . In addition or as an alternative , the sacrificial quantum well can comprise a different thickness than QWs of the active region and in particular a thickness that is such small that its effective bandgap increases to such an extent that carriers will preferentially stay away from it . At the same time the presence of the sacrificial QW does however not hinder carriers from reaching the QWs of the active region .

[0030] Such a sacrificial QW allows to conduct an etching step into portions of the second layer / a base material of the second layer to come as close to the active region as possible without etching into it . The sacrificial QW can thus act like kind of an etch stop layer when etching into the second layer / a base material of the second layer to improve the accuracy and stability of the etching process .

[0031] According to some aspects , the semiconductor layer stack comprises more than one sacrificial quantum well arranged between the active region and the second layer . In particular one or a number of sacrificial quantum wells are arranged directly adj acent to the active region and optionally one or some other sacrificial quantum wells are arranged between other layers of the semiconductor layer stack between the active region and the second layer . In all cases it can be desired that the sacrificial quantum wells are conf igured / designed to not cause any 2024PF00929 or at least only little carrier recombination when using the optoelectronic device as intended .

[0032] According to some aspects , the first sacrificial quantum well comprises a doping of the second conductivity type . In particular the sacrificial quantum well can be doped in the way the central region of the second layer is . This can further supress any unwanted residual recombination within the sacrificial quantum well .

[0033] According to some aspects , the thickness of the sacrificial quantum well is smaller than the thickness of the at least one quantum well of the active region, in particular by a factor of 2 . According to some aspects , the sacrificial quantum well comprises a thickness of less than 10 nm, in particular less than 5 nm, or less than 3 nm, or less than 2 nm . Such a thickness increases the effective bandgap of the sacrificial quantum well to such an extent that carriers will preferentially stay away from it . At the same time the presence of the sacrificial QW does however not hinder carriers from reaching the QWs of the active region .

[0034] In particular the sacrificial QW can have a different thickness and / or material composition than the QW ( s ) of the active region so that their effective bandgap is larger . In particular , the thickness of the sacrificial QW is smaller than that of the QW ( s ) of the active region . As a result of the higher bandgap , under current inj ection, the carrier density in the sacrificial QW is kept low and no significant recombination takes place in them.

[0035] According to some aspects , a lateral region of the active region adj acent to the lateral region of the second layer comprises a doping of the first conductivity type . The doping can in particular result from diffusion, during growth, of a dopant of the first conductivity type from the lateral region of the second layer into a lateral region of the active region to change the electrostatic potential of the active region in its lateral region . In particular due to doping of the first conductivity type the band profile within the active region changes even more from a central region of the active region adj acent 2024PF00929 to the central region of the second layer to a lateral region of the active region adj acent to the lateral region of the second layer creating an even larger barrier close to side surface of the active region for a lateral transport of charge carriers . The term even larger can thereby for example be understood in such way that the change in band bending extends further into the active region (more quantum wells of the active region experience the bending ) starting from the second layer than if no doping would be present . The diffusion of the dopant of the first conductivity type can thereby in particular be tailored through the growth conditions ( temperature , growth rate , ...) and choice of dopant species used for providing the lateral region of the second layer . By means of the term of a doping of the first conductivity type of the lateral region of the active region it is however to be understood that this is not equated to an intermixing process of the at least one quantum well of the active region as it would occur for a QWI but the at least one quantum well of the active region remains intact when being doped with the doping of the first conductivity type .

[0036] According to some aspects , the optoelectronic device further comprises a passivation layer covering the side surface and extending at least partly onto the top surface . For example , the passivation layer can cover the lateral region of the second layer and at least partially extend between the second contact layer and the lateral region of the second layer to electrically isolate them from each other . The passivation layer can thereby for example electrically isolate the semiconductor layer stack as well as passivate its material from external influences .

[0037] According to some aspects , the first conductivity type is a n-type and the second conductivity type is a p-type . The first layer as well as the lateral region of the second layer can thus be a n-type semiconductor layer and the central region of the second layer can be a p-type semiconductor layer . It is however to be understood that it is also possible that the first layer as well as the lateral region of the second layer can be a p-type semiconductor layer and the central region of the second layer can be a n-type semiconductor layer . 2024PF00929 12

[0038] The optoelectronic device can m particular be a small light emitting component / element such as a small LED or pLED . A pLED can in particular be a very small LED with edge lengths down to 40 pm, down to 10 pm, down to 5 pm or even less . Such small LEDs can be free of a growth substrate and require a special handling and processing to improve their IQE and light outcoupling efficiency .

[0039] According to some aspects , the optoelectronic device further comprises a third contact layer electrically contacting the lateral region of the second layer but being electrically isolated from the central region of the second layer . The passivation layer can therefore for example be structured on the top surface to allow an electric contact between the third contact layer and the lateral region of the second layer as well as between the second contact layer and the central region of the second layer while isolating them from one another .

[0040] The third contact layer can thereby of the same material system as the semiconductor layer stack but can also be a contact layer comprising a metal and / or a transparent conductive oxide ( TCO ) such as for example indium tin oxide ( ITO ) . By means of the third contact layer a further potential can be applied to allow for a faster switching off of the optoelectronic device .

[0041] The optoelectronic device can therefore for example comprise a switch element configured to electrically connect the second and the third contact layer such that the potential applied to the third contact layer equals the potential that is applied to the second contact layer at the time of switching the optoelectronic device off . As an alternative the optoelectronic device can comprise an integrated circuit configured to apply a potential to the third contact layer that is different to a potential applied to the second contact layer . By this a quasi-ohmic current leakage path is created between the lateral region of the second layer and the first layer , so that no further carriers are inj ected into the active region when switching off the optoelectronic device and the remaining excess charge carriers in the central region of the second layer are discharged via the lateral region of the second layer . The potential applied to the third contact 2024PF00929 layer / lateral region can thereby in particular be chosen to cause a charge carrier sweep from the central region to the lateral region in a preferred manner compared to a charge carrier flow through the active region in the central region .

[0042] According to a further aspect , a respective method for operating the optoelectronic device is provided . The method is in particular a method for operating an optoelectronic device according to the later aspects of the optoelectronic device comprising a third contact layer .

[0043] The method for operating an optoelectronic device according to the aforementioned aspects comprises the steps :

[0044] Switching on the optoelectronic device by providing a respective first potential to the first contact layer and a respective second potential to the second contact layer such that the optoelectronic device emits light of the first wavelength; and Switching off the optoelectronic device by providing a respective third potential , in particular a potential equal to the first potential , to the first contact layer and a respective fourth potential to the second contact layer , in particular a potential such that the difference between the third and fourth potential is below the turn-on voltage of the optoelectronic device , such that the optoelectronic device does not emit light , wherein for faster switching off of the optoelectronic device the fourth potential is also applied to the third contact layer , or a fifth potential , in particular different to the third and fourth potential , is applied to the third contact layer, wherein the fifth potential promotes a charge carrier transportation from the first layer and / or the central region to the lateral region in a preferred manner compared to a charge carrier transportation from the central region to the first layer through the active region . As a result , a leakage channel is opened between the first and third contact layers , sweeping out the charge carriers remaining in the central portion of the active region .

[0045] Depending on at least one of the conductivity type , the doping concentration of the first layer, the lateral region and / or the central 2024PF00929 14 region, and the contact resistance of the contact layers , the potential applied to the third contact layer can in particular be chosen such charge carrier sweep from the central region to the lateral region is promoted while at the same time ensuring that the current flowing between the lateral region of the second layer and the first layer when switching off the optoelectronic device does not get too high ( e . g . , to avoid reliability issues and material damage ) .

[0046] According to a further aspect , a method for manufacturing an optoelectronic device is provided . The method can in particular be a method for manufacturing an optoelectronic device according to at least some of aforementioned aspects . Hence all aspects already described for the optoelectronic device can in the same way be applied to the method for manufacturing the same .

[0047] The method comprises at least the following step :

[0048] Providing on a growth substrate a semiconductor layer stack of at least :

[0049] • a first layer of a first conductivity type ,

[0050] • a second layer , and

[0051] • an active region comprising at least one quantum well arranged between the first and the second layer and being configured to emit light of a first wavelength,

[0052] • wherein the second layer comprises a central region of a second conductivity type as well as a lateral region of the first conductivity type which is adj acent to the active region and laterally surrounds at least portions of the central region;

[0053] Structuring the semiconductor layer stack thereby remaining at least one first portion of the semiconductor layer stack and removing a second portion of the semiconductor layer stack adj acent to the at least one first portion, resulting in an exposed side surface of the at least one first portion comprising at least the first layer , the active region and the lateral region of the second layer ; and

[0054] Providing a first contact layer electrically contacting the first layer and a second contact layer electrically contacting the central region of the second layer but being electrically isolated from the lateral region of the second layer . 2024PF00929

[0055] According to some aspects , the step of providing the semiconductor layer stack comprises :

[0056] Providing the first layer on the growth substrate and the active region on the first layer as well as providing the material of the central region of the second conductivity type on the active region throughout the active region;

[0057] Structuring the material of the central region of the second conductivity type on the active region thereby remaining at least one third portion of the material of the second conductivity type forming the central region and removing a fourth portion of the material of the second conductivity type adj acent to the at least one third portion;

[0058] Providing the material of the lateral region of the first conductivity type in the removed fourth portion of the material of the second conductivity type thereby laterally surrounding at least portions of the central region .

[0059] According to some aspects , the step of providing the semiconductor layer stack comprises :

[0060] Providing the first layer on the growth substrate and the active region on the first layer as well as providing the material of the lateral region of the first conductivity type on the active region throughout the active region;

[0061] Structuring the material of the lateral region of the first conductivity type on the active region thereby remaining at least one fifth portion of the material of the first conductivity type forming the lateral region and removing a sixth portion of the material of the first conductivity type adj acent to the at least one fifth portion;

[0062] Providing the material of the central region of the second conductivity type in the removed sixth portion of the material of the first conductivity type such that it is laterally surrounded at least in portions by the material of the lateral region of the first conductivity type .

[0063] Hence the step of providing the semiconductor layer stack can either comprise a provision of the material of the central region of the second conductivity type or the material of the lateral region of the 2024PF00929 16 first conductivity type on the active region throughout the active region and a structuring of the same to provide a recess in which the other of the two materials is then "regrown" . In particular the latter case can have the advantage that until regrowing the material of the central region of the second conductivity type within a recess of the material of the lateral region of the first conductivity type no material of the second conductivity type is present such that a clean doping profile with a dopant of the first conductivity type is possible and no remains of a possible doping of the second conductivity type may occur in the active region close to the lateral region . Without a thinning step the latter case may however result in an overgrowth of the lateral region of the second layer with the material of the central region of the second conductivity type .

[0064] According to some aspects , the step of structuring the material of the lateral region of the first conductivity type or the step of structuring the material of the central region of the second conductivity type ( depending on which of the material has been provided throughout the active region) is conducted down to a sacrificial quantum well that is arranged adj acent to the active region between the active region and the material of the lateral region of the first conductivity type or the material of the central region of the second conductivity type respectively . The sacrificial QW may in particular allow to conduct the etching step into the material of the lateral region of the first conductivity type or the material of the central region of the second conductivity type to come as close to the active region as possible without etching into it . The sacrificial QW can thus act like kind of an etch stop layer when etching into the material of the lateral region of the first conductivity type or the material of the central region of the second conductivity type to improve the accuracy and stability of the etching process .

[0065] According to some aspects , the step of providing the semiconductor layer stack comprises a step of regrowth during which a dopant of the first conductivity type from the lateral region of the second layer diffuses into a lateral region of the active region adj acent to the lateral region of the second layer . By this a lateral region of the 2024PF00929 17 active region adj acent to the lateral region of the second layer comprises a doping of the first conductivity type . Due to doping with the first conductivity type the band profile within the active region changes even more from a central region of the active region adj acent to the central region of the second layer to a lateral region of the active region adj acent to the lateral region of the second layer creating an even larger barrier close to side surface of the active region for a lateral transport of charge carriers . The diffusion of the dopant of the first conductivity type can thereby in particular be tailored through the growth conditions ( temperature , growth rate , ...) and choice of dopant species used for providing the material of the lateral region of the second layer .

[0066] According to some aspects , the method further comprises a step of providing third contact layer electrically contacting the lateral region of the second layer but being electrically isolated from the central region of the second layer .

[0067] According to some aspects , the method further comprises a step of providing a passivation layer on the side surface as well as at least on portions of the top surface .

[0068] According to some aspects , the method further comprises a step of removing the growth substrate .

[0069] SHORT DESCRIPTION OF THE DRAWINGS

[0070] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0071] Figures 1A and IB show each a side view of an embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ; 2024PF00929

[0072] Figures 2A to 2G show steps of a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0073] Figure 3 shows a step of a further embodiment of a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0074] Figures 4A to 4C show steps of a further embodiment of a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ; and

[0075] Figures 5A to 5C show each a side view of a further embodiment of an embodiment of an optoelectronic device in accordance with some aspects of the proposed principle .

[0076] DETAILED DESCRIPTION

[0077] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

[0078] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , 2024PF00929 19

[0079] "below" , "under" "larger" , "smaller" and the I ke are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0080] The term "semiconductor layer stack" used in the following description may include any semiconductor-based structure that has a semiconductor surface . The layer stack is to be understood to include doped and undoped semiconductors , epitaxial semiconductor layers , possibly supported by a base , and further semiconductor structures . For example , several layers made of a semiconductor material may be grown on a growth substrate made of another semiconductor material or of an insulating material , for example , on a sapphire substrate . Depending on the intended use , the semiconductor may be based on a direct or an indirect semiconductor material . Examples of semiconductor materials particularly suited for generating electromagnetic radiation include , in particular, nitride semiconductor compounds through which, for example , ultraviolet , blue or longer-wave light may be generated, such as GaN, InGaN, AIN, AlGaN, AlGalnN, AlGalnBN, phosphide semiconductor compounds , through which, for example , green or longer-wave light may be generated, such as GaAsP, AlGalnP, GaP, AlGaP , as well as other semiconductor materials such as AlGaAs , SiC, ZnSe , GaAs , ZnO , Ga2O3, diamond, hexagonal BN, and combinations of the materials mentioned . The stoichiometric ratio of the compound semiconductor materials may vary . Further examples of semiconductor materials may include silicon, silicon germanium and germanium. In the context of the present description, the term "semiconductor" also includes organic semiconductor materials .

[0081] The terms "lateral" and "horizontal" , as used in this description, are intended to describe an orientation or alignment which runs essentially parallel to a top surface of the semiconductor layer stack . The horizontal direction may, for example , lie in a plane perpendicular to a direction of growth when layers are grown on .

[0082] The term "vertical" , as used in this description, is intended to describe an orientation which is essentially perpendicular to the top 2024PF00929 20 surface of the semiconductor layer stack . The vertical direction may, for example , correspond to a direction of growth when layers are grown on .

[0083] To the extent that the terms "have" , "contain" , "comprise" , "include" and the like are used herein, they are open-ended terms that indicate the presence of said elements or features , but do not rule out the presence of other elements or features . The indefinite articles and the definite articles include both the plural and the singular, unless the context clearly indicates otherwise .

[0084] Figures 1A and IB show each a side view of an embodiment of an optoelectronic device 1 in accordance with some aspects of the proposed principle .

[0085] The optoelectronic devices 1 each comprise a semiconductor layer stack 2 of a first layer 3 of a first conductivity type , a second layer 4 and an active region 5 comprising at least one quantum well 6 arranged between the first and the second layer 3 , 4 and being configured to emit light of a first wavelength . The second layer 4 comprises a central region 7a of a second conductivity type as well as a lateral region 7b of the first conductivity type which is adj acent to the active region 5 and laterally surrounds the central region 7a .

[0086] The semiconductor layer stack 2 comprises a top surface Ila, a bottom surface 11b opposite the top surface I la and a side surface 11c extending from the bottom surface 11b to the top surface I la and extending through the first layer 3 , the active region 5 and the lateral region 7b of the second layer 4 .

[0087] The optoelectronic device 1 further comprises a passivation layer 14 covering the side surface 11c of the semiconductor layer stack as well as portions of the top surface Ila, in particular portions of the top surface I la that are formed by the lateral region 7b of the second layer 4 . Further a first contact layer 8 electrically contacting the first layer 3 and a second contact layer 9 electrically contacting the 2024PF00929 21 central region 7a of the second layer 4 but being electrically isolated from the lateral region 7b of the second layer 4 are provided .

[0088] In case of the embodiments shown the first conductivity type is an n- type and the second conductivity type is a p-type . The first layer 3 as well as the material of the lateral region 7b of the second layer 4 is thus of a n-type semiconductor material and the material of the central region 7a of the second layer 4 is of a p-type semiconductor material . The order can however also be switched and the first conductivity type can be a p-type and the second conductivity type can be a n-type .

[0089] The dimensions of the central 7a and lateral 7b regions are a matter of design, given a required total size of the light emitting device . From the physical point of view of the potential barrier , the lateral extension of region 7b should be at least a few tens of nanometres ( e . g . , 40-50nm) . On the other hand, a lateral extension of region 7b of up to for example 500 nm is better for blocking the lateral carrier flow . In particular, a compromise must be reached between a limitation due the resolution of lithographic and etch processes and an enlargement of the light emitting device . For example the lateral extension of region 7b can be between 10 nm and a maximum of a few hundreds of nanometres , for example 500nm.

[0090] Due to the different conductivity types of the lateral region 7b of the second layer 4 and the central region 7a of the second layer 4 the band profile within the active region 5 changes from a central region of the active region 5 adj acent to the central region 7a of the second layer 4 to a lateral region of the active region 5 adj acent to the lateral region 7b of the second layer 4 creating a barrier close to side surface 11c of the active region 5 for a lateral transport of charge carriers . Together with the second contact layer 9 , via which a potential can be applied to the central region 7a of the second layer 4 , and which is electrically isolated from the lateral region 7b of the second layer 4 at least when operating the optoelectronic device 1 in an ON-state , this allows for mostly a vertical electron and hole transport through the active region 5 as no or almost no current flows 2024PF00929 through the lateral region 7b of the second layer 4 but through rts remaining central region 7a and causes a reduction of non-radiative recombination at the side surface 11c of the active region 5 .

[0091] In addition to the embodiment shown in Figure 1A the active region 5 of the embodiment shown in Figure IB comprises a lateral region 13 adj acent to the lateral region 7b od the second layer 4 that is doped with a dopant of the first conductivity type . The doping can thereby result from a diffusion of the dopant of the first conductivity type already present in the lateral region 7b od the second layer 4 . The doping of the lateral region 13 of the active region thereby causes an even larger change of the band profile within the active region 5 from a central region of the active region 5 adj acent to the central region 7a of the second layer 4 to the lateral region 13 of the active region 5 creating an even larger barrier close to side surface 11c of the active region 5 for a lateral transport of charge carriers .

[0092] Figures 2A to 2G show steps of a method for manufacturing an optoelectronic device 1 in accordance with some aspects of the proposed principle . In a first step , shown in Figure 2A, a semiconductor layer stack 2 is provided on a growth substrate 15 . The semiconductor layer stack 2 comprises , arranged on the growth substrate 15 in the following order, a first layer 3 of a first conductivity type , an active region 5 comprising one or more quantum wells , and a base material of a later central region of a second layer 4 that is of a second conductivity type . By means of the wavy side surfaces of the semiconductor layer stack 2 , as indicated in the Figures , it is to be understood that only a section of the semiconductor layer stack 2 is shown here and that the semiconductor layer stack 2 may be extended to any side of the drawn embodiments .

[0093] The first conductivity type is thereby in particular an n-type and the second conductivity type is a p-type . The first layer 3 can thus be a n-type semiconductor layer and the base material of a later central region of the second layer 4 can be a p-type semiconductor layer . The active region 5 and in particular the quantum well ( s ) included therein 2024PF00929 can m particular be configured to emit l ght of a f rst wavelength when provided with a respective current supply .

[0094] In a further step, shown in Figure 2B, the semiconductor layer stack 2 and in particular the base material of the later central region of the second layer 4 is structured thereby remaining a third portion 19a of the base material of the later central region of the second layer 4 and removing a fourth portion 19b of the base material of the later central region of the second layer 4 adj acent to the third portion 19a . This structuring results in at least one island of the base material of the later central region of the second layer 4 of the second conductivity type being arranged on the active region 5 . It is however to be understood that also several of such islands can be arranged next to each other even though it is not explicitly depicted in the Figures .

[0095] In a further step , shown in Figure 2C , a base material of the later lateral region of the second layer 4 of the first conductivity type is then regrown on / in the removed fourth portion 19b laterally enclosing the island ( s ) of the base material of the later central region of the second layer 4 that is of the second conductivity type .

[0096] Then, as shown in Figure 2D, the semiconductor layer stack 2 is structured thereby remaining a first portion 17a of the semiconductor layer stack 2 and removing a second portion 17b of the semiconductor layer stack 2 adj acent to the first portion 17a . This structuring results in a top surface Ila and an exposed side surface 11c of the first portion 17a defining the semiconductor layer stack structure of a later optoelectronic device with the second layer 4 comprising a central region 7a of a material of the second conductivity as well as a lateral region 7b surrounding the central region 7a of a material of the first conductivity type . The side surface 11c comprises / extends through the first layer 3 , the active region 5 and through the lateral region 7b of the second layer 4 and in the explicit embodiment shown extends until the growth substrate . It is however to be understood that the etching can also stop before reaching the growth substrate 15 such that several of such first portions 17a can be still connected via a common residue of the first layer 3 or that the etching can go partly 2024PF00929 24 into the growth substrate 15 . Still , several of such first portions 17a can still be connected at least via the growth substrate 15 even if only one of such portions il7a s explicitly depicted .

[0097] The second structuring in particular comprises a step of mesa etching the semiconductor layer stack 2 using a wet or dry chemical etchant , resulting in the side surface 11c comprising the first layer 3 , the active region 5 and the lateral region 7b of the second layer 4 .

[0098] In a further step, shown in Figure 2E , a passivation layer 14 is then deposited on the side surface 11c as well as on the top surface I la , wherein the passivation layer 14 is structured on the top surface Ila to expose a portion of the central region 7a of the second layer 4 . A second contact layer 9 is then provided on the exposed portion of the central region 7a as shown in Figure 2 F, wherein the second contact layer 9 is in particular configured to receive a potential applied to it to drive the later optoelectronic device .

[0099] As shown in Figure 2G, the growth substrate 15 is then removed as well as the first layer 3 is optionally thinned to expose a bottom surface 11b of the semiconductor layer stack 2 and to separate the semiconductor layer stack 2 of an optoelectronic device from the semiconductor layer stack of possibly neighbouring other optoelectronic devices . Then a first contact layer 8 is provided on the bottom surface 11b electrically connecting the first layer and being configured to receive a respectively matching potential applied to it to drive the resulting optoelectronic device ( s ) 1 .

[0100] Figure 3 shows a step of a further embodiment of a method for manufacturing an optoelectronic device 1 in accordance with some aspects of the proposed principle . Figure 3 in particular shows a state / step of a method comparable to that one shown in Figure 1C , wherein in difference to the method shown in Figures 2A to 2G the semiconductor layer stack 2 comprises a sacrificial QW 10 that is arranged between the active region 5 and the second layer 4 . The sacrificial QW 10 allows to conduct the etching step shown in Figure 2B to come as close to the active region 5 as possible without etching 2024PF00929 into it . The sacrificial QW 10 can thus act like kind of an etch stop layer when etching into the base material of the second layer 4 to improve the accuracy and stability of the etching process . The steps shown in Figures 2D to 2G can then conducted in a similar way as already described .

[0101] Figures 4A to 4C show steps of a further embodiment of a method for manufacturing an optoelectronic device 1 in accordance with some aspects of the proposed principle . In a first step, shown in Figure 4A, a semiconductor layer stack 2 is provided on a growth substrate 15 . The semiconductor layer stack 2 comprises , arranged on the growth substrate 15 in the following order , a first layer 3 of a first conductivity type , an active region 5 comprising one or more quantum wells , and a base material of a later lateral region of a second layer 4 that is of the first conductivity type . By means of the wavy side surfaces of the semiconductor layer stack 2 , as indicated in the Figures , it is to be understood that only a section of the semiconductor layer stack 2 is shown here and that the semiconductor layer stack 2 may be extended to any side of the drawn embodiments .

[0102] The first conductivity type is thereby in particular an n-type and the second conductivity type is a p-type . The first layer 3 can thus be a n-type semiconductor layer and the base material of the later lateral region of the second layer 4 can be a n-type semiconductor layer as well . The active region 5 and in particular the quantum well ( s ) included therein can in particular be configured to emit light of a first wavelength when provided with a respective current supply .

[0103] In a further step, shown in Figure 4B, the semiconductor layer stack 2 and in particular the base material of the later lateral region of the second layer 4 is structured thereby remaining a fifth portion 20a of the base material of the later lateral region of the second layer 4 and removing a sixth portion 20b of the base material of the later lateral region of the second layer 4 adj acent to the fifth portion 20a . This structuring results in at least one recess in the base material of the later lateral region of the second layer 4 of the first conductivity type being formed in the base material of the later lateral 2024PF00929 26 region of the second layer 4 on the active region 5 . It is however to be understood that also several of such recesses can be arranged next to each other even though it is not explicitly depicted in the Figures .

[0104] In a further step , shown in Figure 4C , a base material of the later central region of the second layer 4 of a second conductivity type is then regrown in the recess ( es ) and on base material of the later lateral region of the second layer 4 that is of the first conductivity type . It is however to be understood that the base material of the later central region of the second layer 4 of the second conductivity type can also be regrown to only fill the recess ( es ) but does not or not substantially extend onto the base material of the later lateral region of the second layer 4 . The shown structure can then be processed in a way as already described for the steps shown in Figures 2D to 2G to receive a respective optoelectronic device ( s ) .

[0105] Figures 5A to 5C show each a side view of a further embodiment of an embodiment of an optoelectronic device 1 in accordance with some aspects of the proposed principle . The optoelectronics devices 1 shown each comprise a third contact layer 12 being formed on the passivation layer 14 and electrically contacting the lateral region 7b of the second layer 4 but being at least in an ON-state of the optoelectronic device 1 electrically isolated from the second contact layer 9 . In the embodiments shown the third contact layer 12 is in particular formed as a ringlike contact layer electrically contacting the lateral region 7b of the second layer 4 .

[0106] As shown in Figure 5B, the optoelectronic device 1 further comprises a switching element 16 that is configured to electrically connect the second contact layer 9 with the third contact layer in an OFF-state of the optoelectronic device 1 , such that a potential V3applied to the third contact layer 12 equals a potential V2applied to the second contact layer 9 in an OFF-state of the optoelectronic device 1 .

[0107] As shown in Figure 5C , the optoelectronic device 1 further comprises an integrated circuit that is configured to apply a separate potential 2024PF00929 27

[0108] V3to the third contact layer 12 in an OFF-state of the optoelectronic device 1 .

[0109] Both embodiments provide a quasi-ohmic electron current leakage path 5 that is created between the central region 7a and the lateral region 7b of the second layer 4 , so that no or almost no more current flows through the active region 5 when switching off the optoelectronic device 1 but excess charge carriers in the central region 7a of the second layer 4 are discharged via the lateral region 7b of the second0 layer 4 . The potential V3applied to the third contact layer 12 / lateral region 7b can thereby in particular be chosen to cause an excess charge carrier transportation from the central region 7a to the lateral region 7b in a preferred manner compared to a charge carrier transportation through the active region 5 . 5

[0110] 2024PF00929 28

[0111] LIST OF REFERENCES

[0112] 1 optoelectronic device

[0113] 2 semiconductor layer stack

[0114] 3 first layer

[0115] 4 second layer

[0116] 5 active region

[0117] 6 quantum well

[0118] 7a central region

[0119] 7b lateral region

[0120] 8 contact layer

[0121] 9 contact layer

[0122] 10 sacrificial quantum well

[0123] Ila top surface

[0124] 11b bottom surface

[0125] 11c side surface

[0126] 12 contact layer

[0127] 13 lateral region

[0128] 14 passivation layer

[0129] 15 growth substrate

[0130] 16 switch element

[0131] 17a, 17b portion

[0132] 18 integrated circuit

[0133] 19a, 19b portion

[0134] 20a, 20b portion

Claims

2024PF00929 29CLAIMS1. Optoelectronic device (1) , in particular pLED, comprising a semiconductor layer stack (2) of at least: a first layer (3) of a first conductivity type; a second layer (4) ; and an active region (5) comprising at least one quantum well (6) arranged between the first and the second layer (3, 4) and being configured to emit light of a first wavelength; wherein the second layer (4) comprises a central region (7a) of a second conductivity type as well as a lateral region (7b) of the first conductivity type which is adjacent to the active region (5) and laterally surrounds at least portions of the central region (7a) ; wherein the semiconductor layer stack (2) comprises a top surface (Ila) , a bottom surface (11b) opposite the top surface (Ila) and a side surface (11c) extending from the bottom surface (11b) into the direction of the top surface (Ila) and extending through at least the first layer (3) , the active region (5) and the lateral region (7b) of the second layer (4) ; and wherein the optoelectronic device (1) further comprises a first contact layer (8) electrically contacting the first layer (3) and a second contact layer (9) electrically contacting the central region (7a) of the second layer (4) but being electrically isolated from the lateral region (7b) of the second layer (4) .

2. Optoelectronic device (1) according to claim 1, wherein the active region (5) comprises a different electrostatic potential adjacent to the lateral region (7b) of the second layer (4) than adjacent to the central region (7a) of the second layer (4) .

3. Optoelectronic device (1) according to claim 1 or 2, wherein the semiconductor layer stack (2) comprises a sacrificial quantum well (10) arranged adjacent to the active region (5) between the active region (5) and the second layer (4) .2024PF009294. Optoelectronic device (1) according to claim 3, wherein the sacrificial quantum well (10) comprises a larger effective bandgap than the at least one quantum well (6) of the active region (5) .

5. Optoelectronic device (1) according to claim 3 or 4, wherein the sacrificial quantum well (10) comprises a doping of the second conductivity type.

6. Optoelectronic device (1) according to any one of claims 3 to 5, wherein the thickness of the sacrificial quantum well (10) is smaller than the thickness of the at least one quantum well (6) of the active region (5) , in particular by a factor of 2.

7. Optoelectronic device (1) according to any one of claims 1 to 6, wherein a lateral region (13) of the active region (5) adjacent to the lateral region (7b) of the second layer (4) comprises a doping of the first conductivity type.

8. Optoelectronic device (1) according to any one of claims 1 to 7, wherein the side surface (11c) extends from the bottom surface (11b) into the direction of the top surface (Ila) through the first layer (3) , the active region (5) , the lateral region (7b) of the second layer (4) and at least a portion of the central region (7a) of the second layer (4) .

9. Optoelectronic device (1) according to any one of claims 1 to 8, further comprising a passivation layer (14) covering the side surface (11c) and extending onto the top surface (Ila) , and in particular extending at least partially between the second contact layer (4) and the lateral region (7b) of the second layer (4) .

10. Optoelectronic device (1) according to any one of claims 1 to 9, further comprising a third contact layer (12) electrically contacting the lateral region (7b) of the second layer (4) but being electrically isolated from the central region (7a) of the second layer (4) .2024PF0092911. Optoelectronic device (1) according to claim 10, further comprising a switch element (16) configured to electrically connect the second and the third contact layer (9, 12) .

12. Optoelectronic device (1) according to claim 10, further comprising an integrated circuit (18) configured to apply a different potential to the third contact layer (12) than to the second contact layer (9) .

13. Optoelectronic device (1) according to any one of claims 1 to 12, wherein the first conductivity type is an n-type conductivity type and the second conductivity type is a p-type conductivity type.

14. Method for operating an optoelectronic device (1) according to any one of claims 10 to 13 comprising the steps:Switching on the optoelectronic device (1) by providing a respective first potential to the first contact layer (8) and a respective second potential to the second contact layer (9) such that the optoelectronic device (1) emits light of the first wavelength; andSwitching off the optoelectronic device (1) by changing the potentials applied to the first and second contact layers, in particular leaving the potential of the first contact unchanged and modifying the potential of the second contact layer so that their difference drops below the diode turn-on voltage, providing a respective third potential, in particular a potential equal to the first potential, to the first contact layer (8) and a respective fourth potential, in particular a potential such that the difference between the third and fourth potential is below the turn-on voltage of the optoelectronic device, to the second contact layer (9) such that the optoelectronic device (1) does not emit light, wherein for faster switching off of the optoelectronic device (1) the fourth potential is also applied to the third contact layer ( 12 ) , or a fifth potential, in particular different to the third and fourth potential, is applied to the third contact2024PF00929 layer (12) , wherein the fifth potential promotes a charge carrier transportation from the first layer (3) and / or the central region (7a) to the lateral region (7b) in a preferred manner compared to a charge carrier transportation from the central region (7a) to the first layer (3) through the active region (5) .

15. Method for manufacturing an optoelectronic device (1) comprising the steps :Providing on a growth substrate (15) a semiconductor layer stack (2) of at least: a first layer (3) of a first conductivity type, a second layer (4) , and an active region (5) comprising at least one quantum well (6) arranged between the first and the second layer (3, 4) and being configured to emit light of a first wavelength, wherein the second layer (4) comprises a central region (7a) of a second conductivity type as well as a lateral region (7b) of the first conductivity type which is adjacent to the active region (5) and laterally surrounds at least portions of the central region (7a) ;Structuring the semiconductor layer stack (2) thereby remaining at least one first portion (17a) of the semiconductor layer stack (2) and removing a second portion (17b) of the semiconductor layer stack (2) adjacent to the at least one first portion (17a) , resulting in an exposed side surface (11c) of the at least one first portion (17a) comprising at least the first layer (4) , the active region (5) and the lateral region () of the second layer (4) ; and Providing a first contact layer (8) electrically contacting the first layer (3) and a second contact layer (9) electrically contacting the central region (7a) of the second layer (4) but being electrically isolated from the lateral region (7b) of the second layer (4) .

16. Method according to claim 15,2024PF00929 wherein the step of providing the semiconductor layer stack (2) comprises : providing the first layer (3) on the growth substrate (15) and the active region (5) on the first layer (3) as well as providing the material of the central region of the second conductivity type on the active region (5) throughout the active region (5) , structuring the material of the central region (7a) of the second conductivity type on the active region (5) thereby remaining at least one third portion (19a) of the material of the second conductivity type forming the central region (7a) and removing a fourth portion (19b) of the material of the second conductivity type adjacent to the at least one third portion (19a) , providing the material of the lateral region (7b) of the first conductivity type in the removed fourth portion (19b) of the material of the second conductivity type thereby laterally surrounding at least portions of the central region (7a) .

17. Method according to claim 15, wherein the step of providing the semiconductor layer stack (2) comprises : providing the first layer (3) on the growth substrate (15) and the active region (5) on the first layer (3) as well as providing the material of the lateral region (7b) of the first conductivity type on the active region (5) throughout the active region (5) , structuring the material of the lateral region (7b) of the first conductivity type on the active region (5) thereby remaining at least one fifth portion (20a) of the material of the first conductivity type forming the lateral region (7b) and removing a sixth portion (20b) of the material of the first conductivity type adjacent to the at least one fifth portion (20a) , providing the material of the central region (7a) of the second conductivity type in the removed sixth portion (20b) of the material of the first conductivity type such that it is laterally surrounded at least in portions by the material of the lateral region (7b) of the first conductivity type.

18. Method according to claim 16 or 17,2024PF00929 wherein the step of structuring the material of the lateral region (7b) of the first conductivity type or the step of structuring the material of the central region (7a) of the second conductivity type is conducted down to a sacrificial quantum well (10) arranged5 adjacent to the active region (5) between the active region (5) and the material of the lateral region (7b) of the first conductivity type or the material of the central region (7a) of the second conductivity type respectively. 0 19. Method according to any one of claims 15 to 18, wherein step of providing the semiconductor layer stack (2) comprises diffusing a dopant of the first conductivity type from the lateral region (7b) of the second layer (4) into a lateral region (13) of the active region (5) adjacent to the lateral region5 (7b) of the second layer (4) .

20. Method according to any one of claims 15 to 19, further comprising a step of providing third contact layer (12) electrically contacting the lateral region (7b) of the second layer0 (4) but being electrically isolated from the central region (7a) of the second layer (4) .

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