Pixel driving circuit, driving method, display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a pixel driving circuit, a display panel, a display apparatus and a driving method. The pixel driving circuit comprises: a driving sub-circuit, which is electrically connected to a first node, and is used for outputting a driving current under the control of the potential of the first node; a data writing sub-circuit, which is electrically connected to a data line, a first power supply, a first scanning line, a second scanning line and a third scanning line, and is used for using a first power supply voltage to couple a data signal to a second node under the control of a first scanning signal, a second scanning signal and a third scanning signal; a control sub-circuit, which is electrically connected to the driving sub-circuit and a fourth scanning line, and is used for, under the control of a fourth scanning signal, writing the first power supply voltage into the first node by means of the driving sub-circuit and coupling to the first node a potential variation of the second node that is based on the data signal; and a light-emission control sub-circuit, which is electrically connected to a light-emission control line, the driving sub-circuit and a light-emitting element, and is used for writing the driving current into the light-emitting element under the control of a light-emission control signal.

Description

Pixel driving circuit, driving method, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit, driving method, display panel, and display device. Background Technology

[0002] Organic Light Emitting Diode (OLED) displays use driving current provided by the pixel driving circuit to control the OLED's light emission. When a data signal is applied to the driving transistor in the pixel driving circuit, the driving transistor outputs a driving current corresponding to the data signal to the OLED, thereby driving the OLED to emit light of a corresponding brightness.

[0003] When writing data signals to the driving transistor, using data signals to synchronously complete threshold voltage compensation for the driving transistor can reduce display panel flicker. However, the threshold voltage compensation takes a long time, which increases the data signal writing time accordingly, making it difficult to meet the refresh requirements of high refresh rate pixel circuits. Summary of the Invention

[0004] This disclosure provides a pixel driving circuit, driving method, display panel, and display device.

[0005] According to a first aspect, this disclosure provides a pixel driving circuit configured to drive a light-emitting element to emit light. The pixel driving circuit includes: a driving sub-circuit electrically connected to a first node and configured to output a driving current under the control of the potential of the first node; a data writing sub-circuit electrically connected to a data line, a second node, a first power supply, a first scan line, a second scan line, and a third scan line, configured to couple a data signal from the data line to the second node using a first power supply voltage from the first power supply under the control of a first scan signal from the first scan line, a second scan signal from the second scan line, and a third scan signal from the third scan line; a control sub-circuit electrically connected to the first node, the second node, the first power supply, the driving sub-circuit, and a fourth scan line, configured to provide the first power supply voltage to the first node via the driving sub-circuit under the control of a fourth scan signal from the fourth scan line, and to couple the second node to the first node based on the potential change of the data signal; and an emission control sub-circuit electrically connected to an emission control line, the driving sub-circuit, and the light-emitting element, configured to provide a driving current to the light-emitting element under the control of an emission control signal from the emission control line.

[0006] According to a second aspect, this disclosure provides a display panel, including: a scan line configured to provide a scan signal; a data line configured to provide a data signal; a light emission control line configured to provide a light emission control signal; a pixel driving circuit provided in the embodiments of this disclosure; and a light emission element, a first end of which is connected to the pixel driving circuit, and a second end of which is connected to a second power supply.

[0007] According to a third aspect, this disclosure provides a display device, including a display panel provided in embodiments of this disclosure.

[0008] According to a fourth aspect, this disclosure provides a pixel driving method applied to a pixel driving circuit provided in an embodiment of this disclosure. The pixel driving method includes: in a first stage, a first scan signal is at a first level, a second scan signal is at a second level, a third scan signal is at a second level, a fourth scan signal is at a first level, and a light emission control signal is at a first level; in a second stage, a first scan signal is at a second level, a second scan signal is at a first level, a third scan signal is at a second level, a fourth scan signal is at a second level, and a light emission control signal is at a first level; in a third stage, a first scan signal is at a first level, a second scan signal is at a second level, a third scan signal is at a first level, a fourth scan signal is at a first level, and a light emission control signal is at a first level; and in a fourth stage, a first scan signal is at a first level, a second scan signal is at a second level, a third scan signal is at a first level, a fourth scan signal is at a first level, and a light emission control signal is at a second level. Attached Figure Description

[0009] Figure 1 shows a schematic diagram of the pixel circuit according to an embodiment of the present disclosure;

[0010] Figure 2 shows a schematic diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0011] Figure 3 shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

[0012] Figure 4 shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

[0013] Figure 5 shows the signal timing diagram of the pixel circuit in Figure 4;

[0014] Figures 6A to 6D show the equivalent circuit diagrams of the pixel circuit in Figure 4 at different stages;

[0015] Figure 7 shows a simulation diagram of the signal timing in a pixel circuit according to an embodiment of the present disclosure;

[0016] Figure 8 shows a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure;

[0017] Figure 9 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure; and

[0018] Figure 10 shows a schematic flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0020] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0021] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" can refer to a direct connection between two components, or to a connection between two components via one or more other components, wherein the connection method is electrical connection or electrical coupling. Additionally, the two components can also be connected or coupled via wired or wireless means.

[0022] It should be noted that in the description of the embodiments of this disclosure, a node is not an actual component in the circuit, but rather represents a point on a circuit in the circuit diagram. The symbol Data can represent both a data line and the level of a data signal. Similarly, the symbol S1 can represent both the first scan line and the level of the first scan signal, and the symbol ELVSS can represent both the first power supply and the first power supply voltage provided by the first power supply. The following embodiments are the same and will not be described again.

[0023] Figure 1 shows a schematic diagram of the structure of a pixel circuit according to an embodiment of the present disclosure.

[0024] As shown in Figure 1, the pixel circuit 100 includes a pixel driving circuit 10 and a light-emitting element 11.

[0025] In this embodiment of the disclosure, the light-emitting element 11 may be an OLED or other types of current-driven light-emitting elements.

[0026] In this embodiment of the present disclosure, the pixel driving circuit 10 drives the light-emitting element 11 to emit light. The pixel driving circuit 10 includes a driving sub-circuit 101, a data writing sub-circuit 102, a control sub-circuit 103, and a light emission control sub-circuit 104.

[0027] In this embodiment, the driving sub-circuit 101 is electrically connected to the first node N1. Under the control of the potential of the first node N1, the driving sub-circuit 101 outputs a driving current. The driving current flows through the light-emitting element 11 to drive the light-emitting element 11 to emit light.

[0028] In this embodiment, the data writing sub-circuit 102 is electrically connected to the data line Data, the second node N1, the first power supply ELVSS, the first scan line S1, the second scan line S2, and the third scan line S3. Under the control of the first scan signal S1 from the first scan line S1, the second scan signal S2 from the second scan line S2, and the third scan signal S3 from the third scan line S3, the data writing sub-circuit 102 couples the data signal Data from the data line Data to the second node N2 using the first power supply voltage ELVSS of the first power supply ELVSS.

[0029] In this embodiment of the disclosure, the first scan signal S1 can control the data writing sub-circuit 102 to write the data signal Data, the second scan signal S1 can control the data writing sub-circuit 102 to write the first power supply voltage ELVSS, and the third scan signal S3 can control the data writing sub-circuit 102 to couple the data signal Data to the second node N2 using the first power supply voltage ELVSS.

[0030] For example, the first scan signal S1 can control the data writing sub-circuit 102 to write the data signal Data into its own internal node, the second scan signal S1 can control the data writing sub-circuit 102 to write the first power supply voltage ELVSS into its own internal node, and the third scan signal S3 can control the data writing sub-circuit 102 to couple the internal node to the second node N2 based on the potential change of the data signal Data and the first power supply voltage ELVSS, thereby realizing the coupling of the data signal Data to the second node N2.

[0031] In this embodiment, the control sub-circuit 103 is electrically connected to the first node N1, the second node N2, the first power supply ELVSS, the drive sub-circuit 101, and the fourth scan line S4. Under the control of the fourth scan signal S4 from the fourth scan line S4, the control sub-circuit 103 provides the first power supply voltage ELVSS to the first node N1 via the drive sub-circuit 101, and couples the potential change of the second node N2 based on the data signal Data to the first node N1.

[0032] In this embodiment of the disclosure, the control sub-circuit 103 is electrically connected to the first power supply ELVSS via the drive sub-circuit 101. The drive sub-circuit 101 can control the switching between an on / off state and the first power supply ELVSS between the light emission control sub-circuit 104 and the first power supply ELVSS. The control sub-circuit 103 can control the switching between an on / off state and the first node N1 and the drive sub-circuit 101. The drive sub-circuit 101 and the control sub-circuit 103 can jointly control the switching between an on / off state and the first power supply ELVSS between the first node N1 and the first power supply ELVSS.

[0033] For example, under the control of the potential of the first node N1, the driving sub-circuit 103 controls the light-emitting control sub-circuit 104 to be in a connected state with the first power supply ELVSS. At this time, the first power supply voltage ELVSS can be written to the connection point between the control sub-circuit 103 and the driving sub-circuit 101 via the driving sub-circuit 103. Under the control of the fourth scan signal S4, the control sub-circuit 103 controls the first node N1 to be in a connected state with the driving sub-circuit 101. At this time, the potential at the connection point between the control sub-circuit 103 and the driving sub-circuit 101 can be written to the first node N1. In this case, the first power supply voltage ELVSS is written to the first node N1 through the driving sub-circuit 101 and the control sub-circuit 103.

[0034] The driving sub-circuit 101 includes a driving transistor. The first power supply voltage ELVSS passes through the driving transistor in the driving sub-circuit 101, allowing the threshold voltage Vth of the driving transistor to be written into the first node N1, thereby achieving potential compensation of the first node N1 using the threshold voltage Vth of the driving transistor. This reduces the impact of the aging of the driving transistor itself on the output driving current, thus improving the flickering problem of the light-emitting element 11.

[0035] When the fourth scan signal S4 controls the control sub-circuit 103 to be in the off state, the first node N1 can maintain the potential of the previous stage. When the potential of the second node N2 changes, the control sub-circuit 103 can couple the potential change of the second node N2 based on the data signal Data to the first node N1, so that the data signal Data is coupled to the first node N1. At this time, the driving transistor in the driving sub-circuit 101 can output a driving current based on the data signal Data, so that the light-emitting element 11 emits light of corresponding brightness.

[0036] In this embodiment of the disclosure, the light-emitting control sub-circuit 104 is electrically connected to the light-emitting control line EM, the driving sub-circuit 101 and the light-emitting element 11. Under the control of the light-emitting control signal EM from the light-emitting control line EM, the light-emitting control sub-circuit 104 provides driving current to the light-emitting element 11.

[0037] In this embodiment, the first end of the light-emitting element 11 is electrically connected to the light-emitting control sub-circuit 104, and the second end of the light-emitting element 11 is electrically connected to the second power supply ELVDD. The light-emitting control sub-circuit 104 can control the switching between a connected state and a disconnected state between the light-emitting element 11 and the driving sub-circuit 101. For example, under the control of the light-emitting control signal EM, the light-emitting control sub-circuit 104 controls the light-emitting element 11 and the driving sub-circuit 101 to be in a connected state. At this time, a path is formed between the two ends of the light-emitting element 11, and the driving current flows through the light-emitting element 11, driving the light-emitting element 11 to emit light.

[0038] In this embodiment of the disclosure, the second power supply ELVDD can provide a high voltage, and the first power supply ELVSS can provide a low level, such as ground. The voltage provided by the second power supply is higher than the voltage provided by the first power supply.

[0039] In this embodiment, the writing of the data signal Data is controlled by a first scan signal S1, a second scan signal S2, and a third scan signal S3. A fourth scan signal S4 is used to control the compensation of the threshold voltage Vth of the driving transistor. The writing of the data signal Data and the compensation of the threshold voltage Vth are controlled by different scan signals, which separates the writing process of the data signal Data from the compensation process of the threshold voltage Vth. In this case, the writing time of the data signal Data can be shortened, thereby increasing the refresh rate. Furthermore, the compensation of the threshold voltage Vth is achieved using the first power supply voltage ELVSS, and the compensation time of the threshold voltage Vth does not affect the writing time of the data signal Data. This ensures that a sufficiently long time is used to complete the full writing of the threshold voltage Vth while simultaneously shortening the writing time of the data signal Data.

[0040] Figure 2 shows a schematic diagram of the structure of a pixel driving circuit according to an embodiment of the present disclosure.

[0041] As shown in Figure 2, the pixel driving circuit 20 includes a driving sub-circuit 201, a data writing sub-circuit 202, a control sub-circuit 203, and a light emission control sub-circuit 204.

[0042] In this embodiment, the driving sub-circuit 201 and the light-emitting control sub-circuit 204 can refer to the driving sub-circuit 101 and the light-emitting control sub-circuit 104 described above, and similar parts will not be repeated.

[0043] In this embodiment of the disclosure, the data writing sub-circuit 202 includes a first writing unit 221, a second writing unit 222, and a coupling unit 223.

[0044] The first write unit 221 is electrically connected to the first power supply ELVSS, the second scan line S2, and the third node N3. Under the control of the second scan signal S2, the first write unit 221 provides the first power supply voltage ELVSS to the third node N3.

[0045] The second write unit 222 is electrically connected to the data line Data, the first scan line S1, and the third node N3. Under the control of the first scan signal S1, the second write unit 222 writes the data signal Data to the third node N3.

[0046] The coupling unit 223 is electrically connected to the third scan line S3, the second node N2, and the third node N3. Under the control of the third scan signal S3, the coupling unit 223 couples the potential change of the third node N3 based on the data signal Data to the second node N2.

[0047] The first write unit 221 can control the switching between a connected state and a disconnected state between the first power supply ELLVSS and the third node N3. The second write unit 222 can control the switching between a connected state and a disconnected state between the data line Data and the third node N3.

[0048] Under the control of the second scan signal S2, when the first write unit 221 controls the first power supply ELLVSS to be in a connected state with the third node N3, and under the control of the first scan signal S1, the second write unit 222 controls the data line Data to be in a disconnected state with the third node N3, the first power supply voltage ELLVSS is written to the third node N3, and at this time the potential of the third node N3 is the same as the first power supply voltage ELLVSS. Subsequently, under the control of the second scan signal S2, when the first write unit 221 controls the first power supply ELLVSS to be in a disconnected state with the third node N3, and under the control of the first scan signal S1, the second write unit 222 controls the data line Data to be in a connected state with the third node N3, the data signal Data is written to the third node N3, and at this time the potential of the third node N3 jumps from the first power supply voltage ELLVSS to the level voltage of the data signal Data.

[0049] When no signal or voltage is written to the second node N2, if the potential of the third node N3 changes, the coupling unit 233 can couple the potential change of the third node N3 to the second node N2. Since the potential change of the third node N3 is related to the data signal Data, the potential of the coupled second node N2 is also related to the data signal Data.

[0050] For example, coupling unit 223 is also electrically connected to the first power supply ELVSS. Coupling unit 223 can control the switching between a connected state and a disconnected state between the first power supply ELVSS and the second node N2. Under the control of the third scan signal S3, coupling unit 223 controls the first power supply ELVSS to be in a connected state with the second node N2. At this time, the first power supply voltage ELVSS is written into the second node N2, and the potential of the second node N2 is consistent with the first power supply voltage ELVSS. Subsequently, under the control of the third scan signal S3, when coupling unit 223 controls the first power supply ELVSS to be in a disconnected state with the second node N2, if the potential of the third node N3 changes, coupling unit 223 can couple the potential change of the third node N3 to the second node N2.

[0051] In this embodiment of the disclosure, the end time of the coupling unit 223 providing the first power supply voltage ELVSS to the second node N2 is earlier than the start time of the first write unit 221 providing the first power supply voltage ELVSS to the third node N3.

[0052] The moment when coupling unit 223 controls the switching from a connected state to a disconnected state between the first power supply ELVSS and the second node N2 is the end moment when coupling unit 223 supplies the first power supply voltage ELVSS to the second node N2. The moment when the first writing unit 221 supplies the first power supply voltage ELVSS to the third node N3 is the moment when the potential of the third node N3 begins to change. When the first power supply voltage ELVSS stops writing to the second node N2, coupling unit 223 can couple the potential change of the third node N3 to the second node N2.

[0053] In this embodiment of the disclosure, the end time when the first write unit 221 provides the first power supply voltage ELVSS to the third node N3 is earlier than the start time when the second write unit 222 provides the data signal Data to the third node N3.

[0054] The moment when the first writing unit 221 controls the first power supply ELVSS to switch from a connected state to a disconnected state with the third node N3 is the end moment when the first writing unit 221 supplies the first power supply voltage ELVSS to the third node N3. The moment when the second writing unit 222 controls the data line Data to switch from a disconnected state to a connected state with the third node N3 is the start moment when the second writing unit 222 supplies the data signal Data to the third node N3, at which time the writing of the data signal Data is realized. Therefore, the end moment when the first power supply voltage ELVSS is written to the third node N3 is earlier than the start moment when the data signal Data is written to the third node N3, which can avoid the first power supply voltage ELVSS affecting the writing of the data signal Data to the third node N3.

[0055] In this embodiment of the disclosure, the control sub-circuit 203 includes a control unit 231 and a storage unit 232.

[0056] Control unit 231 is electrically connected to the first node N1 and the fourth scan line S4, and is also electrically connected to the first power supply ELVSS via drive sub-circuit 201. Under the control of the fourth scan signal S4, control unit 231 provides the first power supply voltage ELVSS to the first node N1 via drive sub-circuit 201.

[0057] Storage unit 232 is electrically connected to the first node N1 and the second node N2. Storage unit 232 stores the potential of the first node N1 and couples the potential change of the second node N2 based on the data signal to the first node N1.

[0058] In this embodiment, the control unit 231 can control the switching between a connected state and a disconnected state between the first node N1 and the driving sub-circuit 201. The first power supply ELVSS is connected to the first node N1 via the driving sub-circuit 201 and the control unit 231. Under the control of the potential of the first node N1, the driving sub-circuit 201 controls the control unit 231 to be in a connected state with the first power supply ELVSS. Under the control of the fourth scan signal S4, the control unit 231 controls the first node N1 to be in a connected state with the driving sub-circuit 201. At this time, the first node N1 and the first power supply ELVSS are in a connected state. The first power supply voltage ELVSS is written to the first node N1 through the driving sub-circuit 201 and the control unit 231. Since the first power supply voltage ELVSS passes through the driving transistor in the driving sub-circuit 201, the threshold voltage Vth of the driving transistor is also written to the first node N1. At this time, the potential of the first node N1 is the sum of the threshold voltage Vth and the first power supply voltage ELVSS, thereby achieving potential compensation of the first node N1 using the threshold voltage Vth.

[0059] The first power supply voltage ELVSS and the threshold voltage Vth are stored in the storage unit 232. Under the control of the voltage stored in the storage unit 232, the potential of the first node N1 can be maintained as the sum of the threshold voltage Vth and the first power supply voltage ELVSS.

[0060] When the first power supply ELVSS is disconnected from the first node N1, the potential of the first node N1 is not affected by the first power supply ELVSS. If the potential of the second node N2 changes, the potential of the first node N1 will also change accordingly.

[0061] In this embodiment of the disclosure, the control unit 231 in the control sub-circuit 203 provides the first power supply voltage ELVSS to the first node N1 via the drive sub-circuit 201 at a time earlier than the second write unit 222 provides the data signal Data to the third node N3 at a time earlier than the time when the second write unit 222 provides the data signal Data.

[0062] The moment when the control unit 231 and the drive sub-circuit 201 control the first node N1 to switch from the disconnected state to the connected state with the first power supply ELVSS is the moment when the control unit 231 in the control sub-circuit 203 provides the first power supply voltage ELVSS to the first node N1 through the drive sub-circuit 201. At this time, the potential of the first node N1 is compensated using the threshold voltage Vth.

[0063] The moment when the second writing unit 222 controls the data line Data to switch from a disconnected state to a connected state with the third node N3 is the start moment when the second writing unit 222 provides the data signal Data to the third node N3. At this time, the data signal Data is written into the pixel circuit 200.

[0064] Therefore, the threshold voltage Vth compensation for the first node N1 begins earlier than the time when the data signal Data is written into the pixel circuit 200. This increases the compensation duration of the threshold voltage Vth, thereby ensuring that the potential of the first node N1 is fully compensated using the threshold voltage Vth.

[0065] In this embodiment, if the potential of the third node N3 changes, the coupling unit 223 couples the potential change of the third node N3 to the second node N2. At this time, the storage unit 232 also couples the potential change of the second node N2 to the first node N1. Since the potential change of the third node N3 is related to the data signal Data, the potential changes of the second node N2 and the first node N1 are also related to the data signal Data.

[0066] When the potential of the first node N1 is related to the data signal Data, the driving sub-circuit 201 can output a driving current related to the data signal Data, thereby driving the light-emitting element to emit light of corresponding brightness.

[0067] Figure 3 shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0068] As shown in Figure 3, the pixel circuit 300 includes a pixel driving circuit 30 and a light-emitting element 31.

[0069] In this embodiment of the disclosure, the pixel driving circuit 30 includes a driving sub-circuit 301, a data writing sub-circuit 302, a control sub-circuit 303, a light emission control sub-circuit 304, a first reset sub-circuit 305, and a second reset sub-circuit 306.

[0070] In this embodiment, the driving sub-circuit 301, data writing sub-circuit 302, control sub-circuit 303, and light-emitting control sub-circuit 304 can refer to the driving sub-circuit 101, data writing sub-circuit 102, control sub-circuit 103, and light-emitting control sub-circuit 104 described above, and the light-emitting element 31 can refer to the light-emitting element 21 described above. For the sake of brevity, similar parts will not be described again.

[0071] In this embodiment, the first reset circuit 305 is electrically connected to the first signal line Vinit1, the first node N1, and the fifth scan line S5. Under the control of the fifth scan signal S5 from the fifth scan line S5, the first reset circuit 305 provides the first signal Vinit1 from the first signal line Vinit1 to the first node N1.

[0072] The first reset circuit 305 can control the connection or disconnection between the first signal line Vinit1 and the first node N1. For example, under the control of the fifth scan signal S5, the first reset circuit 305 controls the first signal line Vinit1 to be in a connected state with the first node N1. At this time, the first signal Vinit1 is written to the first node N1 to initialize the first node N1.

[0073] Under the control of the initialized potential of the first node N1, the driving sub-circuit 301 can control the connection between the first power supply ELVSS and the control sub-circuit 303. When the first node N1 and the first power supply ELVSS are in a connected state, the first power supply voltage ELVSS and the threshold voltage Vth are written to the first node N1, so that the driving sub-circuit 301 controls the writing of the first power supply voltage ELVSS based on the first power supply voltage ELVSS and the threshold voltage Vth.

[0074] In this embodiment of the disclosure, when the pixel driving circuit 30 drives the light-emitting element 31 to emit light for scanning a frame, the potential of the first node N1 carries the data signal Data of this frame. Before scanning the next frame, the first reset sub-circuit 305 initializes the potential of the first node N1 using the first signal Vinit1, thereby setting the potential of the first node N1 to prevent the potential of the first node N1 from carrying the data signal Data of the previous frame during the scanning of the next frame.

[0075] In this embodiment, the second reset circuit 306 is electrically connected to the fifth scan line S5, the second signal line Vinit2, and the first terminal of the light-emitting element 31. Under the control of the fifth scan signal S5 from the fifth scan line S5, the second reset circuit 306 provides the second signal Vinit2 of the second signal line Vinit2 to the first terminal of the light-emitting element 31.

[0076] In this embodiment of the present disclosure, the second end of the light-emitting element 31 is electrically connected to the second power supply ELVDD. For example, the first end of the light-emitting element 31 can be the cathode of the light-emitting element 31, and the second end of the light-emitting element 31 can be the anode of the light-emitting element 31. The anode of the light-emitting element 31 is electrically connected to the second power supply ELVDD, so the anode voltage of the light-emitting element 31 remains constant.

[0077] The second reset circuit 306 can control the second signal line Vinit2 to be in a connected or disconnected state with the cathode of the light-emitting element 31. For example, under the control of the fifth scan signal S5, the second reset circuit 306 controls the second signal line Vinit2 to be in a connected state with the cathode of the light-emitting element 31. At this time, the second signal Vinit2 is written into the cathode of the light-emitting element 31 to initialize the cathode of the light-emitting element 31.

[0078] When scanning a single frame, after the pixel driving circuit 30 drives the light-emitting element 31 to emit light, the potential of the cathode of the light-emitting element 31 is related to the driving current of this frame. Before scanning the next frame, the second reset sub-circuit 306 uses the second signal Vinit2 to reset the potential of the cathode of the light-emitting element 31, so as to avoid the potential of the cathode of the light-emitting element 31 being related to the driving current of the previous frame during the scanning of the next frame, thereby preventing abnormal light emission of the light-emitting element 31.

[0079] In this embodiment of the disclosure, the first signal Vinit1 provided by the first signal line Vinit1 is a constant voltage signal with a high voltage, and the second signal Vinit2 provided by the second signal line Vinit2 is also a constant voltage signal with a high voltage. The voltages of the first signal Vinit1 and the second signal Vinit2 remain unchanged.

[0080] The voltage of the first signal Vinit1 and the voltage of the second signal Vinit2 can be equal or unequal. When the voltage of the first signal Vinit1 and the voltage of the second signal Vinit2 are equal, the first reset circuit 305 and the second reset circuit 306 can be initialized by the same signal line.

[0081] For example, both the first reset circuit 305 and the second reset circuit 306 can be electrically connected to the first signal line Vinit1. The first reset circuit 305 writes the first signal Vinit1 provided by the first signal line Vinit1 into the first node N1, initializing the potential of the first node N1. The second reset circuit 306 writes the first signal Vinit1 provided by the first signal line Vinit1 into the cathode of the light-emitting element 31, initializing the cathode of the light-emitting element 31.

[0082] For example, both the first reset circuit 305 and the second reset circuit 306 can be electrically connected to the second signal line Vinit2. The first reset circuit 305 writes the second signal Vinit2 provided by the second signal line Vinit2 into the first node N1, initializing the potential of the first node N1. The second reset circuit 306 writes the second signal Vinit2 provided by the second signal line Vinit2 into the cathode of the light-emitting element 31, performing a reset and initializing the cathode of the light-emitting element 31.

[0083] In this embodiment, both the first reset circuit 305 and the second reset circuit 306 can be electrically connected to the second power supply ELVDD. The first reset circuit 305 can use the second power supply voltage ELVDD to replace the first signal Vinit1, thereby writing the second power supply voltage ELVDD into the first node N1 to initialize the potential of the first node N1. The second reset circuit 306 can use the second power supply voltage ELVDD to replace the second signal Vinit2, thereby writing the second power supply voltage ELVDD into the cathode of the light-emitting element 31 to initialize the potential of the cathode of the light-emitting element 31.

[0084] In this embodiment of the disclosure, when the first reset circuit 305 and the second reset circuit 306 share the same signal line for initialization, the connection relationship of the signal lines can be simplified, saving wiring space. When the first reset circuit 305 and the second reset circuit 306 share the second power supply voltage ELVDD for initialization, the wiring of signal lines can be reduced, saving wiring space and facilitating the narrowing of the bezel of the display device.

[0085] Figure 4 shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0086] As shown in Figure 4, the pixel circuit 400 includes a pixel driving circuit and an OLED light-emitting element. The pixel circuit 400 is used for sub-pixels of OLED display devices, for example. The OLED light-emitting element can be of various types, such as top-emitting, bottom-emitting, and dual-sided-emitting OLEDs, and can emit red, green, blue, or white light, etc. The embodiments disclosed herein do not limit this.

[0087] In this embodiment of the disclosure, the pixel driving circuit includes a driving sub-circuit 401, a data writing sub-circuit 402, a control sub-circuit 403, a light emission control sub-circuit 404, a first reset sub-circuit 405, and a second reset sub-circuit 406.

[0088] In this embodiment of the disclosure, the data writing sub-circuit 402 includes transistors T1, T2, and T3 and capacitor C1; the control sub-circuit 403 includes transistor T4 and capacitor C2; the driving sub-circuit 401 includes transistor T5; the light emission control sub-circuit 404 includes transistor T6; the first reset sub-circuit 405 includes transistor T7; and the second reset sub-circuit 406 includes transistor T8.

[0089] In this embodiment, transistors T1 through T8 are all N-type transistors. Transistors T1 through T4 and transistors T6 through T8 can all be used as switching transistors, and transistor T5 is a driving transistor.

[0090] The control electrode of transistor T1 is electrically connected to the first scan line S1, the first electrode of transistor T1 is electrically connected to the third node N3, and the second electrode of transistor T1 is electrically connected to the data line Data.

[0091] The control electrode of transistor T2 is electrically connected to the second scan line S2, the first electrode of transistor T2 is electrically connected to the third node N3, and the second electrode of transistor T2 is electrically connected to the first power supply ELVSS.

[0092] The control electrode of transistor T3 is electrically connected to the third scan line S3, the first electrode of transistor T3 is electrically connected to the second node N2, and the second electrode of transistor T3 is electrically connected to the first power supply ELVSS.

[0093] The first terminal of capacitor C1 is electrically connected to the second node N2, and the second terminal of capacitor C1 is electrically connected to the third node N3.

[0094] The control electrode of transistor T4 is electrically connected to the fourth scan line S4, the first electrode of transistor T4 is electrically connected to the first node N1, and the second electrode of transistor T4 is electrically connected to the fourth node N4.

[0095] The first terminal of capacitor C2 is electrically connected to the first node N1, and the second terminal of capacitor C2 is electrically connected to the second node N2.

[0096] The control electrode of transistor T5 is electrically connected to the first node N1, the first electrode of transistor T5 is electrically connected to the fourth node N4, and the second electrode of transistor T5 is electrically connected to the first power supply ELVSS.

[0097] The control electrode of transistor T6 is electrically connected to the light-emitting control line EM, the first electrode of transistor T6 is electrically connected to the cathode (fifth node N5) of the light-emitting element OLED, and the second electrode of transistor T6 is electrically connected to the fourth node N4.

[0098] The control electrode of transistor T7 is electrically connected to the fifth scan line S5, the first electrode of transistor T7 is electrically connected to the initialization line Vinit, and the second electrode of transistor T7 is electrically connected to the first node N1.

[0099] The control electrode of transistor T8 is electrically connected to the fifth scan line S5, the first electrode of transistor T8 is electrically connected to the second power supply ELVDD, and the second electrode of transistor T8 is electrically connected to the cathode (fifth node N5) of the light-emitting element OLED.

[0100] Figure 5 shows the signal timing diagram of the pixel circuit in Figure 4.

[0101] As shown in Figure 5, the display process of each frame of the image can include a first stage Q1, a second stage Q2, a third stage Q3, and a fourth stage Q4. The first stage Q1 can be a reset stage, the second stage Q2 can be a data writing stage, the third stage Q3 can be a coupling stage, and the fourth stage Q4 is a light emission stage. Figure 5 shows the timing waveforms of each signal in each stage.

[0102] Figures 6A to 6D show the equivalent circuit diagrams of the pixel driving circuit at each stage. Specifically, Figure 6A shows the equivalent circuit diagram of the pixel driving circuit in the first stage Q1 according to an embodiment of the present disclosure; Figure 6B shows the equivalent circuit diagram of the pixel driving circuit in the second stage Q2 according to an embodiment of the present disclosure; Figure 6C shows the equivalent circuit diagram of the pixel driving circuit in the third stage Q3 according to an embodiment of the present disclosure; and Figure 6D shows the equivalent circuit diagram of the pixel driving circuit in the fourth stage Q4 according to an embodiment of the present disclosure. The dashed lines with arrows in Figures 6A to 6D indicate the current direction of the pixel circuit in the corresponding stage.

[0103] Next, with reference to FIG5 and FIGS. 6A to 6D, the operation of the pixel driving circuit according to an embodiment of the present disclosure will be described in detail.

[0104] In the first stage Q1, the first scan signal S1 is low, the second scan signal S2 is high, the third scan signal S3 is high, the fourth scan signal S4 is low, the fifth scan signal S5 is high, and the light emission control signal EM is low.

[0105] Under the control of the high level of the fifth scan, transistors T7 and T8 are turned on. At this time, the initialization signal Vinit is written to the first node N1 through transistor T7. Since the initialization signal Vinit is high, the potential of the first node N1 is high. The second power supply voltage ELVDD is written to the fifth node N5 through transistor T8, initializing the cathode of the OLED element, thereby initializing the cathode voltage of the OLED element to the second power supply voltage ELVDD.

[0106] At this point, the voltage difference across the OLED is less than the OLED's threshold voltage, Voled, which is the OLED's emission threshold voltage. This ensures that the OLED will not emit light during the first stage, Q1.

[0107] Under the control of the low level of the first scan signal S1, transistor T1 is turned off. Under the control of the low level of the fourth scan signal S4, transistor T4 is turned off. Under the control of the low level of the light emission control signal EM, transistor T6 is turned off. At this time, under the control of the high level of the first node N1, transistor T5 is turned on. Under the control of the high level of the second scan signal S2, transistor T2 is turned on. Under the control of the third scan signal S3, transistor T3 is turned on. The first power supply voltage ELVSS is written to the second node N2 through transistor T3, the first power supply voltage ELVSS is also written to the third node N3 through transistor T2, and the first power supply voltage ELVSS is written to the fourth node N4 through transistor T5.

[0108] Based on the inherent characteristics of transistor T5 as a driving transistor, the potential of the fourth node N4 increases to ELVSS+Vth, where Vth is the threshold voltage of transistor T5. Since transistor T5 is an N-type transistor in this embodiment, the threshold voltage Vth can be a positive value.

[0109] In the first stage Q1, the light emission control signal EM transitions from high to low earlier than the fifth scan signal S5 transitions from low to high, and also earlier than the third scan signal S3 transitions from low to high. In this case, the turn-off time of transistor T6 is earlier than the turn-on times of transistors T7, T8, and T3. This prevents the second power supply voltage ELVDD from being mistakenly written into the fourth node N4, and also prevents the first power supply voltage ELVSS from being mistakenly written into the fifth node N5.

[0110] In the second stage Q2, the first scan signal S1 is high, the second scan signal S2 is low, the third scan signal S3 is high, the fourth scan signal S4 is high, the fifth scan signal S5 is low, and the light emission control signal EM is low.

[0111] Under the low level control of the fifth scan signal S5, transistors T7 and T8 are turned off. Under the low level control of the light emission control signal EM, transistor T6 is turned off. Under the low level control of the second scan signal S2, transistor T2 is turned off.

[0112] Under the control of the high level of the first scan signal S1, transistor T1 is turned on, and the data signal Data is written to the third node N3 through transistor T1. At this time, the potential of the third node N3 is the voltage value Data of the data signal Data. The moment when the potential of the data signal Data changes to the voltage value Data can be the same as or slightly later than the moment when the first scan signal S1 changes to a high level. The moment when the first scan signal S1 changes from a high level to a low level can be the same as or slightly later than the moment when the voltage value Data of the data signal Data ends.

[0113] Under the control of the high level of the third scan signal S3, transistor T3 is turned on. At this time, the first power supply voltage ELVSS is written into the second node N2 and charges capacitor C1. The potential of the second node N2 remains at the first power supply voltage ELVSS, and the upper plate of capacitor C1 (the plate of capacitor C1 closest to the second node N2) stores the first power supply voltage ELVSS. Understandably, the lower plate of capacitor C2 (the plate of capacitor C2 closest to the second node N2) also stores the first power supply voltage ELVSS.

[0114] Under the control of the fourth scan signal, transistor T4 is turned on. First node N1 remains at the high level of the previous stage, therefore transistor T5 is turned on. In this case, the first power supply voltage ELVSS is written to first node N1 through transistors T5 and T4, and charges capacitor C2. At this time, the potential VN1 of first node N1 becomes ELVSS + Vth. The upper plate of capacitor C2 (the plate of capacitor C2 closest to first node N1) stores the first power supply voltage ELVSS and the threshold voltage Vth of transistor T5. Since the gate voltage of transistor T5 is ELVSS + Vth and the source voltage of transistor T5 is ELVSS, the gate-source voltage of transistor T5 is consistent with the threshold voltage Vth of transistor T5, and transistor T5 remains on.

[0115] In the second stage Q2, the fourth scan signal S4 transitions from low to high earlier than the first scan signal S1. When the high level of the fourth scan signal S4 controls transistor T4 to turn on, the threshold voltage Vth of transistor T5 is written to the first node N1, thereby achieving potential compensation of the first node N1 using the threshold voltage Vth. When the low level of the first scan signal S1 controls transistor T1 to turn on, the data signal Data is written to the third node N3, thereby achieving the writing of the data signal Data.

[0116] Transistor T4 turns on earlier than transistor T1, so the compensation process for the threshold voltage Vth can begin earlier than the writing process for the data signal Data. Since the compensation process for the threshold voltage Vth takes a long time, the compensation time for the threshold voltage Vth can be increased so that the threshold voltage Vth is completely written to the first node N1.

[0117] The compensation process for the threshold voltage Vth and the writing process for the data signal Data are implemented based on different scan signal controls, which separates the compensation process for Vth from the writing process for Data. Increasing the duration of the Vth compensation process can reduce the duration of the Data writing process. By shortening the Data writing duration, the data refresh rate can be increased.

[0118] In the second stage Q2, the second scan signal S2 changes from high level to low level earlier than the first scan signal S1 changes from low level to high level.

[0119] When the low level of the second scan signal S2 controls the transistor T2 to turn off, the first power supply voltage ELVSS stops writing to the third node N3. When the low level of the first scan signal S1 controls the transistor T1 to turn on, the data signal Data is written to the third node N3, thus realizing the writing of the data signal Data. The turn-off of transistor T2 is earlier than the turn-on of transistor T1, which can prevent the first power supply voltage ELVSS from affecting the writing of the data signal Data to the third node N3.

[0120] In the third stage Q3, the first scan signal S1 is low, the second scan signal S2 is high, the third scan signal S3 is low, the fourth scan signal S4 is low, the fifth scan signal S5 is low, and the light emission control signal EM is low.

[0121] Under the control of the low level of the first scan signal S1, transistor T1 is turned off. Under the control of the low level of the third scan signal S3, transistor T3 is turned off. Under the control of the low level of the fourth scan signal S4, transistor T4 is turned off. Because transistor T3 is turned off, under the action of capacitors C1 and C2, the potential of the second node N2 remains at the potential of the second stage Q2. Because transistor T4 is turned off, under the action of capacitor C2, the potential of the first node N1 remains at the potential of the second stage Q2.

[0122] Under the control of the high level of the second scan signal S2, transistor T2 is turned on. The first power supply voltage ELVSS is written to the third node N3. Since the potential of the second node N2 is not affected by the writing of other signals at this time, when the potential of the third node N3 changes, the potential of the second node N2 also changes accordingly under the bootstrap effect of capacitor C1. Since the potential of the first node N1 is not affected by the writing of other signals at this time, when the potential of the second node N3 changes, the potential of the first node N1 also changes accordingly under the bootstrap effect of capacitor C2.

[0123] Therefore, in the third stage Q3, the potential change of the third node N3 causes a potential change in the second node N2 and a potential change in the first node N1. Since capacitors C1 and C2 are connected in series, the sum of the potential changes of the second node N2 and the first node N1 is the same as the potential change of the third node N3.

[0124] In the second stage Q2, the potential of the third node N3 is Data, and in the third stage Q3, the potential of the third node N3 is ELVSS. Therefore, the potential change of the third node N3 is ELVSS - Data. Capacitors C1 and C2 divide this potential change based on their respective capacitances. Therefore, the potential change of the first node N1 is A*(ELVSS - Data), and the potential change of the second node N2 is B*(ELVSS - Data), where A = C2 / (C1 + C2), B = C1 / (C1 + C2), C1 represents the capacitance of capacitor C1, and C2 represents the capacitance of capacitor C2. Therefore, at this time, the potential of the first node N1 is ELVSS + Vth + A*(ELVSS - Data), and the potential of the second node N2 is ELVSS + B*(ELVSS - Data).

[0125] In the third stage Q3, the third scan signal S3 switches from high level to low level earlier than the second scan signal S2 switches from low level to high level.

[0126] When the low level of the third scan signal S3 controls the transistor T2 to turn off, the first power supply voltage ELVSS stops writing to the second node N2. When the high level of the second scan signal S2 controls the transistor T2 to turn on, the first power supply voltage ELVSS is written to the third node N3. The turn-off of transistor T3 precedes the turn-on of transistor T2, which prevents the first power supply voltage ELVSS from being written to the second node N2. This avoids affecting the effect of capacitor C1 writing the potential change of the third node N3 based on the data signal Data and the first power supply voltage ELVSS to the second node N2. Consequently, it also prevents capacitors C1 and C2 from writing the potential change of the third node N3 based on the data signal Data and the first power supply voltage ELVSS to the first node N1. After the data signal Data is coupled to the first node N1, under the control of the first node N1, transistor T5 can output a drive current related to the data signal Data to drive the OLED to emit light.

[0127] In the fourth stage Q4, the first scan signal S1 is low, the second scan signal S2 is high, the third scan signal S3 is low, the fourth scan signal S4 is low, the fifth scan signal S5 is low, and the light emission control signal EM is high.

[0128] Under the control of the low level of the first scan signal S1, transistor T1 is turned off. Under the control of the low level of the third scan signal S3, transistor T3 is turned off. Under the control of the low level of the fourth scan signal S4, transistor T4 is turned off. Under the control of the high level of the second scan signal S2, transistor T2 is turned on, at which time the first power supply voltage ELVSS is written to the third node N3. Due to the off state of transistors T3 and T4, the potential of the third node N3 is stably maintained at the first power supply voltage ELVSS, which allows the potentials of the second node N2 and the first node N1 to also be stably maintained at the potential of the third stage Q3.

[0129] Under the control of the high level of the light emission control signal EM, transistor T6 is turned on. At this time, the drive current path starts from the second power supply ELVDD, is applied to the light-emitting element OLED, and then passes through transistors T6 and T5 to make the light-emitting element OLED emit light.

[0130] At this point, the potential of the first node N1 remains at ELVSS + Vth + A*(ELVSS - Data) from the previous stage. The drive current Id flowing through transistor T5 can be calculated as Id = K(Vgs - Vth). 2The calculation shows that at this point, the gate voltage of transistor T5 is consistent with the potential of the first node N1, and the source voltage of transistor T5 is consistent with the first power supply voltage ELVSS. Therefore, the gate-source voltage of transistor T5 is Vgs = ELVSS + Vth + A*(ELVSS - Data) - ELVSS, and thus the drive current Id = K(Vgs - Vth). 2 =K(Vth+A*(ELVSS-Data)-Vth) 2 =K*A 2 *(ELVSS-Data) 2 Wherein, K is a parameter related to the process and design of transistor T5, and once transistor T5 is manufactured, this parameter K is a constant.

[0131] It can be seen that the above driving current I DS The threshold voltage Vth of transistor T5 is irrelevant. Therefore, by compensating for the threshold voltage Vth of transistor T5, the pixel driving circuit according to the embodiments of this disclosure can solve the problem of threshold voltage drift caused by the driving transistor due to process technology and long-term operation, eliminate its influence on the driving current Id, and thereby improve the display effect of the display device using it.

[0132] In the description of the embodiments disclosed herein, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0133] In the pixel circuit 400 shown in Figure 4, the pixel circuit includes multiple transistors of the same type. For example, transistors T1 to T8 are all N-type transistors, such as thin-film transistors with an active layer of indium gallium zinc oxide (IGZO). Those skilled in the art will understand that, according to the embodiments of this disclosure, transistors T1 to T8 can also be P-type transistors, such as thin-film transistors with an active layer of low-temperature doped polysilicon (LTPS), by correspondingly changing the level of the gate conduction signal of each transistor.

[0134] When the driving transistor is a P-type transistor, the source of the driving transistor is electrically connected to the second power supply ELVDD, the drain of the driving transistor is electrically connected to the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected to the first power supply ELVSS.

[0135] In this embodiment of the disclosure, the data signal writing process (second stage Q2) and the process of coupling the data signal to the first node N1 (third stage Q3) are performed separately. Therefore, the process of coupling the data signal to the first node N1 will not affect the data signal writing process. Thus, the data signal writing process can be shortened according to actual needs, thereby realizing high-frequency writing of the data signal.

[0136] Referring to Figure 5, the write duration of the data signal Data is determined by the high level of the first scan signal S1. For adjacent pixel circuits in the same row of the pixel array, shortening the write duration of the data signal Data can shorten the duration of the high level (active level) of the first scan signal. By controlling the active levels of the applied first scan signals S1 to be different from each other simultaneously, and by controlling the active levels of other scan signals to partially overlap, for example, by shortening the time interval between the transitions of the applied second scan signals S2 to active levels, the time interval for completing the scan of two adjacent pixel circuits can be shortened, thereby shortening the time to scan one frame and increasing the refresh rate.

[0137] Figure 7 shows a simulation diagram of the signal timing in a pixel circuit according to an embodiment of the present disclosure.

[0138] As shown in Figure 7, the timing sequence of the changes in the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, the fifth scan signal S5 and the light emission control signal can be referred to Figure 5. Similar parts will not be repeated here.

[0139] Figure 7 also shows the changes in the potential of the first node N1, the potential of the second node N2, the potential of the third node N3, and the current value of the drive current Id when the voltage value of the data signal Data is -1V, -1.5V, -2V, -3V, and -3.5V, respectively.

[0140] In this embodiment of the disclosure, when the voltage value Data of the data signal Data changes, the potentials of the first node N1, the second node N2, the third node N3, and the current value of the driving current Id will change accordingly. The changes in the potentials of the first node N1, the second node N2, and the third node N3 at different stages can be referred to the foregoing description.

[0141] In this embodiment, the voltage value Data of the data signal Data is always negative. As the voltage value Data of the data signal Data decreases, the potentials of the first node N1 and the second node N2 gradually increase during the coupling phase, and the current value of the driving current Id also gradually increases during the light emission phase. During the data writing phase, the potential change of the third node N3 is consistent with the corresponding voltage value Data of the data signal Data.

[0142] In this embodiment of the disclosure, when the voltage value Data of the data signal Data changes, the potential of the first node N1 and the current value of the driving current Id also change accordingly, which causes the brightness of the light emitted by the light-emitting element to change accordingly.

[0143] Figure 8 shows a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure.

[0144] As shown in Figure 8, the display panel 800 includes scan lines SL1 to SLn, data lines DL1 to DLm, light emission control lines EM1 to EMn, and a pixel array. Here, m and n are positive integers.

[0145] The pixel array includes multiple pixel circuits arranged in an array, each pixel circuit including a pixel driving circuit and a light-emitting element. Pixel circuits can be referenced to pixel circuits 100, 300, and 400 described above. A first end of the light-emitting element is connected to the pixel driving circuit, and a second end of the light-emitting element is connected to a second power supply.

[0146] In this embodiment of the disclosure, scan lines SL1 to SLn provide scan signals, such as the first scan signal, second scan signal, third scan signal, fourth scan signal, and fifth scan signal described above. Data lines DL1 to DLn provide data signals, such as the data signal Data described above. Light emission control lines EM1 to EMn provide light emission control signals, such as the light emission control signal EM described above.

[0147] Figure 9 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0148] As shown in FIG9, the display device 900 according to an embodiment of the present disclosure may include a display panel 910, a scan driver 920, a data driver 930, a light emission control driver 940, a controller 950, and a power supply 960 that provides an external voltage to the display device 900.

[0149] The display panel 910 includes scan lines SL1-SLn, data lines DL1-DLm, light emission control lines EM1-EMn, and multiple pixel circuits. Scan lines SL1-SLn are configured to provide scan signals. Each scan line SLn may include multiple scan sub-lines, which are respectively used to provide the first scan signal, second scan signal, third scan signal, fourth scan signal, and fifth scan signal in the above embodiments. Data lines DL1-DLm are configured to provide data signals, and control signal lines EM1-EMn are configured to provide light emission control signals. The pixel driving circuits in the pixel circuits include any of the pixel driving circuits provided in the embodiments corresponding to Figures 1, 2, 3, and 4. Here, m and n are positive integers.

[0150] Multiple pixel circuits are supplied with external voltages, such as a first power supply voltage ELVSS, a second power supply voltage ELVDD, a first signal voltage Vinit1, and a second signal voltage Vinit2 from power supply 960. The second power supply voltage ELVDD can be higher than the first power supply voltage ELVSS. The first signal voltage Vinit1 and the second signal voltage Vinit2 can be equal or different, and the first signal voltage Vinit1 and the second signal voltage Vinit2 can be the same as the second power supply voltage ELVDD. Power supply 960 can provide the second power supply voltage ELVSS to the display panel 910 as the first signal voltage Vinit1 and the second signal voltage Vinit2.

[0151] The display panel 910 includes a plurality of pixel circuits arranged in an approximately matrix form. A plurality of scan lines SL1 to SLn extend substantially in a row in a first direction, thus being parallel to each other, and a plurality of data lines extend substantially in a column in a second direction intersecting the first direction, thus being parallel to each other in the arrangement of pixels. However, embodiments of this disclosure are not limited thereto.

[0152] Pixel circuits are respectively connected to a plurality of scan lines SL1 to SLn for transmitting scan signals to the display panel 910. Each pixel circuit is connected to the scan line corresponding to the corresponding pixel row, and each pixel is also connected to the scan line of the previous row. However, embodiments of this disclosure are not limited thereto.

[0153] In addition, each pixel in the multiple pixel circuits is connected to one of the multiple data lines DL1 to DLm that transmit data signals to the display panel 910, and to one of the multiple light emission control lines EM1 to EMn that transmit light emission control signals to the display panel 910.

[0154] The scan driver 920 generates multiple corresponding scan signals and transmits these signals to the pixel circuits via multiple scan lines SL1 to SLn. The data driver 930 transmits data signals to each pixel via multiple data lines DL1 to DLm. The light emission control driver 940 generates light emission control signals and transmits these signals to each pixel circuit via multiple light emission control lines EM1 to EMn.

[0155] The controller 950 converts (or modifies) multiple video signals R, G, and B transmitted from an external source into multiple image data signals DR, DG, and DB, and transmits these signals to the data driver 930. Furthermore, the controller 950 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK to generate control signals, thereby controlling the operation of the scan driver 920, the data driver 930, and the light emission control driver 940. In other words, the controller 950 generates and transmits a scan drive control signal SCS to control the scan driver 920, a data drive control signal DCS to control the data driver 930, and a light emission control signal ECS to control the light emission control driver 940.

[0156] Based on the data signals transmitted through multiple data lines DL1 to DLm, the multiple pixels emit light with brightness (e.g., a predetermined brightness) by providing a driving current to the light-emitting element in each pixel.

[0157] The display device 900 according to the embodiments of this disclosure can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0158] Figure 10 shows a schematic flowchart of a driving method according to an embodiment of the present disclosure.

[0159] As shown in Figure 10, the driving method includes steps S1010 to S1040.

[0160] In this embodiment of the disclosure, the driving method can be applied to the pixel driving circuit 10, pixel driving circuit 20, pixel driving circuit 30 and pixel circuit 400 described above.

[0161] During operation of S1010, in the first stage, the first scan signal is at the first level, the second scan signal is at the second level, the third scan signal is at the second level, the fourth scan signal is at the first level, and the light emission control signal is at the first level.

[0162] During operation S1020, in the second stage, the first scan signal is at the second level, the second scan signal is at the first level, the third scan signal is at the second level, the fourth scan signal is at the second level, and the light emission control signal is at the first level.

[0163] When operating S1030, the first scan signal is at the first level, the second scan signal is at the second level, the third scan signal is at the first level, the fourth scan signal is at the first level, and the light emission control signal is at the first level.

[0164] In operation S1040, in the fourth stage, the first scan signal is at the first level, the second scan signal is at the second level, the third scan signal is at the first level, the fourth scan signal is at the first level, and the light emission control signal is at the second level.

[0165] In this embodiment of the disclosure, steps S1010 to S1040 are similar to the operations performed by the pixel driving circuit 10, pixel driving circuit 20, pixel driving circuit 30 and pixel driving circuit 40 described above, and will not be repeated here.

[0166] For example, the first level is low and the second level is high.

[0167] In this embodiment of the disclosure, in the second stage, the fourth scan signal switches from the first level to the second level earlier than the first scan signal switches from the first level to the second level. Also in the second stage, the second scan signal switches from the second level to the first level earlier than the first scan signal switches from the first level to the second level. In the third stage, the third scan signal switches from the second level to the first level earlier than the second scan signal switches from the first level to the second level.

[0168] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and combinations of blocks in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0169] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0170] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A pixel driving circuit configured to drive a light emitting element to emit light, the pixel driving circuit comprising: a driving sub-circuit electrically connected to a first node, the driving sub-circuit configured to output a driving current under control of an electric potential of the first node; a data writing sub-circuit electrically connected to a data line, a second node, a first power supply, a first scan line, a second scan line, and a third scan line, the data writing sub-circuit configured to couple a data signal from the data line to the second node using a first power supply voltage of the first power supply under control of a first scan signal from the first scan line, a second scan signal from the second scan line, and a third scan signal from the third scan line; a control sub-circuit electrically connected to the first node, the second node, the first power supply, the driving sub-circuit, and a fourth scan line, the control sub-circuit configured to provide the first power supply voltage to the first node via the driving sub-circuit and to couple the second node to the first node based on a potential change of the data signal under control of a fourth scan signal from the fourth scan line; a light emitting control sub-circuit electrically connected to a light emitting control line, the driving sub-circuit, and the light emitting element, the light emitting control sub-circuit configured to provide the driving current to the light emitting element under control of a light emitting control signal from the light emitting control line.

2. The pixel driving circuit according to claim 1, wherein the data writing sub-circuit comprises: a first writing unit electrically connected to the first power supply, the second scan line, and a third node, the first writing unit configured to provide the first power supply voltage to the third node under control of the second scan signal; a second writing unit electrically connected to the data line, the first scan line, and the third node, the second writing unit configured to provide the data signal to the third node under control of the first scan signal; and a coupling unit electrically connected to the third scan line, the second node, and the third node, the coupling unit configured to couple the third node to the second node based on a potential change of the data signal under control of the third scan signal.

3. The pixel driving circuit of claim 1, wherein, the control sub-circuit comprises: a control unit electrically connected to the first node and the fourth scan line, and electrically connected to the first power supply via the driving sub-circuit, the control unit configured to provide the first power supply voltage to the first node via the driving sub-circuit under control of the fourth scan signal; and a storage unit electrically connected to the first node and the second node, the storage unit configured to store an electric potential of the first node and to couple the second node to the first node based on a potential change of the data signal.

4. The pixel driving circuit of claim 1, further comprising: a first reset sub-circuit electrically connected to a first signal line, the first node, and a fifth scan line, the first reset sub-circuit configured to provide a first signal from the first signal line to the first node under control of a fifth scan signal from the fifth scan line.

5. The pixel driving circuit of claim 1, further comprising a second reset sub-circuit electrically connected to the fifth scan line, the second signal line, and the first terminal of the light emitting element, the second reset sub-circuit configured to provide a second signal of the second signal line to the first terminal of the light emitting element under control of a fifth scan signal from the fifth scan line. wherein The second terminal of the light emitting element is electrically connected to a second power supply.

6. The pixel driving method of claim 2, wherein the start time of the control sub-circuit providing the first power voltage to the first node via the driving sub-circuit is earlier than the start time of the second write unit providing the data signal to the third node; and the end time of the first write unit providing the first power voltage to the third node is earlier than the start time of the second write unit providing the data signal to the third node.

7. The pixel driving method according to claim 2, wherein The coupling unit is further configured to provide the first power voltage to the second node under control of the third scan signal. The end time of the coupling unit providing the first power voltage to the second node is earlier than the start time of the first write unit providing the first power voltage to the third node.

8. The pixel driving circuit of claim 2, wherein, The data write sub-circuit comprises a first transistor, a second transistor, a third transistor, and a first capacitor; The control electrode of the first transistor is electrically connected to the first scan line, the first electrode of the first transistor is electrically connected to the third node, and the second electrode of the first transistor is electrically connected to the data line. The control electrode of the second transistor is electrically connected to the second scan line, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first power supply. The control electrode of the third transistor is electrically connected to the third scan line, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the first power supply; and The first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the third node.

9. The pixel driving circuit of claim 3, wherein, The control sub-circuit comprises a fourth transistor and a second capacitor; The control electrode of the fourth transistor is electrically connected to the fourth scan line, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to a fourth node; and The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the second node.

10. The pixel driving circuit of claim 4, wherein, The first reset sub-circuit comprises a fifth transistor; The control electrode of the fifth transistor is electrically connected to the fifth scan line, the first electrode of the fifth transistor is electrically connected to the first signal line, and the second electrode of the fifth transistor is electrically connected to the first node.

11. The pixel driving circuit of claim 5, wherein, The second reset sub-circuit comprises a sixth transistor; The control electrode of the sixth transistor is electrically connected to the sixth scan line, the first electrode of the sixth transistor is electrically connected to the second signal line, and the second electrode of the sixth transistor is electrically connected to the first node. The control electrode of the sixth transistor is electrically connected to the fifth scan line, the first electrode of the sixth transistor is electrically connected to the second signal line, and the second electrode of the sixth transistor is electrically connected to the first end of the light emitting element.

12. The pixel driving circuit of claim 1, wherein, The driving sub-circuit comprises a seventh transistor, the control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to a fourth node, and the second electrode of the seventh transistor is electrically connected to the first power supply; The light emitting control sub-circuit comprises an eighth transistor, the control electrode of the eighth transistor is electrically connected to the light emitting control line, the first electrode of the eighth transistor is electrically connected to the first end of the light emitting element, and the second electrode of the eighth transistor is electrically connected to the fourth node.

13. A display panel, comprising: a scan line configured to provide a scan signal; a data line configured to provide a data signal; a light emitting control line configured to provide a light emitting control signal; a pixel driving circuit according to any one of claims 1-12; and a light emitting element, a first end of the light emitting element being connected to the pixel driving circuit, and a second end of the light emitting element being connected to a second power supply.

14. A display device, comprising the display panel of claim 13.

15. A pixel driving method applied to the pixel driving circuit of any one of claims 1-12, the pixel driving method comprising: in a first stage, a first scan signal is at a first level, a second scan signal is at a second level, a third scan signal is at the second level, a fourth scan signal is at the first level, and a light emitting control signal is at the first level; in a second stage, the first scan signal is at the second level, the second scan signal is at the first level, the third scan signal is at the second level, the fourth scan signal is at the second level, and the light emitting control signal is at the first level; in a third stage, the first scan signal is at the first level, the second scan signal is at the second level, the third scan signal is at the first level, the fourth scan signal is at the first level, and the light emitting control signal is at the first level; and in a fourth stage, the first scan signal is at the first level, the second scan signal is at the second level, the third scan signal is at the first level, the fourth scan signal is at the first level, and the light emitting control signal is at the second level. ​ ​

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