Wafer test data processing method and apparatus, and electronic device and medium
By employing a B/S architecture and memory optimization techniques, the memory overflow problem in traditional C/S architectures when processing large-scale wafer test data has been resolved, improving system processing efficiency and stability while reducing costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HANGZHOU LUNTEK TECH
- Filing Date
- 2026-02-11
- Publication Date
- 2026-06-04
AI Technical Summary
Traditional client-server architectures are prone to memory overflows when processing large-scale wafer test data, leading to system crashes or performance degradation.
Employing a B/S architecture and memory optimization techniques, it optimizes memory usage and data processing workflows through data block processing, streaming processing, and asynchronous generation, including data partitioning, transformation, and deletion.
It effectively solves the memory overflow problem, improves the system's processing efficiency and response speed, enhances the system's stability and reliability, and reduces system costs.
Smart Images
Figure CN2026078447_04062026_PF_FP_ABST
Abstract
Description
A method, apparatus, electronic device, and medium for processing wafer test data. Technical Field
[0001] This application relates to the field of wafer testing technology, and more specifically, to a method, apparatus, electronic device, and medium for processing wafer testing data. Background Technology
[0002] Traditional wafer testing systems typically employ a client-server (CS) architecture for test data processing and map generation. However, as the number of dies on a wafer increases, the traditional CS architecture is prone to memory overflow issues when processing large-scale data, leading to system crashes or performance degradation. Summary of the Invention
[0003] The purpose of this application is to provide a method, apparatus, electronic device and medium for processing wafer test data, so as to solve the above-mentioned problems existing in the prior art, and to optimize the memory overflow problem of traditional CS architecture when processing large-scale wafer test data.
[0004] Firstly, a method for processing wafer test data is provided, applied to a data processing system, the data processing system comprising: a scheduling center and a thread pool; the thread pool comprising multiple processing threads; the method may include:
[0005] Acquire a test sequence consisting of test data from multiple DIEs on the target wafer;
[0006] The test sequence is divided into multiple subsequences by dividing the test data into multiple subsequences;
[0007] The test data in each subsequence is transformed to obtain the target subsequence;
[0008] For target subsequences that meet the deletion criteria, deletion is performed in the corresponding processing thread.
[0009] In one possible implementation, the test data in the test sequence is divided into multiple subsequences, including:
[0010] Based on multiple regions pre-configured on the target wafer, multiple test data in the test sequence are divided to obtain multiple sub-sequences.
[0011] In one possible implementation, the method further includes, before processing the subsequences:
[0012] According to the arrangement order of multiple regions pre-configured on the target wafer, multiple sub-sequences are processed to obtain multiple ordered sub-sequences.
[0013] In one possible implementation, the test data in the test sequence is divided into multiple subsequences, including:
[0014] Based on the performance level of the configuration, the parameters in the test data are clustered to obtain multiple subsequences.
[0015] In one possible implementation, the test data in each subsequence is transformed to obtain the target subsequence, including:
[0016] The test data is output in XML format and then converted into the target result in EXCEL format for storage.
[0017] In one possible implementation, the target subsequence that meets the deletion criteria is deleted in the corresponding processing thread, including:
[0018] The target level of each subsequence is determined based on the configured weight values, weight decay factors, and last access time.
[0019] For any subsequence with a target level, if the target level meets the configured elimination level, then the subsequence corresponding to the target level is deleted.
[0020] In one possible implementation, the configured weight values can be either base weights or dynamic weights.
[0021] Secondly, a wafer test data processing apparatus is provided, applied to a data processing system, the data processing system comprising: a scheduling center and a thread pool; the thread pool comprising multiple processing threads; the apparatus may include:
[0022] The acquisition unit is used to acquire a test sequence consisting of test data from multiple DIEs on the target wafer;
[0023] A partitioning unit is used to divide multiple test data in a test sequence into multiple subsequences;
[0024] The transformation unit is used to transform the test data in each subsequence to obtain the target subsequence;
[0025] The deletion unit is used to delete target subsequences that meet the deletion conditions in the corresponding processing thread.
[0026] Thirdly, an electronic device is provided, which includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;
[0027] Memory, used to store computer programs;
[0028] When a processor executes a program stored in memory, it implements any of the steps described in the first aspect above.
[0029] Fourthly, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when executed by a processor, the computer program implements the steps of any of the methods described in the first aspect above.
[0030] This application provides a method for processing wafer test data. The method includes: acquiring a test sequence composed of test data from multiple DIEs on a target wafer; dividing the test data in the test sequence into multiple subsequences; transforming the test data in each subsequence to obtain a target subsequence; and deleting the target subsequence that meets the deletion conditions in the corresponding processing thread. This application effectively solves the memory overflow problem of traditional client-server architectures when processing large-scale wafer test data by using a browser-server architecture and memory optimization techniques. Through data block processing, streaming processing, and asynchronous generation techniques, the system's processing efficiency and response speed are improved. By optimizing memory usage and data processing flow, the system's stability and reliability are enhanced. Attached Figure Description
[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 is a system architecture diagram of a data processing system provided in an embodiment of this application;
[0033] Figure 2 is a flowchart illustrating a wafer test data processing method provided in an embodiment of this application;
[0034] Figure 3 is a schematic diagram of a wafer test data processing device provided in an embodiment of this application;
[0035] Figure 4 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0037] This application provides a method for processing wafer test data, which can be applied to the system architecture shown in Figure 1. As shown in Figure 1, the data processing system may include a scheduling center and a thread pool; the thread pool includes multiple processing threads; each processing thread also includes multiple sub-threads; each sub-thread can be divided according to the type of test data. This data processing system is designed based on a B / S architecture.
[0038] You can also create dedicated thread groups based on the data processing stage (such as cleaning, feature extraction, defect analysis) or data type (electrical parameters, optical inspection data).
[0039] Traditional wafer testing systems typically employ a client-server (CS) architecture for test data processing and map generation. However, as the number of dies on a wafer increases, the traditional CS architecture is prone to memory overflow issues when processing large-scale data, leading to system crashes or performance degradation.
[0040] Therefore, this application provides a method for processing wafer test data to solve the above-mentioned problems existing in the prior art, and can optimize the memory overflow problem of traditional CS architecture when processing large-scale wafer test data.
[0041] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.
[0042] Figure 2 is a flowchart illustrating a wafer test data processing method provided in an embodiment of this application. As shown in Figure 2, the method may include:
[0043] Step S210: Obtain a test sequence consisting of test data of multiple DIEs on the target wafer.
[0044] Specifically, raw test data is collected and stored in a cloud database for subsequent analysis. Typically, this raw test data includes identification information for each DIE (such as coordinates), test item name, test value, pass / fail status, etc.
[0045] In some embodiments, detailed data in the raw test data is processed, for example, by calculating the average and standard deviation of the test values for the same test item across multiple DIEs on the target wafer to obtain statistical data, in order to understand the performance distribution of DIEs across the entire wafer or a portion thereof. This helps to identify DIEs or regions with abnormal performance.
[0046] In another embodiment, the physical layout of each DIE on the target wafer can be analyzed using spatial statistical methods to identify the spatial distribution characteristics of performance and identify factors that may affect product quality (such as uniformity issues in the manufacturing process).
[0047] Step S220: Divide the multiple test data in the test sequence to obtain multiple subsequences.
[0048] There are several ways to divide it:
[0049] A. Based on multiple regions pre-configured on the target wafer, the test data in the test sequence is divided into multiple sub-sequences.
[0050] Specifically, the process of configuring multiple regions of a target wafer based on physical location can include:
[0051] Concentric rings: The standard wafer is divided into multiple concentric rings extending outward from the center. This method helps to analyze radial differences caused by process steps such as etching and deposition.
[0052] Sector-shaped sections: The standard wafer is divided into several sector-shaped sections with equal angles along the diameter. This division method is suitable for identifying process problems related to wafer rotation.
[0053] Then, multiple subsequences can be processed according to the arrangement order of multiple regions pre-configured on the target wafer to obtain multiple subsequences arranged in an ordered manner.
[0054] B. Based on the performance level of the configuration, the parameters in the test data are clustered to obtain multiple subsequences.
[0055] This means dynamically adjusting the regional division scheme based on the analysis results of the raw data. For example, if it is found that defects under certain patterns are concentrated in a certain area, the division of that area can be refined in a targeted manner for in-depth research. Specifically, based on the analysis results, each area can be classified into different levels.
[0056] Then, based on the level of each region, the subsequences can be processed to obtain multiple ordered subsequences.
[0057] Step S230: Transform the test data in each subsequence to obtain the target subsequence.
[0058] Specifically, for any given test data, the test data is output as an XML file, then converted to an Excel file and stored as the target result. This process is performed under a B / S architecture, and the output Excel file is stored locally.
[0059] In some embodiments, the generated Excel file is compatible with different operating systems and software versions. This can be achieved by: first, importing test data in XML format into a database; then, using SQL queries to extract the required test data from the database; and finally, using the database export function to save the test data as a CSV or Excel file.
[0060] In this method, test data is output to an XML file: In order to reduce memory consumption and avoid CPU utilization reaching 100%, writing test data to an XML file can reduce the data processing pressure in memory, while utilizing the storage capacity of the file system to avoid memory overflow problems.
[0061] Step S240: Delete the target subsequence that meets the deletion conditions in the corresponding processing thread.
[0062] Specifically, the following method is implemented by combining the preset caching algorithm with JVM memory management:
[0063] The target level of each subsequence is determined based on the configured weight values, weight decay factors, and last access time.
[0064] Target level = Last access time + Weight decay factor × Weight value;
[0065] Among them, last access time: the core metric of traditional LRU (the smaller the value, the longer it has not been accessed).
[0066] Weight decay factor: A parameter used to balance time and weight (e.g., 0.5).
[0067] Weight value: A predefined or dynamically calculated priority value.
[0068] Among them, the dynamic calculation method can train a weight prediction model (such as random forest) based on historical data and output dynamic weights; features include: DIE position, test parameter variance, and associated batch yield, etc.
[0069] In this method, even if high-weight data has not been accessed for a long time, its elimination priority may still be lower than that of low-weight data.
[0070] Use a priority queue instead of a traditional linked list to sort the targets by priority.
[0071] For any subsequence with a target level, if the target level meets the configured elimination level, then the subsequence corresponding to the target level is deleted.
[0072] If the target level does not meet the configured elimination level, there is no need to delete the subsequences corresponding to the target level.
[0073] In Java, by implementing a pre-defined caching algorithm such as LinkedHashMap and combining it with the JVM's garbage collection mechanism, invalid memory can be cleaned up in a timely manner. Specifically, the LRU caching algorithm prioritizes frequently used data while releasing infrequently used data, thus optimizing memory usage efficiency. In the wafer DIE testing scenario, the traditional LRU algorithm simply evicts the least used entry based on the data access time. However, in real-world applications, there may be a need to retain critical data for extended periods (such as in high-failure-risk DIEs or data in wafer edge areas). In such cases, a weight enhancement mechanism needs to be introduced. While retaining the core logic of LRU, this mechanism dynamically adjusts the eviction priority to prevent critical data from being removed prematurely.
[0074] In another embodiment, the entire configured cache space is first divided into several different regions, each corresponding to a different type of storage rule or eviction policy.
[0075] Protected Area: This area is specifically designed to store critical data that must be retained long-term, such as high-risk die-on-chips (DIEs) and data from wafer edge regions. This data will not be easily replaced unless it meets certain preset conditions (such as reaching its maximum retention period).
[0076] General area: Follows standard LRU or other eviction policies and is used to store general data.
[0077] Within each partition, a weighted mechanism is introduced to further refine data management. Each entry has an associated weight value, which is dynamically adjusted based on its importance. For example:
[0078] For critical data, a higher initial weight can be given when it is placed in the protected area, and its weight can be increased if the data is accessed again in the subsequent process to ensure that it also receives a higher priority in the protected area.
[0079] In the general area, in addition to using time as the basis for elimination, the weight of the item can also be considered. Even if an item has not been accessed recently, if its weight is high (indicating that it is important to the business), then its elimination time can be appropriately postponed.
[0080] Under this hybrid strategy, when the system needs to decide whether to replace a piece of data, it first checks the region where the data is located. If it is in a protected region, replacement will only be considered if its weight is below a certain threshold or other specific conditions are met; if it is in a normal region, the decision is made by comprehensively considering both time and weight factors.
[0081] Furthermore, rules can be set to allow data to migrate between different areas. For example, as business grows, some items that were not originally considered critical data may become very important. In this case, their weight can be increased, and they can eventually be migrated to a protected area to ensure they are not easily lost. In this way, not only can critical data be properly stored, but cache resources can also be effectively utilized, improving the overall system performance and reliability.
[0082] In some embodiments, the edge DIE of the target wafer is preserved;
[0083] Edge DIEs are prone to failure due to process fluctuations, but test data after completion may no longer be actively accessed. Solution: During initialization, mark the edge DIE weight as 3 (center DIE = 1). Even if it is not accessed for 7 days, its priority is still higher than that of the center DIE, which has not been accessed for 3 days.
[0084] In another embodiment, monitoring of DIEs with high failure risk;
[0085] A new defect pattern has emerged in a batch of DIEs, requiring long-term monitoring. Solution: When the number of defects exceeds the configured threshold, automatically increase the weight of all DIEs in that batch. Manually mark critical DIEs as "permanently retained" (weight = ∞, requiring independent management).
[0086] After the corresponding target subsequence is deleted from the processing thread, the thread becomes idle. To improve overall system efficiency and resource utilization, a scheduling center can manage the task allocation of these processing threads. When a processing thread completes processing a subsequence of a specified type, it reports its current status to the scheduling center (e.g., by sending a heartbeat message), indicating that it has become "idle." Upon receiving the status update from the processing thread, the scheduling center makes a decision based on the workload of all processing threads in the system. Specifically, the scheduling center checks if there are other running but heavily loaded processing threads of the same type. If it finds that there is test data of the same type waiting to be processed, and the corresponding processing thread is busy, the scheduling center can retrieve a portion of unprocessed data subsequences from the task queue of the busy thread. Then, this portion of subsequences is reassigned to the processing thread that has just become idle for processing.
[0087] This approach not only prevents some processing threads from remaining idle for extended periods but also reduces the pressure on overloaded threads, resulting in a more even workload distribution. This helps improve the overall system throughput and response speed.
[0088] An asynchronous generation technique is employed, placing the generation of the Excel spreadsheet in a background thread. Through multi-threaded concurrency, the system can continue processing other tasks while the Excel spreadsheet is being generated, thereby improving overall generation efficiency.
[0089] This application provides a method for processing wafer test data. The method includes: acquiring a test sequence composed of test data from multiple DIEs on a target wafer; dividing the multiple test data in the test sequence to obtain multiple subsequences; transforming the test data in each subsequence to obtain a target subsequence; and deleting the target subsequence that meets the deletion conditions in the corresponding processing thread. This application can solve the following problems:
[0090] Memory overflow issue: By using a B / S architecture and memory optimization techniques, the memory overflow problem of traditional CS architecture when processing large-scale wafer test data has been effectively solved.
[0091] Improved system performance: Through technologies such as data block processing, streaming processing, and asynchronous generation, the system's processing efficiency and response speed have been improved.
[0092] Reduced costs: Reduced reliance on hardware resources lowers the overall cost of the system.
[0093] Enhanced system stability: By optimizing memory usage and data processing flow, the stability and reliability of the system are enhanced.
[0094] Corresponding to the above method, this application embodiment also provides a wafer test data processing apparatus, as shown in FIG3, the apparatus comprising:
[0095] Acquisition unit 310 is used to acquire a test sequence consisting of test data of multiple DIEs on the target wafer;
[0096] The partitioning unit 320 is used to partition multiple test data in the test sequence to obtain multiple subsequences;
[0097] The conversion unit 330 is used to convert the test data in each subsequence to obtain the target subsequence;
[0098] The deletion unit 340 is used to delete target subsequences that meet the deletion conditions in the corresponding processing thread.
[0099] The functions of each functional unit of the wafer test data processing device provided in the above embodiments of this application can be implemented through the above method steps. Therefore, the specific working process and beneficial effects of each unit in the wafer test data processing device provided in the embodiments of this application will not be repeated here.
[0100] This application embodiment also provides an electronic device, as shown in FIG4, including a processor 410, a communication interface 420, a memory 430 and a communication bus 440, wherein the processor 410, the communication interface 420 and the memory 430 communicate with each other through the communication bus 440.
[0101] Memory 430 is used to store computer programs;
[0102] When the processor 410 executes the program stored in the memory 430, it performs the following steps:
[0103] Acquire a test sequence consisting of test data from multiple DIEs on the target wafer;
[0104] The test sequence is divided into multiple subsequences by dividing the test data into multiple subsequences;
[0105] The test data in each subsequence is transformed to obtain the target subsequence;
[0106] For target subsequences that meet the deletion criteria, deletion is performed in the corresponding processing thread.
[0107] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.
[0108] The communication interface is used for communication between the aforementioned electronic devices and other devices.
[0109] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.
[0110] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0111] Since the implementation methods and beneficial effects of the various devices in the above embodiments of the electronic device can be achieved by referring to the steps in the embodiments shown in Figure 2, the specific working process and beneficial effects of the electronic device provided in this application embodiment will not be repeated here.
[0112] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform a wafer test data processing method as described in any of the above embodiments.
[0113] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute a wafer test data processing method as described in any of the above embodiments.
[0114] Those skilled in the art will understand that the embodiments in this application can be provided as methods, systems, or computer program products. Therefore, the embodiments in this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments in this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0115] This application describes embodiments of methods, apparatus (systems), and computer program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.
[0116] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.
[0117] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.
[0118] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected," "coupled," or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0119] Although preferred embodiments have been described in this application, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the embodiments in this application are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments in this application.
[0120] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the embodiments of this application and their equivalents, then these modifications and variations are also intended to be included in the embodiments of this application.
Claims
1. A method for processing wafer test data, characterized in that, The method is applied to a data processing system, which includes a scheduling center and a thread pool; the thread pool includes multiple processing threads; the method includes: acquiring a test sequence composed of test data from multiple DIEs on a target wafer; dividing the multiple test data in the test sequence to obtain multiple subsequences; transforming the test data in each subsequence to obtain a target subsequence; and deleting the target subsequence that meets the deletion conditions in the corresponding processing thread.
2. The method as described in claim 1, characterized in that, Multiple test data in the test sequence are divided into multiple subsequences, including: Based on multiple regions pre-configured on the target wafer, multiple test data in the test sequence are divided into multiple subsequences.
3. The method as described in claim 2, characterized in that, Before processing each subsequence, the method further includes: processing the multiple subsequences according to the arrangement order of multiple regions pre-configured on the target wafer to obtain multiple subsequences arranged in an ordered manner.
4. The method as described in claim 1, characterized in that, The test data in the test sequence is divided into multiple subsequences, including: Based on the configured performance level, the parameters in the test data are clustered to obtain multiple subsequences.
5. The method as described in claim 1, characterized in that, The test data in each subsequence is transformed to obtain the target subsequence, including: outputting the test data in XML format and then converting it into the target result in EXCEL format for storage.
6. The method as described in claim 1, characterized in that, For target subsequences that meet the deletion conditions, deletion is performed in the corresponding processing thread, including: determining the target level of each subsequence based on the configured weight value, weight decay factor, and last access time; for any target level of a subsequence, if the target level meets the configured elimination level, then the subsequence corresponding to the target level is deleted.
7. The method as described in claim 6, characterized in that, The configured weight values are either base weights or dynamic weights.
8. A wafer test data processing apparatus, characterized in that, The device is applied to a data processing system, which includes a scheduling center and a thread pool; the thread pool includes multiple processing threads; the device includes: an acquisition unit for acquiring a test sequence composed of test data from multiple DIEs on a target wafer; a partitioning unit for partitioning the multiple test data in the test sequence to obtain multiple subsequences; a transformation unit for transforming the test data in each subsequence to obtain a target subsequence; and a deletion unit for deleting the target subsequence that meets the deletion conditions in the corresponding processing thread.
9. An electronic device, characterized in that, The electronic device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor, when executing the program stored in the memory, implements the steps of the method described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-7.