Chip package design optimization method and apparatus, storage medium, and electronic device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INTERNATIONAL INNOVATION CENTER OF TSINGHUA UNIVERSITY SHANGHAI
- Filing Date
- 2025-01-21
- Publication Date
- 2026-06-11
AI Technical Summary
In the field of semiconductor packaging, mismatch between materials and circuits leads to uneven heat distribution and thermal stress, affecting the reliability and lifespan of chip packaging.
By acquiring circuit and material parameter information, packaging parameter information, and chip thermal management parameter information, thermal simulation and stress simulation are performed to optimize circuit wiring design, pin positions, and chip stack-up or arrangement positions, and iterative optimization is carried out based on simulation results.
This improved the reliability and quality of chip packaging, reduced production costs, and shortened time to market.
Smart Images
Figure CN2025073640_11062026_PF_FP_ABST
Abstract
Description
Optimization methods and apparatus for chip packaging design, storage media, electronic devices
[0001] Cross-references to related applications
[0002] This disclosure claims priority to Chinese Patent Application No. 202411791102.X, filed on December 5, 2024, entitled "Optimization Method and Apparatus for Chip Packaging Design, Storage Medium, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of chip packaging technology, and in particular to a chip packaging design optimization method, a computer-readable storage medium, an electronic device, and a chip packaging design optimization apparatus. Background Technology
[0004] In the field of semiconductor packaging, the matching of protective layer circuitry and materials, back-side process circuitry and materials, bump circuitry and materials, carrier layer circuitry and materials, and cooling system materials is crucial. Mismatches between these components and materials can lead to a variety of problems. For example, a mismatch between protective layer circuitry and materials may prevent the protective layer from effectively dispersing or absorbing heat generated by the chip, resulting in localized overheating. A mismatch between back-side process circuitry and materials may lead to inefficient heat conduction, resulting in uneven heat distribution and localized hot spots. Bumps are critical for connecting the chip to external circuitry; material mismatches may cause asynchronous thermal expansion between the bumps and the chip or packaging substrate, causing mechanical stress. The carrier layer is the foundation supporting the entire chip structure; material mismatches may prevent the carrier layer from evenly dispersing heat, affecting the thermal stability of the entire package. A mismatch between cooling system materials and the chip or other components may lead to inefficient heat conduction, failing to effectively transfer heat away from the heat source.
[0005] Due to the mismatch between the aforementioned materials and circuitry, when the circuit is powered on, the difference in the coefficients of thermal expansion of the different materials will cause internal thermal stress. Under the long-term influence of thermal stress, the circuit may deform, break, or degrade in performance, leading to package failure or shortened lifespan.
[0006] Public content
[0007] This disclosure aims to at least partially address one of the technical problems in the related art. To this end, the first objective of this disclosure is to propose an optimization method for chip packaging design, which involves acquiring circuit and material parameter information, packaging parameter information, and chip thermal management parameter information. Based on the circuit and material parameter information, packaging parameter information, chip thermal management parameter information, and the actual functional yield of the chip, thermal simulation and stress simulation are performed. The circuit wiring design and pin locations, as well as the target stack-up or arrangement positions of the chip, are determined based on the simulation results of the thermal and stress simulations. This improves the reliability and quality of the chip packaging.
[0008] The second objective of this disclosure is to provide a computer-readable storage medium.
[0009] The third objective of this disclosure is to propose an electronic device.
[0010] The fourth objective of this disclosure is to provide an optimization device for chip packaging design.
[0011] To achieve the above objectives, a first aspect of this disclosure proposes an optimization method for chip packaging design. The method includes: acquiring circuit and material parameter information, packaging parameter information, and chip thermal management parameter information; performing thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the actual functional yield of the chip, so as to determine the circuit wiring design and pin positions, as well as the target stack-up or arrangement position of the chip, based on the simulation results of the thermal simulation and stress simulation.
[0012] According to the chip packaging design optimization method of this disclosure, circuit and material parameter information, packaging parameter information, and chip thermal management parameter information are obtained. Based on the circuit and material parameter information, packaging parameter information, chip thermal management parameter information, and the actual functional yield of the chip, thermal simulation and stress simulation are performed. The circuit wiring design and pin locations, as well as the target stack-up or arrangement positions of the chip, are determined based on the simulation results of the thermal and stress simulations. Therefore, this method can improve the reliability and quality of chip packaging.
[0013] In addition, the chip packaging design optimization method according to the above embodiments of this disclosure may also have the following additional technical features:
[0014] According to one embodiment of this disclosure, the acquisition of circuit and material parameter information includes: acquiring protective layer circuit and material information, chip back-side process circuit and material information, circuit bump circuit and material information, and carrier circuit and material information.
[0015] According to one embodiment of this disclosure, obtaining packaging parameter information includes: obtaining packaging material information, wafer stack-up packaging information, and underfill material information.
[0016] According to one embodiment of this disclosure, obtaining chip thermal management parameter information includes: obtaining heat dissipation structure and packaging information.
[0017] According to one embodiment of this disclosure, the step of performing thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the actual functional yield of the chip, in order to determine the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the simulation results of the thermal simulation and stress simulation, further includes: optimizing the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the comparison results of the chip functional yield obtained after simulation and the actual functional yield.
[0018] According to one embodiment of this disclosure, the method further includes: acquiring the probe point coordinates and test information of the test probe chip; performing thermal simulation and stress simulation based on the probe point coordinates and test information of the test probe chip, circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the simulation results of thermal simulation and stress simulation.
[0019] According to one embodiment of this disclosure, the method further includes: optimizing the passivation layer, redistribution layer, bump type and material, package type and material, location of stacked integrated circuits, material of carrier or interposer, and heat dissipation device based on simulation results.
[0020] To achieve the above objectives, a second aspect of this disclosure provides a computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the above-described method for optimizing chip packaging design.
[0021] The computer-readable storage medium according to embodiments of the present disclosure can improve the reliability and quality of chip packaging by implementing the above-described chip packaging design optimization method during execution.
[0022] To achieve the above objectives, an electronic device is provided in a third aspect of this disclosure, including a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the above-described chip packaging design optimization method.
[0023] The electronic device according to the embodiments of this disclosure can improve the reliability and quality of chip packaging by performing the above-described chip packaging design optimization method.
[0024] To achieve the above objectives, a fourth aspect of this disclosure provides an optimization apparatus for chip packaging design. The apparatus includes: an acquisition module for acquiring circuit and material parameter information, packaging parameter information, and chip thermal management parameter information; and a design module for performing thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the chip's functional yield, so as to determine the circuit wiring design and pin positions, as well as the target stack-up or arrangement position of the chip, based on the simulation results of the thermal simulation and stress simulation.
[0025] According to an embodiment of the chip packaging design optimization apparatus of this disclosure, an acquisition module is used to acquire circuit and material parameter information, packaging parameter information, and chip thermal management parameter information. A design module is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the chip's functional yield. Based on the simulation results of the thermal and stress simulations, the device determines the circuit wiring design, pin locations, and the target stack-up or arrangement positions of the chip. Therefore, this apparatus can improve the reliability and quality of chip packaging.
[0026] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description
[0027] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0028] Figure 1 is a flowchart of a chip packaging design optimization method according to an embodiment of the present disclosure;
[0029] Figure 2 is a flowchart of an optimization method for chip packaging design according to a specific example of this disclosure;
[0030] Figure 3 is a block diagram of an electronic device according to an embodiment of the present disclosure;
[0031] Figure 4 is a block diagram of an optimization device for chip packaging design according to an embodiment of the present disclosure. Detailed Implementation
[0032] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.
[0033] The following description, with reference to the accompanying drawings, outlines an optimization method for chip packaging design, a computer-readable storage medium, an electronic device, and an apparatus for optimizing chip packaging design, all based on embodiments of this disclosure.
[0034] Figure 1 is a flowchart of an optimization method for chip packaging design according to an embodiment of the present disclosure.
[0035] As shown in Figure 1, the chip packaging design optimization method of this disclosure embodiment may include the following steps:
[0036] S1, acquire circuit and material parameter information, packaging parameter information and chip thermal management parameter information;
[0037] S2 performs thermal and stress simulations based on circuit and material parameters, packaging parameters, chip thermal management parameters, and the chip's actual functional yield. The simulation results are used to determine the circuit wiring design, pin locations, and the target stack-up or arrangement of the chip.
[0038] Specifically, the process begins by acquiring circuit and material parameter information, packaging parameter information, and chip thermal management parameter information. Circuit and material parameter information may include circuit parameters, such as electrical parameters including resistance, capacitance, inductance, voltage, and current ratings, as well as material properties, such as physical properties (e.g., electrical conductivity, thermal conductivity), chemical stability, thermal properties (e.g., thermal conductivity, coefficient of thermal expansion), and mechanical strength. Packaging parameter information may include packaging structure, such as the package geometry, including dimensions, shape, and internal layout, as well as packaging material information, such as the thermal and mechanical properties of plastics, ceramics, or metals. Chip thermal management parameter information may include heat dissipation structures and thermal interface materials, such as the materials and dimensions of heat sinks, heat pipes, or vapor chambers, and the thermal conductivity of the thermal interface materials.
[0039] After obtaining circuit and material parameter information, packaging parameter information, and chip thermal management parameter information, thermal simulation and stress simulation can be performed based on these parameters and the chip's actual functional yield. During thermal simulation, a detailed thermal simulation model of the chip and package can be constructed based on the collected parameter information, and simulation boundary conditions can be set, including ambient temperature, heat source distribution, and heat dissipation conditions. The thermal simulation is then run to analyze the temperature distribution and heat flow path of the chip under different operating conditions, and to evaluate the thermal stress caused by the mismatch between temperature gradient and coefficient of thermal expansion. Stress simulation can include constructing a mechanical simulation model of the chip and package, considering different mechanical loads and support conditions, inputting mechanical properties such as the material's elastic modulus, Poisson's ratio, and yield strength, and running stress simulation to analyze the stress distribution and deformation of the chip and package under different mechanical conditions.
[0040] Therefore, by performing thermal and stress simulations, the heat distribution generated by the chip during operation can be predicted using simulation technology, and the mechanical stresses that the chip may encounter during manufacturing and use, such as thermal expansion or contraction due to temperature changes, can be simulated. Based on the simulation results of thermal and stress simulations, the circuit routing design and pin locations, as well as the target stack-up or arrangement of the chip, can be determined. For example, optimizing the circuit routing design can reduce thermal resistance and electrical losses, improve signal integrity, determine the optimal pin locations to reduce thermal stress and electrical interference, and, based on the thermal and stress simulation results, determine the optimal stack-up or arrangement of the chip in the package to achieve optimal thermal management and mechanical stability.
[0041] This enables optimal thermal management and mechanical performance, improves chip performance and reliability, and also helps reduce production costs and shorten time to market.
[0042] Furthermore, according to one embodiment of this disclosure, obtaining circuit and material parameter information includes: obtaining protective layer circuit and material information, chip back-side process circuit and material information, circuit bump circuit and material information, and carrier circuit and material information.
[0043] Specifically, circuit and material parameter information is a critical step in the semiconductor packaging design and manufacturing process, essential for ensuring the reliability, performance, and lifespan of the package. When acquiring circuit and material parameter information, information on the sheath circuit and materials, the back-side process circuit and materials, the bump circuit and materials, and the carrier circuit and materials can be obtained. Specifically, sheath circuit information may include the layout, routing design, and electrical parameters (such as resistance, capacitance, and inductance) of the sheath circuit. Sheath material information may include material type, such as polymer, ceramic, or glass. Back-side process circuit and material information includes silicon, metals (aluminum, copper), etc. Bump circuit information may include bump design, such as the shape, size, and layout of the bumps, as well as electrical connections, such as the connection methods between the bumps and the chip and packaging substrate. It may also include electrical parameters, such as the resistance and inductance of the bumps. Bump material information includes material type, such as copper, tin, or gold. The carrier circuit information may include the layout and routing design of the carrier layer circuit, and the carrier material information may include materials such as glass fiber reinforced epoxy resin substrate, BT (Bismaleimide-Triazine) resin, ceramics, etc.
[0044] For example, relevant information can be obtained by acquiring the material's technical specifications from the material supplier, or simulation software can be used to model the performance of the circuit and materials, predicting their performance under actual operating conditions. By combining this information, the package design can be optimized, ensuring the matching between the circuit and materials, and improving the overall performance and reliability of the package.
[0045] Furthermore, according to one embodiment of this disclosure, obtaining packaging parameter information includes: obtaining packaging material information and wafer stack-up packaging information and underfill material information.
[0046] Specifically, in the semiconductor packaging field, obtaining packaging parameter information is a crucial step in ensuring packaging reliability and performance. This information includes packaging material information, wafer stack-up packaging information, and underfill material information. Packaging material information may include substrate material information, such as glass fiber reinforced epoxy substrates and BT resin, as well as packaging shell materials, such as plastics and ceramics, and may also include soldering materials and conductive materials. Wafer stack-up packaging information includes wafer material, wafer size and layout (e.g., dimensions including length, width, and thickness, and layout as single-layer, double-layer, or multi-layer stacking), and wafer protective layers, such as silicon nitride and photoresist. Underfill material information may include material type, such as epoxy resin and acrylic resin, as well as thermal properties, electrical properties (e.g., dielectric constant, loss factor), and chemical properties (e.g., moisture resistance, chemical corrosion resistance).
[0047] For example, relevant information can be obtained by acquiring the technical specifications of materials from material suppliers, or simulation software can be used to model the performance of circuits and materials and predict their performance under actual operating conditions. By combining this information, the packaging design can be optimized to ensure the reliability and performance of the package, while reducing production costs and improving production efficiency.
[0048] Furthermore, according to one embodiment of this disclosure, obtaining chip thermal management parameter information includes: obtaining heat dissipation structure and packaging information.
[0049] Specifically, thermal management is a crucial aspect of semiconductor chip design and packaging, directly impacting chip performance, reliability, and lifespan. Obtaining thermal management parameters reveals information about the heat dissipation structure and packaging. Heat dissipation structure design includes the shape, size, material, and layout of the heat sink, as well as the contact method between the heat sink and the chip. Heat dissipation structure materials include the material's thermal conductivity (which determines the efficiency of heat transfer), coefficient of thermal expansion (ensuring the expansion matching between the heat dissipation structure and the chip during temperature changes), and mechanical strength (ensuring the stability of the heat dissipation structure under mechanical pressure). Packaging information includes the package material, such as plastic, ceramic, or metal; the packaging structure includes the connection between the chip and the package, the internal layout of the package, and the package's thermal characteristics, such as thermal diffusivity (the thermal diffusivity of the packaging material, affecting the speed of heat propagation within the package), thermal capacity (the thermal capacity of the packaging material, affecting the package's response speed to temperature changes), and coefficient of thermal expansion (the coefficient of thermal expansion of the packaging material, affecting the package's stability under temperature changes).
[0050] For example, relevant information can be obtained by acquiring the technical specifications of materials from material suppliers, or simulation software can be used to model the performance of circuits and materials, predicting their performance under actual operating conditions. By combining this information, the chip's heat dissipation design can be optimized, ensuring that the chip maintains good thermal management under various operating conditions, thereby improving the chip's performance and reliability.
[0051] According to one embodiment of this disclosure, thermal simulation and stress simulation are performed based on circuit and material parameter information, packaging parameter information, chip thermal management parameter information, and the actual functional yield of the chip, so as to determine the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the simulation results of thermal simulation and stress simulation. It also includes: optimizing the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the comparison results of the chip functional yield obtained after simulation and the actual functional yield.
[0052] Specifically, after performing thermal and stress simulations based on circuit and material parameters, packaging parameters, chip thermal management parameters, and the chip's actual functional yield, the chip's functional yield, including potential failure modes and failure rates, can be predicted based on the simulation results. The predicted functional yield is then compared with the actual functional yield to identify differences and deviations. Based on the comparison results, iterative optimizations are performed on circuit routing design, pin locations, and chip stack-up or arrangement. Design parameters, such as wiring length, width, material selection, pin layout, and chip location, are adjusted to improve the consistency between simulation and actual functional yield.
[0053] For example, during iterative optimization of circuit routing design, if simulations show hotspots in certain areas, rerouting is performed to distribute heat, such as increasing trace width or changing trace paths. For signal integrity issues, such as crosstalk or reflections, routing is adjusted to reduce these effects, which may include increasing shielding, adjusting trace spacing, or using different insulating materials. Power and ground layouts are optimized to provide stable power distribution and good signal grounding, reducing noise and interference. During iterative optimization of pin locations, based on simulation results, pin locations are adjusted to optimize electrical performance, such as reducing impedance mismatch and signal delay. If certain pin areas overheat, pins are rerouted to improve heat distribution, which may involve changing pin size or repositioning them away from hotspots. The impact of pin locations on mechanical stress is considered to ensure that pin layout does not lead to excessive bending or stress concentration. During iterative optimization of chip stack-up or arrangement, based on comparison results, the chip stack-up or arrangement is adjusted to optimize the overall package heat distribution, ensuring uniform heat distribution and effective conduction to the heat dissipation structure. Consider the impact of chip stacking or arrangement on package mechanical stability, ensure stability under temperature changes and mechanical shocks, and optimize chip placement to reduce signal transmission delay and improve signal integrity, especially in high-speed or high-frequency applications.
[0054] Therefore, through this iterative optimization process, the performance of circuit routing design, pin positions, and chip stacking or arrangement can be gradually improved, ultimately achieving the goal of improving chip functional yield and overall packaging performance.
[0055] According to one embodiment of this disclosure, the chip packaging design optimization method further includes: obtaining the probe point coordinates and test information of the test probe chip; performing thermal simulation and stress simulation based on the probe point coordinates and test information of the test probe chip, circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the simulation results of thermal simulation and stress simulation.
[0056] Specifically, the process involves acquiring the coordinates and test information of the test probe chip points. This can be achieved using sophisticated measuring equipment, such as a confocal microscope or laser scanning microscope, to obtain the precise coordinates of the chip probe points and record the X, Y, and Z coordinates of each point. Test information collection includes electrical testing to collect parameters such as resistance, capacitance, and inductance of the probe points. Functional testing verifies the electrical functions and performance of each probe point. Fault analysis is also included, recording the failure modes and failure rates of the probe points, particularly the test conditions under which failures occur. Therefore, the probe coordinates and test information can be integrated with circuit, material, packaging, and thermal management parameters to construct a comprehensive simulation model, including circuit routing, packaging structure, and thermal management components.
[0057] Based on the chip's thermal characteristics and packaging parameters, boundary conditions and heat sources are set for the thermal simulation model. Thermal simulations are run to analyze the temperature distribution and hot spots of the chip under different operating conditions, and to assess the thermal stress caused by the mismatch between temperature gradients and coefficients of thermal expansion. Based on the material properties of the package and the chip, boundary conditions and loads are set for the mechanical simulation model. Stress simulations are run to analyze the stress distribution and deformation of the chip and package under different mechanical conditions, predicting fatigue life and potential fracture risk due to cyclic stress. Therefore, based on the thermal simulation results, circuit routing can be adjusted to reduce hot spots and thermal resistance, signal transmission paths can be optimized, and routing can be optimized to reduce crosstalk, reflections, and signal delay, thereby improving signal integrity.
[0058] When optimizing pin placement, electrical test results can be used to adjust pin positions to improve electrical performance, reduce impedance mismatch and signal delay, and consider the impact of pin placement on heat distribution to optimize layout and improve thermal management. When optimizing chip stack-up or arrangement, the chip stack-up or arrangement can be adjusted to optimize the overall package heat distribution, and the impact of chip position on package mechanical stability can be considered to ensure stability under temperature changes and mechanical shocks.
[0059] Therefore, optimizing the chip packaging design based on the probe chip's probe point coordinates and test information ensures that the design meets performance requirements and improves the chip's functional yield. This not only improves the chip's performance and reliability but also helps reduce production costs and shorten product time-to-market, providing solid technical support for the patent claims.
[0060] According to one embodiment of this disclosure, the chip packaging design optimization method further includes: optimizing the passivation layer, redistribution layer, bump type and material, package type and material, location of stacked integrated circuits, material of carrier or interposer, and heat dissipation device based on simulation results.
[0061] Specifically, the passivation layer protects the chip surface from physical damage and chemical corrosion, provides insulation properties, and prevents electrical short circuits. Passivation materials with optimal dielectric properties, chemical stability, and thermal stability, such as silicon dioxide (SiO2) and silicon nitride (Si3N4), can be selected based on simulation results. The thickness of the passivation layer can be adjusted to optimize electrical insulation performance and mechanical protection capabilities. Furthermore, the layout and opening design of the passivation layer can be adjusted based on simulation results to reduce parasitic capacitance and improve signal integrity.
[0062] The redistribution layer redistributes I / O endpoints on the chip to accommodate the layout requirements of the package substrate. The RDL's circuit layout can be optimized based on simulation results, reducing resistance and capacitance and improving signal transmission speed. For example, copper or other conductive materials with low resistivity and good adhesion can be selected. Bumps, serving as the electrical and mechanical connection between the chip and the package substrate, can be optimized in terms of type selection, such as choosing the most suitable bump type based on simulation results (e.g., solder bumps, copper pillar bumps), and materials. Materials with good conductivity and heat resistance, such as SnAgCu solder, can be selected. Furthermore, the geometry can be optimized, such as adjusting the bump's geometry and size to optimize contact area and mechanical strength.
[0063] Package type and materials protect the chip, provide physical support, and enable electrical connections. Package materials can be optimized, such as selecting materials with good thermal conductivity, mechanical strength, and electrical insulation, like BT resin. Package structure design can be optimized, such as improving thermal management efficiency and mechanical stability. The placement of stacked integrated circuits in a multi-chip package can be optimized to improve performance. For example, the placement of stacked integrated circuits can be adjusted based on simulation results to minimize signal delay and power supply noise, and the thermal distribution of the stacked integrated circuits can be considered to optimize the layout for improved heat dissipation efficiency.
[0064] The material of the carrier or interposer provides physical support and electrical connection between the chip and the packaging substrate. Material selection can be optimized by choosing materials with good thermal conductivity and mechanical strength, such as silicon interposers or glass carriers. Alternatively, design optimization can be used to refine the thickness and layout of the interposer to improve electrical performance and thermal management efficiency. Heat dissipation devices remove heat from the chip surface to keep the chip at a safe operating temperature. Heat dissipation structures can be optimized, such as designing efficient heat dissipation structures based on simulation results, like heat pipes, vapor chambers, or heat sinks. Material selection can also be optimized, such as choosing materials with high thermal conductivity, like copper or aluminum.
[0065] This ensures that the chip packaging design achieves the best balance between electrical performance, thermal management, mechanical stability, and cost-effectiveness.
[0066] The optimization method of this disclosure will be described below with reference to Figure 2.
[0067] As a specific example, the chip package design optimization method disclosed herein may include the following steps:
[0068] S101 acquires circuit and material parameter information, packaging parameter information, and chip thermal management parameter information.
[0069] S102, obtain the coordinates of the probe points on the test probe chip and the test information.
[0070] S103 performs thermal and stress simulations based on the probe chip probe point coordinates and test information, circuit and material parameter information, packaging parameter information, chip thermal management parameter information, and the chip's actual functional yield. Based on the simulation results of thermal and stress simulations, it determines the circuit wiring design, pin positions, and the target stack-up or arrangement position of the chip.
[0071] S104 optimizes the passivation layer, redistribution layer, bump type and material, package type and material, location of stacked integrated circuits, carrier or interposer material, and heat dissipation device based on simulation results.
[0072] S105, based on the comparison results of the chip functional yield obtained after simulation and the actual functional yield, optimizes the circuit routing design and pin positions as well as the target stack-up or arrangement position of the chip.
[0073] In summary, the chip packaging design optimization method according to the embodiments of this disclosure obtains circuit and material parameter information, packaging parameter information, and chip thermal management parameter information. Based on the circuit and material parameter information, packaging parameter information, chip thermal management parameter information, and the actual functional yield of the chip, thermal simulation and stress simulation are performed. The circuit wiring design and pin locations, as well as the target stack-up or arrangement positions of the chip, are determined based on the simulation results of the thermal and stress simulations. Therefore, this method can improve the reliability and quality of chip packaging.
[0074] Corresponding to the above embodiments, this disclosure also proposes a computer-readable storage medium.
[0075] The computer-readable storage medium of this disclosure stores a program that, when executed by a processor, implements the above-described chip packaging design optimization method.
[0076] According to the computer-readable storage medium of the present disclosure, by performing the above-described chip packaging design optimization method, the reliability and quality of the chip packaging can be improved.
[0077] Corresponding to the above embodiments, this disclosure also proposes an electronic device.
[0078] As shown in FIG3, the electronic device 200 of this embodiment may include: a memory 210, a processor 220, and a program stored on the memory 210 and executable on the processor 220. When the processor 220 executes the program, it implements the above-described chip packaging design optimization method.
[0079] The electronic device according to the embodiments of this disclosure can improve the reliability and quality of chip packaging by performing the above-described chip packaging design optimization method.
[0080] Corresponding to the above embodiments, this disclosure also proposes an optimization device for chip packaging design.
[0081] As shown in FIG4, the chip packaging design optimization device 100 of this disclosure includes: an acquisition module 110 and a design module 120.
[0082] The acquisition module 110 is used to acquire circuit and material parameter information, packaging parameter information, and chip thermal management parameter information. The design module 120 is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the chip's functional yield, so as to determine the circuit wiring design and pin positions, as well as the target stack-up or arrangement position of the chip, based on the simulation results of the thermal simulation and stress simulation.
[0083] According to one embodiment of this disclosure, the acquisition module 110 acquires circuit and material parameter information, specifically for: acquiring protective layer circuit and material information, chip back-side process circuit and material information, circuit bump circuit and material information, and carrier circuit and material information.
[0084] According to one embodiment of this disclosure, the acquisition module 110 acquires packaging parameter information, specifically for: acquiring packaging material information, wafer stack-up packaging information, and underfill material information.
[0085] According to one embodiment of this disclosure, the acquisition module 110 acquires chip thermal management parameter information, specifically for: acquiring heat dissipation structure and packaging information.
[0086] According to one embodiment of this disclosure, the design module 120 is further configured to: perform thermal simulation and stress simulation based on circuit and material parameter information, packaging parameter information, chip thermal management parameter information and actual functional yield of the chip, so as to determine the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the simulation results of thermal simulation and stress simulation, and optimize the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the comparison results of the chip functional yield obtained after simulation and the actual functional yield.
[0087] According to one embodiment of this disclosure, the design module 120 is further configured to: acquire the probe point coordinates and test information of the test probe chip; perform thermal simulation and stress simulation based on the probe point coordinates and test information of the test probe chip, circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the simulation results of thermal simulation and stress simulation.
[0088] According to one embodiment of this disclosure, the design module 120 is further configured to: optimize the passivation layer, redistribution layer, bump type and material, package type and material, location of stacked integrated circuits, material of carrier or interposer, and heat dissipation device based on simulation results.
[0089] It should be noted that for details not disclosed in the chip packaging design optimization apparatus of this disclosure, please refer to the details disclosed in the chip packaging design optimization method of this disclosure, which will not be repeated here.
[0090] According to an embodiment of the chip packaging design optimization apparatus of this disclosure, an acquisition module is used to acquire circuit and material parameter information, packaging parameter information, and chip thermal management parameter information. A design module is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the chip's functional yield. Based on the simulation results of the thermal and stress simulations, the device determines the circuit wiring design, pin locations, and the target stack-up or arrangement positions of the chip. Therefore, this apparatus can improve the reliability and quality of chip packaging.
[0091] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.
[0092] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0093] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0094] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0095] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0096] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.
Claims
1. A method for optimizing chip packaging design, the method comprising: Acquire circuit and material parameter information, packaging parameter information, and chip thermal management parameter information; Based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the actual functional yield of the chip, thermal simulation and stress simulation are performed to determine the circuit wiring design and pin positions, as well as the target stack-up or arrangement position of the chip, according to the simulation results of thermal simulation and stress simulation.
2. The chip packaging design optimization method according to claim 1, wherein, The acquisition of circuit and material parameter information includes: Obtain information on the protective layer circuitry and materials, the chip back-side process circuitry and materials, the circuit bump circuitry and materials, and the carrier circuitry and materials.
3. The chip packaging design optimization method according to claim 1, wherein, The acquisition of encapsulation parameter information includes: Obtain information on packaging materials, wafer stack-up packaging, and underfill materials.
4. The chip packaging design optimization method according to claim 1, wherein, The acquisition of chip thermal management parameter information includes: Obtain information on the heat dissipation structure and packaging.
5. The chip packaging design optimization method according to claim 1, wherein, The step of performing thermal and stress simulations based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information, and the chip's actual functional yield, to determine the circuit wiring design and pin locations, as well as the target stack-up or arrangement location of the chip based on the simulation results of the thermal and stress simulations, further includes: Based on the comparison between the chip functional yield obtained after simulation and the actual functional yield, the circuit routing design, pin positions, and target stack-up or arrangement positions of the chip can be optimized.
6. The chip packaging design optimization method according to claim 1, wherein, The method further includes: Obtain the coordinates of the probe points on the test probe chip and test information; Based on the probe chip probe point coordinates and test information, circuit and material parameter information, packaging parameter information, chip thermal management parameter information, and actual functional yield of the chip, thermal simulation and stress simulation are performed to determine the circuit wiring design and pin positions, as well as the target stack-up or arrangement position of the chip, according to the simulation results of thermal simulation and stress simulation.
7. The chip packaging design optimization method according to claim 1, wherein, The method further includes: Based on simulation results, the passivation layer, redistribution layer, bump type and material, package type and material, location of stacked integrated circuits, carrier or interposer material, and heat dissipation equipment are optimized.
8. A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the method for optimizing chip package design according to any one of claims 1-7.
9. An electronic device, comprising: A memory, a processor, and a program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the chip packaging design optimization method according to any one of claims 1-7.
10. An optimization apparatus for chip packaging design, the apparatus comprising: The acquisition module is used to acquire circuit and material parameter information, packaging parameter information, and chip thermal management parameter information; The design module is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the chip functional yield, so as to determine the circuit wiring design and pin positions and the target stack-up or arrangement position of the chip based on the simulation results of thermal simulation and stress simulation.