Semiconductor device and method for fabricating semiconductor device

Abstract

The present invention provides a stacked semiconductor device (1) having a BSPDN structure which can be fabricated efficiently and at high yield. In this semiconductor device (1), a first semiconductor chip (5), a TSV chip (90), and a second semiconductor chip (110) are stacked, in that order. When a first direction (1011) is defined to be the direction proceeding from the first semiconductor chip (5) to the TSV chip (90) and a second direction (1012) is defined to be the direction opposite the first direction (1011), a front side interconnect layer (34) is formed on the first-direction (1011) side of the first semiconductor chip (5), and a back side power delivery interconnect layer (70) is formed on the second-direction (1012) side of the first semiconductor chip (5). A through-silicon via (91) is formed in the TSV chip (90). The front side interconnect layer (34) and the second semiconductor chip (110) are connected by way of the through-silicon via (91). The second semiconductor chip (110) has a memory or logic function.

Description

Semiconductor device and method for manufacturing the same 【0001】 The present invention relates to a semiconductor device and a method for manufacturing the same. 【0002】 A stacked semiconductor device in which a memory chip or the like is stacked on a logic chip has been proposed. Patent Document 1 discloses a technique in which a layer in which through-silicon vias (TSVs) are formed is formed between a logic chip and a memory chip, and the logic chip and the memory chip or the like are connected via the TSVs. 【0003】 U.S. Patent Application Publication No. 2020 / 0303351 【0004】 By the way, a backside power delivery network (BSPDN) structure has been proposed. When the BSPDN structure is adopted, wiring is also formed on the back surface of a substrate such as silicon. Also, the wiring for connecting the back surface and the front surface of the substrate becomes complicated. 【0005】 When manufacturing a semiconductor device having a structure in which a bottom chip has a BSPDN structure and a memory chip or the like is stacked on the bottom chip as a top chip by bonding wafers together, the yield tends to decrease. This is because the yield on the bottom chip side and the yield on the top chip side are multiplied. 【0006】 Conventionally, for a semiconductor device having a structure in which a bottom chip has a BSPDN structure and a memory chip or the like is stacked on the bottom chip, no semiconductor device that can be manufactured efficiently and with a high yield has been proposed. 【0007】 Therefore, an object of the present invention is to provide a stacked semiconductor device having a BSPDN structure that can be manufactured efficiently and with a high yield. 【0008】The semiconductor device of the present invention comprises a first semiconductor chip, a TSV chip, and a second semiconductor chip, wherein the first semiconductor chip, the TSV chip, and the second semiconductor chip are stacked in this order, the direction from the first semiconductor chip toward the TSV chip is defined as the first direction, and the direction opposite to the first direction is defined as the second direction, a surface wiring layer is formed on the first direction side of the first semiconductor chip, a back power wiring layer is formed on the second direction side of the first semiconductor chip, through-silicon vias are formed on the TSV chip, the surface wiring layer and the second semiconductor chip are connected via the through-silicon vias, and the second semiconductor chip has memory or logic functionality. 【0009】 The present invention provides a method for manufacturing a semiconductor device, comprising: a first bonding step of bonding a TSV chip having a plurality of silicon through-vias formed on the first direction side of the substrate, a first semiconductor chip having a surface wiring layer formed on the first direction side of the substrate, and a back power wiring layer formed on the second direction side of the substrate which is opposite to the first direction; and a second bonding step of bonding a second semiconductor chip having memory or logic functions to the first direction side of the TSV chip. 【0010】 According to the present invention, it is possible to provide a stacked semiconductor device having a BSPDN structure that can be manufactured efficiently and with high yield. By selecting and using only good quality chips for the first semiconductor chip, TSV chip, and second semiconductor chip, semiconductor devices can be manufactured with high yield. 【0011】This is a cross-sectional view of a semiconductor unit according to an embodiment of the present invention. This is a cross-sectional view of a semiconductor device in the manufacturing process, showing the manufacturing process of a semiconductor device joint for illustrating hybrid bonding in an embodiment of the present invention. This is a cross-sectional view of a joint for illustrating hybrid bonding in an embodiment of the present invention. 【0012】 (Semiconductor Unit) Referring to Figure 1, an embodiment of the semiconductor unit 300 and semiconductor device 1 of the present invention will be described. Figure 1 is a cross-sectional view of the semiconductor unit 300. 【0013】 As shown in Figure 1, the semiconductor unit 300 comprises a semiconductor device 1 and a mounting substrate 200. The semiconductor device 1 is connected to the mounting substrate 200 via solder bumps 120 placed between the semiconductor device 1 and the mounting substrate 200. 【0014】(Semiconductor device) The semiconductor device 1 comprises a first semiconductor chip 5, a TSV chip 90, and a second semiconductor chip 110. The first semiconductor chip 5 and the TSV chip 90 are stacked and bonded via a TSV chip bonding layer 40. The second semiconductor chip 110 and the TSV chip 90 are stacked and bonded via a second semiconductor chip bonding layer 118. 【0015】 (Definition of Direction) As shown in Figure 1, the direction in which the first semiconductor chip 5 and the TSV chip 90 are stacked is defined as the stacking direction 1010. The direction from the first semiconductor chip 5 toward the TSV chip 90 is defined as the first direction 1011. The direction opposite to the first direction 1011 is defined as the second direction 1012. The first direction 1011 is also the direction from the TSV chip 90 toward the second semiconductor chip 110. Both the first direction 1011 and the second direction 1012 are parallel to the stacking direction 1010. 【0016】 As shown in Figure 1, the direction perpendicular to the stacking direction 1010 is defined as the third direction 1003. 【0017】 (Back side and front side) The side with the first direction 1011 is defined as the front side and will be referred to as the front side 1011. The side with the second direction 1012 is defined as the back side and will be referred to as the back side 1012. 【0018】 (Front and back surfaces) The main surface of the object on the side of the first direction 1011 is defined as the front surface. The main surface of the object on the side of the second direction 1012 is defined as the back surface. 【0019】 (Backside Power Delivery Network Structure) The semiconductor device 1 has a backside power delivery network (BSPDN) structure. Specifically, the first semiconductor chip 5 in the semiconductor device 1 has a backside power delivery network structure. The structure will be described in detail below. 【0020】(First Semiconductor Chip) The first semiconductor chip 5 is a semiconductor chip having logic functionality. The first semiconductor chip 5 comprises a wafer layer 14, a back surface insulator layer 60, a back surface metal laminate layer 70, a front surface silicon layer 22, a trench isolation portion 24, a front surface element layer 32, and a front surface wiring layer 34. The wafer layer 14 can be a silicon substrate. The front surface silicon layer 22 and the trench isolation portion 24 are arranged at the same position in the stacking direction 1010. 【0021】 (Back surface of the first semiconductor chip) The back surface of the wafer layer 14 is defined as the back surface 14B of the wafer layer. On the back surface side 1012 of the wafer layer 14, a back surface insulating layer 60 and a back surface metal laminate layer 70 are formed in order from the back surface 14B of the wafer layer. 【0022】 The back surface insulating layer 60 is formed of, for example, silicon dioxide. 【0023】 The backside metal laminate layer 70 is also called BMI (Backside metal stack). The backside metal laminate layer 70 is a backside power wiring layer formed in the backside back-end process (BS-BEOL: Backside Back-End of Line). The backside metal laminate layer 70 is a backside wiring layer on which wiring related to power in the backside power supply network structure is mainly formed. VDD wiring related to power supply voltage and VSS wiring related to grounding are formed on the backside metal laminate layer 70. 【0024】 (Surface of the first semiconductor chip) The surface of the wafer layer 14 is defined as the wafer layer surface 14F. The portion comprising the surface silicon layer 22 and the trench separation portion 24 is defined as the surface insulating layer 20. On the surface side 1011 of the wafer layer 14, the surface insulating layer 20, the surface element layer 32, and the surface wiring layer 34 are formed in order from the wafer layer surface 14F. 【0025】 The surface silicon layer 22 of the surface insulating layer 20 is formed of silicon, similar to the wafer layer 14. The trench isolation portion 24 of the surface insulating layer 20 is also called STI (Shallow Trench Isolation). The trench isolation portion 24 is formed of, for example, silicon dioxide. 【0026】The surface element layer 32 is an element layer formed in the surface front-end process (FS-FEOL: Frontside Front-End of Line). The surface wiring layer 34 is a wiring layer formed in the surface back-end process (FS-BEOL: Frontside Back-End of Line). 【0027】 (Buried power wiring and nanosilicon through-vias) Buried power wiring 26 and nanosilicon through-vias (n-TSV) 64 are formed on the first semiconductor chip 5. The buried power wiring 26 is also called a BPR (Buried power rail). 【0028】 As shown in Figure 1, the embedded power wiring 26 and the nanosilicon through-via 64 are continuous in the stacking direction 1010. Electrical conductivity is enabled between the back side 1012 and the front side 1011 of the first semiconductor chip 5 via the embedded power wiring 26 and the nanosilicon through-via 64. Specifically, for example, electrical connection is enabled between the back metal laminate layer 70 and the front element layer 32. 【0029】 Examples of materials for forming the nanosilicon through-vias 64 include tungsten and ruthenium. Examples of materials for forming the embedded power wiring 26 include tungsten, ruthenium, and cobalt. 【0030】 A via (not shown) may be formed on the first direction 1011 side of the embedded power wiring 26. This via connects, for example, the end of the embedded power wiring 26 on the first direction 1011 side to the surface element layer 32. 【0031】 (Backside Power Supply Wiring Layer) The back surface of the backside insulator layer 60 is defined as the backside insulator layer 60B. The surface of the frontside insulator layer 20 is defined as the frontside insulator layer 20F. In the stacking direction 1010, the portion from the backside insulator layer 60B to the frontside insulator layer 20F is defined as the backside power supply wiring layer 3. In the first semiconductor chip 5, the backside power supply network structure is mainly realized by the backside power supply wiring layer 3. 【0032】(TSV Chip) A TSV chip 90 is provided on the surface side 1011 of the first semiconductor chip 5. The TSV chip 90 has a structure in which through-silicon vias (TSV) 91 are formed on the silicon substrate 92. Electrical conductivity is possible between the back side 1012 and the front side 1011 of the TSV chip 90 via the through-silicon vias 91. 【0033】 The TSV chip 90 is provided on the surface side 1011 of the first semiconductor chip 5. 【0034】 The surface of the first semiconductor chip 5 is defined as the first semiconductor chip surface 5F. The surface of the surface wiring layer 34 is defined as the surface wiring layer surface 34F. In the example shown in Figure 1, the surface wiring layer surface 34F becomes the first semiconductor chip surface 5F. 【0035】 A TSV chip bonding layer 40 is formed on the surface 5F of the first semiconductor chip. The TSV chip bonding layer 40 is a layer for bonding the first semiconductor chip 5 and the TSV chip 90. The TSV chip 90 is bonded to the surface 5F of the first semiconductor chip via the TSV chip bonding layer 40. 【0036】 The bonding between the TSV chip 90 and the first semiconductor chip 5 can be, for example, hybrid bonding. When the bonding between the TSV chip 90 and the first semiconductor chip 5 is hybrid bonding, the TSV chip bonding layer 40 can be a hybrid bonding layer provided on the back surface 90B of the TSV chip and the surface 34F of the surface wiring layer, respectively. A hybrid bonding layer comprises, for example, an insulating portion formed of silicon oxide or silicon carbonitride and a metal electrode portion formed of copper. The insulating portion and metal electrode portion of the hybrid bonding layer are arranged such that when the hybrid bonding layers are stacked, their insulating portions and metal electrode portions are in contact with each other. The hybrid bonding layer will be described later. 【0037】 When the TSV chip 90 and the first semiconductor chip 5 are joined by hybrid bonding, the wiring length required for bonding can be shortened. 【0038】(Capacitor) A capacitor 98 may be formed on the TSV chip 90. The capacitor 98 can be, for example, a trench-type capacitor. The surface of the TSV chip 90 is defined as the TSV chip surface 90F. The back surface of the TSV chip 90 is defined as the TSV chip back surface 90B. The capacitor 98 is formed in a trench formed from the TSV chip surface 90F toward the TSV chip back surface 90B. The capacitor 98 will be described later. 【0039】 (Second semiconductor chip) The second semiconductor chip 110 is provided on the surface side 1011 of the TSV chip 90. The second semiconductor chip 110 may be, for example, a memory chip or a chip having logic functions. Multiple second semiconductor chips 110 may be provided on the surface side 1011 of the TSV chip 90. 【0040】 The back surface of the second semiconductor chip 110 is defined as the back surface 110B of the second semiconductor chip. A second semiconductor chip bonding layer 118 is formed on the back surface 110B of the second semiconductor chip. The second semiconductor chip bonding layer 118 is a layer for bonding the second semiconductor chip 110 and the TSV chip 90. The second semiconductor chip 110 is bonded to the TSV chip 90 via the second semiconductor chip bonding layer 118. 【0041】 The bonding between the second semiconductor chip 110 and the TSV chip 90 can be hybrid bonding. When the bonding between the second semiconductor chip 110 and the TSV chip 90 is hybrid bonding, the second semiconductor chip bonding layer 118 can be a hybrid bonding layer provided on the back surface 110B of the second semiconductor chip and the front surface 90F of the TSV chip, respectively. The hybrid bonding layer can be the same as the hybrid bonding layer described for the TSV chip bonding layer 40. 【0042】 The bonding between the second semiconductor chip 110 and the TSV chip 90 is not limited to bonding by hybrid bonding. The bonding between the second semiconductor chip 110 and the TSV chip 90 can also be done by soldering, for example, using solder balls. 【0043】When the bonding is performed by hybrid bonding, the wiring length can be shortened as described above. When the bonding is performed by soldering, it can be performed at a low cost and with a high yield. 【0044】 (Mold part) In the semiconductor device 1, a mold part 114 is formed so as to cover the first semiconductor chip 5, the TSV chip 90, and the second semiconductor chip 110. The surface of the second semiconductor chip 110 is defined as the second semiconductor chip surface 110F. A main surface parallel to the stacking direction 1010 of the second semiconductor chip 110 is defined as the second semiconductor chip side surface 110S. The mold part 114 covers the second semiconductor chip surface 110F and the second semiconductor chip side surface 110S of each second semiconductor chip 110. The mold part 114 covers the entire side circumferential surface of the second semiconductor chip 110. 【0045】 (Mounting substrate) The semiconductor unit 300 has a configuration in which the semiconductor device 1 as described above is connected to the mounting substrate 200 via solder bumps 120. The mounting substrate 200 is not particularly limited. Examples of the mounting substrate 200 include a redistribution layer such as a silicon interposer, an organic substrate formed of an epoxy resin or the like, and a printed wiring board. 【0046】 (Dimensions) The dimensions of the semiconductor device 1 will be described. The length in the direction parallel to the stacking direction 1010 of the object is defined as the thickness. 【0047】 The thickness of the back metal laminated layer 70 is defined as the back metal laminated layer thickness 70T. The back metal laminated layer thickness 70T can be 1 μm or more and 6 μm or less. Typically, the back metal laminated layer thickness 70T can be about 3 μm. 【0048】 The thickness of the back power supply wiring layer 3 is defined as the back power supply wiring layer thickness 3T. The back power supply wiring layer thickness 3T can be 100 nm or more and 1000 nm or less. Typically, the back power supply wiring layer thickness 3T can be about 500 nm. 【0049】The thickness of the surface element layer 32 is defined as the surface element layer thickness 32T. The surface element layer thickness 32T can be between 10 nm and 50 nm. Typically, the surface element layer thickness 32T can be about 20 nm. 【0050】 The thickness of the surface wiring layer 34 is defined as the surface wiring layer thickness 34T. The surface wiring layer thickness 34T can be between 0.3 μm and 1.2 μm. Typically, the surface wiring layer thickness 34T can be about 0.6 μm. 【0051】 The thickness of the TSV chip 90 is defined as the TSV chip thickness 90T. The TSV chip thickness 90T can be between 20 μm and 200 μm. 【0052】 The thickness 3T of the back power supply wiring layer may be less than the distance between the surface element layer 32 of the first semiconductor chip 5 and an element layer (not shown) of the second semiconductor chip 110 in the stacking direction 1010. The thickness 3T of the back power supply wiring layer may be less than the distance between the first semiconductor chip 5 and the second semiconductor chip 110 in the stacking direction 1010. The thickness 3T of the back power supply wiring layer may be thinner than the TSV chip thickness 90T. 【0053】 Next, the diameter of the nanosilicon through-via 64 will be described. The diameter of the nanosilicon through-via 64 is defined as the nanosilicon through-via diameter 64R. The nanosilicon through-via diameter 64R can be between Φ50 nm and Φ200 nm. Typically, the nanosilicon through-via diameter 64R can be around Φ100 nm. 【0054】 The nanosilicon through-via diameter 64R is measured on the back surface 60B of the back-surface insulating layer. In other words, the nanosilicon through-via diameter 64R is measured on the nanosilicon through-via 64 exposed from the back surface 60B of the back-surface insulating layer. 【0055】In the semiconductor device 1 of this embodiment, the first semiconductor chip 5 and the second semiconductor chip 110 can be connected by interposing a TSV chip 90. By interposing the TSV chip 90, the first semiconductor chip 5 and the second semiconductor chip 110 can be tested, and the semiconductor device 1 can be manufactured using only good chips. By using chips that have been confirmed to be good, the yield of the semiconductor device 1 can be increased. 【0056】 Furthermore, by interposing the TSV chip 90, the method of joining the first semiconductor chip 5 and the second semiconductor chip 110 can be appropriately selected. For example, as described above, the method of joining the TSV chip 90 and the second semiconductor chip 110 can be selected from hybrid bonding and solder bonding. 【0057】 As described above, the semiconductor device 1 of this embodiment provides a stacked semiconductor device 1 having a BSPDN structure that can be manufactured efficiently and with high yield. 【0058】 (Method of Manufacturing a Semiconductor Device) The method of manufacturing the semiconductor device 1 of this embodiment will be described with reference to Figures 2A to 2N. Figures 2A to 2N are cross-sectional views of the semiconductor device during the manufacturing process, showing the manufacturing steps of the semiconductor device 1 in this order. 【0059】 (Carrier substrate preparation process) Figure 2A shows the first carrier wafer 10 after the carrier substrate preparation process. The carrier substrate preparation process is a process of preparing the substrate for forming elements and the like on the surface side 1011 of the semiconductor device 1. 【0060】 In the carrier substrate preparation process, a silicon wafer is prepared as the first carrier wafer 10. The surface of the first carrier wafer 10 is defined as the first carrier wafer surface 10F. The back surface of the first carrier wafer 10 is defined as the first carrier wafer back surface 10B. An embedded etch stop layer 21 is formed on the first carrier wafer surface 10F. The embedded etch stop layer 21 can be formed from, for example, SiGe. 【0061】A wafer layer 14 is formed on the surface side 1011 of the embedded etch stop layer 21. In other words, the embedded etch stop layer 21 and the wafer layer 14 are formed sequentially on the surface side 1011 of the first carrier wafer 10. The surface of the wafer layer 14 is defined as the wafer layer surface 14F. 【0062】 As the silicon wafer in the carrier substrate preparation process, for example, an SOI wafer (Silicon-On-Insulator wafer: silicon substrate with an insulating layer) can be used. Alternatively, a SiGe / Si Epitaxial wafer can be used as the silicon wafer in the carrier substrate preparation process. This SiGe layer functions as an embedded etch stop layer. 【0063】 (Surface Insulating Layer Formation Process) Figure 2B shows the surface insulating layer 20 after the surface insulating layer formation process. The surface insulating layer formation process is a process of forming trench separation portions 24 and the like on the wafer layer surface 14F of the wafer layer 14. 【0064】 In the surface insulating layer formation process, the embedded power wiring 26 is formed together with the surface silicon layer 22 and trench separation portion 24 that constitute the surface insulating layer 20. The embedded power wiring 26 is formed at a position corresponding to the position where the nanosilicon through-via 64 will be formed later. The trench separation portion 24 is also formed to cover at least a portion of the embedded power wiring 26. By covering the embedded power wiring 26 with the trench separation portion 24, the insulating properties of the embedded power wiring 26 are enhanced. 【0065】 The surface of the surface insulating layer 20 is defined as the surface insulating layer surface 20F. The surface insulating layer surface 20F is also the surface of the surface silicon layer 22 and the surface of the trench separation portion 24. 【0066】 (Surface element layer and surface wiring layer formation process) Figure 2C shows the surface element layer 32 and surface wiring layer 34 after the surface element layer and surface wiring layer formation process. The surface element layer and surface wiring layer formation process is a process of sequentially forming the surface element layer 32 and the surface wiring layer 34 on the surface insulating layer surface 20F of the surface insulating layer 20. 【0067】As mentioned above, the surface element layer 32 is formed in the surface front-end process (FS-FEOL: Frontside Front-End of Line). The surface element layer 32 includes active elements and transistor elements. The surface wiring layer 34 is formed in the surface back-end process (FS-BEOL: Frontside Back-End of Line). 【0068】 (TSV Carrier Wafer Bonding Process) Figure 2D shows the TSV carrier wafer 50 after the TSV carrier wafer bonding process. The TSV carrier wafer bonding process is a process of bonding the TSV carrier wafer 50 to the surface wiring layer surface 34F. The TSV carrier wafer bonding process is also called the first bonding process. 【0069】 In the TSV carrier wafer bonding process, the TSV carrier wafer 50 is bonded to the surface wiring layer surface 34F via the TSV chip bonding layer 40. The bonding method can be, for example, hybrid bonding. Hybrid bonding will be explained later. 【0070】 The front surface of the TSV carrier wafer 50 is defined as the TSV carrier wafer surface 50F. The back surface of the TSV carrier wafer 50 is defined as the TSV carrier wafer back surface 50B. 【0071】 Before the TSV carrier wafer bonding process, TSV trench vias 56 are formed on the TSV carrier wafer 50. The TSV trench vias 56 are formed from the main surface which becomes the back surface 50B of the TSV carrier wafer toward the main surface which becomes the front surface 50F of the TSV carrier wafer. The TSV trench vias 56 do not penetrate the TSV carrier wafer 50. Later, when the TSV carrier wafer 50 is ground, the TSV trench vias 56 penetrate the TSV carrier wafer 50. By penetrating the TSV carrier wafer 50, the TSV trench vias 56 become through-silicon vias 91. 【0072】(First carrier wafer grinding process) Figure 2E shows the wafer layer 14 after the first carrier wafer grinding process. The first carrier wafer grinding process is a process in which the first carrier wafer 10 is ground from the back surface 10B of the first carrier wafer to expose the embedded etch stop layer 21. 【0073】 In the previous TSV carrier wafer bonding process, the TSV carrier wafer 50 was bonded to the surface wiring layer 34 as a permanent carrier wafer. Therefore, in order to form the back side 1012 of the wafer layer 14, the first carrier wafer 10 is ground in the first carrier wafer grinding process. 【0074】 (Etch stop layer removal process) Figure 2F shows the wafer layer 14 after the etch stop layer removal process. The etch stop layer removal process is a process of removing the embedded etch stop layer 21 from the wafer layer 14. 【0075】 The method for removing the embedded etch stop layer 21 is not particularly limited. The method for removing the embedded etch stop layer 21 can be appropriately selected depending on the material used to form the embedded etch stop layer 21. The embedded etch stop layer 21 is removed by the etch stop layer removal process, and the back surface 14B of the wafer layer 14 is exposed. If necessary, the exposed back surface 14B of the wafer layer may be polished to smooth it. 【0076】 (Back surface insulating layer formation process) Figure 2G shows the back surface insulating layer 60 after the back surface insulating layer formation process. The back surface insulating layer formation process is a process of forming the back surface insulating layer 60 on the back surface 14B of the wafer layer. 【0077】 The process following the back surface insulator layer formation step involves the back surface 1012 of the wafer layer 14. First, a back surface insulator layer 60 is formed on the back surface 14B of the wafer layer, for example, using silicon dioxide. The method for forming the back surface insulator layer 60 can be appropriately selected, such as chemical vapor deposition (CVD) or sputtering. The back surface of the back surface insulator layer 60 is defined as the back surface 60B of the back surface insulator layer. 【0078】(Nanosilicon through-via formation process) Figure 2H shows the nanosilicon through-via 64 after the nanosilicon through-via formation process. The nanosilicon through-via formation process is a process of forming through-vias from the back surface 60B of the back surface insulating layer toward the embedded power wiring 26. 【0079】 In the nanosilicon through-via formation process, vias are formed so as to connect from the back side 1012 of the wafer layer 14 to the embedded power wiring 26, thereby enabling electrical conductivity between the back side 1012 and the front side 1011 of the wafer layer 14. As mentioned above, vias (not shown) may be formed on the front side 1011 of the embedded power wiring 26 to connect the embedded power wiring 26 and the surface element layer 32. 【0080】 (Backside Metal Laminate Formation Process) Figure 2I shows the backside metal laminate 70 after the backside metal laminate formation process. The backside metal laminate formation process is a process of forming a wiring layer on the backside 1012 of the wafer layer 14. 【0081】 In the backside metal laminate formation process, a wiring layer is formed on the backside 1012 of the wafer layer 14 in the backside back-end process (BS-BEOL). The backside metal laminate 70 is usually formed as a thick layer with a thickness of 1 μm or more. The backside of the backside metal laminate 70 is defined as the backside 70B of the backside metal laminate. 【0082】 (Second carrier wafer bonding process) Figure 2J shows the second carrier wafer 80 after the second carrier wafer bonding process. The second carrier wafer bonding process is a process of bonding the second carrier wafer 80 to the back surface 70B of the back surface metal laminate layer. 【0083】 The method for joining the second carrier wafer is not particularly limited. The second carrier wafer serves as a support when processing the surface side 1011 of the wafer layer 14. The back surface of the second carrier wafer 80 is defined as the back surface 80B of the second carrier wafer. 【0084】(TSV Carrier Wafer Grinding Process) Figure 2J further shows the TSV chip 90 after the TSV carrier wafer grinding process. The TSV carrier wafer grinding process is a process in which the TSV carrier wafer 50 shown in Figure 2I is ground from the TSV carrier wafer surface 50F to expose the TSV trench vias 56. The TSV trench vias 56 penetrate the TSV carrier wafer 50 as the TSV carrier wafer 50 is ground. The TSV trench vias 56 become through-silicon vias 91 by penetrating the TSV carrier wafer 50. After the TSV carrier wafer grinding process, the TSV carrier wafer 50 becomes a TSV chip 90 in which through-silicon vias 91 are formed on the silicon substrate 92. The surface of the TSV chip 90 is defined as the TSV chip surface 90F. 【0085】 (Second semiconductor chip bonding process) Figure 2K shows the second semiconductor chip 110 after the second semiconductor chip bonding process. The second semiconductor chip bonding process is a process of bonding the second semiconductor chip 110 to the TSV chip surface 90F of the TSV chip 90. The second semiconductor chip bonding process is also called the second bonding process. 【0086】 The second semiconductor chip 110 is bonded to the TSV chip 90 via a second semiconductor chip bonding layer 118. The method of bonding the second semiconductor chip 110 to the TSV chip 90 is not particularly limited, as described above, and can include hybrid bonding, solder bonding, etc. 【0087】 The second semiconductor chip bonding process can be a die-to-wafer process. As shown in Figure 2K, one or more dies, i.e., the second semiconductor chip 110, are bonded to the wafer-shaped TSV chip 90. In other words, when viewed in the second direction 1012, the second semiconductor chip 110 is smaller than the TSV chip 90 and the first semiconductor chip 5. 【0088】 After the mold portion 114 described below is formed, the semiconductor device 1 may be diced into individual pieces, for example, each second semiconductor chip 110. 【0089】(Capacitor) A capacitor 98 is formed on the TSV chip 90. It is preferable to form the capacitor 98 before the second semiconductor chip bonding process. The capacitor 98 can be a trench capacitor, and in particular a deep trench capacitor. In a trench capacitor, the capacitor is formed in a trench formed from the TSV chip surface 90F toward the back side 1012. The length of the trench in the stacking direction 1010, that is, the depth of the trench, can be, for example, 20 μm or more and 40 μm or less. 【0090】 A trench capacitor includes a dielectric layer, a first electrode layer, and a second electrode layer. In other words, the dielectric layer, the first electrode layer, and the second electrode layer are provided within the trench. The dielectric layer is sandwiched between the first electrode layer and the second electrode layer. This generates capacitance in the dielectric layer. 【0091】 A trench-type capacitor is formed by extending the first electrode layer, dielectric layer, and second electrode layer in the stacking direction. The first electrode layer, dielectric layer, and second electrode layer may bend within the trench and extend alternately to the back side 1012 and the front side 1011. This allows for the generation of a larger capacitance. 【0092】 The material of the dielectric layer is not particularly limited. By using a material with a high dielectric constant, the capacitance can be increased, and materials such as silicon oxide, silicon nitride, tantalum oxide, titanium oxide, hafnium oxide, hafnium silicate, HfSiON, and HfAlON can be used. The materials of the first electrode layer and the second electrode layer are not particularly limited. The materials of the first electrode layer and the second electrode layer can be, for example, copper. 【0093】By forming a capacitor 98 on the TSV chip 90, the power supply voltage can be stabilized, and high-frequency noise in particular can be reduced. When a semiconductor chip is placed on the front surface 1011 of the TSV chip 90, it may be necessary to run power lines from the back surface 1012 of the first semiconductor chip 5 to the front surface 1011 of the TSV chip 90. For example, in such a case, forming a capacitor 98 on the TSV chip 90 makes it easier to stabilize the power supply voltage. 【0094】 (Molding Process) Figure 2L shows the second semiconductor chip 110 after the molding process. The molding process is a process in which the entire surface side 1011 of the second carrier wafer 80, including the first semiconductor chip 5, the TSV chip 90, and the second semiconductor chip 110, is covered with molding resin. 【0095】 In the molding process, if multiple second semiconductor chips 110 are bonded to the TSV chip 90, the area between adjacent second semiconductor chips 110 is also covered with molding resin to form a molded portion 114. 【0096】 (Solder bump formation process) Figure 2M shows the solder bumps 120 after the solder bump formation process. The solder bump formation process is a process of forming solder bumps 120 on the back side 1012 of the back metal laminate layer 70. 【0097】 In the solder bump formation process, the second carrier wafer 80 is removed by grinding from the back surface 80B of the second carrier wafer before the formation of the solder bumps 120. The molded portion 114 is formed in the molding process. This eliminates the need for support on the carrier substrate. The semiconductor device 1 is completed by removing the second carrier wafer 80. 【0098】By removing the second carrier wafer 80, the back surface 70B of the back metal laminate layer is exposed. Solder bumps 120 are formed on the exposed back surface 70B of the back metal laminate layer. This makes it possible to connect the semiconductor device 1 to the mounting substrate 200, as shown in Figure 1. Note that the means of connecting the semiconductor device 1 to the mounting substrate 200 is not limited to solder bumps 120. Various means of connecting the semiconductor device 1 to the mounting substrate 200 can be used. 【0099】 (Mold Grinding Process) Figure 2N shows the mold portion 114 after the mold grinding process. The surface of the mold portion 114 is defined as the mold surface 114F. The mold grinding process is a process of grinding the mold surface 114F. 【0100】 The length of the semiconductor device 1 in the stacking direction 1010 can be shortened by the mold grinding process. This makes the semiconductor device 1 thinner. In the example shown in Figure 2N, the mold surface 114F is aligned with the second semiconductor chip surface 110F. The length of the mold 114 to be ground in the stacking direction 1010 in the mold grinding process is not particularly limited. For example, the mold surface 114F may be located on the surface side 1011 of the second semiconductor chip surface 110F. 【0101】 (Hybrid bonding) 【0102】 As described above, the first semiconductor chip 5 and the TSV chip 90 are bonded via the TSV chip bonding layer 40. Furthermore, the second semiconductor chip 110 and the TSV chip 90 are bonded via the second semiconductor chip bonding layer 118. Hybrid bonding is one possible method of bonding in both cases. 【0103】 Hybrid bonding will be described with reference to Figures 3A and 3B. Figures 3A and 3B are schematic cross-sectional views of the TSV chip bonding layer 40 or the second semiconductor chip bonding layer 118. 【0104】The base portions 300A and 300B shown in Figures 3A and 3B refer to two parts connected via a bonding layer. The combination of base portion 300A and base portion 300B is either a first semiconductor chip 5 and a TSV chip 90, or a second semiconductor chip 110 and a TSV chip 90. 【0105】 As shown in Figure 3A, when hybrid bonding is performed, the TSV chip bonding layer 40 and the second semiconductor chip bonding layer 118 become two hybrid bonding layers divided in the stacking direction 1010, namely hybrid bonding layer 310A and hybrid bonding layer 310B. 【0106】 Hybrid bonding layers 310A and 310B are formed on each of the members to be joined. Hybrid bonding layer 310A is formed on the main surface 330A of the base portion 300A. Hybrid bonding layer 310B is formed on the main surface 330B of the base portion 300B. 【0107】 As shown in Figure 3B, during bonding, the main surface 320A of the hybrid bonding layer 310A and the main surface 320B of the hybrid bonding layer 310B come into contact. The hybrid bonding layer 310A and the hybrid bonding layer 310B are then bonded together to form a single bonded layer, namely the TSV chip bonded layer 40 or the second semiconductor chip bonded layer 118. 【0108】 The hybrid bonding layer 310A and the hybrid bonding layer 310B each include an insulating portion and a metal electrode portion. The insulating portion of the hybrid bonding layer 310A is designated as insulating portion 312A, and the insulating portion of the hybrid bonding layer 310B is designated as insulating portion 312B. The metal electrode portion of the hybrid bonding layer 310A is designated as metal electrode portion 314A, and the metal electrode portion of the hybrid bonding layer 310B is designated as metal electrode portion 314B. 【0109】As shown in Figure 3B, the base portions 300A and 300B are positioned so that the insulating portion 312A of the hybrid bonding layer 310A and the insulating portion 312B of the hybrid bonding layer 310B are aligned. Similarly, the base portions 300A and 300B are positioned so that the metal electrode portion 314A of the hybrid bonding layer 310A and the metal electrode portion 314B of the hybrid bonding layer 310B are aligned. 【0110】 The main surface 320A of the hybrid bonding layer 310A and the main surface 320B of the hybrid bonding layer 310B are brought close together and into contact in the lamination direction 1010. Then, the hybrid bonding layer 310A and the hybrid bonding layer 310B are bonded by heating and pressurizing them. 【0111】 When the metal electrode portion is made of copper, the metal electrode portion 314A and the metal electrode portion 314B are joined by copper diffusion bonding. The insulating portion 312A and the insulating portion 312B are joined by siloxane bonding, for example, when the insulating portion is made of silicon oxide. This completes the hybrid bonding. 【0112】 Furthermore, the joining process can be divided into two stages: a preliminary crimp and a final crimp, each involving different temperatures or pressures. In this case, only the insulating portion is joined during the preliminary crimp, while the metal electrode portion is joined during the final crimp. This reduces the risk of short-circuit failures. 【0113】 The embodiments of the present invention have been described above. The present invention is not limited to the embodiments described above, and various modifications, variations, and combinations are possible. 【0114】<1> A semiconductor device comprising a first semiconductor chip, a TSV chip, and a second semiconductor chip, wherein the first semiconductor chip, the TSV chip, and the second semiconductor chip are stacked in this order, the direction from the first semiconductor chip toward the TSV chip is defined as the first direction, and the direction opposite to the first direction is defined as the second direction, a surface wiring layer is formed on the first direction side of the first semiconductor chip, a back power wiring layer is formed on the second direction side of the first semiconductor chip, through-silicon vias are formed on the TSV chip, the surface wiring layer and the second semiconductor chip are connected via the through-silicon vias, and the second semiconductor chip has memory or logic functionality. 【0115】 <2> When viewed in the second direction, the second semiconductor chip is smaller than the first semiconductor chip, as described in <1>. 【0116】 <3> The semiconductor device according to <1> or <2>, wherein a capacitor is formed on the TSV chip. 【0117】 <4> The semiconductor device according to <3>, wherein the capacitor is provided in a trench formed in the first direction or the second direction from the main surface of the TSV chip. 【0118】 <5> The semiconductor device according to any one of <1> to <4>, wherein the second semiconductor chip is bonded to the TSV chip by hybrid bonding. 【0119】 <6> The second semiconductor chip is soldered to the TSV chip and is a semiconductor device according to any one of <1> to <4>. 【0120】 <7> When viewed in the second direction, the second semiconductor chip is smaller than the first semiconductor chip, a capacitor is formed on the TSV chip, and the second semiconductor chip is bonded to the TSV chip by hybrid bonding, the semiconductor device according to <1>. 【0121】<8> A method for manufacturing a semiconductor device, comprising: a first semiconductor chip having a surface wiring layer formed on the first direction side of the substrate, a back power wiring layer formed on the second direction side of the substrate opposite to the first direction; a first bonding step of bonding a TSV chip having a plurality of silicon through-vias formed on the first direction side of the surface wiring layer; and a second bonding step of bonding a second semiconductor chip having memory or logic function to the first direction side of the TSV chip. 【0122】1 Semiconductor device 3 Backside power supply wiring layer 3T Backside power supply wiring layer thickness 5 First semiconductor chip 5F First semiconductor chip surface 6 Second electrode layer 10 First carrier wafer 10B Backside of first carrier wafer 10F First carrier wafer surface 14 Wafer layer 14B Backside of wafer layer 14F Wafer layer surface 20 Surface insulating layer 20F Surface insulating layer surface 21 Etch stop layer 22 Surface silicon layer 24 Trench separation section 26 Power wiring 32 Surface element layer 32T Surface element layer thickness 34 Surface wiring layer 34F Surface wiring layer surface 34T Surface wiring layer thickness 40 TSV chip bonding layer 50 Carrier wafer 50B Backside of carrier wafer 50F Carrier wafer surface 56 Trench via for TSV 60 Backside insulating layer 60B Backside insulating layer 64 Nanosilicon through-via 64R Nanosilicon through-via diameter 70 Backside metal laminated layer 70B Backside metal laminated layer 70T Backside metal laminated layer thickness 80 Second carrier wafer 80B Backside of second carrier wafer 90 TSV chip 90B Backside of TSV chip 90F Front of TSV chip 90T TSV chip thickness 91 Silicon through-via 92 Silicon substrate 98 Capacitor 100 Second semiconductor chip 110 Second semiconductor chip 110B Backside of second semiconductor chip 110F Front of second semiconductor chip 110S Side of second semiconductor chip 114 Molded part 114F Front of molded part 118 Second semiconductor chip bonding layer 120 Solder bump 200 Mounting substrate 300 Semiconductor unit 300A Base 300B Base 310A Hybrid bonding layer 310B Hybrid bonding layer 312A Insulating part 312B Insulating part 314A Metal electrode part 314B Metal electrode part 320A Main surface 320B Main surface 330A Main surface 330B Main surface 1003 Third direction 1010 Lamination direction 1011 First direction 1011 Front side 1012 Second direction 1012 Back side

Claims

1. A semiconductor device comprising a first semiconductor chip, a TSV chip, and a second semiconductor chip, wherein the first semiconductor chip, the TSV chip, and the second semiconductor chip are stacked in this order, the direction from the first semiconductor chip toward the TSV chip is defined as the first direction, and the direction opposite to the first direction is defined as the second direction, a surface wiring layer is formed on the first direction side of the first semiconductor chip, a back power wiring layer is formed on the second direction side of the first semiconductor chip, through-silicon vias are formed on the TSV chip, the surface wiring layer and the second semiconductor chip are connected via the through-silicon vias, and the second semiconductor chip has memory or logic functionality.

2. The semiconductor device according to claim 1, wherein, when viewed in the second direction, the second semiconductor chip is smaller than the first semiconductor chip.

3. The semiconductor device according to claim 1, wherein a capacitor is formed on the TSV chip.

4. The semiconductor device according to claim 3, wherein the capacitor is provided in a trench formed in the first or second direction from the main surface of the TSV chip.

5. The semiconductor device according to claim 1, wherein the second semiconductor chip is bonded to the TSV chip by hybrid bonding.

6. The semiconductor device according to claim 1, wherein the second semiconductor chip is soldered to the TSV chip.

7. The semiconductor device according to claim 1, wherein, when viewed in the second direction, the second semiconductor chip is smaller than the first semiconductor chip, a capacitor is formed on the TSV chip, and the second semiconductor chip is bonded to the TSV chip by hybrid bonding.

8. A method for manufacturing a semiconductor device, comprising: a first semiconductor chip having a surface wiring layer formed on the first direction side of a substrate, a back power wiring layer formed on the second direction side of the substrate opposite to the first direction; a first bonding step of bonding a TSV chip having a plurality of silicon through-vias formed on the first direction side of the surface wiring layer; and a second bonding step of bonding a second semiconductor chip having memory or logic function to the first direction side of the TSV chip.

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