Chip-embedded package

By forming a stepped structure and connectors on a metal substrate, the problems of electrical breakdown and leakage when power chips are embedded in printed circuit boards are solved, achieving higher electrical insulation and reliability as well as greater wiring freedom.

WO2026123556A1 Publication Date: 2026-06-18SHENNAN CIRCUITS
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
SHENNAN CIRCUITS
Filing Date
2025-04-30
Publication Date
2026-06-18

AI Technical Summary

⚠Technical Problem

Existing methods of embedding power chips in printed circuit boards can easily lead to electrical breakdown or leakage, affecting the switching frequency and the electrical insulation of the package.

⚗Method used

The chip-embedded package structure is adopted. By forming a stepped structure on the first side of the metal substrate, the thickness of the second surface is reduced. Connectors are used to extend horizontally across the second surface within the molding layer to the first side of the base circuit board, increasing the spacing to ensure electrical insulation. At the same time, the molding layer is used to wrap the connectors to reduce leakage and electrical breakdown.

🎯Benefits of technology

It improves the electrical insulation and reliability of the embedded chip package, increases wiring freedom, reduces the risk of leakage and electrical breakdown, and ensures electrical insulation of different lead-out signals when they are routed laterally.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present application discloses a chip-embedded package. The chip-embedded package comprises a base circuit board, a chip unit, a plastic packaging layer, and a plurality of connecting members; the chip unit is fixedly mounted in a corresponding mounting slot, and the chip unit comprises a metal substrate and a chip; a step having a first surface and a second surface is formed on the metal substrate, and the chip is fixedly connected to the second surface; the first surface protrudes from the second surface, and the second surface extends to at least one side edge of the metal substrate; one end of each connecting member is correspondingly connected to the chip, and the other end of the connecting member extends to a first side of the plastic packaging layer so as to be exposed; the connecting members include a first connecting member, one end of the first connecting member is connected to a first side of the chip, and the other end of the first connecting member crosses the second surface to horizontally extend to a first side of the base circuit board and extend to the edge of a board so as to be exposed. By means of the described arrangement, the present application can reduce the risk of electrical aging and insulation failure of the chip-embedded package.
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