Optically isolated solid-state relay

Abstract

The present application relates to the technical field of solid-state relays, and provides an optically isolated solid-state relay. The optically isolated solid-state relay comprises: an input delay circuit, an input discharge circuit, an isolation module, an output delay circuit, an output anti-interference circuit, and an MOS transistor. The input delay circuit is used for performing delay processing on an input signal. The input discharge circuit is configured to provide a discharge circuit for an input capacitor when an input is turned off. The input delay circuit comprises the input capacitor. An output end of the output delay circuit is connected to a gate and a source of the MOS transistor. The output delay circuit is used for performing slow turn-on processing on the MOS transistor. The output anti-interference circuit is connected between the output delay circuit and the MOS transistor. The output anti-interference circuit is configured to provide a discharge path for a gate-source voltage of the MOS transistor when a peak voltage is generated at an output end of the MOS transistor. By implementing the technical solution provided in the present application, the reliability and stability of the optically isolated solid-state relay are improved.

Description

A type of optically isolated solid-state relay Technical Field

[0001] This application relates to the field of solid-state relay technology, specifically to an optically isolated solid-state relay. Background Technology

[0002] Solid-state relays (SSRs) offer advantages such as small size, high reliability, and long lifespan, and are gradually replacing traditional electromagnetic contact relays in high-reliability applications, particularly in demanding control systems. SSRs also prevent arcing that can occur with contact relays. However, in recent years, magnetically isolated SSRs have shown poor performance in electromagnetic compatibility (EMC) tests, exhibiting false triggering at certain frequency bands.

[0003] In systems with high reliability requirements (such as ignition systems), a delay of several milliseconds is typically required to prevent false turn-on of solid-state relays due to input interference signals. This is usually implemented using an RC network. However, when the delay time requirement is long, the time constant of the RC network is large. During turn-off, the capacitor discharges slowly, and the field-effect transistor may burn out due to partial conduction. This results in poor reliability and stability of solid-state relays in related technologies. Therefore, providing a solid-state relay with delayed turn-on and rapid input discharge has become an urgent technical problem to be solved in this field. Summary of the Invention

[0004] To address the aforementioned issues, this application provides an optically isolated solid-state relay.

[0005] In a first aspect, this application provides an optically isolated solid-state relay, comprising: an input delay circuit, an input discharge circuit, an isolation module, an output delay circuit, an output anti-interference circuit, and a MOSFET. The input delay circuit is connected between the input terminal of the optically isolated solid-state relay and the input terminal of the isolation module, and is used to delay the input signal. The input discharge circuit is connected to the input delay circuit and is configured to provide a discharge path for the input capacitor when the input is turned off. The input delay circuit includes an input capacitor. The input terminal of the output delay circuit is connected to the output terminal of the isolation module, and the output terminal of the output delay circuit is connected to the gate and source of the MOSFET. The drain and source of the MOSFET serve as the positive and negative output terminals of the optically isolated solid-state relay, respectively. The output delay circuit is used to perform a soft-turn-on process on the MOSFET. The output anti-interference circuit is connected between the output delay circuit and the MOSFET, and is configured to provide a discharge path for the gate-source voltage of the MOSFET when a spike voltage is generated at the output terminal of the MOSFET.

[0006] Optionally, the input delay circuit includes: a first resistor, a first capacitor, a first diode, and a first Zener diode. The first terminal of the first resistor is electrically connected to the positive input terminal of the opto-isolated solid-state relay. The second terminal of the first resistor is electrically connected to the positive terminal of the first diode. The negative terminal of the first diode is electrically connected to the negative terminal of the first Zener diode. The positive terminal of the first Zener diode is electrically connected to the positive input terminal of the isolation module. The negative input terminal of the isolation module is electrically connected to the negative input terminal of the opto-isolated solid-state relay. The first capacitor is connected between the negative terminal of the first Zener diode and the negative input terminal of the opto-isolated solid-state relay. The first capacitor is the input capacitor.

[0007] Optionally, the input bleeder circuit includes: a first transistor, a second transistor, a second resistor, and a third resistor. The first transistor is a PNP transistor, with its emitter electrically connected to the negative terminal of a first Zener diode, its base electrically connected to the positive terminal of the first diode, and its collector electrically connected to the negative input terminal of the opto-isolated solid-state relay via the second resistor. The second transistor is an NPN transistor, with its collector electrically connected to the base of the first transistor, its base electrically connected to the collector of the first transistor, and its emitter electrically connected to the negative input terminal of the opto-isolated solid-state relay. When the input is turned off, the voltage across the first capacitor is rapidly discharged through the second resistor. The third resistor is connected between the base of the first transistor and the negative input terminal of the opto-isolated solid-state relay.

[0008] Optionally, the isolation module includes a light-emitting diode (LED) chip and a photovoltaic cell chip. The positive terminal of the LED chip is electrically connected to the positive terminal of the first Zener diode, and the negative terminal of the LED chip is electrically connected to the negative input terminal of the optically isolated solid-state relay. The positive terminal of the photovoltaic cell chip is electrically connected to the gate of the MOSFET through an output delay circuit, and the negative terminal of the photovoltaic cell chip is electrically connected to the negative output terminal of the optically isolated solid-state relay. The isolation module is used to achieve optical isolation between the input and output of the optically isolated solid-state relay.

[0009] Optionally, the capacitance value of the first capacitor can be adjusted to meet the delay time requirements of the input delay circuit.

[0010] Optionally, the output delay circuit includes a fourth resistor, a second capacitor, and a fifth resistor. The first end of the fourth resistor is electrically connected to the positive output terminal of the isolation module, the second end of the fourth resistor is electrically connected to the gate of the MOSFET through the fifth resistor, the second capacitor is connected between the second end of the fourth resistor and the negative output terminal of the isolation module, and the negative output terminal of the isolation module is electrically connected to the negative output terminal of the opto-isolated solid-state relay.

[0011] Optionally, the output anti-interference circuit includes a third transistor, which is a PNP transistor. The emitter of the third transistor is electrically connected to the gate of the MOSFET, the base of the third transistor is electrically connected to the second terminal of the fourth resistor, and the collector of the third transistor is electrically connected to the source of the MOSFET. When a spike voltage is generated at the output terminal of the MOSFET, the gate-source voltage of the MOSFET is discharged through the third transistor.

[0012] Optionally, the output anti-interference circuit also includes a sixth resistor, which is connected in parallel with the second capacitor.

[0013] Optionally, the aforementioned optically isolated solid-state relay further includes: a second Zener diode, wherein the negative terminal of the second Zener diode is electrically connected to the gate of the MOSFET, and the positive terminal of the second Zener diode is electrically connected to the source of the MOSFET.

[0014] Optionally, the MOSFET mentioned above is an NMOS transistor.

[0015] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. They solve problems such as mis-conduction, slow capacitor discharge, output surges, and damage from spike voltages, improving the reliability and stability of the opto-isolated solid-state relay. By reducing faults caused by mis-conduction, semi-conduction burnout, and damage from spike voltages, they extend the service life of the opto-isolated solid-state relay. 2. The discharge circuit composed of the first transistor and the second transistor can quickly conduct when the input is turned off, allowing the voltage across the first capacitor to be quickly released through the second resistor, improving the reliability and safety of the system and avoiding the problem of semi-conduction or even burnout of the field-effect transistor caused by the slow capacitor discharge during turn-off in the RC network of related technologies. 3. The output anti-interference circuit can effectively reduce the impact of spike voltages on the circuit, helping to absorb and discharge spike voltages, and enhancing the anti-interference capability of the entire opto-isolated solid-state relay. Attached Figure Description

[0016] Figure 1 is a structural block diagram of an optically isolated solid-state relay provided in an embodiment of this application; Figure 2 is a schematic diagram of the input circuit of an optically isolated solid-state relay provided in an embodiment of this application; Figure 3 is a schematic diagram of the output circuit of an optically isolated solid-state relay provided in an embodiment of this application; Figure 4 is a schematic diagram of the circuit of an optically isolated solid-state relay with delay and anti-interference provided in an embodiment of this application.

[0017] Explanation of reference numerals in the attached diagram: R1 - First resistor, R2 - Second resistor, R3 - Third resistor, R4 - Fourth resistor, R5 - Fifth resistor, R6 - Sixth resistor, C1 - First capacitor, C2 - Second capacitor, D1 - First diode, ZD1 - First Zener diode, ZD2 - Second Zener diode, V1 - First transistor, V2 - Second transistor, V3 - Third transistor, V4 - Light-emitting diode chip, V5 - Photovoltaic cell chip, Q1 - NMOS transistor, IM1 - Isolation module. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0019] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0020] In the description of the embodiments of this application, the term "multiple" means two or more. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0021] The embodiments of this application will be described below with reference to Figures 1-4.

[0022] This application provides an optically isolated solid-state relay, as shown in Figure 1. Figure 1 is a structural block diagram of an optically isolated solid-state relay provided in an embodiment of this application, including: an input delay circuit, an input discharge circuit, an isolation module, an output delay circuit, an output anti-interference circuit, and a MOSFET. The input delay circuit is connected between the input terminal of the optically isolated solid-state relay and the input terminal of the isolation module, and is used to delay the input signal. The input discharge circuit is connected to the input delay circuit and is configured to provide a discharge circuit for the input capacitor when the input is turned off. The input delay circuit includes an input capacitor. The input terminal of the output delay circuit is connected to the output terminal of the isolation module, and the output terminal of the output delay circuit is connected to the gate and source of the MOSFET. The drain and source of the MOSFET serve as the positive and negative output terminals of the optically isolated solid-state relay, respectively. The output delay circuit is used to perform a soft-turn-on process on the MOSFET. The output anti-interference circuit is connected between the output delay circuit and the MOSFET. The output anti-interference circuit is configured to provide a discharge path for the gate-source voltage of the MOSFET when a spike voltage is generated at the output terminal of the MOSFET.

[0023] In the above embodiments, the optically isolated solid-state relay implements input signal delay processing, effectively preventing false turn-on phenomena caused by input interference signals. Simultaneously, the input discharge circuit provides a fast discharge path for the input capacitor when the input is turned off, avoiding the risk of MOSFET half-conduction burnout caused by slow capacitor discharge. The output delay circuit performs soft turn-on processing on the MOSFET, further improving the system's stability and reliability. The output anti-interference circuit provides a discharge path for the gate-source voltage of the MOSFET when a voltage spike is generated at the MOSFET output, enhancing the device's anti-interference capability. This technical solution solves problems such as false turn-on, slow capacitor discharge, output surges, and damage from voltage spikes, improving the reliability and stability of the optically isolated solid-state relay. By reducing faults caused by false turn-on, half-conduction burnout, and damage from voltage spikes, it extends the service life of the optically isolated solid-state relay.

[0024] The optically isolated solid-state relay structure of this embodiment includes an input delay circuit, an input discharge circuit, an isolation module, an output delay circuit, an output anti-interference circuit, and a MOSFET. The input delay circuit delays the input signal, which helps prevent false triggering caused by input interference. The input delay circuit effectively delays the input signal, ensuring that operation only begins after receiving a valid signal for a sustained period, avoiding malfunctions caused by brief interference. The input discharge circuit is connected to the input delay circuit, providing a fast discharge path for the input capacitor, solving the problems of slow capacitor discharge and potential half-conduction burnout of the MOSFET. The isolation module provides electrical isolation between the input and output, improving the relay's safety and reliability. The output delay circuit provides a soft turn-on process for the MOSFET, helping to reduce output surges and instability. The output anti-interference circuit provides a discharge path for the MOSFET's gate-source voltage, preventing voltage spikes from damaging the MOSFET. The MOSFET acts as the relay's output switch, with its drain and source serving as the positive and negative output terminals of the optically isolated solid-state relay, respectively. By using an input delay circuit, the response time of the input signal can be extended, thereby preventing false turn-on caused by input interference signals. The input discharge circuit can quickly discharge the charge in the input capacitor, avoiding the risk of the MOSFET burning out during half-conduction. The output delay circuit can slow down the turn-on speed of the output terminal, reducing output surges and instability. The output anti-interference circuit provides a discharge path for the gate-source voltage of the MOSFET, preventing voltage spikes from damaging the MOSFET. In summary, the circuit structure of the optically isolated solid-state relay in this embodiment significantly improves the performance of the solid-state relay, making it more suitable for high-reliability applications.

[0025] In an optional embodiment, as shown in FIG2, the input delay circuit includes: a first resistor R1, a first capacitor C1, a first diode D1, and a first Zener diode ZD1. The first end of the first resistor R1 is electrically connected to the positive input terminal of the opto-isolated solid-state relay, the second end of the first resistor R1 is electrically connected to the positive terminal of the first diode D1, the negative terminal of the first diode D1 is electrically connected to the negative terminal of the first Zener diode ZD1, the positive terminal of the first Zener diode ZD1 is electrically connected to the positive input terminal of the isolation module IM1, the negative input terminal of the isolation module IM1 is electrically connected to the negative input terminal of the opto-isolated solid-state relay, and the first capacitor C1 is connected between the negative terminal of the first Zener diode ZD1 and the negative input terminal of the opto-isolated solid-state relay. The first capacitor C1 is an input capacitor.

[0026] In the above embodiments, input signal delay processing is implemented, effectively preventing false triggering caused by input interference signals. As shown in Figure 2, the input circuit of this optically isolated solid-state relay includes an input delay circuit and an input discharge circuit. Specifically, the input delay circuit, composed of a first resistor R1, a first capacitor C1, a first diode D1, and a first Zener diode ZD1, ensures that the input signal triggers subsequent circuit actions only after a predetermined delay time by delaying the input signal, thereby improving the stability and reliability of the system. Furthermore, this design can adapt to delay requirements in different application scenarios, enhancing the product's flexibility and applicability.

[0027] The first resistor R1 and the first capacitor C1 together form an RC delay circuit. The delay time can be adjusted by combining the forward voltage drop of the first Zener diode ZD1 and the LED chip V4 in the input terminal of the isolation module IM1. The delay time is the time it takes for the voltage across the first capacitor C1 to rise to the sum of the Zener diode ZD1's regulated voltage and the forward voltage drop of the LED chip V4 in the isolation module IM1. This embodiment, through the combination of the first resistor R1, the first capacitor C1, the first diode D1, and the first Zener diode ZD1, can precisely control the delay of the input signal, meeting the time control requirements of specific applications. The function of the first Zener diode ZD1 is to stabilize the voltage, ensuring that the input signal voltage is at a safe and stable level, and avoiding the impact of voltage fluctuations on relay operation.

[0028] In an optional embodiment, as shown in FIG2, the input discharge circuit includes: a first transistor V1, a second transistor V2, a second resistor R2 and a third resistor R3, wherein the first transistor V1 is a PNP transistor, the emitter of the first transistor V1 is electrically connected to the negative terminal of the first Zener diode ZD1, the base of the first transistor V1 is electrically connected to the positive terminal of the first diode D1, and the collector of the first transistor V1 is electrically connected to the negative input terminal of the optically isolated solid-state relay through the second resistor R2; The second transistor V2 is an NPN transistor. The collector of the second transistor V2 is electrically connected to the base of the first transistor V1, and the base of the second transistor V2 is electrically connected to the collector of the first transistor V1. The emitter of the second transistor V3 is electrically connected to the negative input terminal of the opto-isolated solid-state relay. When the input is turned off, the voltage across the first capacitor C1 is rapidly discharged through the second resistor R2. The third resistor R3 is connected between the base of the first transistor V1 and the negative input terminal of the opto-isolated solid-state relay.

[0029] In the above embodiment, when the input is turned off, the voltage across the first capacitor C1 of the optically isolated solid-state relay can be quickly discharged through the second resistor R2, thereby avoiding the problem of slow capacitor discharge in the RC network of related technologies, which leads to the semi-conductivity or even burnout of the field-effect transistor. Specifically, the discharge circuit composed of the first transistor V1 and the second transistor V2 can quickly conduct when the input is turned off, so that the voltage across the first capacitor C1 is quickly released through the second resistor R2, improving the reliability and safety of the system.

[0030] In existing technologies, when the input signal is turned off, the charge discharge rate in the input capacitor may be slow, causing components such as field-effect transistors (FETs) to remain in a semi-conductive state, which may lead to burnout or other malfunctions over time. The input discharge circuit, through a carefully designed combination of transistors (first transistor V1 and second transistor V2) and resistors (second resistor R2 and third resistor R3), achieves rapid discharge of charge from the input capacitor (first capacitor C1). When the input signal is turned off, first transistor V1 and second transistor V2 form a discharge path, allowing the voltage across first capacitor C1 to drop rapidly, thus preventing malfunctions caused by FETs and other components remaining in a semi-conductive state for extended periods. Rapid discharge of capacitor charge not only protects FETs and other components from damage but also improves the stability and reliability of the entire circuit, which helps extend the relay's lifespan and reduce downtime due to malfunctions. The rapid discharge effect is achieved through a two-stage amplification using first transistor V1 and second transistor V2.

[0031] In an optional embodiment, the isolation module IM1 includes a light-emitting diode chip V4 and a photovoltaic cell chip V5. The positive terminal of the light-emitting diode chip V4 is electrically connected to the positive terminal of the first Zener diode ZD1, and the negative terminal of the light-emitting diode chip V4 is electrically connected to the negative input terminal of the optically isolated solid-state relay. The positive terminal of the photovoltaic cell chip V5 is electrically connected to the gate of the MOSFET through an output delay circuit, and the negative terminal of the photovoltaic cell chip V5 is electrically connected to the negative output terminal of the optically isolated solid-state relay. The isolation module IM1 is used to achieve optical isolation between the input and output of the optically isolated solid-state relay.

[0032] In the above embodiment, the optically isolated solid-state relay achieves effective optical isolation between the input and output, ensuring the safety and stability of the relay under high-voltage environments. Specifically, the combined use of the light-emitting diode chip V4 and the photovoltaic cell chip V5 allows the input signal to be transmitted to the output terminal via optical signals, avoiding the electromagnetic interference problems present in traditional electrical isolation methods and improving the system's anti-interference capability. Simultaneously, this optical isolation design effectively prevents interference signals at the input terminal from directly affecting the output terminal, further enhancing the reliability and safety of the relay.

[0033] The isolation module IM1 (also known as the optical isolation module) in this embodiment uses a light-emitting diode (LED) chip V4 and a photovoltaic cell chip V5 to achieve optical isolation, as shown in Figures 2-4. This eliminates the influence of electromagnetic interference, ensuring the reliability and stability of the signal transmission as the optical signal is unaffected by electromagnetic fields. The LED chip V4 converts the input signal into an optical signal, which is then received and converted back into an electrical signal by the photovoltaic cell chip V5, achieving complete electrical isolation between the input and output. The isolation module uses a combination of LED chip V4 and photovoltaic cell chip V5 to achieve complete electrical isolation between the input and output. This effectively prevents electrical noise, interference, and the risk of electric shock, improving the safety and reliability of the relay. As optocouplers, the LED chip V4 and photovoltaic cell chip V5 have fast response speeds and low transmission delays. Furthermore, since optical signal transmission is unaffected by electrical characteristics, signal distortion is greatly reduced, improving relay performance. As solid-state components, the LED chip V4 and photovoltaic cell chip V5 possess high reliability and stability. They are not easily affected by environmental factors such as temperature and humidity, thus maintaining stable isolation over long periods.

[0034] In an optional embodiment, the capacitance value of the first capacitor C1 can be adjusted to meet the delay time requirements of the input delay circuit.

[0035] In the above embodiments, the delay time of the input delay circuit can be flexibly adjusted to adapt to the needs of different application scenarios. Specifically, the capacitance value of the first capacitor C1 can be adjusted according to actual needs, thereby precisely controlling the delay time of the input signal, ensuring effective prevention of false triggering under various operating conditions, and improving the reliability and stability of the system.

[0036] This embodiment allows for adjustment of the capacitance value of the first capacitor C1 to meet different delay time requirements. This increases the flexibility and applicability of the optically isolated solid-state relay, enabling its application in a wider range of scenarios. There is no need to design and manufacture different relays for each delay time requirement; the desired delay time can be achieved simply by adjusting the capacitance value. This reduces design and manufacturing costs and improves production efficiency. When the delay time needs to be adjusted, only the capacitor needs to be replaced or adjusted, without requiring large-scale modifications to the entire circuit. This simplifies the maintenance and upgrade process and reduces maintenance costs.

[0037] In an optional embodiment, as shown in FIG3, the output delay circuit includes: a fourth resistor R4, a second capacitor C2 and a fifth resistor R5, wherein the first end of the fourth resistor R4 is electrically connected to the positive output terminal of the isolation module IM1, the second end of the fourth resistor R4 is electrically connected to the gate of the MOS transistor through the fifth resistor R5, the second capacitor C2 is connected between the second end of the fourth resistor R4 and the negative output terminal of the isolation module IM1, and the negative output terminal of the isolation module IM1 is electrically connected to the negative output terminal of the opto-isolated solid-state relay.

[0038] In the above embodiments, the output signal is slow-on processing is implemented, which effectively avoids the current surge caused by the rapid turn-on of the MOSFET and improves the stability and reliability of the system; at the same time, the delay time is controlled by the RC network, so that the output delay is adjustable to meet the needs of different application scenarios.

[0039] As shown in Figure 3, the output circuit of this optically isolated solid-state relay includes an output delay circuit, an output anti-interference circuit, and a MOSFET. In this embodiment, the output delay circuit, through the combination of a fourth resistor R4, a second capacitor C2, and a fifth resistor R5, controls the output response time. When the input signal changes, the output does not respond immediately but changes only after a delay. This achieves gradual control of the MOSFET gate voltage rise, effectively avoiding current surges caused by rapid conduction. This helps reduce electrical shocks and interference, and improves circuit stability. By adjusting the resistance values ​​of the fourth resistor R4, the second capacitor C2, and the fifth resistor R5, the output delay time can be flexibly adjusted to meet the needs of different application scenarios. This increases the flexibility and applicability of the relay; the output delay function provides a smooth transition when the relay switches states, reducing the impact and damage to the load equipment caused by instantaneous voltage or current changes; the output delay circuit can effectively filter out instantaneous interference in the input signal, ensuring that the output signal will only change after the input signal has been continuous for a period of time, avoiding malfunctions of the load equipment; the charging and discharging process of the second capacitor C2 ensures a smooth transition of the output signal when it is turned on and off, reducing the impact on the load equipment and improving the reliability and lifespan of the system.

[0040] In an optional embodiment, as shown in FIG3, the output anti-interference circuit includes a third transistor V3, which is a PNP transistor. The emitter of the third transistor V3 is electrically connected to the gate of the MOSFET, the base of the third transistor V3 is electrically connected to the second terminal of the fourth resistor R4, and the collector of the third transistor V3 is electrically connected to the source of the MOSFET. When a spike voltage is generated at the output terminal of the MOSFET, the gate-source voltage of the MOSFET is discharged through the third transistor V3.

[0041] In the above embodiment, when a spike voltage is generated at the output terminal of the MOSFET, the third transistor V3 quickly turns on to discharge the gate-source voltage of the MOSFET, thereby effectively avoiding the risk of damage to the MOSFET due to overvoltage and improving the stability and reliability of the opto-isolated solid-state relay.

[0042] During the switching process of a MOSFET, voltage spikes are easily generated due to parasitic parameters and rapid voltage changes in the circuit. This can lead to device damage or affect circuit stability. Without effective spike suppression measures, the spikes generated by the MOSFET during switching can damage the circuit, especially in high-frequency switching applications. In this embodiment, by using a third transistor V3, when a voltage spike is generated at the output of the MOSFET, the gate-source voltage of the MOSFET can be discharged through the third transistor V3, effectively reducing the impact of the voltage spike on the circuit. The addition of the third transistor V3 provides an additional anti-interference path, which helps to absorb and discharge voltage spikes, enhancing the anti-interference capability of the entire opto-isolated solid-state relay. The discharge of voltage spikes can protect the MOSFET from the effects of voltage spikes, extend the life of the MOSFET, and improve the reliability of the entire relay. By discharging voltage spikes, the system can better cope with various interferences, improving anti-interference capability and stability. The output circuit of the solid-state relay in the related technology does not provide an effective output anti-interference circuit. As a result, when the output voltage rises at a fast rate, part of the output voltage will be coupled to the gate through the parasitic capacitance between the drain and gate of the MOSFET and charge the second capacitor C2. Since there is no fast discharge circuit in the circuit, the coupled voltage cannot be discharged quickly. When the accumulated charge exceeds the threshold voltage of the power MOSFET, it will cause the power MOSFET to turn on erroneously. The output anti-interference circuit provided in this embodiment can solve this problem.

[0043] In an optional embodiment, as shown in FIG3, the output anti-interference circuit further includes a sixth resistor R6, wherein the sixth resistor R6 is connected in parallel with the second capacitor C2.

[0044] In the above embodiment, when a voltage spike is generated at the output terminal of the MOSFET, the gate-source voltage of the MOSFET can be quickly discharged through the third transistor V3, effectively protecting the MOSFET from damage. Simultaneously, the sixth resistor R6 is connected in parallel with the second capacitor C2, further accelerating the charging and discharging speed of the second capacitor C2 and improving the system's response speed and stability.

[0045] When the photovoltaic cell chip does not provide a fast discharge path, rapid discharge can be achieved through the sixth resistor. In this embodiment, the sixth resistor R6 and the second capacitor C2 are connected in parallel to form an RC discharge circuit. When it is necessary to discharge the gate-source voltage, the sixth resistor R6 can provide an additional discharge path, accelerating the discharge process of the capacitor and thus more effectively suppressing voltage spikes. By accelerating the discharge speed of the second capacitor C2, the MOSFET can enter the fully off state more quickly when turned off, reducing the partial conduction time and lowering the risk of burnout. The combination of the sixth resistor R6 and the third transistor V3 provides a dual protection mechanism. The third transistor V3 is responsible for rapidly discharging the gate-source voltage when a voltage spike occurs, while the sixth resistor R6 accelerates the discharge process of the second capacitor C2, further reducing the duration of the voltage spike. By accelerating the capacitor discharge speed and enhancing the voltage spike discharge effect, the system can better cope with various interferences and abnormal situations, reduce the failure rate of the MOSFET, and improve the stability and reliability of the system.

[0046] In an optional embodiment, the optically isolated solid-state relay further includes a second Zener diode ZD2, wherein the negative terminal of the second Zener diode ZD2 is electrically connected to the gate of the MOSFET, and the positive terminal of the second Zener diode ZD2 is electrically connected to the source of the MOSFET.

[0047] In the above embodiment, the second Zener diode ZD2 can play a voltage stabilizing role when the gate-source voltage of the MOSFET exceeds a certain threshold, effectively protecting the MOSFET from overvoltage impact, improving the voltage withstand capability of the MOSFET, and thus enhancing the reliability and stability of the entire opto-isolated solid-state relay.

[0048] As shown in Figures 3 and 4, a second Zener diode ZD2 is also provided in the output circuit. By setting the second Zener diode ZD2, the maximum voltage of the MOSFET gate can be limited, preventing excessive voltage from damaging the MOSFET and thus protecting it. The addition of the second Zener diode ZD2 helps stabilize the gate voltage of the MOSFET, reduces the impact of voltage fluctuations on the MOSFET's operating state, and improves the stability of the circuit. The second Zener diode ZD2 can absorb and limit voltage spikes caused by external interference or internal circuit changes, enhancing the anti-interference capability of the entire optically isolated solid-state relay.

[0049] In an optional embodiment, the MOS transistor is an NMOS transistor Q1.

[0050] In the above embodiment, NMOS transistor Q1 is selected as the output control element, which makes it perform well in terms of low power consumption and high efficiency, while improving the overall performance of the system.

[0051] The NMOS transistor Q1, with its low on-resistance, reduces power loss and improves circuit efficiency. Its fast switching characteristics enhance circuit response speed, which is crucial for applications requiring rapid switching. Furthermore, the NMOS transistor Q1 performs exceptionally well in high-frequency and high-power applications, exhibiting high reliability and stability. This allows the relay to operate stably for extended periods in these applications, reducing the failure rate. The NMOS transistor Q1 also maintains stable performance at high temperatures, adapting to various harsh operating conditions and improving the system's environmental adaptability and reliability.

[0052] It should be noted that the embodiments described above are only some embodiments of this application, and not all embodiments. The present application will be described in detail below with reference to specific embodiments.

[0053] This application provides a time-delay anti-interference optically isolated solid-state relay. Figure 4 is a circuit diagram of a time-delay anti-interference optically isolated solid-state relay provided in this application. The circuit includes an input section (or input circuit) and an output section (or output circuit). An isolation module is connected between the input circuit and the output circuit to achieve electrical isolation between the input and output. The isolation module includes a light-emitting diode chip V4 and a photovoltaic cell chip V5. The input circuit is shown in Figure 2, and the output circuit is shown in Figure 3.

[0054] The working principles of the input circuit and the output circuit are explained below.

[0055] (1) Input Circuit The input circuit structure of the solid-state relay in this embodiment is shown in Figure 2. Its delay function is achieved through a first capacitor C1, a first resistor R1, a first Zener diode ZD1, and a light-emitting diode chip V4. The first capacitor C1 and the first resistor R1 form an RC delay network. The delay time can be adjusted by combining the first Zener diode ZD1 and the light-emitting diode chip V4. The delay time is the time it takes for the voltage across the first capacitor C1 to rise to the sum of the Zener diode ZD1's regulated voltage and the LED chip V4's on-state voltage.

[0056] The circuit shown in Figure 2 also has anti-temperature drift function. By utilizing the temperature drift characteristics of the first Zener diode ZD1 (with a Zener voltage greater than 6.2V) and the LED chip V4 (at low temperatures, the forward voltage of the LED chip V4 increases, and the Zener voltage of the first Zener diode ZD1 decreases, thus offsetting the effect of temperature change; at high temperatures, the two change in opposite directions, similarly offsetting the effect of temperature change), the circuit improves the disadvantage of large temperature drift during delay across the entire temperature range.

[0057] Furthermore, some related technologies employ a combination of multiple resistors to achieve the delay, which imposes significant limitations on the resistor values ​​and may lead to a shortened delay time during high-frequency switching. In contrast, the delay function in the circuit of Figure 2 in this embodiment is only affected by the first capacitor C1, the first resistor R1, the first Zener diode ZD1, and the LED chip V4. Under the condition of ensuring the rated voltage, the LED drive current I... C With an input current ≥10mA, the resistance value of the first resistor R1 can be determined. Afterward, only the capacitance value of the first capacitor C1 needs to be adjusted to achieve the desired delay time. In Figure 2, the effect of the first diode D1 on the input delay is negligible. The main function of the first diode D1 is to ensure that when the input is off, the voltage across the first capacitor C1 is discharged through the first transistor V1, rather than directly through the third resistor R3, thus achieving rapid discharge.

[0058] For the input delay circuit shown in Figure 2, when the product is turned on, the voltage relationship through the RC series circuit is: U=U0e -t / τ In the formula: Uo is the relay input voltage in V; t is time; τ is the time constant of the RC circuit.

[0059] From the above formula, the input connection time of the product can be obtained as: T≈-τln[1-(U2+U E1 [) / (U0-U1)], where U1 represents the forward voltage drop of the first diode, U2 represents the voltage regulation value of the first Zener diode, and U E1 This indicates the on-state voltage drop of the LED chip V4 in the isolation module IM1.

[0060] In this circuit, the first resistor R1 and the first capacitor C1 form an RC delay network, which, together with the first Zener diode ZD1 and the LED chip V4, adjusts the delay time. The delay time is the time it takes for the voltage across the first capacitor C1 to rise to the sum of the Zener diode ZD1's regulated voltage and the LED chip V4's on-state voltage. At the same time, this circuit also has an anti-temperature drift function, which is achieved through the opposite temperature drift characteristics of the first Zener diode ZD1 and the LED chip V4.

[0061] The key to the input circuit in this embodiment lies in the fact that this relay product uses a first diode D1, a first transistor V1, a second transistor V2, and a second resistor R2 to form a fast input discharge circuit, thus improving upon the slow input discharge of related technologies. When the input is off, due to the presence of the first diode D1, when the voltage across the first capacitor C1 is more than 0.7V higher than the base of the first transistor V1, the first transistor V1 will conduct, and the voltage across the first capacitor C1 will be discharged through the second resistor R2. Furthermore, since the second resistor R2 is independent of the delay-on system, its resistance value is not limited by the parameters of other components in the circuit, and its discharge rate is greatly improved compared to circuits in related technologies.

[0062] (2) Output circuit The output circuit structure of the solid relay in this embodiment of the application is shown in Figure 3.

[0063] For the output soft-turn-on circuit, the soft-turn-on principle of the circuit in Figure 3 is as follows: the fourth resistor R4 and the second capacitor C2 form an RC delay network. In addition, the parasitic capacitance between the fifth resistor R5 and the drain-gate of the NMOS transistor Q1 also forms a delay network, which plays a soft-turn-on role and also has an anti-input interference function. When there is a strong interference voltage at the input, the voltage coupled to the secondary side will be filtered and absorbed by the RC circuit (such as R4C2), which has a good anti-input interference capability. On this basis, the output circuit of this embodiment reduces the risk of product mis-turn-on caused by the output peak voltage by adding a third transistor V3. When a peak voltage is suddenly applied to the output, the coupled gate-source voltage V GS The capacitor C2 is charged through the BE junction of the third transistor V3. During the charging process, the third transistor V3 will be turned on, and the gate-source voltage will be discharged through the third transistor V3. This limits the coupled gate voltage to the on-state voltage drop of the BE junction of the transistor, thereby relaxing the requirement for the threshold voltage of the field-effect transistor. Even if the threshold voltage of the field-effect transistor is low, there will be no false turn-on when a sudden peak voltage is applied to the output.

[0064] The output circuit of the solid-state relay in the related technology does not use the third transistor V3 as shown in Figure 3, resulting in poor immunity to output spike interference. Because the electrodes of the power MOSFET are not physically isolated, parasitic capacitance exists between them. When the output voltage rises rapidly, part of the output voltage will couple to the gate through parasitic capacitance (such as the parasitic capacitance between the drain and gate of the NMOS transistor), charging the second capacitor C2. Due to the lack of a fast discharge circuit in the loop, the coupled voltage cannot be discharged quickly. When the accumulated charge exceeds the threshold voltage of the power MOSFET, it will cause the power MOSFET to malfunction and turn on. Therefore, the output circuit of the solid-state relay in the related technology has poor performance. The output circuit of the embodiment of this application effectively improves the immunity to output spike interference.

[0065] In summary, the embodiments of this application provide a solid-state relay circuit that simultaneously features delayed turn-on, rapid input discharge, and anti-interference capabilities.

[0066] It should be noted that the above embodiments of the apparatus are only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided above belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0067] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0068] The above description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the disclosure herein.

[0069] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art that are not described in this disclosure.

Claims

1. A light-isolated solid-state relay, characterized in that, include: The circuit includes an input delay circuit, an input bleeder circuit, an isolation module, an output delay circuit, an output anti-interference circuit, and a MOSFET. The input delay circuit is connected between the input terminal of the optically isolated solid-state relay and the input terminal of the isolation module, and the input delay circuit is used to delay the input signal; The input discharge circuit is connected to the input delay circuit. The input discharge circuit is configured to provide a discharge circuit for the input capacitor when the input is turned off. The input delay circuit includes the input capacitor. The input terminal of the output delay circuit is connected to the output terminal of the isolation module, and the output terminal of the output delay circuit is connected to the gate and source of the MOS transistor. The drain and source of the MOS transistor serve as the positive and negative output terminals of the optically isolated solid-state relay, respectively. The output delay circuit is used to perform a soft-turn-on process on the MOS transistor. The output anti-interference circuit is connected between the output delay circuit and the MOS transistor. The output anti-interference circuit is configured to provide a discharge path for the gate-source voltage of the MOS transistor when a spike voltage is generated at the output terminal of the MOS transistor.

2. The optically isolated solid-state relay according to claim 1, characterized in that, The input delay circuit includes: a first resistor, a first capacitor, a first diode, and a first Zener diode, wherein, The first end of the first resistor is electrically connected to the positive input terminal of the optically isolated solid-state relay, the second end of the first resistor is electrically connected to the positive terminal of the first diode, the negative terminal of the first diode is electrically connected to the negative terminal of the first Zener diode, the positive terminal of the first Zener diode is electrically connected to the positive input terminal of the isolation module, the negative input terminal of the isolation module is electrically connected to the negative input terminal of the optically isolated solid-state relay, and the first capacitor is connected between the negative terminal of the first Zener diode and the negative input terminal of the optically isolated solid-state relay, wherein the first capacitor is the input capacitor.

3. The optically isolated solid-state relay according to claim 2, characterized in that, The input discharge circuit includes: a first transistor, a second transistor, a second resistor, and a third resistor, wherein, The first transistor is a PNP transistor. The emitter of the first transistor is electrically connected to the negative terminal of the first Zener diode, the base of the first transistor is electrically connected to the positive terminal of the first diode, and the collector of the first transistor is electrically connected to the negative input terminal of the optically isolated solid-state relay through the second resistor. The second transistor is an NPN transistor. The collector of the second transistor is electrically connected to the base of the first transistor, the base of the second transistor is electrically connected to the collector of the first transistor, and the emitter of the second transistor is electrically connected to the negative input terminal of the optically isolated solid-state relay. When the input is turned off, the voltage across the first capacitor is rapidly discharged through the second resistor. The third resistor is connected between the base of the first transistor and the negative input terminal of the optically isolated solid-state relay.

4. The optically isolated solid-state relay according to claim 2, characterized in that, The isolation module includes a light-emitting diode (LED) chip and a photovoltaic cell chip. The positive terminal of the LED chip is electrically connected to the positive terminal of the first Zener diode, and the negative terminal of the LED chip is electrically connected to the negative input terminal of the optically isolated solid-state relay. The positive terminal of the photovoltaic cell chip is electrically connected to the gate of the MOS transistor through the output delay circuit, and the negative terminal of the photovoltaic cell chip is electrically connected to the negative output terminal of the optically isolated solid-state relay. The isolation module is used to achieve optical isolation between the input and output of the optically isolated solid-state relay.

5. The optically isolated solid-state relay according to claim 2, characterized in that, The capacitance value of the first capacitor can be adjusted to meet the delay time requirements of the input delay circuit.

6. The optically isolated solid-state relay according to claim 1, characterized in that, The output delay circuit includes: a fourth resistor, a second capacitor, and a fifth resistor, wherein, The first end of the fourth resistor is electrically connected to the positive output terminal of the isolation module, the second end of the fourth resistor is electrically connected to the gate of the MOS transistor through the fifth resistor, the second capacitor is connected between the second end of the fourth resistor and the negative output terminal of the isolation module, and the negative output terminal of the isolation module is electrically connected to the negative output terminal of the optically isolated solid-state relay.

7. The optically isolated solid-state relay according to claim 6, characterized in that, The output anti-interference circuit includes a third transistor, which is a PNP transistor. The emitter of the third transistor is electrically connected to the gate of the MOS transistor, the base of the third transistor is electrically connected to the second terminal of the fourth resistor, and the collector of the third transistor is electrically connected to the source of the MOS transistor. When a spike voltage is generated at the output terminal of the MOS transistor, the gate-source voltage of the MOS transistor is discharged through the third transistor.

8. The optically isolated solid-state relay according to claim 7, characterized in that, The output anti-interference circuit further includes a sixth resistor, wherein the sixth resistor is connected in parallel with the second capacitor.

9. The optically isolated solid-state relay according to claim 1, characterized in that, The optically isolated solid-state relay further includes a second Zener diode, wherein the negative terminal of the second Zener diode is electrically connected to the gate of the MOS transistor, and the positive terminal of the second Zener diode is electrically connected to the source of the MOS transistor.

10. The optically isolated solid-state relay according to claim 9, characterized in that, The MOS transistor is an NMOS transistor.

Images