Configurable pulsed laser diode driver

Abstract

A laser diode driver includes a clock terminal to receive a clock signal, a configuration terminal to receive configuration data, drive terminals, and charge terminals. A first charge terminal is operable to charge a source capacitor of a resonant circuit that includes the source capacitor, an inductor, and a bypass capacitor. Each drive terminal is operable to be directly electrically connected to an anode or a cathode of a laser diode or directly electrically connected to ground. A pattern of drive signals delivered to the laser diode, an output selection, and a grouping are configured based on the configuration data. The laser diode driver is operable to control a current through the resonant circuit to generate high current pulses through the laser diode that correspond to peak currents of a resonant waveform emitted at respective anodes of the laser diode, timing of the high current pulses is synchronized using the clock signal.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Nonprovisional Application No. 17 / 446,606, filed August 31, 2021, and U.S. Provisional Application No. 63 / 075,527, filed September 8, 2020, and U.S. Provisional Application No. 63 / 127,794, filed December 18, 2020, all of which are incorporated herein by reference in their entirety for all purposes. Background Technology

[0003] For example, laser-based ranging systems in lidar often use pulsed laser diode driver circuits to generate short, high-current pulses that pass through the laser diode to emit a corresponding laser pulse. The reflected laser pulse is received by the lidar system and used to determine the distance between the lidar system and the reflecting point. The spatial resolution of a lidar system is partly determined by the width of the laser pulse, so it is generally desirable to generate light pulses with a width of approximately 5 ns or less. However, the parasitic inductance of the pulsed laser diode driver circuit and the laser diode must often be overcome to achieve the desired short pulse width. For example, many laser diodes have at least one junction line that can provide an inductance of 1 nH, thus limiting the slew rate of the current pulse unless a very high voltage is available. Therefore, some conventional pulsed laser diode driver circuits use high source voltages, often greater than 40V to 100V, to achieve the desired pulse width. For example, GaN field-effect transistor (FET) switching devices are often used in conventional pulsed laser diode driver circuits because these switching devices can withstand such high voltages. However, pulsed laser diode driver circuits using GaN technology may be more expensive and / or more difficult to integrate with silicon-based architectures.

[0004] There are many types of laser diode package configurations, ranging from packages that house a single laser diode to packages that house four laser diodes (“quadruple packs”), and even packages that house arrays of tens of thousands of laser diodes. Furthermore, the package pin outputs differ between various laser diode configurations (e.g., between the package pin outputs of a single-sided or quad-sided emitting laser diode configuration and the package pin outputs of a vertical-cavity surface-emitting laser (VCSEL) laser diode configuration). Summary of the Invention

[0005] In some embodiments, a laser diode driver includes a clock terminal operable to receive a clock signal, a configuration terminal operable to receive configuration data, a charging terminal, and a drive terminal. A first charging terminal of the charging terminal is operable to charge a first source capacitor of a first resonant circuit. The first resonant circuit includes the first source capacitor, a first inductor, and a first bypass capacitor. Each drive terminal is operable to be directly electrically connected to the anode or cathode of the laser diode or directly electrically connected to ground. The mode, output selection, and grouping of the drive signal delivered to the laser diode are configured based on the configuration data. The laser diode driver is operable to control the current through the first resonant circuit to generate high-current pulses through the laser diode, the high-current pulses corresponding to the peak current of a resonant waveform emitted at the corresponding anode of the laser diode, the timing of the high-current pulses being synchronized using the clock signal.

[0006] In some embodiments, a device includes a clock terminal operable to receive a clock signal, a configuration terminal operable to receive configuration data, a charging terminal, and a drive terminal. A first charging terminal is directly electrically connected to a first source capacitor of a first resonant circuit. The first resonant circuit includes the first source capacitor, a first inductor, and a first bypass capacitor. Each drive terminal is directly electrically connected to the anode or cathode of a laser diode or directly electrically connected to ground. The first inductor has a first terminal and a second terminal, the first terminal of the first inductor being operable to receive a charging voltage from the first charging terminal of the plurality of charging terminals. The first source capacitor has a first terminal directly electrically connected to the first terminal of the first inductor and a second terminal electrically coupled to ground. The first bypass capacitor has a first terminal directly electrically connected to the second terminal of the first inductor and a second terminal directly electrically connected to the second terminal of the first source capacitor. The device is operable to control the current through the first resonant circuit to generate high-current pulses through the laser diode, the high-current pulses corresponding to the peak current of a resonant waveform emitted at a corresponding anode of the laser diode, the timing of the high-current pulses being synchronized using the clock signal. Attached Figure Description

[0007] According to some implementation plans Figures 1A to 1C This is a simplified circuit diagram of a pulsed laser diode driver with the first common topology.

[0008] According to some implementation plans Figures 2A to 2D It shows the relationship with Figure 1A The diagram shows a simplified graph of the signals related to the operation of the pulsed laser diode driver.

[0009] According to some implementation plans Figure 3 It is used for Figures 1A to 1C The example shown is a portion of an operating sequence of a pulsed laser diode driver.

[0010] According to some implementation plans Figures 4A to 4D This is a simplified circuit diagram of a pulsed laser diode driver with a second common topology.

[0011] According to some implementation plans Figures 5A to 5D This is a simplified circuit diagram of a pulsed laser diode driver with a third common topology.

[0012] According to some implementation plans Figures 6A to 6D This is a simplified circuit diagram of a pulsed laser diode driver with the fourth common topology.

[0013] According to some implementation plans Figures 7A to 7E This is a simplified circuit diagram of a pulsed laser diode driver with the fifth common topology.

[0014] According to some implementation plans Figures 8A to 8B This is a simplified circuit diagram of a pulsed laser diode driver with a sixth common topology.

[0015] According to some implementation plans Figures 9A to 9B This is a simplified circuit diagram of a pulsed laser diode driver with the seventh common topology.

[0016] According to some implementation plans Figure 10A This is a simplified circuit diagram of a configurable pulsed laser diode driver.

[0017] According to some implementation plans Figure 10B It shows and Figure 10A The diagram shows a simplified circuit diagram of a circuit used with a configurable pulsed laser diode driver.

[0018] According to some implementation plans Figure 11 It shows Figure 10A A simplified circuit diagram of a configurable pulsed laser diode driver when configured to drive two quadruple-group laser diode packages.

[0019] According to some implementation plans Figure 12 It shows Figure 10A A simplified circuit diagram of a configurable pulsed laser diode driver when it is configured to drive a single array of eight laser diodes.

[0020] According to some implementation plans Figure 13 It shows Figure 10A A simplified circuit diagram of a configurable pulsed laser diode driver when it is configured to drive a single array of 16 laser diodes.

[0021] According to some implementation plans Figure 14 This is a simplified circuit diagram of another configurable pulsed laser diode driver configured to drive a 64-row VCSEL laser diode array.

[0022] According to some implementation plans Figure 15 yes Figure 10A A table showing example configurations for configurable pulsed laser diode drivers.

[0023] According to some implementation plans Figures 16A to 16B yes Figure 10A A partial view of a table showing an example configuration of a configurable pulsed laser diode driver.

[0024] According to some implementation plans Figure 17 yes Figure 14 A photograph showing a portion of the implementation of the configurable pulsed laser diode driver. Detailed Implementation

[0025] According to some implementations, compared to conventional solutions that rely on fixed and often unavoidable parasitic capacitances and inductances in the circuitry, the pulsed laser diode driver circuit (“pulsed laser diode driver”) disclosed herein generates high-current (e.g., 40 Amp) ultrashort pulses (e.g., 4 ns) to emit laser pulses from a laser diode using a tunable resonant circuit. The tunable resonant circuit provides easily adjustable parameters that control the pulse width, peak current, charging time, recovery time, decay time, and other adjustable parameters of the pulsed laser diode driver. Implementations of a switching sequence for driving the pulsed laser diode driver disclosed herein are operable to generate a resonant waveform at the anode of the laser diode to produce high-current pulses through the laser diode, the voltage level of which is advantageously sufficient to support the high-current pulses, rather than exceeding the voltage level required to generate them.

[0026] Therefore, implementations of such pulsed laser diode drivers can advantageously generate high-current pulses using low input voltages (e.g., 6V, 9V, 15V, etc.), and thus can use silicon-based switches instead of GaN-based switches used in many conventional solutions. Any of the pulsed laser diode drivers disclosed herein can therefore be integrated into a single semiconductor die. The implementations of the pulsed laser diode drivers disclosed herein advantageously use discrete inductors (e.g., vias or surface mount components) intentionally added to the pulsed laser diode driver to generate resonant waveforms, rather than relying on parasitic inductances of the pulsed laser diode driver (e.g., the laser diode, junction wires, or inter-circuit connections). As a result, the laser driver implementations disclosed herein are easy to tune and have a reproducible architecture. In contrast, conventional pulsed laser diode drivers often employ multiple techniques to overcome the effects of parasitic inductances in the pulsed laser diode driver and the laser diode itself, and thus teach against intentionally adding additional inductance to the pulsed laser diode driver. Compared to conventional solutions that only have source capacitors or only consider the non-tunable parasitic capacitance of the pulsed laser diode driver, the pulsed laser diode driver disclosed herein advantageously includes a bypass capacitor in addition to such intentionally added inductors. This bypass capacitor can be used by the designer to easily tune the desired pulse width emitted by the laser diode. Again, such conventional solutions teach against adding additional capacitance to the pulsed laser diode driver. Because conventional solutions rely on the parasitic capacitance and inductance of conventional laser drivers, modifying parameters such as pulse width may require redesigning or rearranging the conventional solution. In contrast, the parameters (e.g., pulse width) of the pulsed laser diode driver disclosed herein can be tuned by simply changing component values.

[0027] There are many types of laser diode package configurations, ranging from packages housing a single laser diode to packages housing four laser diodes (“quadruple packs”), and even arrays of tens of thousands of laser diodes in a single package. Furthermore, the package pin outputs differ between various laser diode configurations (e.g., between the package pin outputs of a single-sided or quad-sided emitting laser diode configuration and the package pin outputs of a vertical-cavity surface-emitting laser (VCSEL) laser diode configuration). However, the laser diodes in various configurations share similar characteristics, such as the high threshold turn-on voltage and internal series resistance that determine the transfer function of the laser diode device. As disclosed herein, configurable pulsed laser diode drivers are advantageously operable to control a wide variety of laser diode package configurations that can be varied in terms of the number, type, and grouping of laser diodes.

[0028] According to some implementation plans Figures 1A to 1CThis is a simplified circuit diagram of pulsed laser diode drivers 101 to 103 using a first common topology to drive the laser diode using a low-side switch. Each of the pulsed laser diode drivers 101 to 103 typically includes a source resistor R. S Source capacitor C S Damping resistor R Damp Inductor L S Bypass capacitor C BP Laser diode D L Bypass switch M BP and laser diode switch M DL Laser diode switch M DL It is configured as a low-side switch. Controller 120, nodes 110 and 112, and laser diode D are also shown. L parasitic inductance L DL DC input voltage V in Source capacitor C S Source voltage V at the location s Through inductor L S current i LS Through laser diode D L current i DL Bypass switch gate driver signal GATE BP and the laser diode switching gate driver signal GATE DL .

[0029] The topology of pulsed laser diode drivers 101 to 103 with respect to bypass capacitor C BP The placement is changed. In each of the topologies of pulsed laser diode drivers 101 to 103, the source resistor R... S The first terminal is configured to be directly electrically connected to the DC input voltage V. in Source capacitor C S The first terminal is directly electrically connected to the source resistor R. S The second terminal, source capacitor C S The second terminal is directly electrically connected to the damping resistor R. Damp The first terminal. Damping resistor R Damp The second terminal of the inductor L is directly electrically connected to a bias voltage node, for example, ground. S The first terminal is directly electrically connected to the source resistor R. S The second terminal and source capacitor C S The first terminal. Bypass switch M BP The drain node is directly connected to the inductor L S The second terminal, and the bypass switch M BPThe source node is directly electrically connected to the bias voltage node. Laser diode D L The anode is directly electrically connected to the inductor L S The second terminal, and the laser diode D L The cathode is directly electrically connected to the laser diode switch M. DL The drain node. Laser diode switch M DL The source node is directly electrically connected to the bias voltage node.

[0030] Bypass switch M BP Configured to receive the bypass switch gate driver signal GATE at the gate node BP Bypass switch gate driver signal GATE BP Operable based on the bypass switch gate driver signal GATE BP The voltage level is used to turn the bypass switch M on or off. BP Similarly, the laser diode switch M DL Configured to receive the laser diode switching gate driver signal GATE at the gate node. DL Laser diode gate driver signal GATE DL Operable based on laser diode switching gate driver signal GATE DL The voltage level is used to turn the laser diode switch M on or off. DL In some embodiments, the pulsed laser diode driver circuit disclosed herein includes one or more bootstrap circuits or other level-shifting circuits to drive one or more high-side switches. Bypass switch M BP and laser diode switch M DL Any one or both can be implemented as an N-type switch or a P-type switch. In some embodiments, the bypass switch M BP and laser diode switch M DL It is implemented as a silicon-based or silicon carbide-based field-effect transistor (FET). Described herein as two or more components having directly electrically connected terminals, with a DC current path between the respective terminals of the two or more components. For example, the first and second components are not directly electrically connected via a capacitor connected in series between the first and second components.

[0031] like Figure 1A A simplified circuit diagram of the pulsed laser diode driver 101 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode D L The anode. In these embodiments, the bypass capacitor C BPThe second terminal is directly electrically connected to the bias voltage node. For example... Figure 1B A simplified circuit diagram of the pulsed laser diode driver 102 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode D L The anode. Bypass capacitor C BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal. For example... Figure 1C A simplified circuit diagram of the pulsed laser diode driver 103 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode D L The anode. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the laser diode switch M. DL Drain terminals and laser diode D L The cathode.

[0032] In some embodiments, pulsed laser diode drivers 101 to 103 are configured to receive a DC input voltage V having a voltage range of approximately 10V to 20V. in This is advantageously lower than the input voltage used by many conventional pulsed laser diode drivers. Inductor L S This refers to the physical components added to the pulsed laser diode drivers 101 to 103 (i.e., the opposite of the representation of parasitic inductance caused by components or interconnections such as bonding wires). Similarly, the bypass capacitor C BP This refers to the physical components added to the pulsed laser diode drivers 101 to 103 (i.e., the opposite of the representation of parasitic capacitance). One advantage of using physical inductors and capacitors instead of parasitic inductors is that the inductor L... S and bypass capacitor C BP The value can be easily modified by the designer or even the end user. In contrast, conventional designs that rely on parasitic reactance may require redesign and / or rearrangement to change the operating parameters.

[0033] As disclosed in this article, the DC input voltage V in Inductor L S Inductance, source capacitor C S Capacitors and damping resistors R Damp The resistor and bypass capacitor C BPThe value of the capacitor can be advantageously selected (“tuned”) to achieve the desired operation of the pulsed laser diode drivers 101 to 103 (e.g., charging time, pulse width, pulse voltage, pulse current). For example, the current flowing through the laser diode D... L current i DL The pulse width can be adjusted by changing the bypass capacitor C. BP The capacitance value is used for tuning. The current flows through the laser diode D. L current i DL The peak current level of the pulse can be adjusted by adjusting the supply capacitor C. S Source voltage V s To tune. Source capacitor C S The capacitance value can be tuned to adjust the timing delay of the current pulse and the voltage across the laser diode D. L current i DL The upper limit of the damping resistor R. Damp The resistance value depends on the supply capacitor C. S The capacitance value can be tuned within a range, such that the low-frequency resonant damping of the pulsed laser diode driver disclosed herein is insufficient at lower resistances (e.g., at approximately R0). Damp =0.1 ohms), or critical damping (e.g., at approximately R). Damp =0.4 ohms). Damping resistor R Damp Operable to prevent the current in the generated resonant waveform from becoming negative, thereby enabling the bypass switch M. BP Or laser diode switch M DL The body diode. Although for the critical damping case, through the laser diode D L current i DL The resulting maximum current level is relatively low, but this can be improved by increasing the DC input voltage V. in The voltage level can be used to easily adjust the current level. In other implementations, the damping resistor R Damp This will be completely removed from the design (i.e., the source capacitor C). S The second terminal is directly electrically connected to the bias voltage node. In other embodiments, the damping resistor R Damp The resistance value is set to zero ohms.

[0034] In some implementations, the DC input voltage V in The voltage is approximately 15V, and the inductor L S The inductance is approximately 6nH, and the source capacitor C S The capacitance is approximately 100nF, and the damping resistor R Damp The resistance is approximately 0.1 ohms, and the bypass capacitor C BP The capacitance is approximately 1 nF. In some implementations, the damping resistor R...Damp The voltage at the first terminal is received by the controller 120 to provide power through the damping resistor R. Damp The current indication.

[0035] The controller 120 may be integrated with any embodiment of the pulsed laser diode driver disclosed herein, or the controller may be circuitry or a module outside of any embodiment of the pulsed laser diode driver disclosed herein. The controller 120 is operable to generate one or more gate drive signals sufficient to control one or more laser diode switches M. DL and one or more bypass switches M BP The controller 120 is operable to sense the voltage and / or current at any of nodes 110 and 112 and at nodes similar to or identical to nodes 110 and 112 described herein or at other nodes of the pulsed laser diode driver disclosed herein. The controller 120 may include one or more timing circuits, lookup tables, processors, memory, or other modules to control the pulsed laser diode driver disclosed herein. The operation of the pulsed laser diode drivers 101 to 103 will be referenced... Figures 2A to 2D The simplified curves 201 to 207 are explained in detail, and the example switch sequence 300 is shown in... Figure 3 As shown in the image.

[0036] According to some implementation plans Figures 2A to 2D It shows the relationship with Figure 1A Simplified graphs 201 to 207 show the signals associated with the operation of the pulsed laser diode driver 101. However, the signals associated with the operation of pulsed laser diode drivers 101 to 103, 401 to 404, 501 to 504, 601 to 604, 701 to 705, 801 to 802, and 901 to 902 are similar to or the same as those shown in simplified graphs 201 to 207.

[0037] Simplified graph 201 illustrates the bypass switch gate driver signal GATE. BP Voltage curve of 220, laser diode gate switch driver signal GATE DL The voltage curve of 221, through inductor L S current i LS The current curve of 222, through the laser diode D L current i DL The current curve of 223 and the source capacitor C S Source voltage V at the location SThe voltage curves for 224 are all within the same duration. Details of these signals are described below. Bypass switch gate driver signal GATE. BP 220 and laser diode switching gate driver signal GATE DL The voltage curve for the 221 has been level-shifted for readability, but it actually represents a low-voltage input. Additionally, the bypass switch gate driver signal GATE... BP 220 and laser diode switching gate driver signal GATE DL The voltage curve of 221 assumes the laser diode switch M DL and bypass switch M BP It is an NFET device. However, if a PFET device is used instead, the bypass switch gate driver signal GATE is required. BP 220 and laser diode switching gate driver signal GATE DL The polarity of 221 is reversed.

[0038] In the bypass switch M BP The bypass switch gate driver signal GATE is received at the gate node (e.g., from controller 120). BP After the claimed level of 220, bypass switch M BP It is enabled (i.e., switched to the closed (ON) state). Similarly, in the laser diode switch M... DL The laser diode switching gate driver signal GATE is received at the gate node (e.g., from controller 120). DL After the claimed level of 221, the laser diode switch M DL Enabled. As highlighted in graph 202, when bypass switch M... BP When enabled, the rising current i LS 222 begins to flow through inductor L S Thus in the inductor L S A magnetic flux is established at the point. When the current i LS When 222 has reached the desired level (e.g., determined by controller 120 using sensed current, voltage, timer circuitry, or by design constraints), the bypass switch M... BP The bypass switch gate driver signal GATE is received at the gate node (e.g., from controller 120). BP The 220 declaring level is then used to disable the bypass switch M. BP (That is, switching to the OFF state). As highlighted in graph 203, when the bypass switch M... BP When it is deactivated, through inductor L S The established current i has no other current path. LS222 was redirected through laser diode D L This results in short (e.g., 2ns to 5ns) high current (e.g., >30A) pulses flowing through the laser diode D. L This causes the laser diode D to... L The laser pulse is emitted. Because energy in the form of magnetic flux is already stored in the inductor L. S Therefore, the current flows through the laser diode D. L high current pulse i DL It can be significantly greater than the current flowing through the inductor L. S current i LS The reactance value of the laser diode driver disclosed herein can be advantageously selected to generate high-current pulses i DL The expected current amplitude.

[0039] From laser diode D L After transmission, the bypass switch receives the bypass switch gate driver signal GATE. BP The claimed level of 220 was re-enabled, and the laser diode switch M... DL The gate driver signal GATE is switched via the laser diode. DL The claimed level of 221 remains in the enabled state. As highlighted in graph 204, bypass switch M... BP and laser diode switch M DL All are advantageously maintained in the enabled state because of the storage in the source capacitor C S The source voltage Vs 224 at the point is discharged. As highlighted in graph 205, when the bypass switch M... BP and laser diode switch M DL When maintained in the enabled state, via laser diode D L (Importantly, via laser diode D) L parasitic inductance L DL The current i DL 223 decreases to zero. Afterwards, bypass switch M... BP and laser diode switch M DL All are driven by the bypass switch gate driver signal GATE BP 220 and laser diode switching gate driver signal GATE DL The deactivation claim level of 221 (e.g., from controller 120) is disabled. This is because the laser diode switch M... DL Until it passes through laser diode D L parasitic inductance L DL The current was reduced to zero before it was deactivated, so the high voltage spikes were advantageously avoided in the laser diode D. L It forms at the anode because of the parasitic inductance LDL The current does not change rapidly. Because this advantageously mitigates such high voltage spikes, there is no need to select a laser diode switch M. DL This allows the pulsed laser diode driver disclosed herein to withstand high voltages, thereby simplifying the design and reducing its cost compared to conventional solutions. Furthermore, because such high voltage spikes are mitigated, the pulsed laser diode driver disclosed herein does not require the voltage buffer circuit commonly used in conventional solutions, further simplifying the design and reducing its cost compared to conventional solutions.

[0040] The high-current pulse 223 is the first and largest peak of the resonant waveform emitted by the reactive portion of the pulsed laser diode driver circuit. This reactive portion includes the source capacitor C. S Inductor L S Laser diode D L parasitic inductance L DL and bypass capacitor C BP In addition to the advantages mentioned above, the bypass switch M BP It also reduces the subsequent resonant waveform "ringing" after the high-current pulse 223 is generated. As shown in curve 206, if in the high-current pulse i DL After 223' is generated, the bypass switch gate driver signal GATE... BP If 220' is not claimed, then ringing occurs through inductor L. S current i LS On 222', it appears through the laser diode D L current i DL 223', and appears on the source capacitor C S Source voltage V at the location S 224' on.

[0041] As mentioned earlier, the source capacitor C S Inductor L S and bypass capacitor C BP The value of can be advantageously chosen or “tuned” by the designer to meet the desired performance criteria of the pulsed laser diode driver disclosed herein. For example, the bypass capacitor C BP The capacitance value can be based on the laser diode D L current i DL The desired pulse width is selected. Figure 207 shows the selection when the bypass capacitor C... BP The pulse 223 generated when the capacitance is equal to 1nF, and the pulse generated when the bypass capacitor C BPThe pulse 223” is generated when the capacitance is equal to 4nF. In applications requiring a wider pulse (e.g., pulse 223”), the source voltage V… S The value can be increased accordingly. Additionally, in some implementations, the bypass switch gate driver signal GATE is... BP The width of the release claim section of 220 has been widened to accommodate wider pulses.

[0042] According to some implementation plans, and as referenced Figures 2A to 2C As described, Figure 3 The diagram is used for Figures 1A to 1B The example switch sequence 300 shown is a portion of the operation of the pulsed laser diode drivers 101 to 103. However, the switch sequence 300 is similar to or the same as the corresponding switch sequences for the operation of the pulsed laser diode drivers 401 to 404, 501 to 504, 601 to 604, 701 to 705, 801 to 802 and 901 to 902.

[0043] In the pre-charging step 301, the bypass switch M BP and laser diode switch M DL Open (i.e., non-conductive). During pre-charge step 301, the source capacitor C S Through the source resistor R S Charging is initiated. In pre-current step 302, bypass switch M... BP and laser diode switch M DL It transitions to a closed state, thereby allowing current i LS Flow through inductor L S To store energy in the form of magnetic flux in inductor L S In the middle. Even if two switches (M) DL M BP In the pre-flow step 302, when the circuit is closed, the bypass switch M... BP The bypass path will carry all current i LS This is because it is necessary to overcome the limitations of laser diode D. L The bandgap voltage allows current to flow through the laser diode D. L .

[0044] In some implementations, in the bypass switch M BP After switching to the closed state, the laser diode switch M DL It transitions to a closed state. In pulse generation step 303, bypass switch M... BP It switches to the open state, while the laser diode switch M DL Maintaining it in a closed state, thereby generating light through the laser diode D. L High current pulse. When bypass switch M BP When switched to the on state, the laser diode DL The voltage at the anode rises rapidly until the laser diode D... L The bandgap voltage is overcome and the laser diode D L Current begins to conduct. This is due to the bypass capacitor C. BP and laser diode D L parasitic inductance L DL The resulting resonant circuit is formed in the laser diode D. L The voltage at the anode will advantageously rise up to overcome the limitations of the laser diode D. L The bandgap voltage is required and is typically higher than the source voltage V. S .

[0045] In discharge step 304, bypass switch M BP and laser diode switch M DL Maintaining the closed state to drain the energy stored in the source capacitor C S The charge in the middle, thereby reducing the charge through the parasitic inductance L DL current i DL In the laser diode switch M DL When switched to the on state, it advantageously eliminates the laser diode D. L The high voltage spike at the anode. In step 305, the bypass switch M... BP and laser diode switch M DL It transitions to the open state, thus returning to the pre-charge state at step 301. This is because the source capacitor C... S Source voltage V at the location S The laser diode D is completely discharged at the end of discharge step 304, so a very small current flows through it. L Therefore, when switch M DL M BP When the laser diode D transitions to the on state in step 305, there is an advantageously very small overshoot, thereby preventing damage to the laser diode D. L and switch M DL M BP This can cause damage. In some implementations, the time interval between the total pulse signal and the bypass signal is selected such that the source capacitor C... S In switch M DL M BP Completely discharge before transitioning to the open state in step 305.

[0046] Other topologies of pulsed laser drivers that have the same or similar advantages and similar operation as pulsed laser diode drivers 101 to 103 will be disclosed below. The example topologies disclosed herein are not an exhaustive list of possible topologies that have the same or similar advantages and similar operation as pulsed laser diode drivers 101 to 103. For example, those skilled in the art will appreciate that some modifications can be made while still adhering to the general operating principles disclosed herein. These modifications include the placement of a bypass capacitor C. BP Component values ​​and the addition of series components to provide a DC current path.

[0047] According to some implementation plans Figures 4A to 4D This is a simplified circuit diagram of pulsed laser diode drivers 401 to 404, configured to drive two or more laser diodes arranged in a common anode configuration, representing a second common topology. Each of the pulsed laser diode drivers 401 to 404 typically includes a source resistor R. S Source capacitor C S Damping resistor R Damp Inductor L S Bypass capacitor C BP Two or more laser diodes D L 1 To D L n and bypass switch M BP Pulsed laser diode drivers 401 to 402 each include two or more laser diode switches M. DL 1 To M DL n The pulsed laser diode drivers 403 to 404 include a single laser diode switch M. DL 1 .

[0048] The controller 120, nodes 410 and 412, and laser diode D are also shown. L 1 To D L n The corresponding parasitic inductance L DL 1 To L DL n DC input voltage V in Source capacitor C S Source voltage V at the location S Through inductor L S current i LS Through laser diode D L 1 To D L n The corresponding current iDL 1 to i DL n and the bypass switch gate driver signal GATE BP The pulsed laser diode drivers 401 to 402 each utilize the corresponding laser diode switching gate driver signal GATE. DL 1 To GATE DL n The pulsed laser diode drivers 403 to 404 use a single laser diode to switch the gate driver signal GATE. DL 1 The electrical connections of pulsed laser diode drivers 401 to 404 are similar to or the same as those described for pulsed laser diode drivers 101 to 103. The topology of pulsed laser diode drivers 401 to 404 relates to the bypass capacitor C. BP The placement has changed.

[0049] like Figure 4A Pulsed laser diode driver 401 and Figure 4D A simplified circuit diagram of the pulsed laser diode driver 404 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode D L 1 To D L n The anode. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the bias voltage node. For example... Figures 4B to 4C A simplified circuit diagram of pulsed laser diode drivers 402 to 403 is shown. In some embodiments, bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode D L 1 To D L n The corresponding anode. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal. In some implementations, the DC input voltage V in Inductor L S Inductance, source capacitor C S Capacitors and damping resistors R Damp The resistor and bypass capacitor C BPThe capacitance value is similar to or the same as those described in reference pulsed laser diode drivers 101 to 103. However, the DC input voltage V in Inductor L S Inductance, source capacitor C S Capacitors and damping resistors R Damp The resistor and bypass capacitor C BP The value of the capacitor can be advantageously selected to achieve the desired operation of the pulsed laser diode drivers 401 to 404 (e.g., charging time, pulse width, pulse voltage, pulse current level). The operation of the pulsed laser diode drivers 401 to 404 is related to... Figures 2A to 2D Simplified curves 201 to 206 and Figure 3 The operation of the pulsed laser diode drivers 101 to 103 is similar to or the same as that of the example switch sequence 300 shown in detail.

[0050] In some implementations, controller 120 is configured to determine the laser diode D L 1 To D L n How many are simultaneously enabled and the DC input voltage V is adjusted accordingly based on the determination. in The voltage level is adjusted to supply the required amount of current (e.g., using a digitally adjustable voltage source (not shown) controlled by a digital control signal from controller 120).

[0051] According to some implementation plans Figures 5A to 5D This is a simplified circuit diagram of pulsed laser diode drivers 501 to 504, configured to drive the laser diode using a high-side switch, representing a third common topology. Each of the pulsed laser diode drivers 501 to 504 typically includes a source resistor R. S Source capacitor C S Damping resistor R Damp Inductor L S Bypass capacitor C BP Laser diode D L Bypass switch M BP and laser diode switch M DL Laser diode switch M DL It is configured as a high-side switch.

[0052] The controller 120, nodes 510 and 512, and laser diode D are also shown. L parasitic inductance L DL DC input voltage V in Source capacitor C S Source voltage V at the location S Through inductor L Scurrent i LS Through laser diode D L current i DL Bypass switch gate driver signal GATE BP and the laser diode switching gate driver signal GATE DL The electrical connections of the pulsed laser diode drivers 501 to 504 are largely similar to or the same as those described for pulsed laser diode drivers 101 to 103. However, unlike the low-side configuration of the pulsed laser diode drivers 101 to 103, the laser diode switch M... DL The drain node is directly connected to the inductor L S The second terminal and bypass switch M BP The drain node. Laser diode switch M DL The source node is directly electrically connected to the laser diode D. L The anode, and the laser diode D L The cathode is directly electrically connected to the bias voltage node. The topology of the pulsed laser diode drivers 501 to 504 is related to the bypass capacitor C. BP The placement has changed.

[0053] like Figure 5A A simplified circuit diagram of the pulsed laser diode driver 501 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode switch M DL The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is directly electrically connected to the bias voltage node. For example... Figure 5B A simplified circuit diagram of the pulsed laser diode driver 502 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the laser diode switch M. DL The source node and laser diode D L The anode. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the bias voltage node. For example... Figure 5C A simplified circuit diagram of the pulsed laser diode driver 503 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S Second terminal, bypass switch M BP The drain node and laser diode switch M DL The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is directly electrically connected to the source capacitor C.S The second terminal and the damping resistor R Damp The first terminal. For example... Figure 5D A simplified circuit diagram of the pulsed laser diode driver 504 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the laser diode switch M. DL The source node and laser diode D L The anode. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal.

[0054] According to some implementation plans Figures 6A to 6D This is a simplified circuit diagram of pulsed laser diode drivers 601 to 604 in a fourth common topology, configured to drive two or more laser diodes in a common-cathode configuration using a high-side switch. Each pulsed laser diode driver 601 to 604 typically includes a source resistor R. S Source capacitor C S Damping resistor R Damp Inductor L S Bypass capacitor C BP Bypass switch M BP Two or more laser diodes D L 1 To D L n and two or more corresponding laser diode switches M DL 1 To M DL n .

[0055] The controller 120, nodes 610, 612, 614, and laser diode D are also shown. L 1 To D L n The corresponding parasitic inductance L DL 1 To L DL n DC input voltage V in Source capacitor C S Source voltage V at the location S Through inductor L S current i LS Through laser diode D L 1 To D L n The corresponding current iDL 1 to i DL n Bypass switch gate driver signal GATE BP and laser diode switch M DL 1 To M DL n The corresponding laser diode switch gate driver signal GATE DL 1 To GATE DL n .

[0056] The electrical connections of pulsed laser diode drivers 601 to 604 are largely similar to or the same as those described for pulsed laser diode drivers 501 to 504. However, the topology of pulsed laser diode drivers 601 to 604 relates to the bypass capacitor C. BP Their placement changes to each other.

[0057] like Figure 6A A simplified circuit diagram of the pulsed laser diode driver 601 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and the laser diode switch M DL 1 To M DL n and bypass switch M BP The corresponding drain node. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the bias voltage node. For example... Figure 6B A simplified circuit diagram of the pulsed laser diode driver 602 is shown. In some embodiments, the bypass capacitor C BP 1 To C BP n The corresponding first terminal is directly electrically connected to the laser diode switch M. DL 1 To M DL n The corresponding source node of any one of them and coupled to the corresponding anode of the laser diode of that laser diode switch. In these embodiments, the bypass capacitor C BP 1 To C BP n The second terminal is directly electrically connected to the bias voltage node. For example... Figure 6C A simplified circuit diagram of the pulsed laser diode driver 603 is shown. In some embodiments, the bypass capacitor C BPThe first terminal is directly electrically connected to the inductor L S The second terminal and the laser diode switch M DL 1 To M DL n and bypass switch M BP The corresponding drain node. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal. For example... Figure 6D A simplified circuit diagram of the pulsed laser diode driver 604 is shown. In some embodiments, the bypass capacitor C BP 1 To C BP n The corresponding first terminal is directly electrically connected to the laser diode switch M. DL 1 To M DL n The corresponding source node is coupled to the anode of the laser diode of that laser diode switch. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal.

[0058] In some implementations, controller 120 is operable to determine the laser diode D L 1 To D L n How many are simultaneously enabled and the DC input voltage V is adjusted accordingly based on the determination. in The voltage level is adjusted to supply the required amount of current (e.g., using a digitally adjustable voltage source (not shown) controlled by a digital control signal from controller 120).

[0059] According to some implementation plans Figures 7A to 7E This is a simplified circuit diagram of pulsed laser diode drivers 701 to 705, configured to drive laser diodes using a half-bridge configuration, representing a fifth common topology. Each of the pulsed laser diode drivers 701 to 704 typically includes a source resistor R. S Source capacitor C S Damping resistor R Damp Inductor L S Bypass capacitor C BP Bypass switch M BP Laser diode D L and laser diode switch M DLThe pulsed laser diode driver 705 further includes two or more laser diodes D. L 1 To D L n Instead of a single laser diode D L Two or more laser diodes D L 1 To D L n Each of them has a corresponding parasitic inductance L DL 1 To L DL n and the corresponding current representation i DL 1 to i DL n However, the pulsed laser diode driver 705 lacks support for two or more laser diodes D. L 1 To D L n Independent control.

[0060] The controller 120, nodes 710 and 712, and laser diode D are also shown. L parasitic inductance L DL DC input voltage V in Source capacitor C S Source voltage V at the location S Through inductor L S current i LS Through laser diode D L current i DL Through two or more laser diodes D L 1 To D L n current i DL 1 to i DL n Bypass switch gate driver signal GATE BP and laser diode switch M DL laser diode switch gate driver signal GATE DL .

[0061] The electrical connections of the pulsed laser diode drivers 701 to 704 are largely similar to or the same as those described for pulsed laser diode drivers 501 to 503. However, unlike the high-side configuration of the pulsed laser diode drivers 501 to 503, the bypass switch M... BP The drain node is directly electrically connected to the laser diode switch M. DLThe source node and laser diode D L The anode. Bypass switch M BP The source node is directly electrically connected to the bias voltage node. Therefore, as shown in the simplified circuit diagrams of pulsed laser diode drivers 701 to 704, the laser diode D... L By bypass switch M BP and laser diode switch M DL A half-bridge configuration is used to drive it. The topology of pulsed laser diode drivers 701 to 704 is related to the bypass capacitor C. BP The placement has changed.

[0062] like Figure 7A A simplified circuit diagram of the pulsed laser diode driver 701 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode switch M DL The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is electrically connected to the bias voltage node. For example... Figure 7B A simplified circuit diagram of the pulsed laser diode driver 702 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the laser diode switch M. DL The source node and bypass switch M BP The drain node and laser diode D L The anode. In these embodiments, the bypass capacitor C BP The second terminal is directly electrically connected to the bias voltage node. For example... Figure 7C A simplified circuit diagram of the pulsed laser diode driver 703 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal and laser diode switch M DL The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal. For example... Figure 7D A simplified circuit diagram of the pulsed laser diode driver 704 is shown. In some embodiments, the bypass capacitor C BP The first terminal is directly electrically connected to the laser diode switch M. DL The source node and bypass switch M BP The drain node and laser diode D L The anode. In these embodiments, the bypass capacitor CBP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal.

[0063] like Figure 7E A simplified circuit diagram of the pulsed laser diode driver 705 is shown, with two or more laser diodes D L 1 To D L n By bypass switch M BP and laser diode switch M DL The half-bridge configuration drives simultaneously. In the example shown, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal, while the bypass capacitor C BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal. However, a bypass capacitor C can be used. BP Other configurations, such as reference Figures 7A to 7D The configurations described.

[0064] According to some implementation plans Figures 8A to 8B This is a simplified circuit diagram of pulsed laser diode drivers 801 to 802, configured to drive the laser diode using a high-side switch, representing a sixth common topology. Pulsed laser diode drivers 801 to 802 typically include a source resistor R. S Source capacitor C S Damping resistor R Damp Inductor L S Bypass capacitor C BP Laser diode D L Bypass switch M BP and laser diode switch M DL The controller 120, nodes 810 and 812, and laser diode D are also shown. L The corresponding parasitic inductance L DL DC input voltage V in Source capacitor C S Source voltage V at the location S Through inductor L S current i LS Through laser diode D L current i DL Bypass switch gate driver signal GATE BP and the laser diode switching gate driver signal GATE DLThe electrical connections of pulsed laser diode driver 801 are similar to or the same as those described for pulsed laser diode driver 101. The difference between pulsed laser diode drivers 801 to 802 lies in the laser diode switch M. DL The drain node is directly electrically connected to the source resistor R. S The second terminal and source capacitor C S The first terminal. Laser diode switch M DL The source node is directly electrically connected to the inductor L S The first terminal. Laser diode D L The anode is directly electrically connected to the inductor L S The second terminal, and the laser diode D L The cathode is directly electrically connected to the bias voltage node. As shown in the figure, the pulsed laser diode drivers 801 to 802 are advantageously configured so that the laser diode switch M... DL Electrically connected to inductor L S With source capacitor C S Between. Therefore, when the bypass switch M BP Discontinued to generate via laser diode D L During high current pulses, the laser diode switch M DL The drain node does not receive in the inductor L S The high voltage spike emitted at the second terminal.

[0065] The difference between pulsed laser diode drivers 801 and 802 lies in the bypass capacitor C. BP Placement. For example... Figure 8A As shown, in some implementations, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal, laser diode D L anode and bypass switch M BP The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is directly electrically connected to the bias voltage node. For example... Figure 8B As shown, in some implementations, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal, laser diode D L anode and bypass switch M BP The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal.

[0066] In other implementations, inductor L S and laser diode switch M DL The respective positions of the pulsed laser diode drivers 801 to 802 can be interchanged, such that the inductor L S The first terminal is directly electrically connected to the source capacitor C. S The first terminal, and the laser diode switch M DL The drain terminal is directly connected to the inductor L. S The second terminal.

[0067] According to some implementation plans Figures 9A to 9B This is a simplified circuit diagram of pulsed laser diode drivers 901 to 902 in a seventh common topology, configured to drive the laser diode using only a bypass switch. Pulsed laser diode drivers 901 to 902 typically include a source resistor R. S Source capacitor C S Damping resistor R Damp Inductor L S Bypass capacitor C BP Laser diode D L and bypass switch M BP Nodes 910 and 912, and laser diode D are also shown. L The corresponding parasitic inductance L DL DC input voltage V in Source capacitor C S Source voltage V at the location S Through inductor L S current i LS Through laser diode D L current i DL and the bypass switch gate driver signal GATE BP The electrical connections of pulsed laser diode drivers 901 to 902 are similar to or the same as those described for pulsed laser diode driver 101. The difference between pulsed laser diode drivers 901 to 902 lies in the laser diode switch M. DL Eliminated. Laser diode D L The anode is directly electrically connected to the inductor L S The second terminal, and the laser diode D L The cathode is directly electrically connected to the bias voltage node. In these embodiments, the DC input voltage V in The voltage level limit is no more than that of the laser diode D. L The forward bias voltage level of the laser diode D, thereby controlling the voltage level of the forward bias voltage. L It remains in the open state (i.e., non-conductive) until the current flowing through the bypass switch is temporarily stopped in the inductor L.S A voltage higher than the forward bias voltage is applied at the second terminal.

[0068] The difference between pulsed laser diode drivers 901 and 902 lies in the bypass capacitor C. BP Placement. For example... Figure 9A As shown, in some implementations, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal, laser diode D L anode and bypass switch M BP The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is directly electrically connected to the bias voltage node. For example... Figure 9B As shown, in some implementations, the bypass capacitor C BP The first terminal is directly electrically connected to the inductor L S The second terminal, laser diode D L anode and bypass switch M BP The drain node. In these embodiments, the bypass capacitor C... BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal and the damping resistor R Damp The first terminal.

[0069] The embodiments of the pulsed laser diode driver disclosed herein are also operable to provide current pulses to a device other than a laser diode. For example, the embodiments of the pulsed laser diode driver disclosed herein are operable to provide current pulses to a light-emitting diode (i.e., a non-laser LED). Additionally, the embodiments of the pulsed laser diode driver disclosed herein are operable to provide current pulses to another circuit or device without a laser diode, said circuit or device being configured to receive current pulses for purposes other than emission.

[0070] In some embodiments, two or more instances of the laser diode drivers disclosed herein are configured to drive corresponding laser diodes. For example, four instances of the pulsed laser diode driver 802 can be used to drive a laser diode package comprising four laser diodes. In this embodiment, each of the laser diodes in the laser diode package is driven by an instance of the pulsed laser diode driver 802.

[0071] Configurable pulsed laser diode driver

[0072] There are many types of laser diode package configurations within a single laser diode package, ranging from a single diode to an array of tens of thousands of laser diodes. Furthermore, the package pin outputs differ between various laser diode configurations (e.g., between the package pin outputs of a single-sided or quad-sided emitting laser diode configuration and the package pin outputs of a VCSEL laser diode configuration).

[0073] Regardless of the package details, laser diodes share similar fundamental characteristics, such as high threshold turn-on voltage and internal series resistance, which determine the transfer function of the laser diode device. Furthermore, regardless of the package type, many laser diode applications frequently require very narrow, high-current pulses with relatively low repetition rates to limit power consumption within the laser diode. The configurable pulsed laser diode driver disclosed herein advantageously utilizes references... Figures 1A to 9B The bypass resonant driver architecture is described to drive many different pin configurations and laser emission sequences of various packaged laser diode devices.

[0074] According to some implementation plans Figure 10A This is a simplified circuit diagram of a configurable pulsed laser diode driver (“laser diode driver”) 1002. Generally, the configurable pulsed laser diode driver 1002 includes an input voltage terminal VIN, an operating voltage terminal VDD, a bias voltage terminal VSS, a clock terminal “clock”, charging terminals CIN1 to CIN4, and drive terminals ROW1 to ROW. n And configuration terminals, including pulse configuration terminals pw0 to pw1 and output selection configuration terminals s0 to s1. k The system includes mode configuration terminals m0 to m1, group configuration terminals e0 to e1, and charging configuration terminals c0 to c1. The number of terminals available for use as charging terminals, drive terminals, pulse configuration terminals, and configuration terminals can be selected during design as needed. Therefore, in some embodiments, the number of bits available for use as each of the charging terminals, drive terminals, and configuration terminals can be [number missing]. Figure 10A The different values ​​shown. For example, the charging terminals can be implemented as cin1 to cin. p The mode configuration terminals can be implemented as m0 to m q The group configuration terminals can be implemented as e0 to e r Furthermore, the charging configuration terminals can be implemented as C0 to C. s , where k, n, p, q, r, and s are any corresponding integers.

[0075] Drive terminals row1 to row nThis includes a first set of programmable drive terminals (e.g., 4 terminals, 8 terminals, 16 terminals, 32 terminals, 64 terminals, 128 terminals, or another number of terminals) and a second set of non-programmable drive terminals (e.g., one terminal, four terminals, or another number of terminals). For example, in some embodiments, the configurable pulsed laser diode driver 1002 has 16 programmable drive terminals and one non-programmable drive terminal. In other embodiments, the configurable pulsed laser diode driver 1002 has 64 programmable drive terminals and four non-programmable drive terminals (e.g., a 16-1 ratio).

[0076] row1 to row n The configuration of the programmable drive terminals is determined based on configuration data set using the configuration terminals of the configurable pulsed laser diode driver 1002. The values ​​of the configuration data determine the output type, grouping, and timing scheme of the configurable pulsed laser diode driver 1002. For an example of a 16-channel implementation of the configurable pulsed laser diode driver 1002, the 16 channels are controlled according to configuration data set using pulse configuration terminals pw0 to pw1, four output selection configuration terminals s0 to s3, mode configuration terminals m0 to m1, grouping configuration terminals e0 to e1, and charging configuration terminals c0 to c1. In this example, row1 to row... n Sixteen of the drive terminals are programmable, and row1 to row2 are programmable. n One of the drive terminals is non-programmable. The non-programmable terminal is configured to always generate a bypass signal, as described below. For an example of a 64-channel implementation of the configurable pulsed laser diode driver 1002, the 64 channels are controlled according to configuration data set using pulse configuration terminals pw0 to pw1, six output selection configuration terminals s0 to s5, mode configuration terminals m0 to m1, group configuration terminals e0 to e1, and charging configuration terminals c0 to c1. In this example, row1 to row... n Of the 64 drive terminals, row1 to row2 are programmable. n Four of the drive terminals are non-programmable, and these non-programmable drive terminals are configured to always generate bypass signals, as described below.

[0077] In any example implementation of the configurable pulsed laser diode driver 1002, it is used for, as referenced Figures 1A to 9B The described resonant bypass architecture powered by one or more laser diodes is driven by two types of signals: pulse signals and bypass signals, controlled by a configurable pulsed laser diode driver 1002.

[0078] refer to Figures 2A to 2D The laser diode switch M DLUsing a laser diode to switch the gate driver signal GATE DL The current controlled by 221 is an example of a pulse signal. In some implementations, the pulse signal controls the current by selectively employing either a high bias voltage level or a low bias voltage level. That is, the pulse signal can selectively generate or absorb current and pass through the circuit.

[0079] By bypass switch M BP Use the bypass switch gate driver signal GATE BP The 220-controlled current is an example of a bypass signal. In some implementations, the bypass signal controls the current by selectively employing either a high bias voltage level or a low bias voltage level. That is, the bypass signal can selectively generate or absorb current and allow it to pass through the circuit.

[0080] Pulse signals are typically provided by supplying a first control signal to a first circuit (e.g., a switch, such as the M described above and implemented as an NFET or PFET). DL The first circuit is electrically connected to the cathode or anode of the laser diode to control the current passing through it. In some embodiments, the first circuit is internal to the configurable pulsed laser diode driver 1002. In other embodiments, the first circuit is external to the configurable pulsed laser diode driver 1002.

[0081] The bypass signal is typically controlled by a resonant circuit to power the high-current pulses supplying the laser diode (e.g., Figures 2A to 2D The generation of 223, 223', 223" shown above. The bypass signal is typically generated by providing a second control signal to a second circuit (e.g., a switch, such as the MFET or PFET described above and implemented as an NFET or PFET). BP The second circuit is electrically connected to the resonant circuit to control the current passing through it. In some embodiments, the second circuit is internal to the configurable pulsed laser diode driver 1002. In other embodiments, the second circuit is external to the configurable pulsed laser diode driver 1002.

[0082] The bypass signal and the pulse signal are very similar, except that the bypass signal contains a very short interval after the negative edge of the clock signal. This interval is responsible for creating a resonant overshoot by controlling the current through the resonant circuit. This current turns on the laser diode for a very short duration (1 ns to 5 ns) to generate a high-current pulse.

[0083] The mode configuration terminals m0 to m1 of the configurable pulsed laser diode driver 1002 are set with row1 to row2. nThe "type" of each associated signal in the programmable drive terminal indicates whether it is a pulse signal or a bypass signal. (row1 to row...) n The non-programmable drive terminals are configured such that they always generate a corresponding bypass signal. As a simplified example of a configurable pulsed laser diode driver 1002 implementing a 16-channel driver, see [reference]. Figure 15 Table 1500, such as the combination mode configuration value M=0 determined by mode configuration terminals m0 to m1, configures programmable drive terminals row1 to row2. 16 (Columns labeled "1" to "16") enable each drive terminal to operate to generate a pulse signal ("P"). Non-programmable driver terminals row 17 (Row marked "17") is configured to always generate a bypass signal ("B").

[0084] In Table 1500, “P” indicates a pulse signal and “B” indicates a bypass signal. Additionally, “CX” indicates the charge delivered to each of the charging terminals cin1 to cin4 during the positive portion of each clock cycle, “C1” indicates the charge delivered to charging terminal cin1 during each clock cycle, “C2” indicates the charge delivered to charging terminal cin2 during each clock cycle, and so on.

[0085] refer to Figure 10A Output selection configuration terminals s0 to s k Synchronized with the clock signal received at the clock terminal of the configurable pulsed laser diode driver 1002. For each clock cycle, the output selection configuration terminals s0 to s0 are used. k The selection of pulse and bypass signals based on the combination mode configuration value will appear in row1 to row2. n Which terminals in the programmable drive terminals? As a simplified example, set the output selection configuration terminal s0 to logic high and set the output selection configuration terminals s1 to s2 to s3 to s4 to s5 to s6 to s7 to s8 to s9 ... k Setting all other terminals to logic low will result in the pulse signal or bypass signal appearing only on row1 for each clock cycle. Similarly, setting the output selection configuration terminal s1 to logic high and setting the output selection configuration terminals s0, s2 to s... k Setting all other terminals to logic low will cause the pulse signal or bypass signal to appear only on row2 for each clock cycle. However, the values ​​of the rest of the configuration data for the configurable pulsed laser diode driver 1002 can further modify this behavior. For each clock cycle, the bypass signal always appears on the non-programmable output driver terminals (e.g., row2). 17 )superior.

[0086] Group configuration terminals e0 to e1 determine how to select configuration terminals s0 to s for the output. k Grouping is performed. As a simplified example when the configurable pulsed laser diode driver 1002 implements a 16-channel driver, refer to... Figure 15 Table 1500, such as the combination group configuration value E=0 determined by the group configuration terminals e0 to e1, configures the output selection configuration terminals s1 to s k This allows for the independent selection of row1 through row1 based on the received output configuration data. n Each programmable drive terminal. Therefore, row1 to row2 can be driven within the same clock cycle. n Each programmable drive terminal is selectively powered to drive the corresponding connected laser diode. Similarly, the combined group configuration value E=1, determined by the group configuration terminals e0 to e1, configures the output to select the configuration terminals s1 to s2. k This allows for the independent selection of only row1 to row1 based on the received output configuration data. n Programmable drive terminal pairs (i.e., ignore output selection configuration terminals s1 to s) k The least significant bit (LSB) of row1. Therefore, only row1 to row2 can be processed within the same clock cycle. n Multiple pairs of programmable drive terminals are selectively powered to drive the connected laser diodes. As another example, the combined group configuration value E=2, determined by the group configuration terminals e0 to e1, configures the output selection configuration terminals s1 to s2. k This allows for the independent selection of only row1 to row1 based on the received output configuration data. n The programmable drive terminals are grouped four times (i.e., ignoring the output selection configuration terminals s1 to s2). k (Two LSBs).

[0087] refer to Figure 10A The charging configuration terminals c0 to c1 determine which of the charging terminals cin1 to cin4 are relative to the output selection configuration terminals s1 to s4. k The value is timed. A capacitor (i.e., similar to the source capacitor C described above) is connected to one or more of the resonant circuits at the charging terminals cin1 to cin4. s The circuit can be configured to charge the input voltage terminal vin to a voltage level during the positive portion of the clock cycle. The voltage received at the input voltage terminal vin is similar to the source voltage Vs described above. Therefore, in some embodiments, when the charging terminals cin1 to cin4 are "timing", a voltage similar to the source voltage Vs charges the source capacitor of the resonant circuit during the positive portion of each clock cycle.

[0088] As a simplified example, when the configurable pulsed laser diode driver 1002 implements a 16-channel driver, refer to Figure 15 Table 1500, such as the combination charging configuration value C=0 determined by charging configuration terminals c0 to c3, configures charging terminals cin1 to cin4 such that each charging terminal is timed for each clock cycle, regardless of the output selection configuration terminals s1 to s4. k How is the value determined? Similarly, the combined charging configuration value C=1, determined by charging configuration terminals c0 to c3, configures charging terminals cin1 to cin4 such that charging terminal cin1 (“C1”) is configured for output selection when configuring terminals s1, s5, s9, or s 13 When set to logic high, each clock cycle is timed, and the charging terminal cin2 (“C2”) is configured for output selection via terminals s2, s6, and s7. 10 or s 14 Each clock cycle when set to logic high is timed, and so on. As another example, the combined charging configuration value C=2, determined by charging configuration terminals c0 to c3, configures charging terminals cin1 to cin4, such that charging terminal cin1 is configured for output selection when terminals s1, s2, s9, or s... 10 Each clock cycle in which any one of them is set to logic high is counted, and so on.

[0089] refer to Figure 10A Pulse configuration terminals pw0 and pw1 are used to set the pulse offset and pulse width to activate each laser diode during each clock cycle. A first resistor value coupled between pulse configuration terminal pw0 and ground is configured to offset the pulse at the negative clock edge of the clock signal received at the clock terminal of the configurable pulsed laser diode driver 1002. A second resistor value coupled between pulse configuration terminal pw1 and ground determines the width of each high-current pulse that activates the corresponding laser diode. For example, Figure 2D The diagram shows two pulses 223, 223 with varying widths and offset from the negative edge of signal 220.

[0090] The switching performed within the configurable pulsed laser diode driver 1002 can be implemented using an NFET or PFET device. Advantageously, such a switch can be implemented using conventional silicon or silicon carbide-based switches instead of high-voltage GAN devices. The signal routing, logic, and timing functions performed within the configurable pulsed laser diode driver 1002 can be performed using appropriate signal routing, logic, and timing circuitry as understood by those skilled in the art.

[0091] According to some implementation plans Figure 10B It shows and Figure 10AThe diagram shows a simplified circuit diagram of a circuit used in conjunction with a configurable pulsed laser diode driver 1002. The laser diode circuit 1022' typically includes one or more laser diodes D having an anode and a cathode. L As described above. Laser diode D L The parasitic inductance of the anode is represented by inductor L. DL In this document, a simplified schematic representation of the laser diode circuit 1022' is used to simplify the diagram. The resonant circuit 1024' typically includes an inductor L. S Source capacitor C S Bypass capacitor C BP And optional damping resistor R Damp For reference Figures 1A to 9B As described. Inductor L S The first terminal is directly electrically connected to the source capacitor C. S The first terminal. In some implementations, the source capacitor C S The second terminal is connected to the damping resistor R Damp Electrically coupled to a bias voltage (e.g., ground). In other embodiments, the source capacitor C S The second terminal of the inductor L is directly electrically connected to the bias voltage. S The second terminal (“bypass”) is directly electrically connected to the bypass capacitor C. BP The first terminal. Bypass capacitor C BP The second terminal is directly electrically connected to the source capacitor C. S The second terminal. The charging terminal (“charging”) of the resonant circuit 1024' is directly electrically connected to the source capacitor C. S The first terminal. As indicated, a simplified schematic representation of the resonant circuit 1024' can be used herein to simplify the diagram.

[0092] According to some implementation plans Figure 11 It shows when Figure 10A This is an example of a simplified schematic diagram of a circuit 1100 including the configurable pulsed laser diode driver when the configurable pulsed laser diode driver 1002 is configured as a 16-channel driver 1102 to drive two quadruple-group laser diode packages (each in a common-cathode configuration). Typically, the circuit 1100 includes a configurable pulsed laser diode driver (“driver”) 1102, which is... Figure 10AA 16-channel implementation of a configurable pulsed laser diode driver 1002 is shown, comprising a first group of four laser diode circuits 1122a to 1122d (i.e., the first "quadruple group"), a second group of four laser diode circuits 1122e to 1122h (i.e., the second quadruple group), configuration resistors R1 and R2, an optional controller 1120, and four resonant circuits 1124a to 1124d connected as shown. The optional controller 1120 is similar to the controller 120 described above and is operable to provide configuration data to the 16-channel driver 1102 as described below. Also shown are clock signals and / or control signals (indicated as abstract square wave signals), a high bias voltage level Vdd, a low bias voltage level Vss, an input voltage signal Vin, and indications of signal routes Cin1 to Cin4, anode 1 to anode 4, and cathode 1 to cathode 2.

[0093] Optional controller 1120 is operable to provide digital signals such as logic states (i.e., configuration data) and clock signals to driver 1102 (e.g., indicated by the clock and abstract square wave signals at terminals s0 to s3, Vdd, and Vss). In some embodiments, optional controller 1120 may be or may include a programmable memory device or counter circuitry. In some such embodiments, optional controller 1120 is a programmable memory device configured to provide configuration data to driver 1102, and the clock signal received by driver 1102 is provided from a source other than optional controller 1120 (e.g., from clock generation circuitry or an oscillator, not shown). Some components of circuit 1100 have been removed from... Figure 11 Omissions are used to simplify the description, but the existence is still understood.

[0094] Each of the laser diode circuits 1122a to 1122h is connected to Figure 10B The laser diode circuit 1022' shown is identical. Similarly, each of the resonant circuits 1124a to 1124d is identical to... Figure 10B The resonant circuit shown is the same as 1024'.

[0095] Principle and reference of driver 1102 controlling laser diode circuits 1122a to 1122h Figure 1B The principle shown and described is similar. That is, each resonant circuit 1124a to 1124d has similar functionality to the resonant circuit of the pulsed laser diode driver 102, which includes an inductor L. S Bypass capacitor C BP Source capacitor C S and damping resistor R Damp Similarly, each of the four groups of laser diodes 1122a to 1122d and 1122e to 1122h is associated with the laser diode D of the pulsed laser diode driver 102.L similar.

[0096] With reference to the diagram Figure 1B The laser diode switch M shown and described DL Switched laser diode D L Similarly, to control the current, the current through the laser diode circuits 1122a to 1122h is controlled by the 16-channel driver 1102 (e.g., based on a pulse signal) according to the clock signal received at the clock terminal of the driver 1102. This is similar to controlling the current via... Figure 1B The current in the resonant circuit shown passes through the switch. Figure 1B Bypass switch M BP In contrast to control, the current through the resonant circuits 1124a to 1124d is similarly controlled by the 16-channel driver 1102 (e.g., according to the bypass signal).

[0097] The values ​​of resistors R1 and R2 configure the desired pulse width of the emitted laser pulse and the offset of the emitted laser pulse from the falling clock edge of the clock signal received at the clock terminal of driver 1102. Configuration bits m0 to m1, e0 to e1, and c0 to c1 are pulled (e.g., "hard-wired" or dynamically controlled by controller 1120) to logic high values ​​(e.g., using a high bias voltage Vdd) or logic low values ​​(e.g., using a low bias voltage Vss) such that driver 1102 operates with the desired configuration of M=2, E=3, C=0, as shown below. Figure 11 As shown, the mode configuration value M is a decimal value set by mode configuration terminals m0 to m1, the group configuration value E is a decimal value set by group configuration terminals e0 to e1, and the charging configuration value C is a decimal value set by charging configuration terminals c0 to c1.

[0098] Figure 15 Table 1500, as shown, specifies various configurations for the 16-channel driver 1102 for each combination of configuration values. For example... Figure 11 As shown, referring to Table 1500, the driver 1102 is configured as follows with mode configuration value M=2: Driver terminals row1 and row9 electrically couple the corresponding anodes (anode 1) of laser diode circuits 1122a and 1122e to the bypass terminals of resonant circuit 1124a to receive bypass signals; driver terminals row2 and row... 10 The corresponding anodes (anode 2) of laser diode circuits 1122b and 1122f are electrically coupled to the bypass terminals of resonant circuit 1124b to receive bypass signals; drive terminals row7 and row 15 The corresponding anodes (anode 3) of laser diode circuits 1122c and 1122g are electrically coupled to the bypass terminal of resonant circuit 1124c to receive bypass signals; drive terminals row8 and row 16The corresponding anodes (anode 4) of laser diode circuits 1122d and 1122h are electrically coupled to the bypass terminal of resonant circuit 1124d to receive bypass signals; the driving terminals including row3 to row6 selectively (i.e., according to the pulse signal) couple the corresponding cathodes (cathode 1) of laser diode circuits 1122a to 1122d to ground (i.e., Vss); and the driving terminals including row3 to row6 selectively (i.e., according to the pulse signal) couple the corresponding cathodes (cathode 1) of laser diode circuits 1122a to 1122d to ground; ... 11 to row 14 The driving terminals selectively (i.e., according to the pulse signal) electrically couple the corresponding cathodes (cathode 2) of the laser diode circuits 1122e to 1122h to ground. Therefore, similar to... Figure 1B The pulsed laser diode driver 102 is configurable to block or allow the corresponding current through the laser diode circuits 1122a to 1122h by controlling the pulse signal at the corresponding cathode of the laser diode circuits 1122a to 1122h.

[0099] refer to Figure 15 Table 1500, with charging configuration value C=0, configures driver 1102 as follows: charging terminal cin1 controls the current (Cin1) supplied to the charging terminal of resonant circuit 1124a during each clock cycle; charging terminal cin2 controls the current (Cin2) supplied to the charging terminal of resonant circuit 1124b during each clock cycle; charging terminal cin3 controls the current (Cin3) supplied to the charging terminal of resonant circuit 1124c during each clock cycle; and charging terminal cin4 controls the current (Cin4) supplied to the charging terminal of resonant circuit 1124d during each clock cycle. During each clock cycle, the capacitors of resonant circuits 1124a to 1124d are charged according to the input voltage Vin at the input voltage terminal vin.

[0100] refer to Figure 15 Table 1500, group configuration value E=3 configures driver 1102 such that every eight adjacent drive terminals (e.g., row1 to row8 and row9 to row8) are configured such that... 16 Together, they are driven by the output selection signals received at the output selection configuration terminals s0 to s3. That is, the output selection terminal s3 becomes the LSB for output selection between laser diode circuits 1122a to 1122d and laser diode circuits 1122e to 1122h.

[0101] According to some implementation plans Figure 12 It shows when Figure 11Another example of a simplified circuit diagram of circuit 1200 including the configurable 16-channel laser diode driver 1102 when configured to drive a single array of eight laser diodes (in a common anode configuration) is shown. Typically, circuit 1200 includes a configurable pulsed laser diode driver 1102, a single laser diode array 1222 of eight laser diodes connected as shown, configuration resistors R1, R2, an optional controller 1120, and a single resonant circuit 1224. Clock signals and / or control signals (indicated as abstract square wave signals), a high bias voltage level Vdd, a low bias voltage level Vss, an input voltage signal Vin, and indications of signal routing Cin1, anode 1, and cathode 1 to cathode 8 are also shown. Some components of circuit 1200 have been removed from... Figure 12 Omissions are used to simplify the description, but the existence is still understood.

[0102] Each laser diode circuit of the laser diode array 1222 is connected to Figure 10B The laser diode circuit 1022' shown is the same. Similarly, the resonant circuit 1224 is the same as... Figure 10B The resonant circuit shown is the same as 1024'.

[0103] Driver 1102 controls and references the laser diodes of laser diode array 1222. Figure 1B and / or Figure 4B The control shown and described is similar. That is, the resonant circuit 1224 has similar functionality to the resonant circuit of the pulsed laser diode driver 102, which includes an inductor L. S Bypass capacitor C BP Source capacitor C S and damping resistor R Damp Each of the laser diodes in the laser diode array 1222 is connected to the laser diode D of the pulsed laser diode driver 102. L Parasitic inductor L DL Similarly, based on the clock signal received at the clock terminal of driver 1102, the laser diodes of laser diode array 1222 and laser diode D... L Similarly, via a switch as reference Figure 1B The laser diode switch M shown and described DL To control. Resonant circuit 1224 and Figure 1B The resonant circuit shown is similarly controlled by a switch. Figure 1B Bypass switch M BP To control.

[0104] The values ​​of resistors R1 and R2 configure the desired pulse width of the emitted laser pulse and the offset of the emitted laser pulse from the falling clock edge of the clock signal received at the clock terminal of driver 1102. In the example shown, driver 1102 operates with a desired configuration setting of M=1, E=1, C=3, where the mode configuration value M is a decimal value set by mode configuration terminals m0 to m1, the group configuration value E is a decimal value set by group configuration terminals e0 to e1, and the charging configuration value C is a decimal value set by charging configuration terminals c0 to c1.

[0105] like Figure 12 As shown, for reference Figure 15 Table 1500, with mode configuration value M=1, configures driver 1102 as follows: drive terminals row2, row4, row6, row8, row 10 row 12 row 14 and row 16 The corresponding anodes of the laser diodes in the laser diode array 1222 are electrically coupled to the bypass terminals of the resonant circuit 1224 to provide bypass signals; including row1, row3, row5, row7, row9, row 11 row 13 and row 15 The drive terminals control the corresponding cathodes 1 to 8 of the laser diode array 1222. (Drive terminal row) 17 Link to the ground (Vss).

[0106] refer to Figure 15 Table 1500 configures the driver 1102 with a charging configuration value C=3, such that charging terminals cin1 to cin4 jointly control the current supplied to the charging terminals of the resonant circuit 1224. Therefore, for any value of the output selection configuration terminals s0 to s3, charge will be supplied to the charging terminals of the resonant circuit 1224.

[0107] refer to Figure 15 Table 1500 configures driver 1102 with a group configuration value E=1, such that every two adjacent drive terminals (e.g., row1 and row2, row3 and row4, etc.) are selected together. This achieves individual control of each laser diode in the laser diode array 1222. Specifically, if output selection terminal s0 is set to a logic high value, while all other output selection configuration terminals s1 to s3 are set to logic low values, the pulse signal and bypass signal will appear separately and according to the clock cycle only on drive terminals row1 and row2.

[0108] According to some implementation plans Figure 13 It shows when Figure 11Another example of a simplified circuit diagram 1300 including the configurable pulsed laser diode driver 1102 when configured to drive a single array containing sixteen laser diodes (in a common anode configuration) is shown. Typically, circuit 1300 includes the configurable pulsed laser diode driver 1102, a single laser diode array 1322 of sixteen laser diodes connected as shown, configuration resistors R1, R2, an optional controller 1120, and a single resonant circuit 1324. Clock signals and / or control signals (indicated as abstract square wave signals), a high bias voltage level Vdd, a low bias voltage level Vss, an input voltage signal Vin, and indications of signal routing Cin1, anode 1, and cathode 1 to cathode 16 are also shown. Some components of circuit 1300 have been removed from... Figure 13 Omitted to simplify the description, but still understood to exist. Each laser diode circuit of the laser diode array 1322 is connected to... Figure 10B The laser diode circuit 1022' shown is the same. Similarly, the resonant circuit 1324 is the same as... Figure 10B The resonant circuit shown is the same as 1024'.

[0109] Driver 1102 controls and references the laser diodes of laser diode array 1322. Figure 12 The control shown and described for the laser diode array 1222 is similar.

[0110] In the example shown, the driver 1102 operates with the desired configuration settings of M=0, E=0, C=0, where the mode configuration value M is a decimal value set by the mode configuration terminals m0 to m1, the group configuration value E is a decimal value set by the group configuration terminals e0 to e1, and the charging configuration value C is a decimal value set by the charging configuration terminals c0 to c1.

[0111] like Figure 13 As shown, for reference Figure 15 Table 1500, with mode configuration value M=0, configure driver 1102 as follows: drive terminal row 17 The corresponding anodes of the laser diodes in the laser diode array 1322 are electrically coupled to the bypass terminals of the resonant circuit 1324; and the driving terminals row1 to row2 are driven. 16 Control the corresponding cathodes 1 to 16 of the laser diode array 1322.

[0112] refer to Figure 15 Table 1500 configures the driver 1102 with a charging configuration value C=0, such that charging terminals cin1 to cin4 jointly control the current supplied to the charging terminals of the resonant circuit 1324. Therefore, for any value of the output selection configuration terminals s0 to s3, charge will be supplied to the charging terminals of the resonant circuit 1324.

[0113] refer to Figure 15 Table 1500 configures driver 1102 with group configuration value E=0, such that each drive terminal (e.g., row1, row2, row3, etc.) is driven individually. However, for each clock cycle of driver 1102, a bypass signal appears at drive terminal row1. 17 Therefore, the individual control of each laser diode in the laser diode array 1322 is based on the control of drive terminals row1 to row2. 16 To achieve this through control.

[0114] According to some implementation plans Figure 14 It shows when Figure 10A This is an example of a simplified circuit diagram 1400 including the configurable pulsed laser diode driver 1002 when it is configured to drive a 64-row VCSEL laser diode array (in a common anode configuration). Typically, circuit 1400 includes the configurable pulsed laser diode driver 1402, which is... Figure 10A An implementation of a configurable pulsed laser diode driver 1002 is shown, comprising a 64-row VCSEL laser diode circuit 1452, configuration resistors R1 and R2, an optional controller 1120, and a resonant circuit 1424 connected as illustrated. The optional controller 1120 is similar to the controller 120 described above. The optional controller 1120 is operable to provide digital signals, such as logic states and clock signals, to the driver 1402. In some embodiments, the optional controller 1120 may be or may include a programmable memory device. In some such embodiments, the optional controller is a programmable memory device configured to provide configuration data to the driver 1402, and the clock signal received by the driver 1402 is provided from a source other than the optional controller 1120 (e.g., from a clock generation circuit or oscillator, not shown). Also shown are clock signals and / or control signals (indicated as abstract square wave signals), a high bias voltage level Vdd, a low bias voltage level Vss, an input voltage signal Vin, and indications of signal routing Cin1, anode 1, and cathode 1 to cathode 64. Some components of circuit 1400 have been removed from Figure 14 Omissions are used to simplify the description, but the existence is still understood.

[0115] Each laser diode in the laser diode circuit 1452 represents a row of laser diodes in a VCSEL array. A VCSEL array can have hundreds of emitters, but in principle... Figure 10B The laser diode circuit 1022 shown operates similarly. Similarly, the resonant circuit 1424 and... Figure 10BThe resonant circuit 1024' shown is identical. Therefore, the driver 1402 controls and references the laser diode in the laser diode circuit 1452. Figure 1B and / or Figure 4B The control shown and described is similar. That is, the resonant circuit 1324 has similar functionality to the resonant circuit of the pulsed laser diode driver 102, which includes an inductor L. S Bypass capacitor C BP Source capacitor C S and damping resistor R Damp Similarly, each row of laser diodes in the laser diode circuit 1452 is connected to the laser diode D of the pulsed laser diode driver 102. L similar.

[0116] Driver 1402 controls and references the multi-row laser diodes of laser diode circuit 1452. Figure 12 The control shown and described for the laser diode array 1222 is similar.

[0117] The values ​​of resistors R1 and R2 configure the desired pulse width of the emitted laser pulse and the offset of the emitted laser pulse from the falling clock edge of the clock signal received at the clock terminal of driver 1402. In the example shown, driver 1402 operates with a desired configuration setting of M=0, E=0, C=0, where the mode configuration value M is a decimal value set by mode configuration terminals m0 to m1, the group configuration value E is a decimal value set by group configuration terminals e0 to e1, and the charging configuration value C is a decimal value set by charging configuration terminals c0 to c1.

[0118] Figures 16A to 16B Table 1600, as shown, specifies various configurations of driver 1402 for each combination of configuration values. Within Table 1600, “P” indicates a pulse signal and “B” indicates a bypass signal. Additionally, “CX” indicates the charge delivered to each of charging terminals cin1 to cin4 during each clock cycle (e.g., during the positive portion), “C1” indicates the charge delivered to charging terminal cin1 during each clock cycle, “C2” indicates the charge delivered to charging terminal cin2 during each clock cycle, and so on.

[0119] like Figure 14 As shown, for reference Figures 16A to 16B Table 1600, with mode configuration value M=0, configures driver 1402 as follows: including row 65 to row 68 The drive terminals of the VCSEL laser diode circuit 1452 are electrically coupled to the corresponding anode terminals of the resonant circuit 1424 to receive bypass signals; and include row1 to row2.64 The drive terminals control the individual cathodes 1 to 64 of the VCSEL laser diode circuit 1452 to receive pulse signals.

[0120] refer to Figures 16A to 16B Table 1600, with charging value C=0, configures driver 1402 so that charging terminals cin1 to cin4 jointly control the current supplied to the charging terminals of resonant circuit 1424.

[0121] refer to Figures 16A to 16B Table 1600 configures driver 1402 with a group configuration value E=0, such that each of the drive pins (e.g., row1, row2, row3, etc.) is driven individually. Therefore, individual control of each row of laser diodes in the VCSEL laser diode circuit 1452 is driven based on the signals received at select terminals s0 to s5. However, based on the bump pattern of driver 1402, groups of four channels can be combined, such that each four-channel group is associated with a specific bump. For example, drive terminals row1 to row4 can be electrically connected to bump 1, drive terminals row5 to row8 can be electrically connected to bump 2, and so on.

[0122] According to some implementation plans Figure 17 for Figure 14 Photograph 1700 shows a portion of an implementation of the configurable pulsed laser diode driver 1402. Figure 14 The configurable pulsed laser diode driver 1402 is advantageously designed to directly bond pad-to-pad to a VCSEL laser diode array with 80 μm pitch bonding pads. In some embodiments, the final back-end processing for the configurable pulsed laser diode drivers 1002 / 1102 / 1402 utilizes a redistribution layer (RDL) for final connection between the CMOS metal processing layer and the bonding pads. By changing this final back-end RDL layer, for example by collecting 64 output terminals into four groups of completely different bump wafer-level chip-scale packages (WLCSPs) with an advantageously configurable bump pitch of 320 μm, a 16-channel edge-emitting diode driver capable of generating 40 Amp 1-5 ns pulses is produced. Because there are only 17 outputs in these embodiments (16 programmable, one non-programmable), the RDL image is left-shifted by the output selection configuration bits s0 to s5, causing the four output selection configuration terminals s0 to s3 to determine the selection of the 16 drive terminals row1 to row2. 16 Which of the following. In some implementations, one or more additional configuration terminals are set to various configuration values ​​as part of the RDL mapping to configure the configurable pulsed laser diode driver 1002 / 1102 / 1402 to a 16-channel, 64-channel, or other channel number mode.

[0123] Furthermore, many quadruple laser diode packages have two anode connections on either side of the package and a large common cathode connection at the center of the package. Therefore, for example, the combination of the mode configuration value M=2 and the bump configuration of the RDL mapping advantageously creates a signal and physical correspondence with such laser diode packages.

[0124] Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which are illustrated in the accompanying drawings. Each example has been provided by way of explanation and not as a limitation thereof. In fact, although the specification has been described in detail with respect to specific embodiments of the invention, it will be understood that modifications, variations, and equivalent embodiments of these embodiments will readily occur to those skilled in the art upon gaining an understanding of the foregoing. For example, a feature described or illustrated in part as one embodiment may be used with another embodiment to produce yet another embodiment. Therefore, this object is intended to cover all such modifications and variations within the scope of the appended technical solutions and their equivalents. These and other modifications and variations of the invention may be practiced by those skilled in the art without departing from the scope of the invention (which is set forth more specifically in the appended claims). Furthermore, those skilled in the art will understand that the foregoing description is illustrative only and is not intended to limit the invention.

Claims

1. A laser diode driver, the laser diode driver comprising: A clock terminal, operable to receive a clock signal; Multiple configuration terminals, operable to receive configuration data; A plurality of charging terminals, wherein a first charging terminal of the plurality of charging terminals is operable to charge a first source capacitor of a first resonant circuit, the first resonant circuit including the first source capacitor, a first inductor and a first bypass capacitor; as well as A plurality of drive terminals, each operable to be directly electrically connected to the anode or cathode of a plurality of laser diodes or directly electrically connected to ground, wherein: the plurality of drive terminals includes one or more non-programmable drive terminals and a plurality of programmable drive terminals, wherein the plurality of programmable drive terminals are configured by configuration data such that each programmable drive terminal is operable to generate a pulse signal; each of the one or more non-programmable drive terminals is configured to always generate a bypass signal, the pulse signal controlling the flow of a corresponding high-current pulse through the plurality of laser diodes for activating the plurality of laser diodes; and the bypass signal controlling the current through the first resonant circuit to generate the corresponding high-current pulse; in: The mode, output selection, and grouping of the drive signals delivered to the plurality of laser diodes are configured based on the configuration data, and the drive signals include the pulse signal and the bypass signal; and The laser diode driver is operable to control the current through the first resonant circuit to generate high-current pulses through the plurality of laser diodes, the high-current pulses corresponding to the peak current of the resonant waveform emitted at the respective anodes of the plurality of laser diodes, the timing of the high-current pulses being synchronized using the clock signal.

2. The laser diode driver as described in claim 1, wherein: The first inductor has a first terminal and a second terminal, wherein the first terminal of the first inductor is operable to receive a charging voltage from the first charging terminal of the plurality of charging terminals; The first source capacitor has a first terminal directly electrically connected to the first terminal of the first inductor and a second terminal electrically coupled to ground; and The first bypass capacitor has a first terminal that is directly electrically connected to the second terminal of the first inductor and a second terminal that is directly electrically connected to the second terminal of the first source capacitor.

3. The laser diode driver as described in claim 1, wherein: The plurality of configuration terminals includes a plurality of pulse configuration terminals; and The plurality of pulse configuration terminals are operable to set the pulse offset and pulse width for activating each of the plurality of laser diodes during each clock cycle of the clock signal.

4. The laser diode driver as described in claim 3, wherein: The plurality of pulse configuration terminals are operable to be directly electrically connected to a plurality of resistors; and The pulse offset and pulse width used to activate each of the plurality of laser diodes during each clock cycle of the clock signal are based on the corresponding resistor values ​​of the plurality of resistors.

5. The laser diode driver as described in claim 1, wherein: The plurality of configuration terminals includes a plurality of output selection configuration terminals; and The plurality of output selection configuration terminals are operable to cyclically select which of the plurality of drive terminals the drive signal will appear at for each clock cycle of the clock signal.

6. The laser diode driver as described in claim 5, wherein: The plurality of configuration terminals includes a plurality of grouped configuration terminals; and The plurality of group configuration terminals are operable to configure how the plurality of output selection configuration terminals are grouped.

7. The laser diode driver as claimed in claim 1, wherein: The plurality of configuration terminals includes a plurality of mode configuration terminals; and The plurality of mode configuration terminals are operable to set which of the pulse signal or the bypass signal in the drive signals will appear at one or more of the plurality of drive terminals.

8. The laser diode driver as claimed in claim 1, wherein: The plurality of configuration terminals includes a plurality of charging configuration terminals; and The plurality of charging configuration terminals are operable to control the current delivered from the plurality of charging terminals to the first resonant circuit during each clock cycle.

9. The laser diode driver as claimed in claim 1, wherein: The second charging terminal of the plurality of charging terminals is operable to charge the second source capacitor of the second resonant circuit; and The second resonant circuit includes a second source capacitor, a second inductor, and a second bypass capacitor.

10. The laser diode driver as claimed in claim 1, wherein: In response to receiving first configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high current pulses through the plurality of laser diodes grouped in a common anode configuration; and In response to receiving second configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high current pulses through the plurality of laser diodes grouped in a common cathode configuration.

11. The laser diode driver as claimed in claim 1, wherein: In response to receiving first configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high current pulses through the plurality of laser diodes grouped into a single laser diode array; and In response to receiving second configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high current pulses through the plurality of laser diodes grouped into a plurality of laser diode arrays.

12. The laser diode driver as claimed in claim 1, wherein: The plurality of laser diodes includes a plurality of side-emitting laser diodes.

13. The laser diode driver as claimed in claim 1, wherein: The plurality of laser diodes includes a plurality of vertical cavity surface-emitting laser diodes.

14. An apparatus comprising a laser diode driver as claimed in claim 1, wherein: The bump pattern of the device is directly electrically connected to two or more of the plurality of drive terminals.

15. An apparatus comprising a laser diode driver as claimed in claim 1, wherein: The redistribution layer of the device physically configures the device to directly bond pad to pad to a vertical cavity surface-emitting laser diode array.

16. An electronic device, the electronic device comprising: A clock terminal, operable to receive a clock signal; Multiple configuration terminals, operable to receive configuration data; Multiple charging terminals, wherein the first charging terminal of the multiple charging terminals is directly electrically connected to the first source capacitor of the first resonant circuit, and the first resonant circuit includes the first source capacitor, the first inductor, and the first bypass capacitor. as well as Multiple drive terminals, each directly electrically connected to the anode or cathode of multiple laser diodes or directly electrically connected to ground, wherein: the multiple drive terminals include one or more non-programmable drive terminals and multiple programmable drive terminals, wherein the multiple programmable drive terminals are configured by configuration data such that each programmable drive terminal is operable to generate a pulse signal; each of the one or more non-programmable drive terminals is configured to always generate a bypass signal, the pulse signal controlling the flow of a corresponding high-current pulse through the multiple laser diodes to activate the multiple laser diodes; and the bypass signal controlling the current through the first resonant circuit to generate the corresponding high-current pulse; in: The first inductor has a first terminal and a second terminal, wherein the first terminal of the first inductor is operable to receive a charging voltage from the first charging terminal of the plurality of charging terminals; The first source capacitor has a first terminal that is directly electrically connected to the first terminal of the first inductor and a second terminal that is electrically coupled to ground; The first bypass capacitor has a first terminal directly electrically connected to the second terminal of the first inductor and a second terminal directly electrically connected to the second terminal of the first source capacitor; and The device is operable to control the current through the first resonant circuit to generate high-current pulses through the plurality of laser diodes, the high-current pulses corresponding to the peak current of the resonant waveform emitted at the respective anodes of the plurality of laser diodes, the timing of the high-current pulses being synchronized using the clock signal.

17. The apparatus of claim 16, further comprising: The second resonant circuit includes a second source capacitor, which is directly electrically connected to the second charging terminal among the plurality of charging terminals. The second resonant circuit also includes a second inductor and a second bypass capacitor. in: The second inductor has a first terminal and a second terminal, wherein the first terminal of the second inductor is operable to receive the charging voltage from the second charging terminal of the plurality of charging terminals; The second source capacitor has a first terminal directly electrically connected to the first terminal of the second inductor and a second terminal electrically coupled to ground; and The second bypass capacitor has a first terminal that is directly electrically connected to the second terminal of the second inductor and a second terminal that is directly electrically connected to the second terminal of the second source capacitor.

18. A laser diode driver, the laser diode driver comprising: A clock terminal, operable to receive a clock signal; A plurality of charging terminals, wherein a first charging terminal of the plurality of charging terminals is operable to charge a first source capacitor of a first resonant circuit, the first resonant circuit including the first source capacitor, a first inductor and a first bypass capacitor; as well as A plurality of drive terminals, each operable to be directly electrically connected to the anode or cathode of a plurality of laser diodes or directly electrically connected to ground, wherein: the plurality of drive terminals includes one or more non-programmable drive terminals and a plurality of programmable drive terminals, wherein the plurality of programmable drive terminals are configured by configuration data such that each programmable drive terminal is operable to generate a pulse signal; each of the one or more non-programmable drive terminals is configured to always generate a bypass signal, the pulse signal controlling the flow of a corresponding high-current pulse through the plurality of laser diodes for activating the plurality of laser diodes; and the bypass signal controlling the current through the first resonant circuit to generate the corresponding high-current pulse; in: The laser diode driver is operable to control the current through the first resonant circuit to generate high-current pulses through the plurality of laser diodes, the high-current pulses corresponding to the peak current of the resonant waveform emitted at the respective anodes of the plurality of laser diodes, the timing of the high-current pulses being synchronized using the clock signal.

19. The laser diode driver of claim 18, wherein: The first inductor has a first terminal and a second terminal, wherein the first terminal of the first inductor is operable to receive a charging voltage from the first charging terminal of the plurality of charging terminals; The first source capacitor has a first terminal directly electrically connected to the first terminal of the first inductor and a second terminal electrically coupled to ground; and The first bypass capacitor has a first terminal that is directly electrically connected to the second terminal of the first inductor and a second terminal that is directly electrically connected to the second terminal of the first source capacitor.

20. The laser diode driver of claim 18, further comprising: Multiple pulse configuration terminals; in: The plurality of pulse configuration terminals are operable to set the pulse offset and pulse width for activating each of the plurality of laser diodes during each clock cycle of the clock signal.

21. The laser diode driver of claim 20, wherein: The plurality of pulse configuration terminals are operable to be directly electrically connected to a plurality of resistors; and The pulse offset and pulse width used to activate each of the plurality of laser diodes during each clock cycle of the clock signal are based on the corresponding resistor values ​​of the plurality of resistors.

22. The laser diode driver of claim 18, further comprising: Multiple output selection configuration terminals; in: The plurality of output selection configuration terminals are operable to cyclically select, for each clock cycle of the clock signal, which of the plurality of drive terminals will deliver drive signals to the plurality of laser diodes.

23. The laser diode driver of claim 22, further comprising: Multiple group configuration terminals; in: The plurality of group configuration terminals are operable to configure how the plurality of output selection configuration terminals are grouped.

24. The laser diode driver of claim 22, further comprising: Multiple mode configuration terminals; in: The plurality of mode configuration terminals are operable to set which of the pulse signal or the bypass signal in the drive signals will appear at one or more of the plurality of drive terminals.

25. The laser diode driver of claim 18, further comprising: Multiple charging configuration terminals; in: The plurality of charging configuration terminals are operable to control the current delivered from the plurality of charging terminals to the first resonant circuit during each clock cycle.

26. The laser diode driver of claim 18, wherein: The second charging terminal of the plurality of charging terminals is operable to charge the second source capacitor of the second resonant circuit; and The second resonant circuit includes a second source capacitor, a second inductor, and a second bypass capacitor.

27. The laser diode driver of claim 18, further comprising: Multiple configuration terminals, operable to receive configuration data; in: In response to receiving first configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high-current pulses through the plurality of laser diodes grouped in a common-anode configuration; and In response to receiving second configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high current pulses through the plurality of laser diodes grouped in a common cathode configuration.

28. The laser diode driver of claim 18, further comprising: Multiple configuration terminals, operable to receive configuration data; in: In response to receiving first configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high-current pulses through the plurality of laser diodes grouped into a single laser diode array; and In response to receiving second configuration data at the plurality of configuration terminals, the laser diode driver is configured to generate high current pulses through the plurality of laser diodes grouped into a plurality of laser diode arrays.

29. The laser diode driver of claim 18, wherein: The plurality of laser diodes includes a plurality of side-emitting laser diodes.

30. The laser diode driver of claim 18, wherein: The plurality of laser diodes includes a plurality of vertical cavity surface-emitting laser diodes.

31. An apparatus comprising a laser diode driver as described in claim 18, wherein: The bump pattern of the device is directly electrically connected to two or more of the plurality of drive terminals.

32. An apparatus comprising a laser diode driver as described in claim 18, wherein: The redistribution layer of the device physically configures the device to directly bond pad to pad to a vertical cavity surface-emitting laser diode array.

33. An electronic device, the electronic device comprising: A clock terminal, operable to receive a clock signal; Multiple charging terminals, wherein the first charging terminal of the multiple charging terminals is directly electrically connected to the first source capacitor of the first resonant circuit, and the first resonant circuit includes the first source capacitor, the first inductor, and the first bypass capacitor. as well as Multiple drive terminals, each drive terminal being directly electrically connected to the anode or cathode of multiple laser diodes or directly electrically connected to ground, wherein: the multiple drive terminals include one or more non-programmable drive terminals and multiple programmable drive terminals, wherein the multiple programmable drive terminals are configured by configuration data such that each programmable drive terminal is operable to generate a pulse signal; each of the one or more non-programmable drive terminals is configured to always generate a bypass signal, the pulse signal controlling the flow of a corresponding high-current pulse through the multiple laser diodes for activating the multiple laser diodes; and the bypass signal controlling the current through the first resonant circuit to generate the corresponding high-current pulse; in: The first inductor has a first terminal and a second terminal, wherein the first terminal of the first inductor is operable to receive a charging voltage from the first charging terminal of the plurality of charging terminals; The first source capacitor has a first terminal that is directly electrically connected to the first terminal of the first inductor and a second terminal that is electrically coupled to ground; The first bypass capacitor has a first terminal directly electrically connected to the second terminal of the first inductor and a second terminal directly electrically connected to the second terminal of the first source capacitor; and The device is operable to control the current through the first resonant circuit to generate high-current pulses through the plurality of laser diodes, the high-current pulses corresponding to the peak current of the resonant waveform emitted at the respective anodes of the plurality of laser diodes, the timing of the high-current pulses being synchronized using the clock signal.

34. The apparatus of claim 33, further comprising: The second resonant circuit includes a second source capacitor, which is directly electrically connected to the second charging terminal among the plurality of charging terminals. The second resonant circuit also includes a second inductor and a second bypass capacitor. in: The second inductor has a first terminal and a second terminal, wherein the first terminal of the second inductor is operable to receive the charging voltage from the second charging terminal of the plurality of charging terminals; The second source capacitor has a first terminal directly electrically connected to the first terminal of the second inductor and a second terminal electrically coupled to ground; and The second bypass capacitor has a first terminal that is directly electrically connected to the second terminal of the second inductor and a second terminal that is directly electrically connected to the second terminal of the second source capacitor.

Images