Processor structure based on odd-even scheduling and allocation, and chip and electronic device

Abstract

The present disclosure relates to the technical field of processors. Provided are a processor structure based on odd-even scheduling and allocation, and a chip and an electronic device. In the processor structure based on odd-even scheduling and allocation provided in the present disclosure, a free physical register file is divided into an odd part and an even part in a renaming phase, and whether an odd physical register or an even physical register is allocated for the current renaming operation is determined according to an instruction type. The embodiments provided by the present disclosure can reduce by half the number of write ports of a register file, and can effectively perform the allocation and instruction scheduling of physical registers in combination with a register allocation balancing algorithm.

Description

Processor architectures, chips, and electronic devices based on parity scheduling and allocation

[0001] Cross-reference to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202411805670.0, filed on December 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of processor technology, and in particular to a processor architecture, chip, and electronic device based on parity scheduling and allocation. Background Technology

[0004] In superscalar processors, a crucial stage is register renaming. This involves resolving write-after-write (WAW) and write-after-read (WAR) dependencies by allocating physical registers from the free physical register list (freeList), thus achieving out-of-order execution. Therefore, a key component is the physical register file. Physical register files are typically categorized based on type, such as integer register files, floating-point register files, and vector register files. Summary of the Invention

[0005] This disclosure provides a processor architecture, chip, and electronic device based on parity scheduling and allocation.

[0006] The first aspect of this disclosure provides a processor architecture based on parity scheduling and allocation, including a front-end instruction fetch unit, an instruction decoding unit, a renaming unit, a dispatch unit, multiple reservation stations, multiple execution units, and two register files that are coupled together in sequence; wherein, the instruction decoding unit is used to generate control signals for instruction splitting based on the type of the instruction to be processed; the number of reservation stations and the number of execution units are the same as the number of types of instructions to be processed;

[0007] The dispatch unit is used to dispatch and distribute the instructions to be processed according to the control signal;

[0008] Each execution unit includes an odd execution component and an even execution component, and the two register files include an odd register file and an even register file. The odd execution component in the execution unit is coupled to the odd register file, and the even execution component in the execution unit is coupled to the even register file.

[0009] The renaming unit is used to rename the registers of the instruction to be processed; the renaming unit stores an odd register list OddFreeList and an even register list EvenFreeList, and the entries in OddFreeList and EvenFreeList store the numbers of free physical registers; the renaming unit determines whether to allocate a free physical register according to the type of the instruction to be processed and decides whether to allocate a register in OddFreeList or EvenFreeList based on the state of the ping-pong signal corresponding to each type; wherein, the ping-pong signal toggles its state according to whether the previous instruction allocated an odd or even register.

[0010] In some embodiments, the dispatch unit includes a misc dispatch queue and a load / store dispatch queue. It is understood that the dispatch unit can be further subdivided according to requirements; for example, the misc dispatch queue can be divided into alu, mul, etc.

[0011] In some embodiments, the reservation station includes an arithmetic reservation station (ALU Reservation), a mixed reservation station (Misc Reservation), a read (load) reservation station (Load Reservation), and a store reservation station (Store Reservation); wherein the ALU Reservation and the Misc Reservation are coupled to the misc dispatch queue, and the Load Reservation and the Store Reservation are coupled to the load / store dispatch queue.

[0012] In some embodiments, the execution unit includes an arithmetic ALU execution unit, a hybrid Misc execution unit, a write load execution unit, and a store execution unit; wherein:

[0013] The ALU execution unit is coupled to the ALU Reservation, the Misc execution unit is coupled to the Misc Reservation, the Load execution unit is coupled to the Load Reservation, and the Store execution unit is coupled to the Store Reservation.

[0014] In some embodiments, the structures of OddFreeList and EvenFreeList are pointer-read-write first-in-first-out (FIFO) queues.

[0015] In some embodiments, the renaming unit is further configured to determine, based on the number of odd / even instructions of each type in the previous renaming phase, whether the current renaming phase should preferentially allocate physical registers from the odd register file or from the even register file.

[0016] In some embodiments, the status array in the retention station includes an odd status array and an even status array. When the pending instruction is updated, both the odd status array and the even status array are updated simultaneously.

[0017] In some embodiments, the renaming unit is further configured to update the corresponding counter counter according to whether the allocation is odd or even when a physical register is allocated for the instruction to be processed, and the counter counter is used to update the corresponding enqueue pointer respectively.

[0018] A second aspect of this disclosure provides a chip including the parity-based scheduling and allocation processor architecture described in the first aspect.

[0019] A third aspect of this disclosure provides an electronic device including the chip described in the second aspect. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 is a schematic diagram of a processor structure based on parity scheduling and allocation provided in an embodiment of this disclosure.

[0022] Figure 2 is a schematic diagram of the structure of the register list freeList provided in an embodiment of this disclosure.

[0023] Figure 3 is a schematic diagram of the renaming phase allocation of physical registers provided in an embodiment of this disclosure.

[0024] Figure 4 is a schematic diagram of register allocation balance during the renaming stage provided in an embodiment of this disclosure.

[0025] Figure 5 is a schematic diagram of the generation logic of various types of ping-pong signals in the first instruction of the renaming stage provided in the embodiments of this disclosure.

[0026] Figure 6 is a schematic diagram of the allocBalance logic determining the allocation pointer update during the renaming stage provided in an embodiment of this disclosure.

[0027] Figure 7 is a schematic diagram of the release and update process of allocBalance provided in the embodiments of this disclosure.

[0028] Figure 8 is a schematic diagram of the source operand wake-up logic in the status array of the reserved station provided in the embodiments of this disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0030] How to allocate physical registers and schedule instructions is a problem that the industry urgently needs to solve.

[0031] The increase in standard cells, area, and critical path for each additional write port in the register file is as follows:

[0032] 1. Increase in standard unit quantity:

[0033] Each additional write port requires an N-bit write address decoder, with a complexity of O(log₂ N). Each register bit requires an N-input multiplexer, also with a complexity of O(log₂ N). Therefore, the total increase in standard cells is O(M*log₂ N), where M is the register bit width and N is the number of registers in the physical register file. For example, for a 32-bit register file with 32 registers, each additional write port increases the standard cells by approximately 32*log₂ 32 = 160 standard cells.

[0034] 2. Increase in area:

[0035] The increase in area is mainly reflected in the increased area of ​​the write address decoder and multiplexer circuits. The area complexity of these two circuits is proportional to log₂N, so the total area increase is approximately O(M*log₂N). In the example above, the area increase is approximately the area of ​​160 standard cells.

[0036] 3. Increased critical path:

[0037] Each additional write port requires a corresponding write address decoder and multiplexer circuit. These circuits increase the critical path latency of the register file by approximately O(log₂ N). For the example of 32 registers, the increase in critical path latency is approximately log₂ 32 = 5 standard cell delays.

[0038] In summary, each additional write port in the register file results in approximately O(M*log₂ N) increases in standard cell size, O(M*log₂ N) area, and O(log₂ N) critical path latency. Therefore, the number of read / write ports in the register file directly affects the register area and read / write timing.

[0039] The embodiments of this disclosure provide a solution in which the free physical register file is divided into odd and even parts during the renaming phase. Each renaming operation provides `even_freeList` with a renaming width of `renameWidth` free registers and `odd_freeList` with `renameWidth` free registers. The instruction determines whether to allocate odd or even physical registers for the current renaming operation based on the instruction type and the odd / even allocation balancing logic. Through these embodiments, the number of write ports to the register file can be reduced by half, the write timing of the register file is optimized, and physical register allocation and instruction scheduling are effectively performed.

[0040] Figure 1 is a schematic diagram of a processor architecture based on parity scheduling and allocation provided in an embodiment of this disclosure. As shown in Figure 1, the processor includes a front-end instruction fetch unit 112, an instruction decode unit 113, a rename unit 114, a dispatch unit 115, reservation stations 122A, 122B, 122C, and 122D, an execution unit 124, 125, 126, and 127, and two register files.

[0041] As those skilled in the art will know, the number of reservation stations and execution units is the same as the number of types of instructions to be processed. In the embodiment shown in Figure 1, the types of instructions to be processed can include four types (arithmetic ALU type, mixed Misc type, write load type, and store type), therefore, there are also four reservation stations and four execution units, each corresponding to a different type. In actual design, the design can be modified as needed and is not limited to this.

[0042] The instruction decoding unit 113 is used to generate control signals for instruction splitting based on the type of the instruction to be processed. The instruction to be processed will obtain a control signal for the execution unit type FuType after passing through the Decode Unit 113. This signal is usually used as the control signal for instruction splitting. For example, in this embodiment of the disclosure, the instructions are divided into alu type, misc type (other arithmetic instructions besides alu instructions, which usually have long or variable execution cycles, such as multiplication and division instructions), and load / store memory access instruction type.

[0043] Each execution unit includes two execution components (even / odd), namely, an odd execution component and an even execution component. As shown in Figure 1, execution unit 124 includes an even execution component (Even-ExeUnit) 124A and an odd execution component (Odd_ExeUnit) 124B; execution unit 125 includes an even execution component 125A and an odd execution component 125B; execution unit 126 includes an even execution component 126A and an odd execution component 126B; and execution unit 127 includes an even execution component 127A and an odd execution component 127B.

[0044] As shown in Figure 1, in this embodiment of the present disclosure, the front-end instruction fetch unit 112 is coupled to the instruction decoding unit 113, the instruction decoding unit 113 is coupled to the renaming unit 114, and the renaming unit 114 is coupled to the dispatch unit 115. The dispatch unit 115 includes two dispatch scheduling queues, namely a misc dispatch queue 120A and a write / store dispatch queue 120B.

[0045] In this embodiment of the disclosure, the register file includes two register files, namely an odd register file 130B and an even register file 130A. The odd execution component in each execution unit is coupled to the odd register file 130B, and the even execution component in each execution unit is coupled to the even register file 130A.

[0046] In this embodiment of the disclosure, the dispatch unit 115 is used to dispatch and distribute the pending instruction according to the control signal. That is, the pending instruction is distributed according to whether it is a memory access type during the dispatch stage and coupled to misc dispatch queue 120A and load / store dispatch queue 120B respectively.

[0047] Based on the four categories of instructions to be processed mentioned above, in this embodiment of the disclosure, the reservation station may include an arithmetic reservation station (ALU Reservation 122A), a mixed reservation station (Misc Reservation 122B), a write reservation station (Load Reservation 122C), and a store reservation station (Store Reservation 122D). The ALU Reservation and the Misc Reservation are coupled to the misc dispatch queue, and the Load Reservation and the Store Reservation are coupled to the load / store dispatch queue. Specifically, as shown in Figure 1, the misc dispatch queue 120A is coupled to ALU Reservation 122A and Misc Reservation 122B, and the load / store dispatch queue 120B is coupled to load Reservation 122C and store Reservation 122D.

[0048] In this embodiment, the execution unit includes an arithmetic ALU execution unit, a hybrid Misc execution unit, a write load execution unit, and a store execution unit; wherein: the ALU execution unit is coupled to the ALU Reservation, the Misc execution unit is coupled to the Misc Reservation, the Load execution unit is coupled to the Load Reservation, and the Store execution unit is coupled to the Store Reservation. For example, as shown in Figure 1, ExuUnit 124 can be an arithmetic ALU execution unit, ExuUnit 125 can be a hybrid Misc execution unit, ExuUnit 126 can be a write load execution unit, and ExuUnit 127 can be a store execution unit; ALU Reservation 122A is coupled to ExuUnit 124, Misc Reservation 122B is coupled to ExuUnit 125, load Reservation 122C is coupled to ExuUnit 126, and store reservation 122D is coupled to ExuUnit 127. Even-ExeUnit 124A, EvenExeUnit 125A, Even-ExeUnit 126A, and Even-ExeUnit 127A are coupled to EvenRegFile 130A, and Even-ExeUnit 124B, Odd-ExeUnit 125B, Odd-ExeUnit 126B, and Odd-ExeUnit 127B are coupled to OddRegFile 130B. It should be noted that embodiments of this disclosure may include other combinations and interfaces not shown in Figure 1.

[0049] The renaming unit 114 is used to rename registers for instructions to be processed. Register renaming is achieved by allocating a temporary physical register for the instruction, rather than directly using the logical register referenced in the instruction. By renaming registers, a temporary physical register can be allocated for each instruction, thus avoiding conflicts such as read-after-write (WAR) and write-after-write (WAW) operations and improving execution efficiency.

[0050] Figure 2 is a schematic diagram of the structure of the register list freeList provided in this embodiment. In this embodiment, freeList is split into two parts: the odd register list OddFreeList and the even register list EvenFreeList. As shown in Figure 2, the odd / even register list evenOddFreeList 160 consists of two sub-modules: the even register list EvenFreeList 160A and the odd register list OddFreeList 160B. The structure of OddFreeList and EvenFreeList can be a first-in-first-out (FIFO) queue for pointer read / write, with each entry storing the number of a free physical register. Here, even_enqPtr represents the allocation pointer of EvenFreeList 160A, Odd_enqPtr represents the allocation pointer of OddFreeList 160B, even_deqPtr represents the release pointer of EvenFreeList 160A, and Odd_deqPtr represents the release pointer of OddFreeList 160B. phyRegNum represents the total number of physical registers.

[0051] The renaming unit 114 determines whether to allocate a free physical register based on the type of the instruction to be processed, and decides whether to allocate a register in the OddFreeList or the EvenFreeList based on the state of the ping-pong signal corresponding to each type; wherein, the state of the ping-pong signal is toggled according to whether the previous instruction allocated an odd or even register. In some embodiments, the renaming unit 114 also maintains multiple ping-pong signals, and each ping-pong signal corresponds to the type of the instruction to be processed. For example, an ALU type instruction to be processed corresponds to one ping-pong signal, and the state of the ping-pong signal toggles between "0" and "1". For example, "0" represents "true", corresponding to allocating a register from the even register file 130A; "1" represents "false", corresponding to allocating a register from the odd register file 130A. For example, if the register allocated for the previous ALU type instruction is from even register file 130A, it will trigger a state change of the ping-pong signal, such as from "0" to "1", and then a register needs to be allocated from odd register file 130A for the next ALU type instruction.

[0052] In this embodiment of the disclosure, the default emission selection algorithm in the reserved station can be an emission algorithm based on the age matrix. The even emission mask is the emission mask in the reserved station with all source operands ready, ANDed with the last bit of the physical register (i.e., after inverting the last bit of the physical register, ANDed with the emission mask in the reserved station with all source operands ready, to obtain the even emission mask). The odd emission mask is the emission mask in the reserved station with all source operands ready, ANDed with the last bit of the physical register (i.e., ANDed with the emission mask in the reserved station with all source operands ready, to obtain the odd emission mask). Then, the oldest one is selected from the even / odd emission masks.

[0053] Figure 3 is a schematic diagram of the physical register allocation during the renaming stage according to an embodiment of this disclosure. Each cycle, an even number of physical registers (e.g., 10) of the renaming width are given from EvenFreeList 160A, and an odd number of physical registers (e.g., 10) of the renaming width are given from OddFreeList 160B. The process for determining the destination physical register number for each instruction is shown in Figure 3.

[0054] Determine the instruction type. In this embodiment, instructions are categorized as follows: alu, misc, load / store (in practice, this is not limited to these, but the type of execution unit connected to the reserved station must be coupled). Determine whether a destination register (rd) is truly needed (this condition can vary; for example, the store instruction naturally does not have a destination register (rd), and the jump instruction also does not have a destination register (rd). In this embodiment, arithmetic instructions without a destination register (rd) are categorized under alu). If a destination register (rd) is truly needed, the allocation is determined based on whether the ping-pong signal of this type (in this embodiment, there are four types: alu_pingpong, misc_pingpong, load_pingpong, and store_pingpong, where store_pingpong is a dummy ping-pong and does not require allocBalance logic) is true or false. For example, a true ping-pong indicates allocation from an even free physical register, and vice versa. The register renaming width bar instruction executes this logic serially, and the ping-pong logic of each instruction needs to be toggled based on whether the previous allocation is odd or even. In Figure 3, pdest represents the physical destination register. If the destination register (rd) is not needed, pdest is always assigned a value of 0 or 1.

[0055] After the last instruction completes the above process, the masks allocated to even channels are accumulated to update EvenFreeList 160Aeven_enqPtr, and the masks allocated to odd channels are accumulated to update OddFreeList 160Bod_enqPtr. The update logic for EvenFreeList160A even_deqPtr is as follows: if the instruction commit is valid, the old even-numbered physical registers are written back (based on the lowest bit of the physical register number being 0); during rollback, only the number of even-numbered physical registers to be rolled back needs to be calculated to allow even_deqPtr to revert, without updating the table entries.

[0056] Furthermore, in implementation, an imbalance in register parity allocation can easily cause the parallelism of the execution unit to decrease from the actual 2 to 1. For example, consider the following scenario in ExuUnit 124 as shown in Figure 1: if two instruction operands are ready at the same time, but the destination physical registers are both even or both odd, the two instructions can only be issued serially from the reserved station, while the other execution unit remains idle. Therefore, embodiments of this disclosure also provide register allocation balancing logic. For example, the renaming unit 114 is further configured to determine, based on the number of odd / even instructions of each type in the previous renaming phase, whether the current renaming phase prioritizes allocating physical registers from the odd register file or the even register file; that is, considering the number of odd and even instructions of each type across the entire processing core to determine which type of idle physical register file the current renaming phase prioritizes allocating physical registers from.

[0057] Figure 4 is a schematic diagram of register allocation balance during the renaming stage provided in this embodiment. Figure 5 is a schematic diagram of the generation logic of ping-pong signals of various types for the first instruction in the renaming stage provided in this embodiment. The organizational structure is shown in Figure 4 as type-odd-even balance allocation (FuType_evenOddAllocBalance) 180, which consists of two sub-modules: EvenBalance 180A and OddBalance 180B. In this embodiment, FuType refers to the instruction type, including alu, misc, and load, etc. Both EvenBalance 180A and OddBalance 180B are first-in-first-out (FIFO) queues maintained by enqueue and dequeue pointers. The distance between the head and tail pointers (actually calculated based on the occupied entries) determines which queue is more empty, the odd or even queue. The ping-pong signal `fuType_pingpong` (i.e., the ping-pong signal) is used to actually control the ping-pong of the first instruction. For example, if the number of even free registers is greater than or equal to the number of odd free registers (Even freeReg num >= odd freeReg num), then ping-pong is set to true; otherwise, it is set to false, as shown in Figure 5. The `phyReg alloc balance` signal is used to initialize the first instruction signal, ensuring that it is not biased towards a particular queue from the beginning.

[0058] Figure 6 is a schematic diagram of the allocation pointer update determined by the allocBalance logic in the renaming stage according to an embodiment of this disclosure. The renaming unit 114 is further configured to update the corresponding counter based on whether the allocation is odd or even when a physical register has been allocated for the instruction to be processed. The counter is used to update the corresponding enqueue pointer. In some embodiments, the allocBalance allocation update process is shown in Figure 6. All valid instructions entering the Rename Unit 114 stage execute this logic serially. Taking the load instruction as an example, each instruction checks in parallel whether there is a destination register. If so, it checks the state of the ping-pong signal. If the ping-pong signal is true, the "load even alloc mask" is set to 1, indicating that a register is allocated in EvenFreeList. If the ping-pong signal is false, the "load odd alloc mask" is set to 1, indicating that a register is allocated in OddFreeList. Other instructions are similar to the load instruction and will not be described further. In Figure 6, the ping-pong signal corresponding to the load instruction is called load ping-pong, the ping-pong signal corresponding to the alu type instruction is called alu ping-pong, and the ping-pong signal corresponding to the misc type instruction is called misc ping-pong.

[0059] A destination register is indeed needed to update the corresponding counter based on whether the allocation is odd or even. The final counter is used to update the corresponding enqueue pointer.

[0060] Figure 7 is a schematic diagram of the release and update process of allocBalance provided in this embodiment of the disclosure. The release logic of allocBalance is shown in Figure 7, which is only illustrated using the alu type. The instruction is updated during the commit or walk phase:

[0061] 1. Commit phase:

[0062] a.even: Determines write enable based on isAlu_even &&! old_pdest.lsb (the least significant bit of the old / old physical register) assigned during the renaming phase of the instruction. If the number of old / old physical registers submitted by the instruction is even, the number of even-type registers is calculated by accumulating the isAlu_even values ​​carried.

[0063] b.odd: Determines write enable based on isAlu_odd && old_pdest.lsb assigned during the renaming phase of the instruction. If the number of old / old physical registers in the committed instruction is odd, the number of odd-type registers is calculated by accumulating the isAlu_odd values.

[0064] 2. Walk phase:

[0065] a.even: Determines the dequeue pointer backtracking step based on isAlu_even &&! pdest.lsb assigned during the renaming phase of the instruction. If the number of physical registers in the rollback instruction is even, the number of even-type registers is calculated by accumulating the isAlu_even values ​​carried.

[0066] b.odd: The step size for dequeuing pointer rollback is determined based on isAlu_odd && pdest.lsb assigned during the renaming phase of the instruction. If the number of physical registers in the rollback instruction is odd, the number of odd-type registers is calculated by accumulating the isAlu_odd values.

[0067] Figure 8 is a schematic diagram of the source operand wake-up logic in the status array of the reserved station provided in an embodiment of this disclosure. The status array in the reserved station includes an odd status array (odd_statusArray) 170B and an even status array (even_statusArray) 170A. When the pending instruction is updated in the queue, both the odd statusArray and the even statusArray are updated simultaneously.

[0068] In some embodiments, the reserved station wake-up logic is as follows: The partial organization of the statusArray in the reserved station is shown in Figure 8. This example assumes that an alu type instruction has two source operands, psrc_0 and psrc_1. When an instruction is enqueued for update, both blocks (even / odd) are updated simultaneously. The even execution unit or even reserved station fast wake-up port is directly hardwired to even_statusArray 170A, and the odd execution unit or odd reserved station fast wake-up port is directly hardwired to odd_statusArray 170B. This design, even when copying a psrc array, ensures that the circuit stages of the destination register are both log2N', where N' is the number of reserved station wake-up ports. However, by directly hardwired the wake-up ports into two groups, the fan-out of each wakeup port is halved, reducing the insertion of the drive buffer and improving timing.

[0069] The processor architecture based on parity scheduling and allocation provided in this disclosure divides the idle physical register file into odd and even parts during the renaming phase. It determines whether the current renaming operation allocates an odd or even physical register according to the instruction type. The embodiments provided in this disclosure can reduce the number of write ports of the register file by half. In conjunction with the physical register allocation balancing algorithm and the scheduling algorithm, the number of write ports of the register file can be effectively reduced while ensuring performance, and physical register allocation and instruction scheduling can be performed effectively.

[0070] This disclosure also provides a chip applied to an electronic device. The chip includes one or more processors and a communication interface coupled to the processors. The processor can adopt the processor structure based on parity scheduling and allocation provided in the above embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0071] It should be understood that the chip mentioned in the embodiments of this disclosure may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0072] This disclosure also provides an electronic device, which includes a chip. The chip is a processor as provided in the above embodiments. The processor can adopt the processor structure based on parity scheduling and allocation provided in the above embodiments, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0073] The electronic devices provided in this disclosure may include handheld devices with image processing capabilities, vehicle-mounted devices, etc. For example, some electronic devices include: mobile phones, tablets, PDAs, laptops, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving vehicles, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks, or future evolution of public land mobile communication networks. Terminal devices in a network (PLMN), etc., are not limited in this embodiment.

[0074] By way of example and not limitation, in this embodiment, the electronic device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0075] Furthermore, in this embodiment of the disclosure, the electronic device can also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

[0077] All embodiments disclosed herein can be executed individually or in combination with other embodiments, and are all considered to be within the scope of protection claimed by this disclosure.

Claims

1. A processor architecture based on parity scheduling and allocation, comprising a front-end instruction fetch unit, an instruction decode unit, a renaming unit, a dispatch unit, multiple reservation stations, multiple execution units, and two register files, which are sequentially coupled together; wherein, The instruction decoding unit is used to generate control signals for instruction diversion based on the type of the instruction to be processed; the number of the reservation station and the execution unit is the same as the number of types of the instruction to be processed. The dispatch unit is used to dispatch and distribute the instructions to be processed according to the control signal; Each execution unit includes an odd execution component and an even execution component, and the two register files include an odd register file and an even register file. The odd execution component in the execution unit is coupled to the odd register file, and the even execution component in the execution unit is coupled to the even register file. The renaming unit is used to rename the registers of the instruction to be processed; the renaming unit stores an odd register list OddFreeList and an even register list EvenFreeList, and the entries in OddFreeList and EvenFreeList store the numbers of free physical registers; the renaming unit determines whether to allocate a free physical register according to the type of the instruction to be processed and decides whether to allocate a register in OddFreeList or EvenFreeList based on the state of the ping-pong signal corresponding to each type; wherein, the ping-pong signal toggles its state according to whether the previous instruction allocated an odd or even register.

2. The processor architecture based on parity scheduling and allocation according to claim 1, wherein, The dispatch unit includes a misc dispatch queue and a load / store dispatch queue.

3. The processor architecture based on parity scheduling and allocation according to claim 2, wherein, The reservation stations include an arithmetic reservation station (ALU Reservation), a mixed reservation station (Misc Reservation), a write reservation station (Load Reservation), and a store reservation station (Store Reservation); wherein the ALU Reservation and the Misc Reservation are coupled to the misc dispatch queue, and the Load Reservation and the Store Reservation are coupled to the load / store dispatch queue.

4. The processor architecture based on parity scheduling and allocation according to claim 3, wherein, The execution unit includes an arithmetic ALU execution unit, a hybrid Misc execution unit, a write load execution unit, and a store execution unit; wherein: The ALU execution unit is coupled to the ALU Reservation, the Misc execution unit is coupled to the Misc Reservation, the Load execution unit is coupled to the Load Reservation, and the Store execution unit is coupled to the Store Reservation.

5. The processor architecture based on parity scheduling and allocation according to any one of claims 1 to 4, wherein, The structures of OddFreeList and EvenFreeList are pointer-based first-in-first-out (FIFO) queues.

6. The processor architecture based on parity scheduling and allocation according to any one of claims 1 to 5, wherein, The renaming unit is also used to determine, based on the number of odd / even instructions of each type in the previous renaming phase, whether the current renaming phase should preferentially allocate physical registers from the odd register file or from the even register file.

7. The processor architecture based on parity scheduling and allocation according to any one of claims 1 to 6, wherein, The status array in the reserved station includes an odd status array and an even status array. When the pending instruction is updated, both the odd status array and the even status array are updated simultaneously.

8. The processor architecture based on parity scheduling and allocation according to any one of claims 1 to 7, wherein, The renaming unit is also used to update the corresponding counter counter according to whether the allocation is odd or even when a physical register is allocated for the instruction to be processed. The counter counter is used to update the corresponding enqueue pointer respectively.

9. A chip, characterized in that, The processor architecture based on parity scheduling and allocation as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the chip described in claim 9.

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