Protecting semiconductor power switches

Abstract

A controller for a power switch. The controller comprises a sense input configured to be coupled to a main terminal of a power switch, overcurrent detection circuitry coupled to the sense input to receive sense current therefrom, the overcurrent detection circuitry comprising one or more current mirrors coupled and configured to mirror the sense current, and a plurality current comparators each coupled to receive a mirrored version of the sense current from the one or more current mirrors and configured to compare the received mirrored version of the sense current to a respective current threshold.

Description

[0001] Attorney Docket No. 25809-0509W01

[0002] PROTECTING SEMICONDUCTOR POWER SWITCHES

[0003] Field of the Disclosure

[0004] The present invention relates generally to protecting semiconductor switches that switch power in power electronics applications.

[0005] Background

[0006] Electronic and electromagnetic devices use power to operate. Often, electrical power is supplied in one form and must be changed into another form for output, dependent on the application context. For example, electrical power can be supplied either as alternating current or as direct current, but output as the other. The voltage and / or current of the supplied electrical power can differ from the form in which it is output.

[0007] Power electronics deals with processing electrical power to deliver it in a desired form. Power electronic systems are used in a variety of applications, including power generation, power transmission and distribution, and control. In many such applications, the supplied power is switched using power switches to provide the desired output.

[0008] Power switches are switching devices that are designed to switch relatively high voltages and currents. Power switches can be implemented as insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), high-electron-mobility transistors (HEMTs), and the like. Power switches are commonly made using semiconductor materials such as silicon, silicon carbide, gallium nitride, or other semiconductor materials.

[0009] In many power switches, the control terminal is a gate that is coupled to the main (i.e., emitter and collector or source and drain) terminals. To control switching of such power switches, a gate drive unit must appropriately bias the control terminal relative to the emitter or source. In enhancement mode devices, the gate must be positively biased relative to the emitter or source above a threshold voltage level for conduction between the main terminals. A zero or negative gate bias relative to the emitter or source effectively renders the power switch non-conductive. Switching the power switch Attorney Docket No. 25809-0509W01 between conductive and non-conductive states requires that the bias relative to the emitter or source be changed.

[0010] There are many circumstances that can lead to failure of a power switch. For example, in many applications, high voltages are applied across a power switch and high currents are conducted between its main terminals. If the power switch is not properly designed to withstand the high voltages or carry the high currents, the power switch could be damaged. Further, even a properly designed power switch can be damaged under improper operating conditions, including power cross, electrostatic discharge events, power surges, lightning strikes, and others. Depending on the operational context, failure of the power switch can lead not only to failure of the power converter, but also to failure of other equipment and the loss of property and even lives.

[0011] DESCRIPTION OF DRAWINGS

[0012] FIG. 1 schematically illustrates an example of such sense terminal in an application context of a controller for an IGBT power switch.

[0013] FIG. 2 is a graph that schematically represents an example of faulty operation of a power switch during the course of a switching period, overlaid with markings indicating how short circuit / over current conditions can be detected from current measurements.

[0014] FIG. 3 includes graphs with example waveforms that schematically represent an example of a normal and overvoltage condition of a power switch during an ON to OFF transition of the power switch.

[0015] FIG. 4 is a schematic representation of a controller that illustrates circuitry within fault protection circuitry that detects overvoltage conditions from current flow through current sense terminal.

[0016] FIG. 5 is a schematic representation of a controller in which a drive signal generator interoperates with fault protection circuitry to detect overvoltage conditions from current flow through current sense terminal and respond thereto.

[0017] FIG. 6 is a graph with a waveform that schematically represents an example of the gate voltage as a function of time when a controller protects an enhancement mode power Attorney Docket No. 25809-0509W01 switch from an overvoltage condition during a transition from an ON state to an OFF state.

[0018] FIGS. 7, 8 are schematic representations of implementations of controllers in which a drive signal generator interoperates with fault protection circuitry to detect overvoltage conditions from current flow through a current sense terminal and respond thereto.

[0019] FIG. 9 is a graph with a waveform that schematically represents an example of the gate voltage as a function of time when a controller protects an enhancement mode power switch from an overvoltage condition during a transition from an ON state to an OFF state.

[0020] As an aside, the power switches illustrated and described herein are all enhancement mode insulated gate bipolar transistors. This is not necessarily the case. Other types of power switches — including metal-oxide field-effect transistors (MOSFETs), bipolar transistors, junction field-effect transistors, high-electron-mobility transistors (HEMTs) — implemented as either enhancement or depletion mode devices can be used with appropriate modification of the concepts described herein.

[0021] Like reference symbols in the various drawings indicate like elements.

[0022] DETAILED DESCRIPTION

[0023] Examples of a switch fault detector for a switch controller are described herein.

[0024] In a switched mode power converter, a controller can set a power switch into a more conductive ON (i.e., closed) state or an essentially non-conductive OFF (i.e., open) state. Controllers are generally used with protective circuitry to detect and / or prevent various conditions that could harm the power switch and the power converter. Overvoltage conditions and overcurrent conditions are examples.

[0025] Overvoltage conditions generally occur when the power switch is OFF or during turn-off (i.e., the transition from a ON state to an OFF state). Active clamping seeks to prevent overvoltages from arising across the power switch by active control of the power switch or circuitry associated with the power switch. For example, in some implementations, a drive signal input into the control terminal (e.g., the gate or base) of a Attorney Docket No. 25809-0509W01 power switch can be actively controlled to limit the voltage at a main terminal (e.g., the collector or the drain) during turn-off. In many implementations, it is common practice to use transient voltage suppressor (TVS) diodes that are connected between the collector / drain and the base / gate. There are also active clamping techniques that use capacitively-compensated resistor voltage dividers to provide a sensed power switch voltage to a gate driver. The divided voltage that acts as the sensed power switch voltage is compared to a voltage threshold by a comparator that controls the current / voltage provided to the control terminal of the power switch to reduce turn-off overvoltage of the power switch.

[0026] Overcurrent or short circuit conditions generally occur when the power switch is ON or during turn-on (i.e., the transition from OFF to ON). In some cases, the current that flows between the main terminals of the power switch is estimated by measuring the voltage across the main terminals of the power switch. Under normal operating conditions, the voltage across the main terminals of the power switch should fall quickly to a relatively low level during turn on and remain at the low level while the power switch is ON. However, under a short circuit or overcurrent condition, the voltage across the power switch may initially fall but then rise after some time. The rate of increase in the voltage across the power switch may vary depending on the exact nature of the overcurrent or short-circuit condition. Overcurrent conditions may thermally load the power switch and damage the power switch even after a relatively short period of time.

[0027] As discussed above, controllers are generally used in conjunction with protective circuitry that detects and / or responds to or avoids overvoltage or overcurrent conditions and protects the power switch from harm. However, as the operational voltage of the power converter increases, it becomes progressively more difficult to provide overvoltage and overcurrent protection. In particular, an overcurrent or short circuit is generally detected when the voltage across the main terminals of the power switch increases from a low value, e.g., a value approaching zero volts. An overvoltage is necessarily detected when the voltage across the power switch is unduly high. Indeed, overvoltages may approach the rated withstand voltage of the power switch. By way of example, modern high-voltage IGBTs can withstand voltages of 3.3kV or higher. Protection circuitry must Attorney Docket No. 25809-0509W01 thus be able to tolerate a very large range of operational parameters, e.g., when detecting overvoltage or overcurrent conditions. As a result, the protection circuitry is often complex and the level of integration is low. Further, transient voltage suppressor (TVS) diodes are generally costly.

[0028] In one embodiment, the switch controller includes switch fault protection circuitry that both detects and responds to overcurrent or short circuit conditions and actively clamps the voltage across a power switch to prevent overvoltage conditions. In some implementations, both overcurrent and overvoltage conditions can be sensed from current flow through a single current sense terminal formed by a single pin on a package despite the large range of operational parameters discussed above. Additional pins on the packages of power converter controllers — as well as the associated components — can be costly in terms of both money and space (e.g., footprint on a printed circuit board). Further, the input characteristics of such a sense terminal can be favorable relative to sense terminals that sense both current and voltage.

[0029] FIG. 1 schematically illustrates an example of such sense terminal in an application context of a controller 100 for an IGBT power switch 50. In particular, power switch controller 100 includes fault protection circuitry 105 that detects both overcurrent and overvoltage conditions from current flow through a single current sense terminal 110. For didactic purposes, the components of fault protection circuitry 105 that are involved with overcurrent and short circuit protection are illustrated in FIG. 1. Example components of fault protection circuitry 105 that are involved with overvoltage protection are illustrated in FIGS. 4 and 5. However, all components sense fault conditions from current flow through current sense terminal 110 and can be combined in a single controller 100.

[0030] In more detail, controller 100 is packaged in a package 115 that is represented in part. The illustrated portion of package 115 includes current sense terminal 110, as well as a high supply terminal 111, a gate drive terminal 112, an emitter terminal 113, and a low supply terminal 114. Supply terminals 111, 114 are to be coupled across the voltage that powers controller 100 and are coupled to respective of a high supply rail 120 and a low supply rail 125 of controller 100. Emitter terminal 113 is to be coupled to the emitter Attorney Docket No. 25809-0509W01 of IGBT power switch 50. In some implementations, the emitter of power switch 50 is coupled to the low supply voltage and, in these implementations, terminals 114, 113 can be combined into a single terminal. However, in implementations such as the present one where the gate of IGBT power switch 50 is to be biased negatively with respect to the emitter of power switch 50 when power switch 50 is in the OFF state, emitter terminal 113 is maintained at a voltage that is intermediate between the higher voltage on supply terminal 111 and the lower voltage on supply terminal 114, e.g., by a voltage regulator in controller 100.

[0031] Gate drive terminal 112 is configured and coupled to output a drive signal to drive the gate of power switch 50 relative to the emitter, thereby switching power switch 50 back and forth between the essentially insulating OFF state and the conductive ON state. Although a single gate drive terminal 112 is illustrated, some packages may include a high and a low gate drive terminal that are coupled to output high and low drive signals, respectively. A controller with multiple gate drive terminals 112A, 112B is illustrated in FIG. 4. In general, one or more gate resistances (not shown) are included between the gate drive terminal(s) and the gate of power switch 50. In some implementations, controller 100 can include totem pole gate driver circuitry that generates the drive signal output over gate drive terminal(s) 112. In some implementations, under the direction of a control signal received from outside controller 100, the drive signal can coordinate the switching of power switch 50 with the switching of other power switches. For example, power switch 50 can be one of several switches that are switched in a half- or full-bridge configuration, e.g., as part of an inverter, to drive a motor, or the like.

[0032] Current sense terminal 110 is coupled to the collector of IGBT power switch 50 by an input network 70. The illustrated implementation of network 70 includes multiple resistors 72, 74, 76, ... that define the steady state magnitude of the sense current that flows into current sense terminal 110. In the illustrated implementation, three resistors 72, 74, 76 are shown. However, fewer or more resistors can be used depending on the magnitude of the voltages that will appear on the collector of IGBT power switch 50 during operation. For example, in some implementations, resistive network 70 can be configured such that the sense currents are essentially zero when IGBT power switch 50 Attorney Docket No. 25809-0509W01 is in the ON state and between 100 and 800 microamps, for example, between 300 and 500 microamps, when IGBT power switch 50 is in the OFF state. For example, resistive network 70 can have a resistance of between 1 and 15 MOhm, for example, between 2 and 3 MOhm.

[0033] In some implementations, input network 70 also includes one or more capacitors 77, 79. Capacitors 77, 79 help define the transient properties of the sense current that flows into current sense terminal 110. In the illustrated implementation, capacitors 77, 79 and resistor 76 provide a low impedance pathway for switching transients whereas resistors 72, 74, 76 define the magnitude of the sense current in the steady state. Capacitors 77, 79 are particularly appropriate in implementations where power switch 50 is to be switched very rapidly (e.g., where power switch 50 is implemented in silicon carbide).

[0034] Housed within package 115 of controller 100 are a voltage clamp 140, at least one current mirror 130 and one or more instances of current comparator circuitry 135. To schematically represent that there are a number “N” instances of current comparator circuitry 135, a single instance of current comparator circuitry 135 is represented enclosed in dashed brackets with the subscript “N.” Each of the different instances of current comparator circuitry 135 compare a scaled version of the sense current with an individual current threshold. In some implementations, the current thresholds are programmable and controller 100 can be adapted to diverse operational conditions. In others, the current thresholds are fixed and controller 100 is dedicated to particular application contexts. The different instances of current comparator circuitry 135 can be coupled to compare the current that is, e.g., on a corresponding output leg of a current mirror 130 with multiple output legs, on an output leg of a corresponding instance of current mirror 130 with a single output leg, or on combinations thereof. Further, the scaling of the currents that are compared by the different instances of current comparator circuitry 135 relative the sense current can differ so long as the current thresholds are also scaled accordingly.

[0035] Voltage clamp 140 is coupled to clamp the voltage of current sense terminal 110 to a maximum value. In the illustrated implementation, voltage clamp 140 is Attorney Docket No. 25809-0509W01 implemented as a single diode that defines the maximum value of the voltage of current sense terminal 110 relative to the voltage on high supply rail 120. Other implementations are possible, including implementations in which the maximum value of the voltage of current sense terminal 110 is defined relative to other voltages, e.g., relative to the voltage on emitter terminal 113 or the voltage on low supply rail 125.

[0036] The input of current mirror 130 is coupled between current sense terminal 110 and low supply rail 125. A resistor 145 is coupled between current mirror 130 and current sense terminal 110 and provides a degree of protection for current mirror 130 by limiting the sense current, e.g., in the event that current sense terminal 110 is coupled to an unduly high voltage. So long as the voltage of current sense terminal 110 is not clamped, current mirror 130 mirrors the sense current that flows into current sense terminal 110. In other words, the sense current flows from current sense terminal 110 to low supply rail 125 and acts as the control current that is mirrored on an output leg coupled between a node 150 and low supply rail 125.

[0037] Current comparator circuitry 135 is formed by the output leg of current mirror 130 and a programmable current source 155. Programmable current source 155 can be programmed to output a defined current to node 150.

[0038] Node 150, which is coupled between the output of programmable current source 155 and the input to the output leg of current mirror 130, is also coupled to the output 160 of current comparator 135. If the sense current mirrored by current mirror 130 is below the current that is output from programmable current source 155, then the difference will be output on output 160. If the mirrored sense current is above the current that is output from programmable current source 155, then no current will be output on output 160. The current on output 160 thus indicates the presence or the absence of a short circuit or other overcurrent fault and can be used as a logical trigger to turn off power switch 50. Alternatively, a voltage that results from the output impedance of current source 155 can be input into a voltage comparator and used to gate pulses in a drive state signal that indicate that power switch 50 is to be in the ON state. Other approaches to triggering turn off of power switch 50 can also be used. In operation, programmable current source 155 can be set to establish different current thresholds for detecting both overcurrent and Attorney Docket No. 25809-0509W01 overvoltage conditions from current flow through a single current sense terminal 110. In some implementations, the thresholds are programmable and can be tailored to the operational context. Factors that impact the threshold include the magnitude of the voltages that are switched, the characteristics of input network 70, the sensitivity of the loads that are driven, and the like.

[0039] FIG. 2 is a graph 200 that schematically represents an example of faulty operation of a power switch during the course of a switching period, overlaid with markings indicating how short circuit / over current conditions can be detected from sense current measurements.

[0040] Graph 200 includes an x-axis 205 and a y-axis 210. Position along x-axis 205 denotes time. Position along y-axis 210 denotes voltage. Two traces 215, 220 are represented on graph 200. Although the scaling of time along x-axis 205 is common to traces 215, 220, the scaling of voltage along y-axis 210 is different. In particular, trace 215 represents the collector-to-emitter voltage of an IGBT power switch and trace 220 represents the gate-to-emitter voltage of the IGBT power switch. Depending on the operational context, the voltage range for trace 215 can be between, e.g., 0 V to 6.5 kV. Depending on the operational context, the voltage range for trace 215 can be between, e.g., -15 V to 30V, e.g., between -8 V and 15 V. Both voltage ranges are referenced to the emitter voltage, which is represented along x-axis 205. In the context of controller 100 (FIG. 1), the relationship between the sense currents received at current sense terminal 110 and the collector-to-emitter voltage represented by trace 215 will be determined by input network 70.

[0041] Initially at 222, the IGBT power switch is in the OFF state. Collector-to-emitter voltage 215 is at a steady, high level and the gate-to-emitter voltage 220 of the IGBT power switch is negatively biased with respect to the emitter. At time Tl, the IGBT power switch begins transitioning to the ON state. Gate-to-emitter voltage 220 is driven positive and, after the gate threshold voltage is reached, the enhancement-mode IGBT power switch begins to conduct and collector-to-emitter voltage 215 slopes sharply downward during the OFF-to-ON transition at 224. Collector-to-emitter voltage 215 eventually falls to nearly zero at 226, with the residual voltage due to the channel Attorney Docket No. 25809-0509W01 resistance of the IGBT power switch. During the transition, gate-to-emitter voltage 220 has risen to a desired forward-bias level.

[0042] The illustrated OFF-to-ON transition is fault-free and short circuit / over current conditions do not arise during the transition. However, short circuit / over current conditions arises while the IGBT power switch is in the ON state and the collector-to- emitter voltage 215 rises rapidly as the IGBT power switch desaturates at 228. In general, short circuit / over current conditions can have any of a variety of different causes including, e.g., damage to components and / or their insulation, misconnections between lines, and short circuits, for example, in bridge configurations involving multiple power switches. In the illustrated circumstances, the short circuit / over current condition is detected and fault protection circuitry initiates protection by lowering gate-to-emitter voltage 220 at 230.

[0043] Graph 200 is overlaid with markings indicating how sense current can be used to detect short circuit / over current conditions during the OFF-to-ON transition. A series of threshold voltage levels 232, 234, 236 are defined along y-axis 210 and a series of corresponding time periods 242, 244, 246 are defined along x-axis 205. Time periods 242, 244, 246 are all defined relative to time Tl, i.e., time periods 242, 244, 246 all start when the IGBT power switch begins transitioning to the ON state. Each respective threshold voltage level 232, 234, 236 and its corresponding time period 242, 244, 246 together define the circumstances for identifying a fault during the transition from the OFF state to the ON state. In particular, if collector-to-emitter voltage 215 does not fall below threshold voltage level 232 within time period 242, then a fault is detected. Also, if collector-to-emitter voltage 215 does not fall below threshold voltage level 234 within time period 244, then a fault is detected. Similarly, if collector-to-emitter voltage 215 does not fall below threshold voltage level 236 within time period 246, then a fault is detected. As an aside, the number of threshold voltage levels and time periods can be varied. In any case, the illustrated OFF-to-ON transition is fault-free in that collector-to- emitter voltage 215 is always below threshold voltage levels 232, 234, 236 at the end of the corresponding time period 242, 244, 246. Attorney Docket No. 25809-0509W01

[0044] Graph 200 is also overlaid with markings indicating how current measurements can be used to detect short circuit / over current conditions while the IGBT power switch is in the ON state. Once again series of threshold voltage levels 252, 254, 256 are defined along y-axis 210. Threshold voltage levels 252, 254, 256 can be the same levels as threshold voltage levels 232, 234, 236 or they can differ. A series of corresponding time periods 262, 264, 266 are defined along x-axis 205. Time periods 262, 264, 266 are all defined relative to a respective time T2, T3, T4 at which collector-to-emitter voltage 215 rises above the corresponding threshold voltage level 252, 254, 256. As a result, time periods 262, 264, 266 all have different, respective start times T2, T3, T4.

[0045] Each respective threshold voltage level 252, 254, 256 and its corresponding time period 262, 264, 266 together define the circumstances for identifying a fault while the IGBT power switch is the ON state. In particular, once collector-to-emitter voltage 215 rises above one of threshold voltage levels 252, 254, 256, a timer defining the corresponding time period 262, 264, 266 is started. Thus, time period 266 starts at T2 as collector-to-emitter voltage 215 rises above threshold voltage level 256, time period 264 starts at T3 as collector-to-emitter voltage 215 rises above threshold voltage level 254, and time period 262 starts at T4 as collector-to-emitter voltage 215 rises above threshold voltage level 252.

[0046] Time periods 262, 264, 266 act as blanking times for the detection of a fault and their respective durations shortens as the corresponding threshold voltage level 252, 254, 256 increases. Thus, time period 262 — which corresponds to the highest of the threshold voltage levels, namely, threshold voltage level 252 — is shorter than time periods 264, 266. Time period 264 — which corresponds to the middle threshold voltage level, namely, threshold voltage level 254 — is longer than time period 262 and shorter than time periods 266. For a fault to be detected, collector-to-emitter voltage 215 must remain above a threshold voltage level 252, 254, 256 for a duration that is longer than its respective time period 262, 264, 266.

[0047] For example, in graph 200, collector-to-emitter voltage 215 rises above each threshold voltage level 252, 254, 256 in rapid succession due to a short circuit or overcurrent fault condition. However, because the blanking period provided by time Attorney Docket No. 25809-0509W01 period 262 expires first, the fault is detected and a response is triggered on the basis of collector-to-emitter voltage 215 being above threshold voltage level 252. In particular, gate-to-emitter voltage 220 of the IGBT power switch is driven to shut OFF the power switch at the expiry of time period 262. The blanking periods set by time periods 264, 266 have not yet expired, as schematically represented by the arrows on the right side of time periods 264, 266.

[0048] In other circumstances, a fault can be detected and a response triggered on the basis of collector-to-emitter voltage 215 being above either threshold voltage level 254 or 256. For example, collector-to-emitter voltage 215 could rise above threshold voltage level 256 but never reach threshold voltage level 252, 254. Time periods 262, 264 would never start. However, if collector-to-emitter voltage 215 remains above threshold voltage level 256 until expiry of the blanking period set by time period 266, then a fault will be detected and a response triggered. By using multiple threshold voltage levels and time periods, diverse short circuit or overcurrent fault conditions can be detected.

[0049] FIG. 3 includes graphs 305, 310, 315, 320 with example waveforms that schematically represent an example of a normal and overvoltage condition of a power switch, namely, during an ON to OFF transition of the power switch. Position along the x-axes denotes time and position along y-axes denotes voltage.

[0050] In particular, the waveforms in graphs 305, 310 represent a portion of a drive signal UD 325. In general, the gate-to-emitter voltage of the driven power switch will closely follow drive signal UD 325. The illustrated portions of drive signal UD 325 correspond to a time span during which a switch driver drives a transition of the power switch from the conductive ON state to the non-conductive OFF state. In both graphs 305, 310, during the ON time, drive signal UD 325 is at a voltage VON 330 that suffices to maintain the enhancement mode power switch in the conductive ON state. Again referring to both graphs 305, 310, during the OFF time, the drive signal UD 325 is at a voltage VOFF 332 that suffices to maintain the enhancement mode power switch in the non-conductive OFF state. In the illustrated implementation, the voltage VOFF 332 that maintains the enhancement mode power switch in the non-conductive OFF state is Attorney Docket No. 25809-0509W01 negative with respect to the emitter voltage. In other implementations, voltage VOFF 332 can be approximately equal to zero.

[0051] However, the illustrated portions of drive signals UD 325 in graphs 305, 310 differ during the transition between the ON state and the OFF state. In graph 305, circumstances that could give rise to an overvoltage condition do not arise and drive signal UD 325 smoothly transitions between voltages VON 330 and VOFF 332. However, in graph 310, circumstances that could give rise to an overvoltage condition arise. However, the overvoltage is prevented by temporarily stopping drive signal UD 325 from decreasing. Parasitics or even active pull-up may also cause drive signal UD 325 to temporarily increase, in the illustrated scenario, drive signal UD 325 increases twice during the transition between the ON state and the OFF state. In any case, stopping drive signal UD 325 from decreasing actively clamps the collector-to-emitter voltage VCE 335, as illustrated in graph 320.

[0052] In particular, the waveforms in graphs 315, 320 represent the collector-to-emitter voltage VCE 335 during the transition from the ON state to the OFF state. Graph 315 represents a normal, or fault- free, transition. In graph 315, collector-to-emitter voltage VCE 335 rises from nearly zero in the ON state and eventually settles at the voltage 340 that is switched by the power switch. Although collector-to-emitter voltage VCE 335 rises slightly above the switched voltage 340 (mainly due to parasitic inductances), collector- to-emitter voltage VCE 335 remains less than a reference level 345 that indicates an overvoltage condition and is used to trigger active clamping. Collector-to-emitter voltage VCE 335 also remains well below an overvoltage limit 350 that represents the desired maximum collector-to-emitter voltage VCE 335. For example, overvoltage limit 350 can be part of the definition of the safe operating area of the power switch. In contrast, graph 320 represents a transition from the ON state to the OFF state with an overvoltage condition. In graph 320, collector-to-emitter voltage VCE 335 also rises from nearly zero in the ON state but reaches voltages that exceed reference level 345, indicating the overvoltage condition. In the illustrated implementation, the remedial measures are undertaken to both lower collector-to-emitter voltage VCE 335 and ensure that collector- to-emitter voltage VCE 335 remains below overvoltage limit 350. . Attorney Docket No. 25809-0509W01

[0053] FIG. 4 is a schematic representation of controller 100 that illustrates circuitry within fault protection circuitry 105 that detects overvoltage conditions from current flow through current sense terminal 110. The coupling of fault protection circuitry 105 to drive signal generator 405 is also illustrated one implementation of active clamping described. In the illustrated implementation, a current mirror and comparator are used to detect overvoltage conditions from current flow through current sense terminal 110. These are designated, e.g., as current mirror 435 and current source 430. In some implementations, the input leg of current mirror 435 can be coupled to an output leg of current mirror 130. The scaling of the sense current and the magnitudes of the currents against which the scaled sense currents are compared can differ between current source 155 and current source 430. However, in these cases, both over current and overvoltage conditions are both detected by comparing current flow through current sense terminal 110 to thresholds.

[0054] In the illustrated implementation, drive signal generator 405 includes a totem pole gate driver that includes a pull-up transistor 407 and pull down transistor 409. In the illustrated implementation, transistors 407, 409 are MOSFETs that are each coupled to a respective gate drive terminal 112A, 112B. In other implementations, the source of pull- up transistor 407 is coupled to the drain of pull-down transistor 409 at a bridge node that is internal to controller 100 and the bridge node is in turn coupled to a single gate drive terminal 112. In either case, the drain of pull-up transistor 407 is coupled to high supply rail 120 and the source of pull-down transistor 409 is coupled to low supply rail 125.

[0055] The switching of transistors 407, 409 is coordinated by a drive state signal 410. As discussed above, pulses in drive state signal 410 can be gated using the current on output 160 (FIG. 1) to ensure that power switch 50 is not in the ON state during an overcurrent condition. Drive state signal 410 is buffered within drive signal generator 405 by a buffer 412 and an inverting buffer 414. The output of buffer 412 is coupled to the control terminal of pull-up transistor 407. The output of inverting buffer 414 is coupled to a switchable current source 415. The output of current source 415 is coupled to both the control terminal of pull-down transistor 409 and to the input to an output leg of a current mirror 420. When current mirror 420 is conducting, current from current Attorney Docket No. 25809-0509W01 source 415 is split between charging the control terminal of pull-down transistor 409 and flowing through current mirror 420. As discussed further below, this splitting of the current from current source 415 slows the charging of the control terminal of pull-down transistor 409 and actively clamps the driven power switch during a transition from the ON state to the OFF state.

[0056] The input leg of current mirror 420 is coupled to receive a clamp current 425 from fault protection circuitry 105. Clamp current 425 represents the magnitude by which the current from current source 415 is to be reduced, thereby clamping the charging of the control terminal of pull-down transistor 409.

[0057] Fault protection circuitry 105 generates clamp current 425 by comparing the current that flows through current sense terminal 110 to a reference current generated by a current source 430. In more detail, current flows into current source 430 from the output leg of a current mirror 432. The input leg of current mirror 432 is coupled to the output leg of current mirror 435. The input leg of current mirror 435 is coupled to sense terminal 110. Current mirror 435 is also coupled to switching circuitry 433 that switches current mirror 435 on and off in response to drive state signal 410. When drive state signal 410 is high and indicates that the power switch is to be ON or turning on — and hence not subject to overvoltage conditions — switching circuitry 433 prevents current mirror 435 from mirroring the current that flows through current sense terminal 110. When drive state signal 410 is low and indicates that the power switch is to be OFF or turning off — and hence possibly subject to overvoltage conditions — switching circuitry 433 enables current mirror 435 to mirror the sense current that flows through current sense terminal 110. The sense current mirrored by current mirror 435 is also mirrored by current mirror 432 and the current output is subtracted therefrom by current source 430. If the mirrored sense current is greater than the current output by current source 430, then clamp current 425 remains above zero. On the other hand, if the mirrored sense current is less than the current output by current source 430, then clamp current 425 falls to zero. The clamp current 425 flows through the input leg of current mirror 420 and diverts current from current source 415 from charging the control terminal of pull-down Attorney Docket No. 25809-0509W01 transistor 409. An overvoltage is prevented by temporarily reducing the rate of decrease (or even stopping the decrease) of the voltage on the gate of the power switch.

[0058] On the other hand, if the mirrored sense current is greater than the current output by current source 430, then clamp current 425 will not flow and all of the current output from current source 415 can charge the gate of the pull-down transistor 409. The rate of decrease of the voltage on the gate of the power switch will remain at its highest level.

[0059] FIG. 5 is a schematic representation of another implementation of controller 100 in which a drive signal generator 505 interoperates with fault protection circuitry 105 to detect overvoltage conditions from current flow through current sense terminal 110 and respond thereto.

[0060] The illustrated implementation of drive signal generator 505 also includes a totem pole gate driver that includes a pull-up transistor 407 and pull-down transistor 409 that are coupled to respective gate drive terminals 112A, 112B. Under fault-free operating conditions, pull-up and pull-down transistors 407, 409 are driven in accordance with drive state signal 410, which is buffered by buffer 412 and inverting buffer 414.

[0061] However, in contrast with the implementation of controller 100 illustrated in FIG. 4, the output of inverting buffer 414 is coupled to an input of an AND gate 510. The other input of AND gate 510 is coupled to the output of a comparator 515. Comparator 515 is a fast comparator and the output of comparator 515 can switch between high and low states rapidly. Comparator 515 can either be a current comparator or a voltage comparator and the threshold can be either a current threshold or a voltage threshold.

[0062] Comparator 515 is coupled to compare clamp current 425 (or a voltage) to a threshold that represents the level at which overvoltage protection is to be triggered. If overvoltage protection is to be triggered, then the output of comparator 515 will prevent AND gate 510 from passing the inverse of drive state signal 410 to the gate of pull-down transistor 409 by way of a buffer 520. If overvoltage protection is not triggered, then the output of comparator 515 will allow AND gate 510 to pass the inverse of drive state signal 410 to the gate of pull-down transistor 409 by way of buffer 520. Because of the fast response of comparator 515, pull-down transistor 409 can be turned on and off rapidly. The pull-down of the power switch can be thus stopped when the sense current Attorney Docket No. 25809-0509W01 indicates an overvoltage condition and then restarted when the sense current no longer indicates an overvoltage condition.

[0063] FIG. 6 includes a graph 600 with a waveform that schematically represents an example of the gate voltage as a function of time when a controller (e.g., controller 100 in FIG. 5) protects an enhancement mode power switch from an overvoltage condition during a transition from an ON state 605 to an OFF state 610.

[0064] In graph 600, time is represented on the x-axis 615 and the gate voltage is represented on the y-axis 620. In ON state 605, the gate is positively biased relative to the emitter or source, whereas in OFF state 610, the gate is negatively biased relative to the emitter or source. During the course of the transition, an overvoltage condition is sensed. In response, the pull-down of the gate of the power switch is stopped when the sense current indicates an overvoltage condition. For controllers like controller 100 in FIG. 5, when pull-down is stopped, the gate floats and, under certain conditions, can even rise to a level that exceeds the positive bias in ON state 605. At some point, an overvoltage condition is no longer indicated and pull down is restarted in response. In the illustrated example, pull down is stopped and restarted again and again as the power switch moved in and out of responding to overvoltage conditions several times during the transition, resulting in relatively high frequency oscillations 625 in the gate voltage.

[0065] FIG. 7 is a schematic representation of another implementation of controller 100 in which a drive signal generator 705 interoperates with fault protection circuitry 105 to detect overvoltage conditions from current flow through current sense terminal 110 and respond thereto.

[0066] The illustrated implementation of drive signal generator 705 includes a totem pole gate driver that includes a pull-up transistor 707 and pull-down transistor 709 that are coupled to respective gate drive terminals 112A, 112B. Under fault- free operating conditions, pull-up and pull-down transistors 707, 709 are driven in accordance with a drive state signal.

[0067] Akin to the implementation of controller 100 illustrated in FIG. 5, drive signal generator 705 is also configured to stop pull-down of the gate of the power switch in response to an overvoltage condition being indicated. For example, drive signal Attorney Docket No. 25809-0509W01 generator 705 can include comparator 515, AND gate 510, and buffer 520 that respond to a clamp current or a voltage (e.g., clamp current 425) crossing a threshold that represents the level at which overvoltage protection is to be triggered.

[0068] However, in contrast with the implementation of controller 100 illustrated in FIG. 5, drive signal generator 705 does not allow the gate of power switch 50 to float when pull-down is stopped. Rather, drive signal generator 705 includes a monostable multivibrator 710 that is coupled to receive a signal 715 indicating that the clamp current or voltage has crossed the threshold and respond to this indication by defining a time duration during which pull-up transistor 707 is driven into conduction. Pull-up transistor 707 can be driven into conduction by, e.g., current flow pull up transistor 707 or through another transistor. By driving pull-up transistor 707 into conduction, the gate of power switch 50 will be biased to a positive voltage (the voltage on supply terminal 111 in the illustrated implementation) for the time duration. This duration is configured to ensure that the overvoltage condition is no longer present. This duration can either be fixed or programmable.

[0069] FIG. 8 is a schematic representation of another implementation of controller 100 in which a drive signal generator 805 interoperates with fault protection circuitry 105 to detect overvoltage conditions from current flow through current sense terminal 110 and respond thereto.

[0070] The illustrated implementation of drive signal generator 805 includes a totem pole gate driver that, under fault-free operating conditions, drives pull-up and pull-down transistors in accordance with a drive state signal. Also, akin to the implementation of controller 100 illustrated in FIG. 7, drive signal generator 805 is configured to stop pulldown of the power switch in response to an overvoltage condition being indicated and bias the gate of power switch 50 to a positive voltage for a time duration.

[0071] However, in contrast with the implementation of controller 100 illustrated in FIG. 7, drive signal generator 805 does not include a monostable multivibrator within package 115. Rather, drive signal generator 805 is configured to output a signal 815 indicating that the clamp current or voltage has crossed the threshold that represents the level at which overvoltage protection is to be triggered to a monostable multivibrator 810 that is Attorney Docket No. 25809-0509W01 outside the package 115. Monostable multivibrator 810 is coupled to respond to this indication by defining a time duration during which the gate of power switch 50 is to be biased to a positive voltage. In the illustrated implementation, the gate of power switch 50 is biased to the voltage on supply terminal 111, although this is not necessarily the case. Once again, the duration is configured to ensure that the overvoltage condition is no longer present and may be fixed or programmable.

[0072] In the illustrated implementation, signal 815 is output over a dedicated terminal 820. This is not necessarily the case. For example, signal 815 can be output over another terminal that is divided, e.g., in time, frequency, or otherwise.

[0073] FIG. 9 includes a graph 900 with a waveform that schematically represents an example of the gate voltage as a function of time when controller (e.g., controller 100 in FIGS. 7, 8) protects an enhancement mode power switch from an overvoltage condition during a transition from an ON state 905 to an OFF state 910.

[0074] In graph 900, time is represented on the x-axis 915 and the gate voltage is represented on the y-axis 920. In ON state 905, the gate is positively biased relative to the emitter or source, whereas in OFF state 910, the gate is negatively biased relative to the emitter or source. During the course of the transition, an overvoltage condition is sensed. In response, the pull-down of the power switch is stopped and the monostable multivibrator ensures that the gate of the power switch is biased to a positive voltage 930 for a time duration 935 when the sense current indicates an overvoltage condition. After time duration 935 has passed, pull down is restarted.

[0075] Since the gate of the power switch is biased to a positive voltage 930 for time duration 935, there is a more stable response to an overvoltage condition. The switching transients — and associated noise and fluxes — shown in high frequency oscillations 625 are avoided.

[0076] In some cases, an overcurrent condition will again arise after time duration 935 has passed and pull down is restarted. For example, time duration 935 may be too short or positive voltage 930 may be too low for a given set of circumstances.

[0077] Regardless of the reason that an overcurrent condition has returned, pull-down of the power switch is stopped in response to the second detection of an overvoltage Attorney Docket No. 25809-0509W01 condition. In some implementations, when pull-down is stopped, the gate is allowed to float. In some cases, overvoltage conditions are detected multiple times and pull down is stopped and restarted again and again, resulting in relatively high frequency oscillations in the gate voltage, akin to oscillations 625 (FIG. 6). Thus, the response to recurring overvoltage conditions during a single ON-to-OFF transition can include both biasing the gate of the power switch to a defined positive voltage 930 for a defined time duration 935 and allowing the gate to float one or more times during the ON-to-OFF transition.

[0078] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, fault detection circuitry described herein has been illustrated with a single programmable current source 155 and a single output leg of a current mirror 130. However, comparable results can be achieved with multiple current sources and one or more output legs of one or more current mirrors. Accordingly, other implementations are within the scope of the following claims.

Claims

Attorney Docket No. 25809-0509W01WHAT IS CLAIMED IS:

1. A controller for a power switch, the controller comprising: a sense input configured to be coupled to a main terminal of a power switch; overcurrent detection circuitry coupled to the sense input to receive sense current therefrom, the overcurrent detection circuitry comprising one or more current mirrors coupled and configured to mirror the sense current, and a plurality current comparators each coupled to receive a mirrored version of the sense current from the one or more current mirrors and configured to compare the received mirrored version of the sense current to a respective current threshold.

2. The controller of claim 1, wherein the plurality of different current thresholds includes a first current threshold defined by a first threshold current level and a first duration, wherein the first duration is started in response to a power switch beginning a transition from an OFF state to an ON state and a first of the current comparators is configured to output an indication of an overcurrent fault in response to the sense current exceeding the first current threshold at an end of the first duration.

3. The controller of claim 2, wherein the plurality of different current thresholds includes a second current threshold defined by a second threshold current level and a second duration, wherein the second duration of the second current threshold is also started in response to a power switch beginning a transition from an OFF state to an ON state, a second of the current comparators is configured to output an indication of an overcurrent fault in response to the sense current exceeding the second current threshold at an end of the second duration, the second threshold current level is higher than the first threshold current level, and the second duration is shorter than the first duration.

4. The controller of any of claims 1 to 3, wherein the plurality of different current thresholds includes a third current threshold defined by a third threshold currentAttorney Docket No. 25809-0509W01 level and a third duration, wherein the third duration is started in response to the sense current exceeding the third current threshold and a third of the current comparators is configured to output an indication of an overcurrent fault in response to the sense current exceeding the third current threshold at an end of the third duration.

5. The controller of claim 4, wherein the plurality of different current thresholds includes a fourth current threshold defined by a fourth threshold current level and a fourth duration, wherein the fourth duration is started in response to the sense current exceeding the fourth current threshold and a fourth of the current comparators is configured to output an indication of an overcurrent fault in response to the sense current exceeding the fourth current threshold at an end of the fourth duration.

6. The controller of any of claims 1 to 5, wherein at least some of threshold current levels are programmable.

7. The controller of any of claims 1 to 6, wherein the one or more current mirrors comprises a current mirror with a single input leg and multiple output legs.

8. The controller of any of claims 1 to 6, wherein the one or more current mirrors comprises multiple current mirrors with an input leg of at least one of the multiple current mirrors coupled to an output leg of another of the multiple current mirrors.

9. The controller of any of claims 1 to 8, further comprising overvoltage detection circuitry coupled to the sense input to receive sense current therefrom.

10. The controller of claim 9, further comprising overvoltage protection circuitry, wherein the overvoltage protection circuitry comprises: a comparator coupled to receive a mirrored version of the sense current, wherein, in response to the mirrored version of the sense current exceeding a threshold, the comparator is configured to output a signal that represents an amount by which the mirrored version of the sense current exceeds the threshold; and active clamping circuitry configured to reduce or stop driving the power switch into or in an OFF state in response to the amount by which the mirrored version of theAttorney Docket No. 25809-0509W01 sense current exceeds the threshold.

11. The controller of claim 9, further comprising overvoltage protection circuitry, wherein the overvoltage protection circuitry comprises: a comparator coupled to receive a mirrored version of the sense current, wherein, in response to the mirrored version of the sense current exceeding a threshold, the comparator is configured to output a signal indicating that the mirrored version of the sense current exceeds the threshold; and active clamping circuitry configured to stop driving of the power switch into an OFF state in response to the mirrored version of the sense current exceeding the threshold.

12. The controller of claim 11 , wherein the overvoltage protection circuitry is further configured to bias the power switch into an ON state in response to the mirrored version of the sense current exceeding the threshold.

13. The controller of claim 12, wherein the overvoltage protection circuitry is further configured to bias the power switch into the ON state for a duration of time in response to the mirrored version of the sense current exceeding the threshold.

14. The controller of any of claims 1 to 10, wherein the controller is housed within a semiconductor package and the sense input is a single terminal of the semiconductor package.

15. A controller for a power switch, the controller comprising: a sense input configured to be coupled to a main terminal of a power switch; overvoltage detection circuitry coupled to the sense input and configured to detect an overvoltage condition and output an indication of the detection of the overvoltage condition; and overcurrent protection circuitry coupled to receive the indication of the detection of the overvoltage condition from the overvoltage detection, wherein the overcurrent protection circuitry is configured to stop driving the power switch into or in an OFF state and bias the power switch into the ON state in response to the indication of the detection of the overvoltage condition.Attorney Docket No. 25809-0509W0116. The controller of claim 15, wherein the overvoltage detection circuitry comprises: a comparator coupled to receive a mirrored version of a sense current, wherein, in response to the mirrored version of the sense current exceeding a threshold, the comparator is configured to output a signal indicating that the mirrored version of the sense current exceeds the threshold.

17. The controller of claim 15 or 16, wherein the overvoltage protection circuitry is further configured to bias the power switch into the ON state for a duration of time in response to the mirrored version of the sense current exceeding the threshold.

18. The controller of claim 17, wherein the overvoltage protection circuitry comprises a monostable multivibrator configured to define the duration of time.

19. The controller of any one of claims 15 to 18, further comprising the overcurrent detection circuitry of any one of claims 1 to 14.

20. A controller for a power switch, the controller comprising: a semiconductor package housing the controller; a sense terminal configured to be coupled to a main terminal of a power switch; overcurrent detection circuitry coupled to the sense terminal to receive sense current therefrom; and overvoltage detection circuitry coupled to the sense terminal to receive sense current therefrom.

21. A system comprising : the controller of any preceding claim; and an IGBT power switch configured to switch voltages above 1000 volts, wherein the main terminal of the power switch is the collector of the IGBT power switch.

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