SiC SUBSTRATE, SiC EPITAXIAL WAFER, SiC DEVICE, SiC SUBSTRATE MANUFACTURING METHOD, SiC EPITAXIAL WAFER MANUFACTURING METHOD, AND SiC DEVICE MANUFACTURING METHOD

Abstract

This SiC substrate comprises a first main surface, a second main surface, and a joining layer. The first main surface faces the second main surface. The first main surface and the second main surface are each an Si surface or a C surface. The joining layer is located between the first main surface and the second main surface. The joining layer contains a compound formed of carbon and silicon.

Description

SiC substrates, SiC epitaxial wafers, SiC devices, methods for manufacturing SiC substrates, methods for manufacturing SiC epitaxial wafers, and methods for manufacturing SiC devices 【0001】 The present disclosure relates to SiC substrates, SiC epitaxial wafers, SiC devices, methods for manufacturing SiC substrates, methods for manufacturing SiC epitaxial wafers, and methods for manufacturing SiC devices. 【0002】 Silicon carbide (SiC) has a breakdown electric field one order of magnitude larger and a bandgap three times larger than that of silicon (Si). In addition, silicon carbide (SiC) has properties such as a thermal conductivity about three times higher than that of silicon (Si). Therefore, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, etc. In addition, devices using silicon carbide (SiC) can operate in a high temperature range of 150°C or higher. In recent years, SiC epitaxial wafers have been used for semiconductor devices as described above. 【0003】 A semiconductor device using SiC is referred to as a SiC device. A SiC device is manufactured using a SiC epitaxial wafer. A SiC epitaxial wafer is obtained by laminating a SiC epitaxial layer on the surface of a SiC substrate. A SiC substrate is a substrate before a SiC epitaxial layer is laminated. A SiC substrate is cut out from, for example, a SiC ingot (also referred to as a SiC boule). A SiC ingot is a SiC single crystal processed into a cylindrical shape. 【0004】 In recent years, there has been a study on manufacturing a single composite substrate by bonding a plurality of substrates. For example, Patent Document 1 discloses a composite substrate in which a first silicon carbide layer and a second silicon carbide layer having a higher defect density than the first silicon carbide layer are joined. 【0005】 Japanese Unexamined Patent Application Publication No. 2023-9025 【0006】Various processing steps are involved in fabricating semiconductor devices from SiC substrates. SiC substrates can warp during these processing steps. Examples of processing steps that can cause SiC substrate warping include epitaxial layer deposition, surface polishing, oxide film formation, and ion implantation. Warped wafers negatively impact the semiconductor device fabrication process. For example, warped wafers are difficult to focus on during photolithography. Furthermore, warped wafers may come into contact with equipment walls or other parts during the transport process and be damaged. 【0007】 Because composite substrates are made by bonding different substrates together, they are more prone to warping than single substrates. 【0008】 This disclosure has been made in view of the above-mentioned problems and aims to provide a SiC substrate, a SiC epitaxial wafer, a SiC device, a method for manufacturing a SiC substrate, a method for manufacturing a SiC epitaxial wafer, and a method for manufacturing a SiC device, all of which exhibit minimal warping. 【0009】 The inventors, after diligent research, have found that by considering the orientation of the surface polarity of each single crystal substrate to be bonded, a SiC substrate with minimal warping can be obtained. 【0010】 This disclosure provides the following means to solve the above problems. 【0011】 (1) The SiC substrate according to the first embodiment comprises a first main surface, a second main surface, and a bonding layer. The first main surface faces the second main surface. Both the first and second main surfaces are either Si surfaces or C surfaces. The bonding layer is located between the first and second main surfaces. The bonding layer contains a silicon-carbon compound. 【0012】 (2) In the SiC substrate according to the above embodiment, the bonding layer may contain argon. 【0013】 (3) In the SiC substrate according to the above embodiment, the bonding layer may be amorphous. 【0014】(4) In the SiC substrate according to the above embodiment, the bonding layer may be in a range shifted in the thickness direction from the first main surface by a thickness of 30% to 70% of the total thickness. 【0015】 (5) In the SiC substrate according to the above embodiment, 70% or more of the facets of the first main surface may overlap with the facets of the second main surface when viewed from the thickness direction. 【0016】 (6) The SiC substrate according to the above embodiment may have a diameter of 145 mm or more. 【0017】 (7) The SiC substrate according to the above embodiment may have a total thickness of 100 μm or more and 1000 μm or less. 【0018】 (8) The SiC substrate according to the above embodiment may have a BOW absolute value of 30 μm or less. 【0019】 (9) The SiC substrate according to the above embodiment may have a warp of 50 μm or less. 【0020】 (10) The SiC substrate according to the above embodiment may have a first single crystal layer and a second single crystal layer. Both the first single crystal layer and the second single crystal layer are single crystals of SiC. The junction layer may be located between the first single crystal layer and the second single crystal layer. 【0021】 (11) A SiC epitaxial wafer according to a second embodiment comprises a SiC substrate and a SiC epitaxial layer. The SiC epitaxial layer is laminated on the first main surface or the second main surface. 【0022】 (12) The SiC epitaxial wafer according to the above embodiment may have a BOW absolute value of 40 μm or less. 【0023】 (13) The SiC epitaxial wafer according to the above embodiment may have a warp of 60 μm or less. 【0024】(14) A third embodiment of the SiC device comprises a SiC substrate, a SiC epitaxial layer, and an element. The SiC substrate has a first main surface and a second main surface, both of which are Si surfaces or C surfaces, and the SiC substrate has a bonding layer containing a silicon-carbon compound between the first main surface and the second main surface. The SiC epitaxial layer is laminated on the SiC substrate. The element is formed on the SiC epitaxial layer. 【0025】 (15) In the method for manufacturing a SiC substrate according to the fourth embodiment, a first SiC single crystal substrate and a second SiC single crystal substrate are prepared, and the first single crystal substrate and the second single crystal substrate are directly pressed together such that the Si faces face each other or the C faces face each other. 【0026】 (16) In the method for manufacturing a SiC substrate according to the above embodiment, the first single crystal substrate and the second single crystal substrate may be substrates obtained from the same ingot. 【0027】 (17) In the method for manufacturing a SiC substrate according to the above embodiment, the first single crystal substrate and the second single crystal substrate may be adjacent substrates obtained from the same ingot. 【0028】 (18) In the method for manufacturing a SiC epitaxial wafer according to the fifth embodiment, a SiC substrate according to the above embodiment is prepared, and a SiC epitaxial layer is formed on the first main surface or the second main surface of the SiC substrate. 【0029】 (19) In a method for manufacturing a SiC device according to the sixth embodiment, a SiC epitaxial wafer according to the above embodiment is prepared, an element is formed on the SiC epitaxial layer of the SiC epitaxial wafer, and the SiC epitaxial wafer containing the element is formed into a chip. 【0030】 The SiC substrate, SiC epitaxial wafer, and SiC device according to this disclosure exhibit minimal warping. Furthermore, the methods for manufacturing the SiC substrate, SiC epitaxial wafer, and SiC device according to this disclosure can produce SiC substrates, SiC epitaxial wafers, and SiC devices with minimal warping. 【0031】This is a cross-sectional view of the SiC substrate according to this embodiment. This is a plan view of the SiC substrate according to this embodiment. This is a schematic diagram illustrating a method for evaluating the shape (deformation) of a wafer using Warp. This is a schematic diagram illustrating a method for evaluating the shape (deformation) of a wafer using Bow. This is a schematic diagram showing a manufacturing method for the SiC substrate according to this embodiment. This is a cross-sectional view of the SiC epitaxial wafer according to this embodiment. This is a cross-sectional view of the SiC device according to this embodiment. 【0032】 This embodiment will now be described in detail with reference to the drawings as appropriate. The drawings used in the following description may be enlarged for convenience to clearly illustrate the features of this embodiment, and the dimensional ratios of each component may differ from those of the actual components. The materials, dimensions, etc., exemplified in the following description are examples only, and this disclosure is not limited to them. It is possible to modify and implement these examples as appropriate without altering the essence of the invention. 【0033】 In this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. While crystallography dictates that negative exponents are represented by a "-" (bar) above the number, in this specification, the negative sign is placed before the number. 【0034】 First, let's define the directions. The thickness direction of the SiC substrate 1 is defined as the Z direction. The Z direction may be the <0001> direction of the SiC substrate 1, or it may be tilted by an offset angle relative to the <0001> direction. One direction on the plane perpendicular to the Z direction is defined as the X direction. On the plane perpendicular to the Z direction, the direction perpendicular to the X direction is defined as the Y direction. The X direction is, for example, the <11-20> direction of the SiC substrate 1. The Y direction is, for example, the <1-100> direction of the SiC substrate 1. 【0035】 "SiC Substrate" Figure 1 is a cross-sectional view of the SiC substrate 1 according to this embodiment. The SiC substrate 1 has a first main surface 1A and a second main surface 1B. The first main surface 1A and the second main surface 1B are surfaces perpendicular to the Z direction. The first main surface 1A faces the second main surface 1B. 【0036】The first main surface 1A and the second main surface 1B may or may not have an offset angle with respect to the (0001) plane in the <11-20> direction. It is preferable that the first main surface 1A and the second main surface 1B have an offset angle in the <11-20> direction, for example. The offset angle is, for example, greater than 0° and 10° or less, preferably 0.1° or more and 8° or less, more preferably 3.5° or more and 4.5° or less, and even more preferably 4°. The first main surface 1A and the second main surface 1B do not have to have an offset angle with respect to the (0001) plane in the <1-100> direction. 【0037】 The offset angle of the first main surface 1A may be the same as or different from the offset angle of the second main surface 1B. 【0038】 In the <11-20> direction, the absolute value of the difference between the offset angle of the first main surface 1A and the offset angle of the second main surface 1B is preferably less than 1.0°, and more preferably 0.5° or less. When the difference in the offset angle between the first main surface 1A and the second main surface 1B is small, a SiC substrate 1 that is less prone to warping even after processing can be obtained. 【0039】 In the <1-100> direction, the absolute value of the difference between the offset angle of the first main surface 1A and the offset angle of the second main surface 1B is preferably 0.5° or less, and more preferably 0.2° or less. When the difference in the offset angle between the first main surface 1A and the second main surface 1B is small, a SiC substrate 1 that is less prone to warping even after processing can be obtained. 【0040】 The first principal surface 1A and the second principal surface 1B have the same planar polarity. Planar polarity is determined by the elements exposed on the surface, and there are Si faces and C faces. For example, both the first principal surface 1A and the second principal surface 1B are Si faces. For example, both the first principal surface 1A and the second principal surface 1B may be C faces. 【0041】 The Si plane is a (0001) crystal plane. Furthermore, a plane tilted by an offset angle with respect to the (0001) crystal plane is also generally referred to as a Si plane. In this embodiment, a plane tilted by an offset angle with respect to the (0001) crystal plane is one form of the Si plane. 【0042】The C plane is the (000-1) crystal plane. Also, a plane inclined by an offset angle with respect to the (000-1) crystal plane is generally also denoted as the C plane. In this embodiment as well, a plane inclined by an offset angle with respect to the (000-1) crystal plane is an aspect of the Ci plane. 【0043】 The surface polarity of the first main surface 1A or the second main surface 1B can be determined by performing microscopic Raman spectroscopy measurement using extreme ultraviolet light. For example, excitation light is irradiated onto the first main surface 1A or the second main surface 1B, and the Raman scattered light spectrum from the first main surface 1A or the second main surface 1B is measured in a backscattering measurement arrangement. The amplitude of atomic vibration differs depending on whether the surface is a heavy Si atom or a light C atom, and the difference in that amplitude can be detected as a difference in the intensity of the Raman scattered light. Also, although it is a destructive inspection, the Si surface and the C surface can also be discriminated by observing the difference in the shape of the etch pits and the etching rate of each surface with KOH or the like. 【0044】 The SiC substrate 1 has a bonding layer 13 inside. The bonding layer 13 is between the first main surface 1A and the second main surface 1B in the Z direction. The bonding layer 13 spreads in the XY plane. 【0045】 The bonding layer 13 is, for example, between the first single crystal layer 11 and the second single crystal layer 12. The bonding layer 13 is, for example, a layer formed when the first single crystal layer 11 and the second single crystal layer 12 are bonded together. The SiC substrate 1 is, for example, a composite substrate in which the first single crystal layer 11 and the second single crystal layer 12 are bonded together. The SiC substrate 1 has, for example, the first single crystal layer 11, the second single crystal layer 12, and the bonding layer 13 that connects the first single crystal layer 11 and the second single crystal layer 12. 【0046】 The bonding layer 13 contains, for example, an inorganic compound. The bonding layer 13 contains, for example, a compound of silicon and carbon. The bonding layer 13 mainly contains, for example, a compound of silicon and carbon. For example, 90 atom% or more of the bonding layer 13 is a compound of silicon and carbon. 【0047】 When the bonding layer 13 is an organic substance, in post-processes such as film formation of an epitaxial layer and device formation, the organic substance causes contamination and warping. When the bonding layer 13 is the said compound, the bonding layer 13 is less likely to have an adverse effect on post-processes. 【0048】 The bonding layer 13 can be confirmed, for example, by a transmission electron microscope (TEM), X-ray photoelectron spectroscopy (XPS), or the like. The atomic arrangement of the bonding layer 13 is disordered compared to the first single crystal layer 11 and the second single crystal layer 12. The bonding layer 13 may be, for example, amorphous. The bonding layer 13 may contain, for example, amorphous SiC. The bonding layer 13 can be identified by, for example, confirming the atomic arrangement in a transmission electron microscope image or the atomic bonding state measured by X-ray photoelectron spectroscopy. 【0049】 Further, the bonding layer 13 may contain, for example, argon. Argon is included, for example, when the first single crystal layer 11 and the second single crystal layer 12 are bonded together. The presence or absence of argon in the bonding layer 13 can be identified by secondary ion mass spectrometry (SIMS). The presence or absence of the bonding layer 13 can be identified by performing depth analysis in the Z direction from the first main surface 1A or the second main surface 1B. 【0050】 The thickness of the bonding layer 13 is, for example, 0.5 nm or more and 10 nm or less. The thickness of the bonding layer 13 is measured by a transmission electron microscope (TEM). 【0051】 The bonding layer 13 is located between the first main surface 1A and the second main surface 1B in the Z direction. The bonding layer 13 is, for example, in a range shifted by a thickness of 30% or more and 70% or less of the total thickness t of the SiC substrate 1 in the Z direction from the first main surface 1A. Preferably, the bonding layer 13 is in a range shifted by a thickness of 40% or more and 60% or less of the total thickness t in the Z direction from the first main surface 1A, and more preferably in a range shifted by a thickness of 45% or more and 55% or less of the total thickness t. 【0052】 The total thickness t of the SiC substrate 1 is, for example, 100 μm or more and 1000 μm or less. Preferably, the total thickness t of the SiC substrate 1 is 200 μm or more and 800 μm or less, and more preferably 300 μm or more and 600 μm or less. The total thickness t of the SiC substrate 1 is the average value obtained by measuring the thicknesses at 10 different points in the plane using a thickness gauge or the like. 【0053】 Both the first single crystal layer 11 and the second single crystal layer 12 are single crystals of SiC. For example, both the first single crystal layer 11 and the second single crystal layer 12 are single crystals of hexagonal SiC. 【0054】 The first single crystal layer 11 has a first main surface 11A and a second main surface 11B. The first main surface 11A is the same as the first main surface 1A of the SiC substrate 1. The first main surface 11A is, for example, a Si surface or a C surface. The second main surface 11B has a different surface polarity from the first main surface 11A. For example, if the first main surface 11A is a Si surface, the second main surface 11B is a C surface, and if the first main surface 11A is a C surface, the second main surface 11B is a Si surface. 【0055】 The second single crystal layer 12 has a first main surface 12A and a second main surface 12B. The second main surface 12B coincides with the second main surface 1B of the SiC substrate 1. The first main surface 12A is, for example, a Si surface or a C surface. The second main surface 12B has a different planar polarity from the first main surface 12A. For example, if the first main surface 12A is a Si surface, the second main surface 12B is a C surface, and if the first main surface 12A is a C surface, the second main surface 12B is a Si surface. The second main surface 12B has the same planar polarity as the second main surface 11B of the first single crystal layer 11. 【0056】 The thickness of the first single crystal layer 11 is preferably 30% to 70% of the thickness of the second single crystal layer 12, preferably 40% to 60%, and preferably 45% to 55%. When the difference in thickness between the first single crystal layer 11 and the second single crystal layer 12 is small, internal stress is less likely to occur in the SiC substrate 1, and the warping of the SiC substrate 1 is reduced. 【0057】 The film thickness of the second single crystal layer 12 is measured by Fourier transform infrared spectroscopy (FTIR), secondary ion mass spectrometry (SIMS), etc. FTIR is a method that irradiates the sample with infrared light and calculates the film thickness from the reflection spectrum, but measurement may be difficult when the film thickness is less than a few μm. SIMS is a destructive test, but it can measure thickness profiles on the order of nanometers. If the thickness of the second single crystal layer 12 exceeds 10 μm, the resolution decreases, so the sample may be cut at an angle and the line profile of the exposed cut surface may be measured. The film thickness of the first single crystal layer 11 can be calculated by subtracting the film thickness of the second single crystal layer 12 from the total thickness t of the SiC substrate 1. The thickness of the bonding layer 13 is sufficiently thin compared to the film thicknesses of the first single crystal layer 11 and the second single crystal layer 12, so it can be ignored. 【0058】 Figure 2 is a plan view of the SiC substrate 1 according to this embodiment. The plan view shape of the SiC substrate 1 is approximately circular. 【0059】 The SiC substrate 1 may have a notch n for determining the direction of the crystal axis when viewed from the Z direction. The notch n is a groove formed by cutting out a part of the SiC substrate 1 from the outer circumference inward. The SiC substrate 1 may have an orientation flat instead of a notch n. The position of the notch n may differ between the first main surface 1A side and the second main surface 1B side. The notch n may be introduced into the SiC substrate 1 after bonding. 【0060】 The diameter of the SiC substrate 1 is, for example, 6 inches or more, preferably 8 inches or more, more preferably 10 inches or more, and even more preferably 12 inches or more. 【0061】 The diameter of the SiC substrate 1 is, for example, 145 mm or more, preferably 149 mm or more. The diameter of the SiC substrate 1 is, for example, 155 mm or less, preferably 151 mm or less. The diameter of the SiC substrate 1 is, for example, 195 mm or more, preferably 199 mm or more. The diameter of the SiC substrate 1 is, for example, 205 mm or less, preferably 201 mm or less. The diameter of the SiC substrate 1 is, for example, 245 mm or more, preferably 249 mm or more. The diameter of the SiC substrate 1 is, for example, 255 mm or less, preferably 251 mm or less. The diameter of the SiC substrate 1 is, for example, 295 mm or more, preferably 299 mm or more. The diameter of the SiC substrate 1 is, for example, 305 mm or less, preferably 301 mm or less. 【0062】When the SiC substrate 1 is viewed from the Z direction in a plan view, facet F1 may be observed on the first main surface 1A and facet F2 on the second main surface 1B. Facets are regions that grow parallel to the c-plane during crystal growth of a SiC ingot. Facets have a different crystal growth pattern and different properties from regions that have grown using step flow (hereinafter referred to as step flow regions). For example, facets readily incorporate nitrogen and have lower resistance than step flow regions. Facets can be visually confirmed and have a different color from the surrounding step flow regions. Facets are often darker in color than the surrounding step flow regions. 【0063】 When viewed from the Z direction, it is preferable that 70% or more of the facets F1 of the first main surface 1A overlap with the facets F2 of the second main surface 1B. When viewed from the Z direction, it is preferable that 80% or more of the facets F1 of the first main surface 1A overlap with the facets F2 of the second main surface 1B, and it is preferable that 90% or more overlap with the facets F2 of the second main surface 1B. 【0064】 When the positions of facet F1 and facet F2 overlap, the design of the device when fabricating the SiC substrate 1 becomes easier. SiC devices operate when a voltage is applied in the Z direction. Facets and step flow regions have different resistivity. When regions with different resistivity overlap in the Z direction, the resistivity variation of the SiC device increases, making the design of the SiC device difficult. By aligning the positions of facet F1 and facet F2 in the XY plane, the resistivity variation in the Z direction can be reduced. 【0065】 The SiC substrate 1 preferably has a BOW absolute value of 30 μm or less, more preferably 20 μm or less, even more preferably 13 μm or less, and particularly preferably 10 μm or less. 【0066】Figure 3 schematically illustrates the method for evaluating the shape (deformation) of wafer W using Bow. The evaluation method for Bow is the same whether wafer W is a SiC substrate 1 or a SiC epitaxial wafer, as described later. Bow is the position in the height direction of the center c of wafer W with respect to the reference plane Sr. In other words, Bow is the signed distance of the center c of wafer W from the reference plane Sr. The reference plane Sr is the plane that connects the points sp that overlap with each of the multiple supports when viewed from the thickness direction of the first plane Wa. The multiple supports are, for example, positioned to overlap with the circumference 7.5 mm inward from the outer edge of wafer W. For example, wafer W is supported by three supports. Each of the three supports is positioned symmetrically three times with respect to the center of the wafer W that the support is supporting as the central axis. The reference plane Sr is, for example, a three-point reference plane. The larger the absolute value of Bow, the more the wafer W is judged to be deformed. First, the wafer W is placed on three support points on a flat surface F. The reference plane Sr is determined by connecting three points sp on the first surface Wa that lie on the support points when viewed from the thickness direction. The reference plane Sr is then defined as 0, the direction away from the flat surface F relative to the reference plane Sr is defined as +, and the direction towards the flat surface F relative to the reference plane Sr is defined as -. Bow is determined as the height position of the center c of the first surface Wa relative to the reference plane Sr. In other words, Bow is determined as the signed distance of the center c of the first surface Wa from the reference plane Sr. 【0067】 The SiC substrate 1 preferably has a warp of 50 μm or less, more preferably 40 μm or less, even more preferably 30 μm or less, and particularly preferably 22 μm or less. 【0068】Figure 4 schematically illustrates the method for evaluating the shape (deformation) of wafer W using Warp. The method for evaluating Warp is the same whether wafer W is a SiC substrate 1 or a SiC epitaxial wafer, which will be described later. Warp is the distance in the thickness direction between the highest point hp and the lowest point lp of the first surface Wa. The larger the Warp, the more deformed the wafer W is judged to be. First, wafer W is placed on three support points set on a flat surface F. A virtual surface Slp is determined that passes through the lowest point lp on the first surface Wa and is parallel to the flat surface F, and a virtual surface Shp is determined that passes through the highest point hp on the first surface Wa and is parallel to the flat surface F. Warp is determined as the distance in the height direction between the virtual surface Slp and the virtual surface Shp. The height direction is perpendicular to the flat surface F and away from the flat surface F. 【0069】 Next, a method for manufacturing the SiC substrate 1 according to this embodiment will be described. The method for manufacturing the SiC substrate 1 according to this embodiment includes, for example, a preparation step, a bonding step, and a thin-film formation step. Figure 5 is a schematic diagram illustrating the method for manufacturing the SiC substrate 1 according to this embodiment. 【0070】 In the preparation step, first, a first single-crystal substrate 91 and a second single-crystal substrate 92 are prepared. The first single-crystal substrate 91 and the second single-crystal substrate 92 may be obtained from the same SiC ingot, or they may be obtained from different SiC ingots. For example, the first single-crystal substrate 91 and the second single-crystal substrate 92 may be adjacent substrates obtained from the same SiC ingot. 【0071】 SiC ingots generate internal stress during crystal growth, and this internal stress causes warping of substrates obtained from SiC ingots. Therefore, SiC ingots often warp in the same direction. This tendency is particularly strong in adjacent substrates from the same ingot. If the first single-crystal substrate 91 and the second single-crystal substrate 92 warp in the same direction when obtained, their respective warping can be mitigated when they are bonded together with matching surface polarity, thereby reducing the warping of the SiC substrate 1 after bonding. 【0072】In the bonding process, the first single-crystal substrate 91 and the second single-crystal substrate 92 are directly pressed together. A bonding layer 13 is formed when the first single-crystal substrate 91 and the second single-crystal substrate 92 are pressed together. The pressing is performed by applying a load to the two substrates in a high vacuum. The vacuum level of the pressing environment is, for example, 1 × 10⁻⁶ －５ The pressure is less than or equal to Pa, and the load during crimping is, for example, 0.1 MPa or more. 【0073】 When bonding the first single crystal substrate 91 and the second single crystal substrate 92, at least one of the bonding surfaces of the first single crystal substrate 91 and the second single crystal substrate 92 is activated. Activation can be performed, for example, by irradiating the bonding surface with argon. The argon is irradiated onto the bonding surface by reverse sputtering, for example. The argon irradiated at this time is incorporated into the bonding layer 13. 【0074】 The first single crystal substrate 91 has a first main surface 91A and a second main surface 91B, with the second main surface 91B being the bonding surface. The second single crystal substrate 92 has a first main surface 92A and a second main surface 92B, with the first main surface 92A being the bonding surface. The first main surface 91A and the second main surface 92B have the same surface polarity, and the second main surface 91B and the first main surface 92A have the same surface polarity. For example, if the first main surface 91A and the second main surface 92B are Si surfaces, then the second main surface 91B and the first main surface 92A are C surfaces. For example, if the first main surface 91A and the second main surface 92B are C surfaces, then the second main surface 91B and the first main surface 92A are Si surfaces. The bonding surfaces of the first single crystal substrate 91 and the bonding surfaces of the second single crystal substrate 92 face each other either as Si surfaces or as C surfaces. 【0075】 It is preferable to select first single crystal substrates 91 and second single crystal substrates 92 that are curved in the same direction when their Si surfaces are placed on a flat surface. For example, if the first main surface 91A of the first single crystal substrate 91 is the Si surface, then the second main surface 92B of the second single crystal substrate 92 will be the Si surface. 【0076】For example, when the first single crystal substrate 91 is placed on a flat surface with each Si surface facing the flat side, if the outer edge of the first single crystal substrate 91 is warped so that it lifts up relative to the center, then the second single crystal substrate 92 should also be selected so that its outer edge lifts up relative to the center. 【0077】 When the first single-crystal substrate 91 and the second single-crystal substrate 92 are obtained from the same SiC ingot, the direction of warping of each substrate often satisfies this tendency. When the first single-crystal substrate 91 and the second single-crystal substrate 92 are obtained from adjacent substrates of the same SiC ingot, the direction of warping of each substrate is even more likely to satisfy this tendency. 【0078】 Furthermore, if both the first single crystal substrate 91 and the second single crystal substrate 92 have facets, it is preferable to bond them together so that the facets overlap in the Z direction. For example, when flipping the second single crystal substrate 92 over so that the bonding surfaces of the first single crystal substrate 91 and the second single crystal substrate 92 have the same planar polarity, reversing it with the <11-20> direction (also called the offset direction) as the axis will cause the facets of the first single crystal substrate 91 and the facets of the second single crystal substrate 92 to overlap. 【0079】 The surface roughness Ra of the bonding surface between the first single crystal substrate 91 and the second single crystal substrate 92 is preferably 1 nm or less. A low surface roughness of the bonding surface can increase the bonding strength of the bonded surface after bonding. 【0080】In the thinning process, the bonded substrates are thinned until the total thickness reaches the desired thickness. Thinning can be performed, for example, by grinding or polishing both sides of the bonded substrates. The polarity of the first main surface 1A and the second main surface 1B does not change even after thinning. The first single crystal substrate 91 becomes the first single crystal layer 11, and the second single crystal substrate 92 becomes the second single crystal layer 12. If the first single crystal substrate 91 and the second single crystal substrate 92 are sufficiently thin to the required specifications, the thinning process does not need to be performed. In this case, at the time of bonding, the first single crystal substrate 91 becomes the first single crystal layer 11, and the second single crystal substrate 92 becomes the second single crystal layer 12. 【0081】 The SiC substrate 1 according to this embodiment can be obtained by following the procedure described above. 【0082】 The SiC substrate 1 according to this embodiment is less prone to warping because the first main surface 1A and the second main surface 1B have the same surface polarity. The Si surface and the C surface have different properties, for example, different surface roughness. If the surface roughness of the first main surface 1A and the second main surface 1B are different, the SiC substrate will warp due to the Twyman effect, but if the first main surface 1A and the second main surface 1B have the same surface polarity, the Twyman effect is less likely to occur. 【0083】 A SiC substrate 1 with minimal warping is less prone to problems in post-processing when manufacturing SiC devices. Post-processing problems include, for example, transport errors caused by the substrate coming into contact with the equipment during transport, and a decrease in focus during device processing. Therefore, the SiC substrate 1 according to this embodiment is less prone to problems during device manufacturing, thereby improving the yield of SiC devices. 【0084】 "SiC Epitaxial Wafer" Figure 6 is a cross-sectional view of the SiC epitaxial wafer 2 according to this embodiment. The SiC epitaxial wafer 2 comprises a SiC substrate 1 and a SiC epitaxial layer 21. The SiC epitaxial wafer 2 is formed by depositing the SiC epitaxial layer 21 on a SiC substrate in which the first main surface 1A and the second main surface 1B have the same planar polarity. 【0085】The SiC substrate 1 is as described above. The SiC substrate 1 may not have a bonding layer 13, or the bonding layer 13 may not be visible. The bonding layer 13 of the SiC substrate 1 may also be an organic material such as an adhesive. 【0086】 The SiC epitaxial layer 21 is formed on the first main surface 1A or the second main surface 1B of the SiC substrate 1. The SiC epitaxial layer 21 may be undoped SiC or dopant-doped SiC. For example, nitrogen-doped n-type SiC is preferred for the SiC epitaxial layer 21. 【0087】 The thickness of the SiC epitaxial layer 21 is, for example, 3 μm or more, preferably 5 μm or more, more preferably 10 μm or more, and even more preferably 15 μm or more. The thickness of the SiC epitaxial layer 21 may also be, for example, 200 μm or less. 【0088】 The thickness of the SiC epitaxial layer 21 is the average value of the thickness of the SiC epitaxial layer 21 measured at different points in the radial direction of the SiC epitaxial layer 21. For example, the thickness of the SiC epitaxial layer 21 is the average thickness in the radial direction measured along a straight line extending in the <11-20> direction. The thickness is measured, for example, at the center and at multiple measurement points arranged at 10 mm intervals from the center. The intervals between the multiple measurement points may be 15 mm, 20 mm, 25 mm, or 30 mm. 【0089】The thickness of the SiC epitaxial layer 21 can be determined, for example, by optical interference analysis using FTIR (Fourier transform infrared spectrophotometer). FTIR is a method that irradiates a sample with infrared light and calculates the thickness from the reflection spectrum, but measurement can be difficult when the thickness is less than a few micrometers. In this case, it may be possible to measure it using secondary ion mass spectrometry (SIMS). SIMS is a destructive test, but it measures the thickness of the SiC epitaxial layer 21 by measuring the thickness direction profile on the order of nanometers. If the total thickness of the second single crystal layer 12 and the SiC epitaxial layer 21 exceeds 10 μm, the resolution decreases, so the sample may be cut at an angle and the line profile of the exposed cut surface may be measured. 【0090】 The SiC epitaxial wafer 2 preferably has a BOW absolute value of 40 μm or less, more preferably 31 μm or less, even more preferably 21 μm or less, and particularly preferably 10 μm or less. 【0091】 The SiC epitaxial wafer 2 preferably has a warp of 60 μm or less, more preferably 51 μm or less, even more preferably 40 μm or less, and particularly preferably 32 μm or less. 【0092】 A SiC epitaxial wafer 2 can be fabricated by depositing a SiC epitaxial layer 21 onto a SiC substrate 1. The SiC epitaxial layer 21 can be deposited using a known method. The SiC substrate 1 may be fabricated by the above method or may be prepared (obtained) separately. 【0093】 The SiC epitaxial wafer 2 according to this embodiment has a SiC substrate 1 in which the first main surface 1A and the second main surface 1B have the same planar polarity, making it less prone to warping. A SiC epitaxial wafer 2 that is less prone to warping is less likely to cause defects during device manufacturing and improves the yield of devices. 【0094】"SiC Device" Figure 7 is a cross-sectional view of the SiC device 3 according to this embodiment. The SiC device 3 is formed by creating a chip from the SiC epitaxial wafer 2 by forming an element 31 on the SiC epitaxial layer 21 of the SiC epitaxial wafer 2. 【0095】 The SiC device 3 includes, for example, a SiC substrate 1', a SiC epitaxial layer 25, and an element 31. 【0096】 SiC substrate 1' is a chip formed from SiC substrate 1. The first single crystal layer 15 corresponds to the first single crystal layer 11, the second single crystal layer 16 corresponds to the second single crystal layer 12, and the bonding layer 17 corresponds to the bonding layer 13. SiC substrate 1' may not have a bonding layer 13, or the bonding layer 13 may not be visible. The bonding layer 13 of SiC substrate 1 may also be an organic material such as an adhesive. 【0097】 The SiC epitaxial layer 25 is a chip-formed version of the SiC epitaxial layer 21 described above. The SiC epitaxial layer 25 is equivalent to the SiC epitaxial layer 21, except that it is chip-formed. 【0098】 The element 31 is formed on the SiC epitaxial layer 25. The element is a combination of, for example, a transistor, capacitor, inductor, resistor, wiring, etc. Figure 7 shows a transistor as an example of the element 31. If the surface polarity of the first main surface 1'A and the second main surface 1'B of the SiC substrate 1' is the same, there will be no difference in the ease of forming the element 31 on the first main surface 1'A and the second main surface 1'B, and peeling of electrodes, etc. will be less likely to occur. 【0099】 The SiC device 3 can be fabricated, for example, by performing a device formation process, a slimming process, and a chip manufacturing process. 【0100】 In the device formation process, the device 31 is formed on the SiC epitaxial layer 21 of the SiC epitaxial wafer 2. The device 31 can be formed by a known method. The SiC epitaxial wafer 2 may be one that was manufactured using the procedure described above, or it may be one that was prepared (obtained) separately. 【0101】In the slimming process, at least a portion of the first single crystal layer 11 of the SiC substrate 1 is removed. By reducing the thickness of the first single crystal layer 11, the resistivity of the SiC substrate 1 can be lowered. 【0102】 In the chipping process, the SiC epitaxial wafer 2 is chipped for each element 31. By chipping, multiple SiC devices 3 can be obtained from the SiC epitaxial wafer 2. 【0103】 Since the SiC device 3 according to this embodiment is manufactured using a SiC epitaxial wafer 2 that is less prone to warping, defects are less likely to occur during manufacturing. In addition, because the polarity of the surfaces on which electrodes are fabricated is the same, defects such as electrode peeling can be suppressed. 【0104】 While preferred embodiments of this disclosure have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the gist of this disclosure as described in the claims. 【0105】 "Example 1" A first single crystal substrate made of hexagonal SiC with a diameter of 200 mm (8 inches) and a thickness of 350 μm was prepared. When the warp of the first single crystal substrate was measured with the Si surface facing upwards, the Bow was -22 μm and the Warp was 54 μm. 【0106】 A second single-crystal substrate made of hexagonal SiC with a diameter of 200 mm (8 inches) and a thickness of 350 μm was prepared. The second single-crystal substrate was obtained from the same SiC ingot as the first single-crystal substrate, and the first and second single-crystal substrates were located adjacent to each other in the SiC ingot. When the warp of the second single-crystal substrate was measured with the Si surface facing upwards, the Bow was -20 μm and the Warp was 50 μm. 【0107】 Next, the first single-crystal substrate and the second single-crystal substrate were bonded together so that the C-planes were facing each other, and both sides were polished until the total thickness reached 350 μm to produce a SiC substrate. When the cross-section of the polished SiC substrate was examined with a transmission electron microscope, an amorphous bonding layer containing Si and C was confirmed. Furthermore, micro-Raman spectroscopy measurements using extreme ultraviolet light were performed on both main surfaces after polishing, and it was confirmed that both were Si surfaces. 【0108】 Next, the warp of the SiC substrate was measured with the second single crystal substrate facing upwards, and the Bow was -11 μm and the Warp was 22 μm. 【0109】 Next, a 10 μm thick SiC epitaxial layer was deposited on a second single-crystal substrate of the SiC substrate. When the warp of the SiC epitaxial wafer was measured with the second single-crystal substrate facing upwards, the Bow was -8 μm and the Warp was 32 μm. 【0110】 "Example 2" Example 2 differs from Example 1 in that the first single crystal substrate and the second single crystal substrate were bonded together so that the Si surfaces were facing each other. Other conditions were the same as in Example 1, and the same evaluation was performed as in Example 1. 【0111】 "Examples 3 and 4" Examples 3 and 4 differ from Examples 1 and 2 in that the first and second single-crystal substrates were obtained from separate ingots. Other conditions were the same as in Example 1, and the same evaluation was performed as in Example 1. In Examples 3 and 4, when the Si surface was placed on a flat surface, those that were curved in the same direction were selected as the first and second single-crystal substrates. 【0112】 "Comparative Examples 1 and 2" Comparative Examples 1 and 2 differ from Examples 1 and 2 in that the surface polarity of the bonding surfaces of the first single crystal substrate and the second single crystal substrate are different. In Comparative Example 1, the Si surface of the first single crystal substrate was bonded to the C surface of the second single crystal substrate. In Comparative Example 2, the C surface of the first single crystal substrate was bonded to the Si surface of the second single crystal substrate. Other conditions were the same as in Example 1, and the same evaluation was performed as in Example 1. 【0113】 "Comparative Examples 3 and 4" Comparative Examples 3 and 4 differ from Examples 3 and 4 in that the surface polarity of the bonding surfaces of the first single crystal substrate and the second single crystal substrate are different. In Comparative Example 3, the Si surface of the first single crystal substrate was bonded to the C surface of the second single crystal substrate. In Comparative Example 2, the C surface of the first single crystal substrate was bonded to the Si surface of the second single crystal substrate. Other conditions were the same as in Example 1, and the same evaluation was performed as in Example 1. 【0114】 The results of Examples 1-4 and Comparative Examples 1-4 are summarized in Table 1 below. 【0115】 【0116】 Comparing each of Examples 1-4 with each of Comparative Examples 1-4, the Bow and Warp of the wafers were smaller. 【0117】 1, 1' SiC substrate 1A, 1'A, 11A, 12A, 91A, 92A First main surface 1B, 1'B, 11B, 12B, 91B, 92B Second main surface 2 SiC epitaxial wafer 3 SiC device 11, 15 First single crystal layer 12, 16 Second single crystal layer 13, 17 Bonding layer 21, 25 SiC epitaxial layer 31 Device 91 First single crystal substrate 92 Second single crystal substrate F1, F2 Facet

Claims

1. A SiC substrate comprising a first main surface, a second main surface, and a bonding layer, wherein the first main surface faces the second main surface, both the first and second main surfaces are either Si surfaces or C surfaces, the bonding layer is located between the first and second main surfaces, and the bonding layer contains a compound of silicon and carbon.

2. The SiC substrate according to claim 1, wherein the bonding layer contains argon.

3. The SiC substrate according to claim 1, wherein the bonding layer is amorphous.

4. The SiC substrate according to claim 1, wherein the bonding layer is located in a range shifted from the first main surface in the thickness direction by a thickness of 30% to 70% of the total thickness.

5. The SiC substrate according to claim 1, wherein, when viewed from the thickness direction, 70% or more of the facets of the first main surface overlap with the facets of the second main surface.

6. The SiC substrate according to claim 1, wherein the diameter is 145 mm or more.

7. The SiC substrate according to claim 1, wherein the total thickness is 100 μm or more and 1000 μm or less.

8. The SiC substrate according to claim 1, wherein the absolute value of the BOW is 30 μm or less.

9. The SiC substrate according to claim 1, wherein the warp is 50 μm or less.

10. The SiC substrate according to claim 1, having a first single crystal layer and a second single crystal layer, wherein both the first single crystal layer and the second single crystal layer are single crystals of SiC, and the junction layer is located between the first single crystal layer and the second single crystal layer.

11. A SiC epitaxial wafer comprising the SiC substrate described in claim 1 and a SiC epitaxial layer, wherein the SiC epitaxial layer is laminated on the first main surface or the second main surface.

12. The SiC epitaxial wafer according to claim 11, wherein the absolute value of the BOW is 40 μm or less.

13. The SiC epitaxial wafer according to claim 11, wherein the warp is 60 μm or less.

14. A SiC device comprising a SiC substrate, a SiC epitaxial layer, and an element, wherein the SiC substrate has a first main surface and a second main surface, both of which are either Si surfaces or C surfaces, the SiC substrate has a bonding layer containing a silicon-carbon compound between the first main surface and the second main surface, the SiC epitaxial layer is laminated on the SiC substrate, and the element is formed on the SiC epitaxial layer.

15. A method for manufacturing a SiC substrate, comprising preparing a first SiC single crystal substrate and a second SiC single crystal substrate, and directly pressing the first single crystal substrate and the second single crystal substrate together such that the Si faces face each other or the C faces face each other.

16. The method for manufacturing a SiC substrate according to claim 15, wherein the first single crystal substrate and the second single crystal substrate are substrates obtained from the same ingot.

17. The method for manufacturing a SiC substrate according to claim 15, wherein the first single crystal substrate and the second single crystal substrate are adjacent substrates obtained from the same ingot.

18. A method for manufacturing a SiC epitaxial wafer, comprising preparing a SiC substrate according to claim 1, and forming a SiC epitaxial layer on the first main surface or the second main surface of the SiC substrate.

19. A method for manufacturing a SiC device, comprising: preparing a SiC epitaxial wafer according to claim 11; forming an element on the SiC epitaxial layer of the SiC epitaxial wafer; and forming the SiC epitaxial wafer containing the element into a chip.

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