Semiconductor substrate

Abstract

This semiconductor substrate comprises: a template substrate that includes a base substrate containing a crystal having a different lattice constant than a nitride semiconductor crystal, the template substrate having a growth suppression region, an independent first seed region having a longitudinal direction in a first direction, and an independent second seed region having a longitudinal direction in a second direction different from the first direction; an island-form first nitride semiconductor portion arranged from above the first seed region to above the growth suppression region; and an island-form second nitride semiconductor portion arranged from above the second seed region to above the growth suppression region.

Description

【Technical Field】 【0001】 The present disclosure relates to a semiconductor substrate and the like. 【Background Art】 【0002】 Patent Document 1 discloses a method of forming a GaN-based semiconductor layer on a different substrate (for example, a sapphire substrate) using the ELO (Epitaxial Lateral Overgrowth) method. 【Prior Art Documents】 【Patent Documents】 【0003】 【Patent Document 1】 Japanese Patent Application Laid-Open No. 2013-251304 【Summary of the Invention】 【0004】 The semiconductor substrate according to the present disclosure includes a base substrate including a substrate material that is not a nitride semiconductor, a template substrate including a growth suppression region, an independent first seed region having a first direction as a longitudinal direction, and an independent second seed region having a second direction different from the first direction as a longitudinal direction, an island-shaped first nitride semiconductor portion arranged from above the first seed region to above the growth suppression region, and an island-shaped second nitride semiconductor portion arranged from above the second seed region to above the growth suppression region. 【Brief Description of the Drawings】 【0005】 [Figure 1] It is a plan view showing a configuration example of the semiconductor substrate according to the present embodiment. [Figure 2] It is a plan view showing a partially enlarged view of FIG. 1. [Figure 3A] It is a cross-sectional view showing a configuration example of the semiconductor substrate according to the present embodiment. [Figure 3B] It is a cross-sectional view showing a configuration example of the semiconductor substrate according to the present embodiment. [Figure 3C]This is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to this embodiment. [Figure 4] This is a cross-sectional view showing another example of a semiconductor substrate according to this embodiment. [Figure 5] This is a plan view showing an enlarged portion of Figure 2. [Figure 6] This is a plan view showing another configuration example of a semiconductor substrate according to this embodiment. [Figure 7] This is a plan view showing a magnified portion of Figure 6. [Figure 8] This is a plan view showing another configuration example of a semiconductor substrate according to this embodiment. [Figure 9] This is a plan view showing an enlarged portion of Figure 8. [Figure 10] This is a plan view showing another configuration example of a semiconductor substrate according to this embodiment. [Figure 11] This is a plan view showing an enlarged portion of Figure 10. [Figure 12] This is a plan view showing another configuration example of a semiconductor substrate according to this embodiment. [Figure 13] This is a plan view showing an enlarged portion of Figure 12. [Figure 14] This is a plan view showing another configuration example of a semiconductor substrate according to this embodiment. [Figure 15] This is a plan view showing a magnified portion of Figure 14. [Figure 16] This is a plan view showing an example of the configuration of a template substrate according to this embodiment. [Figure 17] This is a plan view showing a magnified portion of Figure 16. [Figure 18] This is a cross-sectional view showing an example of the configuration of a template substrate according to this embodiment. [Figure 19] This is a cross-sectional view showing an example of the configuration of a template substrate according to this embodiment. [Figure 20] This flowchart shows the method for manufacturing a semiconductor substrate according to this embodiment. [Figure 21] This is a block diagram of a semiconductor substrate manufacturing apparatus according to this embodiment. [Figure 22]It is a schematic diagram showing the configuration of a nitride semiconductor forming apparatus according to this embodiment. [Figure 23] It is a cross-sectional view showing a configuration example of a base substrate. [Figure 24] It is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. [Figure 25] It is a cross-sectional view showing a method for manufacturing a semiconductor element according to Example 2. [Figure 26] It is a plan view showing a method for manufacturing a semiconductor element according to Example 2. [Figure 27] It is a cross-sectional view showing a configuration example of a semiconductor substrate according to this embodiment. 【Mode for Carrying Out the Invention】 【0006】 〔Semiconductor Substrate〕 FIG. 1 is a plan view showing a configuration example of a semiconductor substrate according to this embodiment. FIG. 2 is a plan view showing an enlarged part of FIG. 1. FIGS. 3A to 3C are cross-sectional views showing a configuration example of a semiconductor substrate according to this embodiment. As shown in FIGS. 1, 2, and 3A to 3C, a semiconductor substrate 10 (semiconductor wafer) according to this embodiment includes a base substrate BS containing a substrate material that is not a nitride semiconductor, and a template substrate TS including (i) a growth suppression region SP, (ii) an independent first seed region J1 having a longitudinal direction in a first direction D1, and (iii) an independent second seed region J2 having a longitudinal direction in a second direction D2 different from the first direction D1. The semiconductor substrate 10 further includes an island-shaped first nitride semiconductor portion 8F arranged from above the first seed region J1 to above the growth suppression region SP, and an island-shaped second nitride semiconductor portion 8S arranged from above the second seed region J2 to above the growth suppression region SP. The first and second directions D1 and D2 are, for example, different directions on a plane parallel to the base substrate BS. On this plane, a direction orthogonal to the first direction D1 is Y1, a direction orthogonal to the second direction D2 is Y2, and a normal direction of this plane (the thickness direction of the first and second nitride semiconductor portions 8F and 8S) is Z. 【0007】 In the semiconductor substrate 10, as shown in Figures 3A and 3B, the template substrate TS has a mask pattern 6 on the base substrate BS that has a mask portion 5 and a first opening K1 and a second opening K2, the upper surface of the mask portion 5 is a growth suppression region SP, and the upper surface of the base substrate BS may include a first seed region J1 overlapping with the first opening K1 and a second seed region J2 overlapping with the second opening K2. Hereinafter, the seed region including the first and second seed regions J1 and J2 will be collectively referred to as seed region J, the openings of the mask pattern 6 including the first and second openings K1 and K2 will be collectively referred to as opening K, and the nitride semiconductor portion including the first and second nitride semiconductor portions 8F and 8S will be collectively referred to as nitride semiconductor portion 8. The mask pattern 6 may be a mask layer, and the nitride semiconductor portion 8 may be a nitride semiconductor layer. In the semiconductor substrate 10, the orientation from the base substrate BS to the nitride semiconductor portion 8 is "upward". Viewing an object from a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective views) is sometimes called a "planar view." 【0008】 The nitride semiconductor section 8 includes a nitride semiconductor as its main material. The nitride semiconductor may be a group III-V semiconductor, and can be expressed as, for example, AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1). Specific examples of nitride semiconductors include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. 【0009】 The nitride semiconductor portion 8 may be doped (e.g., n-type including a donor) or undoped. The semiconductor substrate refers to a substrate containing a nitride semiconductor, and the base substrate BS may contain a semiconductor other than a nitride semiconductor (e.g., silicon, silicon carbide, etc.) or a non-semiconductor. The base substrate BS and the mask pattern 6 together are sometimes called the template substrate TS. 【0010】 The first nitride semiconductor portion 8F can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the first seed region J1 (the upper surface of the base substrate BS exposed below the first opening K1). The first direction D1 may be the m-axis direction (<1-100> direction) of the first nitride semiconductor portion 8F. The width direction of the first seed region J1 (direction Y1 perpendicular to the first direction D1) may be the a-axis direction (<11-20> direction) of the first nitride semiconductor portion 8F. The thickness direction Z of the first nitride semiconductor portion 8F may be the c-axis direction ( <0001> Direction is also acceptable. 【0011】 The second nitride semiconductor portion 8S can be formed by the ELO method, starting from the second seed region J2 (the upper surface of the base substrate BS exposed below the first opening K1). The second direction D2 may be the m-axis direction (<1-100> direction) of the second nitride semiconductor portion 8S. The width direction of the second seed region J2 (direction Y2 perpendicular to the second direction D2) may be the a-axis direction (<11-20> direction) of the second nitride semiconductor portion 8S. The thickness direction Z of the second nitride semiconductor portion 8S may be the c-axis direction ( <0001> Direction is also acceptable. 【0012】 Of the nitride semiconductor portion 8 (8F·8S), the portion located above the seed region J becomes a dislocation inheritance region with many through-dislocations, while the portion located above the growth suppression region SP (wing portion on the mask portion 5) becomes a low-defect region YS with a lower through-dislocation density compared to the dislocation inheritance region. 【0013】 As shown in Figures 1 and 2, by making the longitudinal directions of the first and second seed regions J1 and J2 different, the stretching directions of the first and second nitride semiconductor portions 8F and 8S are different, which can reduce the warping of the semiconductor substrate 10 caused by the difference in thermal expansion coefficients of the nitride semiconductor portion 8 and the base substrate BS. The substrate material (non-nitride semiconductor) included in the base substrate BS may have a smaller thermal expansion coefficient than the nitride semiconductor (e.g., GaN). 【0014】 The first and second nitride semiconductor portions 8F and 8S are each hexagonal crystals, and the acute angle between the first direction D1 and the second direction D2 may be 60 degrees. 【0015】 The template substrate TS may have one or more first unit regions A1 in which a plurality of independent seed regions J, including a first seed region J1 and with the first direction D1 as the longitudinal direction, are arranged, and one or more second unit regions A2 in which a plurality of independent seed regions J, including a second seed region J2 and with the second direction D2 as the longitudinal direction, are arranged. 【0016】 In the template substrate TS, as shown in Figure 1, multiple first unit regions A1 may be distributed within the plane, and multiple second unit regions A2 may be distributed within the plane. The multiple first unit regions A1 and multiple second unit regions A2 may be arranged such that the first unit regions A1 are not adjacent to each other, and the second unit regions A2 are not adjacent to each other. The multiple first unit regions A1 and multiple second unit regions A2 may each have the same shape. 【0017】 The template substrate TS includes an independent third seed region J3 whose longitudinal shape is in the third direction D3, which is different from the first direction D1 and the second direction D2, and island-shaped third nitride semiconductor portions 8T may be arranged from the third seed region J3 to the growth suppression region SP. As shown in Figure 3C, the mask pattern 6 includes an independent third opening K3 whose longitudinal shape is in the third direction D3, and the upper surface of the base substrate BS may include a third seed region J3 that overlaps with the third opening K3. The third direction D3 is a direction different from the first and second directions D1 and D2 on a plane parallel to the base substrate BS, and the direction perpendicular to the third direction D3 on this plane is defined as Y3. 【0018】 The third nitride semiconductor portion 8T may be a hexagonal crystal, and the acute angle between the first direction D1 and the third direction D3 may be 60 degrees. 【0019】 The template substrate TS may have one or more third unit regions A3, each containing a third seed region J3 and having a longitudinal shape in the third direction D3, with multiple independent openings arranged therein. In the template substrate TS, multiple third unit regions A3 may be distributed within the plane. In this case, the third unit regions A3 may be arranged so that they are not adjacent to each other. 【0020】 In the semiconductor substrate 10, multiple longitudinally shaped seed regions J are formed on a template substrate TS having a different substrate (a main substrate containing a substrate material other than a nitride semiconductor), such that their longitudinal directions are not aligned (not unidirectional) within the substrate plane and do not intersect with each other, and nitride semiconductor portions 8 that grow laterally from the seed regions J may be independent in an island-like manner. Compared to the case where the longitudinal direction of the seed regions J is unidirectional and a large warp occurs in a unidirectional direction, the absolute value of the warp is reduced by distributing the substrate warp in multiple directions. In addition, the warp in multiple directions makes the warp reduction by the strain relaxation layer structure of the base substrate BS more effective. When multiple seed regions J intersect, abnormal growth (e.g., angular protrusions) may occur in the semiconductor crystal grown from the intersection, but such abnormal growth can be avoided by making each seed region J an independent shape. 【0021】 The ends of the first and second nitride semiconductor portions 8F and 8S may be tapered. In ELO of a nitride semiconductor crystal (e.g., GaN), the a-axis direction is the growth direction, and the m-axis direction is the stabilization direction (non-growth direction), with the m-planes extending from both ends of the nitride semiconductor crystal. Therefore, the nitride semiconductor portion 8 obtained by stopping ELO while the a-plane of the nitride semiconductor crystal is exposed will have a tapered shape. 【0022】 Figure 4 is a cross-sectional view showing the configuration of another semiconductor substrate of this embodiment. As shown in Figure 4, in the template substrate TS, a buffer portion 2 may be provided so as to cover the mask pattern 6. A highly reactive AlGaN film can be used for the buffer portion 2. In this case, the upper surface of the buffer portion 2 (AlGaN film) includes a growth suppression region SP that overlaps with the mask portion 5 in a plan view, and a seed region J that overlaps with the opening K in a plan view. On the upper surface of the buffer portion 2 (AlGaN film surface), the region located above the mask portion 5 has low crystallinity and therefore functions as a growth suppression region SP. On the other hand, the region located above the opening K (above the exposed portion of the base substrate BS) has high crystallinity and therefore functions as a seed region J. 【0023】 Figure 5 is a plan view showing an enlarged portion of Figure 2. As shown in Figures 2 and 5, the shapes of the multiple first unit regions A1, multiple second unit regions A2, and multiple third unit regions A3 are all regular hexagons, one of two adjacent sides of the first unit region A1 faces one side of the second unit region A2, and the other faces one side of the third unit region A3. The first direction D1 is perpendicular to a pair of opposite sides of the first unit region A1, and the acute angles formed by the first direction D1 and the second direction D2, and the acute angles formed by the first direction D1 and the third direction D3, may each be 60°. 【0024】 Multiple seed regions J of the same extension direction and length, including the first seed region J1, may be formed in the first unit region A1; multiple seed regions J of the same extension direction and length, including the second seed region J2, may be formed in the second unit region A2; and multiple seed regions J of the same extension direction and length, including the third seed region J3, may be formed in the third unit region A3. 【0025】 Multiple nitride semiconductor portions 8, each having the same stretching direction and length, including a first nitride semiconductor portion 8F, may be formed on the first unit region A1; multiple nitride semiconductor portions 8, each having the same stretching direction and length, including a second nitride semiconductor portion 8S, may be formed on the second unit region A2; and multiple nitride semiconductor portions 8, each having the same stretching direction and length, including a third nitride semiconductor portion 8T, may be formed on the third unit region A3. In this case, since many nitride semiconductor portions 8 with the same stretching direction and length can be formed, the mass production of semiconductor devices using nitride semiconductor portions 8 is excellent. 【0026】 Figure 6 is a plan view showing another configuration example of the semiconductor substrate according to this embodiment. Figure 7 is a plan view showing an enlarged portion of Figure 6. As shown in Figures 6 and 7, the shapes of the plurality of first unit regions A1, plurality of second unit regions A2, and plurality of third unit regions A3 are all regular hexagons, one of two adjacent sides of the first unit region A1 faces one side of the second unit region A2, and the other faces one side of the third unit region A3, the first direction D1 is parallel to a pair of opposite sides of the first unit region A1, and the acute angles formed by the first direction D1 and the second direction D2, and the acute angles formed by the first direction D1 and the third direction D3, may each be 60°. 【0027】 Multiple seed regions J of the same extension direction and of multiple lengths, including the first seed region J1, may be formed in the first unit region A1; multiple seed regions J of the same extension direction and of multiple lengths, including the second seed region J2, may be formed in the second unit region A2; and multiple seed regions J of the same extension direction and of multiple lengths, including the third seed region J3, may be formed in the third unit region A3. 【0028】 Multiple nitride semiconductor portions 8 of the same stretching direction and of multiple lengths, including a first nitride semiconductor portion 8F, may be formed on the first unit region A1; multiple nitride semiconductor portions 8 of the same stretching direction and of multiple lengths, including a second nitride semiconductor portion 8S, may be formed on the second unit region A2; and multiple nitride semiconductor portions 8 of the same stretching direction and of multiple lengths, including a third nitride semiconductor portion 8T, may be formed on the third unit region A3. In this case, nitride semiconductor crystals can be grown efficiently up to the vicinity of the edges of each unit region, thereby increasing the crystal yield. Furthermore, a long nitride semiconductor portion 8 can be formed in the central part of the unit region. 【0029】 Figure 8 is a plan view showing another configuration example of the semiconductor substrate according to this embodiment. Figure 9 is a plan view showing an enlarged portion of Figure 8. As shown in Figures 8 and 9, the shapes of the multiple first unit regions A1, multiple second unit regions A2, and multiple third unit regions A3 are equilateral triangles, one of two adjacent sides of the first unit region A1 faces one side of the second unit region A2, and the other faces one side of the third unit region A3, the first direction D1 is parallel to the direction that bisects the angle between the two adjacent sides of the first unit region A1, and the acute angle formed by the first direction D1 and the second direction D2, and the acute angle formed by the first direction D1 and the third direction D3 may each be 60°. 【0030】 Multiple seed regions J of the same extension direction and of multiple lengths, including the first seed region J1, may be formed in the first unit region A1; multiple seed regions J of the same extension direction and of multiple lengths, including the second seed region J2, may be formed in the second unit region A2; and multiple seed regions J of the same extension direction and of multiple lengths, including the third seed region J3, may be formed in the third unit region A3. 【0031】 Multiple nitride semiconductor portions 8, each having the same stretching direction and multiple lengths, including a first nitride semiconductor portion 8F, may be formed on the first unit region A1; multiple nitride semiconductor portions 8, each having the same stretching direction and multiple lengths, including a second nitride semiconductor portion 8S, may be formed on the second unit region A2; and multiple nitride semiconductor portions 8, each having the same stretching direction and multiple lengths, may be formed on the third unit region A3, including a third nitride semiconductor portion 8T. 【0032】 Figure 10 is a plan view showing another configuration example of the semiconductor substrate according to this embodiment. Figure 11 is a plan view showing an enlarged portion of Figure 10. As shown in Figures 10 and 11, the shapes of the multiple first unit regions A1, multiple second unit regions A2, and multiple third unit regions A3 are square, one of the two opposite sides of the first unit region A1 faces one side of the second unit region A2, and the other faces one side of the third unit region A3, the first direction D1 is parallel to the two opposite sides of the first unit region A1, and the acute angle formed by the first direction D1 and the second direction D2, and the acute angle formed by the first direction D1 and the third direction D3 may each be 60°. 【0033】 Multiple seed regions J of the same extension direction and length, including the first seed region J1, may be formed in the first unit region A1; multiple seed regions J of the same extension direction and length, including the second seed region J2, may be formed in the second unit region A2; and multiple seed regions J of the same extension direction and length, including the third seed region J3, may be formed in the third unit region A3. 【0034】 Multiple nitride semiconductor portions 8, each having the same stretching direction and length, including a first nitride semiconductor portion 8F, may be formed on the first unit region A1; multiple nitride semiconductor portions 8, each having the same stretching direction and length, including a second nitride semiconductor portion 8S, may be formed on the second unit region A2; and multiple nitride semiconductor portions 8, each having the same stretching direction and length, including a third nitride semiconductor portion 8T, may be formed on the third unit region A3. 【0035】 Figure 12 is a plan view showing another configuration example of the semiconductor substrate according to this embodiment. Figure 13 is a plan view showing an enlarged portion of Figure 12. As shown in Figures 12 and 13, the shapes of each of the multiple first unit regions A1 and the multiple second unit regions A2 are square, one of two opposite sides of the first unit region A1 faces one side of the second unit region A2, the first direction D1 is parallel to the two opposite sides of the first unit region A1, and the angle between the first direction D1 and the second direction D2 may be 90°. 【0036】 Multiple seed regions J, each having the same extension direction and length, including a first seed region J1, may be formed in the first unit region A1, and multiple seed regions J, each having the same extension direction and length, may be formed in the second unit region A2, including a second seed region J2. 【0037】 Multiple nitride semiconductor portions 8, each having the same stretching direction and length, including a first nitride semiconductor portion 8F, may be formed on the first unit region A1, and multiple nitride semiconductor portions 8, each having the same stretching direction and length, may be formed on the second unit region A2, including a second nitride semiconductor portion 8S. 【0038】 Figure 14 is a plan view showing another configuration example of the semiconductor substrate according to this embodiment. Figure 15 is a plan view showing an enlarged portion of Figure 14. As shown in Figures 14 and 15, the mask pattern 6 has one or more unit regions AS in which a first seed region J1 and a second seed region J2 are arranged, and island-shaped first nitride semiconductor portions 8F are arranged from the first seed region J1 to the growth suppression region SP, and island-shaped second nitride semiconductor portions 8S may be located from the second seed region J2 to the growth suppression region SP. In the template substrate TS, a plurality of unit regions AS may be arranged in a matrix in the plane. 【0039】 An independent third seed region J3 may be located in the unit region AS, with a longitudinal shape in the third direction D3, which is different from the first direction D1 and the second direction D2. An island-shaped third nitride semiconductor region 8T may be located from the third seed region J3 to the growth suppression region SP. The acute angle formed by the first direction D1 and the second direction D2, and the acute angle formed by the first direction D1 and the third direction D3, may each be 60°. 【0040】 A unit region AS may have a plurality of seed regions J of the same size extending in a first direction D1, including a first seed region J1; a plurality of seed regions J of the same size extending in a second direction D2, including a second seed region J2; and a plurality of openings of the same size extending in a third direction D3, including a third seed region J3. 【0041】 On a unit region AS, there may be a plurality of nitride semiconductor portions 8 of the same size extending in a first direction D1, including a first nitride semiconductor portion 8F; a plurality of nitride semiconductor portions 8 of the same size extending in a second direction D2, including a second nitride semiconductor portion 8S; and a plurality of nitride semiconductor portions 8 of the same size extending in a third direction D3, including a third nitride semiconductor portion 8T. 【0042】 [Template board] Figure 16 is a plan view showing an example of the configuration of a template substrate according to this embodiment. Figure 17 is a plan view showing an enlarged portion of Figure 16. Figures 18 and 19 are cross-sectional views showing an example of the configuration of a template substrate according to this embodiment. As shown in Figures 16 to 19, the template substrate TS according to this embodiment includes a base substrate BS and a mask pattern 6 including a growth suppression region SP, an independent first seed region J1 with the first direction D1 as its longitudinal direction, and an independent second seed region J2 with a second direction D2 different from the first direction D1 as its longitudinal direction. The first and second directions D1 and D2 are, for example, different directions on a plane parallel to the base substrate BS, with Y1 being the direction perpendicular to the first direction D1 and Y2 being the direction perpendicular to the second direction D2 on this plane, and Z being the normal direction of this plane. The template substrate TS has a mask pattern 6 on a base substrate BS that includes a mask portion 5 and a first opening K1 and a second opening K2, the upper surface of the mask portion 5 being a growth suppression region SP, and the upper surface of the base substrate BS may include a first seed region J1 overlapping with the first opening K1 and a second seed region J2 overlapping with the second opening K2. 【0043】 The template substrate TS may have one or more first unit regions A1 in which a plurality of independent seed regions J, including a first seed region J1 and with the longitudinal direction D1, are arranged, and one or more second unit regions A2 in which a plurality of independent seed regions J, including a second seed region J2 and with the longitudinal direction D2, are arranged. In the template substrate TS, as shown in Figure 16, a plurality of first unit regions A1 may be distributed in a plane, and a plurality of second unit regions A2 may be distributed in a plane. The plurality of first unit regions A1 and the plurality of second unit regions A2 may be arranged such that the first unit regions A1 are not adjacent to each other, and the second unit regions A2 are not adjacent to each other. 【0044】 The template substrate TS may include an independent third seed region J3 whose longitudinal shape is in a third direction D3, which is different from the first direction D1 and the second direction D2. The mask pattern 6 may include an independent third opening K3 whose longitudinal shape is in the third direction D3, and the upper surface of the base substrate BS may include a third seed region J3 that overlaps with the third opening K3. 【0045】 Multiple first unit regions A1 and multiple second unit regions A2 may each have the same shape. The template substrate TS may have one or more third unit regions A3 in which multiple independent seed regions J, each having a longitudinal shape in the third direction D3, are arranged, including a third seed region J3. In the template substrate TS, multiple third unit regions A3 may be distributed within the plane. In this case, the third unit regions A3 may be arranged so that they are not adjacent to each other. 【0046】 [Manufacturing method and manufacturing apparatus] Figure 20 is a flowchart showing the method for manufacturing a semiconductor substrate according to this embodiment. As shown in Figure 20, the method for manufacturing a semiconductor substrate according to this embodiment includes the steps of preparing a template substrate TS and supplying nitride semiconductor raw materials to the template substrate TS which rotates with the substrate normal as the axis of rotation. 【0047】 Figure 21 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. As shown in Figure 21, the semiconductor substrate manufacturing method according to this embodiment includes an apparatus M1 for preparing a template substrate TS and an apparatus M2 (nitride semiconductor formation apparatus) for supplying nitride semiconductor raw materials to the template substrate TS which rotates with the substrate normal as the axis of rotation. 【0048】 Figure 22 is a schematic diagram showing the configuration of a nitride semiconductor deposition apparatus according to this embodiment. As shown in Figure 22, the semiconductor substrate manufacturing apparatus 20 includes a stage 21 on which a template substrate TS having a base substrate BS, a growth suppression region SP and a seed region J is placed, a raw material supply device 22 that supplies raw materials for growing nitride semiconductor parts 8 on the template substrate TS, and a control device 24 that controls the raw material supply device 22. The semiconductor substrate manufacturing apparatus 20 may also be provided with a chamber 25 including a stage SG, a flow channel 27 passing through the chamber 25, and a heating device 26 for heating the chamber 25, and the semiconductor substrate 10 may be placed in the flow channel 27. 【0049】 Stage 21 may rotate (using the axis of rotation as the axis normal to the template substrate TS). In Figure 21, the raw material supply device 22 flows the raw material gas horizontally (parallel to the top surface of the template substrate) into the flow channel 27 and exhausts it horizontally, but is not limited to this. The raw material gas may also flow vertically (normal to the template substrate TS). 【0050】 [Example 1] (Base board) Figure 23 is a cross-sectional view showing an example of the base substrate configuration. The base substrate BS may have a main substrate 1 which is a different type of substrate with a different lattice constant from the nitride semiconductor portion 8. The nitride semiconductor portion 8 may contain a GaN-based semiconductor, and the main substrate 1, which is a different type of substrate, may be a silicon substrate. Examples of different types of substrates include a sapphire (Al2O3) substrate and a silicon carbide (SiC) substrate. The plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H-SiC(0001) plane of a SiC substrate. These are examples, and any substrate and plane orientation that can grow the nitride semiconductor portion 8 by the ELO method is acceptable. 【0051】 The base substrate BS includes a main substrate 1 and a base layer 4 on the main substrate 1, and the nitride semiconductor portion 8 may grow from the upper surface (seed region J) of the base layer 4 exposed to the opening K. The base layer 4 may include a GaN-based semiconductor. The base layer 4 may include at least one of a buffer portion 2 and a seed portion 3. The buffer portion 2 can be a GaN-based semiconductor, AlN, SiC, etc. The seed portion 3 can be a nitride semiconductor (e.g., a GaN-based semiconductor, AlN). The base substrate BS is composed of a self-supporting single-crystal substrate such as SiC (e.g., a wafer cut from a bulk crystal), and a mask pattern 6 may be arranged on the single-crystal substrate. The base layer 4 does not have to be formed over the entire surface of the main substrate 1, but may be provided locally so as to overlap with the opening K in a plan view (the base layer 4 is exposed from the opening K). 【0052】 (Mask pattern) The mask pattern 6 includes a mask portion 5 and an opening K. The opening K functions as a growth initiation hole that exposes a seed region J and initiates the growth of the nitride semiconductor portion 8, and the mask portion 5 may function as a selective growth mask (deposition suppression mask) for lateral growth of the nitride semiconductor portion 8. As the mask portion 5, for example, a single layer film containing one of the following can be used: a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 degrees or higher), or a multilayer film containing at least two of these. A thermal oxide film obtained by thermal oxidation treatment of a silicon substrate, a silicon nitride substrate, etc., may also be used as the mask portion 5. 【0053】 As the mask portion 5, a laminated film in which a silicon oxide film and a silicon nitride film are formed in that order can be used. Depending on the film formation conditions, the nitride semiconductor portion 8 and the mask portion 5 may react and adhere to each other, so the upper layer film in contact with the nitride semiconductor portion 8 may be a silicon nitride film. In addition, in the process of locally forming the seed portion 3, the film on the support substrate 1 (the lower layer film) may be removed, and using a silicon oxide film as the lower layer film, which is easy to completely remove from the support substrate 1, also has the effect of improving the process yield. 【0054】 (Film deposition of nitride semiconductor portion) Figure 24 is a cross-sectional view showing the method for manufacturing a semiconductor substrate according to Example 1. In Example 1, the nitride semiconductor portion 8 is a GaN layer, and ELO film deposition was performed on a template substrate TS using an MOCVD apparatus, which is an example of the apparatus M2 (nitride semiconductor deposition apparatus) shown in Figure 21. As an example of ELO film deposition conditions, the following can be used: substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied). 【0055】 The initial growth layer 8p serves as the starting point for lateral growth of the nitride semiconductor layer 8. The initial growth layer 8p can be formed to a thickness of, for example, 30 nm to 1000 nm, 50 nm to 400 nm, or 70 nm to 350 nm. By allowing lateral growth from a state where the initial growth layer 8p slightly protrudes from the mask layer 5, growth of the nitride semiconductor layer 8 in the c-axis direction (thickness direction) is suppressed, enabling high-speed and highly crystallinity lateral growth of the nitride semiconductor layer 8, while also reducing raw material consumption. This makes it possible to form a thin, wide, low-defect nitride semiconductor layer 8 (crystalline nitride semiconductor such as GaN) at low cost. 【0056】 The nitride semiconductor portions 8, which grow laterally in opposite directions from two adjacent openings K, do not come into contact (meet) on the mask portion 5, and have a gap GP, thereby reducing the internal stress of the nitride semiconductor portions 8. This reduces cracks and defects (dislocations) that occur in the nitride semiconductor portions 8. This effect is particularly effective when the main substrate 1 is a different type of substrate. The width of the gap GP can be, for example, 10 μm or less, 5 μm or less, 3 μm or less, or 2 μm or less. 【0057】 Of the nitride semiconductor portion 8, the portion located on the initial growth portion 8p becomes a dislocation inheritance portion with many threading dislocations, while the portion on the mask portion 5 (wing portion) becomes a low-defect portion YS with a threading dislocation density of 1 / 10 or less compared to the dislocation inheritance portion. A threading dislocation is a dislocation that travels through the nitride semiconductor portion 8 in its c-axis direction. <0001> These are dislocations (defects) that extend in the direction. The penetration dislocation density of the low-defect area YS is, for example, 5 × 10⁻⁶. 6 [pcs / cm 2 The following is possible. As described later, when an active portion (active layer) including a light-emitting portion is formed above the nitride semiconductor portion 8, the light-emitting portion can be positioned above the low-defect portion YS (so as to overlap the low-defect portion YS in a plan view). 【0058】 For the low-defect portion YS, the ratio of the size W1 in the a-axis direction to the thickness d1 (W1 / d1) can be set to, for example, 2.0 or more. Using the method of Example 1, W1 / d1 can be set to 1.5 or more, 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. By setting W1 / d1 to 1.5 or more, the internal stress of the nitride semiconductor portion 8 is reduced, and the warping of the semiconductor substrate 10 is reduced. 【0059】 The aspect ratio (ratio of size in the X direction to thickness = WL / d1) of the nitride semiconductor portion 8 can be 3.5 or greater, 5.0 or greater, 6.0 or greater, 8.0 or greater, 10 or greater, 15 or greater, 20 or greater, 30 or greater, or 50 or greater. Furthermore, by using the method of Example 1, the ratio of the size WL of the nitride semiconductor portion 8 in the X direction to the width WK of the opening K (WL / WK) can be 3.5 or greater, 5.0 or greater, 6.0 or greater, 8.0 or greater, 10 or greater, 15 or greater, 20 or greater, 30 or greater, or 50 or greater, thereby increasing the ratio of low-defect portions. The nitride semiconductor portion 8 (including the initial growth portion 8p) shown in Figure 24 can be a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal). 【0060】 [Example 2] Figure 25 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 2. Figure 26 is a plan view showing a method for manufacturing a semiconductor device according to Example 2. Figure 25 includes the steps of: preparing a semiconductor substrate 10, forming a compound semiconductor portion 9 and electrodes E1 and E2 on the semiconductor substrate 10; bonding a laminate T1 including a nitride semiconductor portion 8, a compound semiconductor portion 9, and electrodes E1 and E2 to a support substrate SK via bonding layers H1 and H2; peeling off the base substrate BS; and separating the support substrate SK into a plurality of supports ST to form a semiconductor device SD in which the laminate T1 is held on the supports ST. Before peeling off the base substrate BS, the mask portion 5 may be removed by wet etching or the like. As shown in Figure 26, after forming the compound semiconductor portion 9 and electrodes E1 and E2, the semiconductor substrate 10 may be cut along the edges of the first to third unit regions A1 to A3 of the template substrate TS to form a polygonal substrate P1 containing a plurality of laminates T1 on the first unit region A1, a polygonal substrate P2 containing a plurality of laminates T2 on the second unit region A2, and a polygonal substrate P3 containing a plurality of laminates T3 on the third unit region A3. If the first to third unit regions A1 to A3 have the same shape, the polygonal substrates P1 to P3 will also have the same structure, thus simplifying subsequent processes. 【0061】 The nitride semiconductor portion 8 may be an n-type semiconductor crystal. The compound semiconductor portion 9 may contain a GaN-based semiconductor. The compound semiconductor portion 9 may include an active portion (e.g., an active layer such as a quantum well structure) and a p-type semiconductor portion, and may include an n-type semiconductor portion (e.g., a regrowth layer, an n-type contact layer) below the active portion. If the active portion of the compound semiconductor portion 9 includes a light-emitting portion, the light-emitting portion can be positioned above the low-defect portion YS (overlapping the low-defect portion YS in a plan view). This can increase the luminescence efficiency. 【0062】 Electrode E1 located above the low-defect portion YS may be the anode and electrode E2 may be the cathode. The support substrate SK may have conductive pads in contact with bonding layer H1 and conductive pads in contact with bonding layer H2. Bonding layers H1 and H2 may be formed of solder material. Before, during, or after bonding to the support substrate SK, the longitudinally shaped laminate T1 may be divided into multiple parts (by cutting in the short-side direction), in which case the division process may be carried out by cleavage of the nitride semiconductor portion 8 and the compound semiconductor portion 9 (for example, m-plane cleavage where the cleavage plane is the m-plane). If it is to be a semiconductor laser element, an end-face coating (formation of a reflective mirror film) may be performed on the m-plane, which is the cleavage plane. In Figure 25, the laminate T1 is transferred from the base substrate BS to the support substrate SK, but it is not limited to this. It may be transferred from the base substrate BS to a tape or the like one or more times. 【0063】 The semiconductor element SD may function as an LED (light-emitting diode) element or a semiconductor laser element. The support ST may be a submount substrate. Example 2 includes electronic equipment having the semiconductor element SD (e.g., lighting device, laser device, display device, measuring device, information processing device, etc.). 【0064】 Figure 27 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to this embodiment. As shown in Figures 1 and 27, in each of the first unit region A1, second unit region A2, and third unit region A3, the low-defect portion (wing portion YS) of the nitride semiconductor portion 8 (8F, 8S, 8T) located above the growth suppression region SP may be grown to separate it from the growth suppression region SP. By growing the wing portion YS so that it faces the growth suppression region SP through a gap Q, the stress influence on the nitride semiconductor portion 8 is further reduced, and the warping of the semiconductor substrate 10 including the nitride semiconductor portion 8 can be further reduced. In Figure 27, the seed region J (J1, J2, J3) is located below the growth suppression region SP, but is not limited to this. The seed region J may be located flush with the growth suppression region SP, or it may be located above it. 【0065】 (Additional items) The foregoing disclosures are for illustrative and explanatory purposes only, and not for limitation. Many variations will be obvious to those skilled in the art based on these examples and descriptions, and therefore, these variations are also included in the embodiments. [Explanation of Symbols] 【0066】 1 Main board 5 Mask section 6 Mask Patterns SP growth suppression area 8F First Nitride Semiconductor Section 8S Second Nitride Semiconductor Section 8T Third Nitride Semiconductor Section 10 Semiconductor substrates 20 Semiconductor substrate manufacturing equipment BS base board TS template substrate A1 First Unit Area A2 2nd unit area A3 Third Unit Area D1 1st direction D2 2nd direction D3 Third direction J1 1st Seed Area J2 2nd Seed Area J3 3rd Seed Area K1 1st opening K2 2nd opening K3 Third Opening YS Low-Defect Part

Claims

[Claim 1] A template substrate comprising a base substrate containing a substrate material other than a nitride semiconductor, and including a growth suppression region, an independent first seed region with a first direction as its longitudinal direction, and an independent second seed region with a second direction different from the first direction as its longitudinal direction, An island-shaped first nitride semiconductor portion, whose longitudinal direction is the first direction, is arranged so as to extend from above the first seed region to above the growth suppression region, A semiconductor substrate comprising an island-shaped second nitride semiconductor portion whose longitudinal direction is the second direction, which is arranged from above the second seed region to above the growth suppression region. [Claim 2] The template substrate includes an independent third seed region having a longitudinal shape in a third direction different from the first and second directions. The semiconductor substrate according to claim 1, wherein island-shaped third nitride semiconductor portions are arranged from above the third seed region to above the growth suppression region. [Claim 3] The first nitride semiconductor portion and the second nitride semiconductor portion are each hexagonal crystals. The semiconductor substrate according to claim 1 or 2, wherein the acute angle formed by the first direction and the second direction is 60 degrees. [Claim 4] The third nitride semiconductor portion is a hexagonal crystal, The semiconductor substrate according to claim 2, wherein the acute angle between the first direction and the third direction is 60 degrees. [Claim 5] The semiconductor substrate according to any one of claims 1, 2, and 4, wherein the template substrate has one or more first unit regions in which a plurality of independent seed regions, including the first seed region and with a first direction as the longitudinal direction, are arranged, and one or more second unit regions in which a plurality of independent seed regions, including the second seed region and with a second direction as the longitudinal direction, are arranged. [Claim 6] The semiconductor substrate according to claim 5, wherein in the template substrate, a plurality of first unit regions are dispersed in the plane, and a plurality of second unit regions are dispersed in the plane. [Claim 7] The semiconductor substrate according to claim 6, wherein the first unit regions are not adjacent to each other, and the second unit regions are not adjacent to each other. [Claim 8] The semiconductor substrate according to claim 6, wherein each of the plurality of first unit regions and the plurality of second unit regions has the same shape. [Claim 9] The semiconductor substrate according to claim 5, wherein the template substrate has one or more third unit regions in which a plurality of independent seed regions having a longitudinal shape in a third direction different from the first and second directions are arranged. [Claim 10] The semiconductor substrate according to claim 9, wherein a plurality of third unit regions are dispersed in the plane of the template substrate. [Claim 11] The semiconductor substrate according to claim 8, wherein the shape is one of an equilateral triangle, a square, and a regular hexagon. [Claim 12] The shape is a regular hexagon, and one side of the first unit region and one side of the second unit region are opposite each other. The first direction is perpendicular to a pair of opposite sides of the first unit region, and the acute angle between the first direction and the second direction is 60°. In the first unit region, a plurality of seed regions are formed, including the first seed region, having the same extension direction and the same length; in the second unit region, a plurality of seed regions are formed, including the second seed region, having the same extension direction and the same length. The semiconductor substrate according to claim 11, wherein a plurality of nitride semiconductor portions, including a first nitride semiconductor portion and having the same stretching direction and length, are formed above the first unit region, and a plurality of nitride semiconductor portions, including a second nitride semiconductor portion and having the same stretching direction and length, are formed above the second unit region. [Claim 13] The shape is a regular hexagon, and one side of the first unit region and one side of the second unit region are opposite each other. The first direction is parallel to a pair of opposite sides of the first unit region, and the acute angle formed by the first direction and the second direction is 60°. In the first unit region, a plurality of seed regions are formed, including the first seed region, having the same extension direction and multiple lengths; and in the second unit region, a plurality of seed regions are formed, including the second seed region, having the same extension direction and multiple lengths. The semiconductor substrate according to claim 11, wherein a plurality of nitride semiconductor portions of the same stretching direction and multiple lengths, including a first nitride semiconductor portion, are formed above the first unit region, and a plurality of nitride semiconductor portions of the same stretching direction and multiple lengths, including a second nitride semiconductor portion, are formed above the second unit region. [Claim 14] The semiconductor substrate according to claim 1, wherein the template substrate has one or more unit regions on which the first seed region and the second seed region are arranged. [Claim 15] The semiconductor substrate according to claim 14, wherein in the template substrate, a plurality of unit regions are arranged in a matrix in the plane. [Claim 16] The semiconductor substrate according to claim 14, wherein each unit region has an independent third seed region whose longitudinal shape is in a third direction different from the first and second directions. [Claim 17] The first direction is the <1-100> direction of the first nitride semiconductor portion. The semiconductor substrate according to claim 1, wherein the second direction is the <1-100> direction of the second nitride semiconductor portion. [Claim 18] The semiconductor substrate according to claim 2, wherein the third direction is the <1-100> direction of the third nitride semiconductor portion. [Claim 19] The semiconductor substrate according to any one of claims 1, 2, 4 and 14 to 18, wherein the ends of the first nitride semiconductor portion and the second nitride semiconductor portion are tapered. [Claim 20] The semiconductor substrate according to claim 1, wherein the substrate material is silicon or silicon carbide. [Claim 21] The semiconductor substrate according to any one of claims 1, 2, 4, 14-18 and 20, wherein the first nitride semiconductor portion and the second nitride semiconductor portion include a GaN-based semiconductor. [Claim 22] The semiconductor substrate according to any one of claims 1, 2, 4, 14 to 18 and 20, wherein the base substrate is disc-shaped. [Claim 23] The template substrate has a mask pattern that includes a mask portion, an independent first opening with the first direction as the longitudinal direction, and an independent second opening with the second direction as the longitudinal direction. The upper surface of the mask portion is the growth suppression region, The semiconductor substrate according to any one of claims 1, 2, 4, 14-18 and 20, wherein the upper surface of the base substrate includes a first seed region overlapping the first opening and a second seed region overlapping the second opening.

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