Apparatus and method for processing data by using non-volatile memory device

Abstract

A host device using a multi-level cell non-volatile memory device according to an aspect of the present disclosure may switch data in a high energy consumption state to data in a low energy consumption state during a read operation, and store same in the non-volatile memory device.

Description

Data processing device and method using a non-volatile memory device

[0001] The present disclosure relates to a data processing apparatus and method using a non-volatile memory device.

[0002] Recently, deep neural network (DNN) technology has advanced rapidly and is being utilized in various fields such as image processing, natural language processing, healthcare, and speech recognition. Furthermore, Transformer-based AI models and Large Language Models, which are used in various fields, have simultaneously increased the demand for data transfer between storage devices and computing devices, such as CPUs, due to the increase in weight size. As such, as the amount of matrix multiplication operations between weights and input data increases for the execution of AI models, various methods are being researched to accelerate this processing.

[0003] Meanwhile, the increase in data size has also increased the need to store data in high-capacity storage devices such as NAND flash-based SSDs (Solid State Drives). Consequently, technologies are being developed to reduce the data transfer requirements by performing pre-computations on weighted or input data before transferring them from the storage device to the CPU or GPU. For example, Processing-In-Memory (PIM) technology is being researched to perform Multiply-Accumulate (MAC) operations, which involve multiplication and cumulative summation of data within NAND flash memory. However, since these technologies perform multiplication and addition operations on stored data using the sum of currents and rely on analog methods of accumulating current and charge, they inherently carry issues regarding computational accuracy. Therefore, to resolve these accuracy issues, there is a need for a digital approach rather than an analog one to improve performance in terms of energy consumption when reading data from NAND flash.

[0004] In the present disclosure, for a NAND flash memory that stores data using a plurality of level cells, the read energy consumption in the NAND flash memory is minimized by switching state data with high energy consumption during a read operation to state data with low energy consumption for storage.

[0005] The present disclosure aims to provide a data processing device and method capable of minimizing read energy consumption by utilizing the characteristics of a non-volatile memory device in order to solve the aforementioned problems.

[0006] However, the technical problems that the embodiments of the present disclosure aim to solve are not limited to the technical problems described above, and other technical problems may exist.

[0007] As a technical means for achieving the aforementioned technical problem, a data processing device using a non-volatile memory device according to one aspect of the present disclosure comprises: a non-volatile memory device; and a host device that stores data to be written to the non-volatile memory device, reads data stored in the non-volatile memory device, converts a data code to be stored in the non-volatile memory device, and restores the converted data code, wherein the host device performs a data mapping step of converting input data to be written to the non-volatile memory device into binary data and arranging them to correspond to each memory cell; a data code conversion step of specifying the arranged data as a data code unit to be stored in each memory cell and converting a preset first data code and a third data code into the third data code and the first data code, respectively; and a step of storing the input data in the non-volatile memory device according to the data code, wherein the cell-based non-volatile memory device stores N-bit data (N is a natural number greater than or equal to 2) in each memory cell, and the data code is the N-bit data, 2N It includes data codes, wherein the first data code is the 2 N It is the data code that consumes the most power during a read operation among the data codes.

[0008] Additionally, a data processing method for a non-volatile memory device according to another aspect of the present disclosure comprises: a data mapping step of converting input data to be written to the non-volatile memory device into binary data and arranging them to correspond to each memory cell; a step of specifying the arranged data as a data code unit to be stored in each memory cell and converting a preset first data code and a third data code into the third data code and the first data code, respectively; and a step of storing the input data in the non-volatile memory device according to the data code converted in the step, wherein the non-volatile memory device stores N-bit data (N is a natural number greater than or equal to 2) in each memory cell, and the data code is the N-bit data, 2 N It includes data codes, wherein the first data code is the 2 N It is the data code that consumes the most power during a read operation among the data codes.

[0009] Additionally, an SSD device according to another aspect of the present disclosure comprises a nonvolatile memory device including a plurality of nonvolatile memory cells and a processor for controlling the nonvolatile memory device, wherein the processor is configured to convert input data instructed to be written from the host device into binary data in response to at least one of a write command and a read command of the host device, arrange the arranged data in a data code unit to be stored in each memory cell, specify the arranged data, convert a preset first data code and a third data code into the third data code and the first data code, respectively, and transmit the input data to the nonvolatile memory device according to the data code, wherein the nonvolatile memory device is configured to store N-bit data (N is a natural number greater than or equal to 2) in each memory cell, and the data code is the N-bit data, wherein 2 N It includes data codes, wherein the first data code is the 2 N It is the data code that consumes the most power during a read operation among the data codes.

[0010] According to the means for solving the aforementioned problem, power consumption during data reading of a non-volatile memory device can be minimized by using a data code switching method. In addition, power consumption during data reading can be further increased by additionally using a data mapping method based on cell-first allocation.

[0011] Figure 1 illustrates the threshold voltage distribution of a cell in a typical non-volatile memory.

[0012] Figure 2 is a diagram illustrating the energy consumption during a read operation of a cell of a conventional TLC type non-volatile memory.

[0013] Figure 3 illustrates the ratio of data codes stored in the field of artificial intelligence in a conventional TLC non-volatile memory cell.

[0014] FIG. 4 illustrates a data processing device according to one embodiment of the present disclosure.

[0015] FIG. 5 is a schematic representation of the concept of state transition of a data code according to one embodiment of the present disclosure.

[0016] FIG. 6 is a schematic diagram of a state switching method of a data code according to one embodiment of the present disclosure.

[0017] FIG. 7 is a diagram illustrating a cell-first allocation method of data according to one embodiment of the present disclosure.

[0018] FIG. 8 illustrates a method of converting to the original data code when reading data recorded according to a data code conversion method according to one embodiment of the present disclosure.

[0019] FIG. 9 illustrates a method for restoring data when reading out data recorded according to a cell-first allocation method according to one embodiment of the present disclosure.

[0020] FIG. 10 is a flowchart illustrating a data processing method according to one embodiment of the present disclosure.

[0021] Embodiments of the present disclosure are described below in detail with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present disclosure in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0022] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "electrically connected" with other components interposed between them. Furthermore, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0023] In this specification, the term "part" includes a unit realized by hardware, a unit realized by software, and a unit realized using both. Additionally, one unit may be realized using two or more pieces of hardware, and two or more units may be realized by one piece of hardware. Meanwhile, "part" is not limited to software or hardware, and "part" may be configured to reside in an addressable storage medium or configured to run on one or more processors. Accordingly, as an example, "part" includes components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and "parts" may be combined into a smaller number of components and "parts" or further separated into additional components and "parts." In addition, the components and '~parts' may be implemented to regenerate one or more CPUs within the device.

[0024] Figure 1 illustrates the threshold voltage distribution of a cell of a typical non-volatile memory, Figure 2 is a diagram illustrating the energy consumption during a read operation of a cell of a typical TLC (Triple Level Cell) non-volatile memory, and Figure 3 illustrates the ratio of data codes stored in a cell of a typical TLC non-volatile memory.

[0025] A typical non-volatile memory cell is implemented using a charge trap method, and data can be written to the memory cell through the operation of charging electrons in the charge trap layer or discharging charged electrons. Based on a single-level cell (SLC), it can be distinguished into a programmed state (S1) where data is stored and a deleted state (S0) where data is erased. Meanwhile, in the reading step for reading data, when a reference voltage (Vr) is applied to the gate of the memory cell to be read, the state of the memory cell is read based on whether data flows through the bit line. At this time, if the memory cell is in the programmed state, the voltage of the memory cell is greater than the reference voltage (Vr), so no current flows through the bit line. However, if the memory cell is in the erased state, the voltage of the memory cell is smaller than the reference voltage (Vr), so current flows through the bit line, and the state of the memory cell can be read by sensing this.

[0026] As described, single-level cell nonvolatile memory reads the state of a memory cell using a single threshold voltage, while multi-level cell (MLC) nonvolatile memory reads the state of a memory cell using multiple threshold voltages. In particular, triple-level cell (TLC) nonvolatile memory distinguishes the state of a total of eight memory cells using seven threshold voltages, thereby enabling the storage of three bits of data in one memory cell.

[0027] Referring to Fig. 2, the code of the 3-bit data stored in each memory cell and the data distribution specified for each code can be identified. For example, '111' means a state where the voltage recorded in the memory cell is lower than the minimum threshold voltage, and '101' means a state where the voltage recorded in the memory cell is higher than the maximum threshold voltage.

[0028] And, at the bottom of the distribution graph of the memory cell, the result read when each threshold voltage is applied is indicated. For example, in the case of '111', it is read as an erase state ('1') for all threshold voltages (Vr0~Vr6), and in the case of '101', it is read as a program state ('0') for all threshold voltages (Vr0~Vr6), and the reading result is determined differently for each code. At this time, the erase state ('1') means that current flows through the bit line of the corresponding memory cell.

[0029] Meanwhile, in a non-volatile memory cell of the TLC type, when reading the most significant bit (MSB), center significant bit (CSB), and least significant bit (LSB) of 3-bit data, reference voltages must be applied 2 times, 3 times, and 2 times, respectively. For example, to read the CSB, three reference voltages (Vr1, Vr3, Vr5) are required, and in each case, the BL current is detected to determine whether the CSB value is 1 or 0.

[0030] Due to this structure, there is a problem where energy efficiency decreases as the data code is positioned further to the left, as more bitline current is activated when the reference voltage is applied. In other words, it can be observed that the smaller the charge stored in the trap layer of the memory cell, or the closer the memory cell's state is to the erase state, the greater the current flowing through the bitline during a read operation, resulting in higher power consumption. Put another way, it can be seen that the power consumption during a read operation varies depending on the data code.

[0031] Meanwhile, Figure 3 illustrates the proportion of each data code when the weights of a conventional artificial intelligence model are stored in a non-volatile memory cell of the TLC type. It can be seen that the data of the artificial intelligence model contains a significantly large proportion of data codes that consume more energy than other data codes, such as '111' and '000'.

[0032] Based on this background, the present disclosure proposes a technology that converts an energy-intensive data code into another data code and stores it in a memory cell, and outputs the original data code when the converted data code is read.

[0033] FIG. 4 illustrates a data processing device according to one embodiment of the present disclosure.

[0034] The data processing device (10) may include an SSD device containing non-volatile memory and a host device. Such a data processing device (10) may be implemented in the form of an E-FLASH (embedded flash) device in which flash memory is implemented in an embedded form within a semiconductor circuit. However, this is merely an example, and processing can be performed to enable data code conversion for general commercial flash memory in addition to E-FLASH through the host device.

[0035] The SSD device used in the data processing device (10) of the present disclosure may utilize a multi-level cell non-volatile memory. The multi-level cell non-volatile memory may be a memory device comprising memory cells that store multiple bits other than SLC. In this case, the non-volatile memory device stores N bits (N is a natural number greater than or equal to 2) of data in each memory cell. For convenience of explanation, the following description is based on a TLC memory where N is 3, but the present disclosure is not limited thereto and can be applied to QLC (Quad Level Cell) non-volatile memory, etc. Therefore, the description based on multi-level cell or TLC in this specification is a concept that includes a memory device comprising memory cells that store multiple bits other than SLC, without further explanation.

[0036] Furthermore, the host device performs the function of instructing the storage of data to be written to a non-volatile memory device and instructing the reading of data stored in the non-volatile memory device. In particular, it may be implemented in a form including a CPU or GPU for processing the aforementioned deep neural network. In addition, in one embodiment of the present disclosure, the host device converts a data code to be stored in a non-volatile memory device and restores the converted data code. However, the present invention is not limited thereto, and the method for converting data to be stored and the method for restoring the converted data code disclosed herein can also be performed in an SSD device. For example, the conversion of data and the restoration of the data code can be performed in an embedded processor of an SSD device.

[0037] More specifically, the host device performs a data mapping step of converting input data to be written to a non-volatile memory device into binary data and arranging them to correspond to each memory cell; a data code conversion step of specifying the arranged data as a data code unit to be stored in each memory cell and converting a preset first data code and a third data code into a third data code and a first data code, respectively; and a step of storing the input data in the non-volatile memory device according to the data code. At this time, the data code is N-bit data and includes 2^N data codes, and the first data code is the data code that consumes the most power during a read operation among the 2^N data codes.

[0038] The host device includes one or more main memories in which data to be written to a non-volatile memory device is stored, and data read out after being stored in the non-volatile memory device is stored, wherein the main memory may be SRAM or DRAM. Furthermore, the data may be classified into weight data or input data for matrix multiplication operations of a neural network model, and the main memory for storing weight data and the main memory for storing input data may be separated.

[0039] In addition, the host device may further include a data code processing unit that performs the conversion and restoration steps of the data code described above.

[0040] FIG. 5 is a schematic representation of the concept of state transition of a data code according to one embodiment of the present disclosure.

[0041] As explained earlier, '111' and '000' data codes are statistically frequently used in artificial intelligence models, but reading this data in TLC non-volatile memory presents a problem of increased energy consumption.

[0042] Accordingly, when storing the '111' data code or the '000' data code in a memory cell, it is converted into data with relatively low energy consumption ('101', '001'), respectively, and stored in the memory cell. As previously observed through Figure 2, data codes such as '101' or '001' have relatively lower energy consumption. Then, when the converted data code is read from the non-volatile memory cell, it is restored back to the original data code and output.

[0043] FIG. 6 is a schematic diagram of a state switching method of a data code according to one embodiment of the present disclosure.

[0044] First, a data mapping operation is performed to arrange raw data to be stored in TLC non-volatile memory. In the data mapping operation, the raw data is converted into binary data, which is recorded in page units. For example, when recording '1', '5', and '45' as raw data, they are each converted into 8-bit binary data, which are then recorded in memory cells in page units. The diagram illustrates that after each raw data is converted into 8-bit binary data, they are recorded in different pages (a total of 3 pages). Meanwhile, the three bits placed in the same column (indicated by dotted lines) are stored in each memory cell of the TLC non-volatile memory where a single 3-bit data is stored. In other words, three bits contained in different pages are grouped by column and stored in each memory cell. In the diagram, '000', '000', '001', '000', '001', '011', '000', and '111' are stored in each memory cell starting from the leftmost. However, as previously observed, since the proportion of '000' and '111' is statistically higher, the present disclosure intends to convert them to other data codes.

[0045] In the data code conversion operation, among multiple data codes representing 3 bits, a first data code or a second data code, which is predetermined as having high energy consumption and a high frequency of occurrence during a read operation, is converted to another data code with relatively lower energy consumption. In the present disclosure, '111' is selected as the first data code and '000' is selected as the second data code, but this may be changed depending on the application field. In particular, the frequency of occurrence may be changed depending on the nature of the data.

[0046] In one embodiment of the present disclosure, the first data code is converted to the third data code ('101') which consumes the least amount of data during a read operation. Additionally, the second data code is converted to the fourth data code ('001') which consumes the second least amount of data during a read operation. Furthermore, if the original data is '101' or '001', it is converted to '111' and '000', respectively, to prevent data duplication.

[0047] As such, the data with the converted data code can be verified through the table on the right at the top of Fig. 6. With this configuration, power consumption during reading operations can be minimized by converting the data code. Meanwhile, the conversion relationships of the data codes are stored in a separate lookup table and referenced to be utilized during data retrieval operations. This will be examined in detail later.

[0048] Meanwhile, in addition to the data code conversion mentioned above, we will explain methods to further reduce energy consumption.

[0049] FIG. 7 is a diagram illustrating a cell-first allocation method of data according to one embodiment of the present disclosure.

[0050] In addition to applying the data code conversion method described earlier, we aim to further minimize energy consumption. Specifically, regarding baseline allocation, a conventional data allocation method, each page of binary data is arranged sequentially in the row direction, and three pieces of data are grouped into a data code for each column and stored in a single memory cell. However, according to the data code conversion method discussed earlier, data codes must all be identical, such as '111' or '000', to be eligible for conversion; it has been confirmed that such cases are rare in conventional data allocation methods. In particular, since the method of grouping data codes by column is used while page-sized data is stored arranged in the row direction, unrelated data ends up being grouped into a single data code.

[0051] Accordingly, the present disclosure proposes a cell-first allocation method that maps input data along the column direction (or the direction of extension of the bit line), unlike conventional data allocation methods that map input data in page units. As illustrated, when binary data is '000 010 01', it is mapped along the column direction across multiple pages (pages 0 to 7, a total of 8 pages). In the figure, it can be seen that three sets of binary data are each arranged along the column direction. By arranging data in this way, some of the binary data representing raw data can be stored together in a memory cell that stores 3 bits, so that data with high correlation to each other is grouped into a single data code, thereby increasing the number of data codes subject to conversion.

[0052] FIG. 8 illustrates a method for restoring the original data code when reading data recorded according to a data code conversion method according to one embodiment of the present disclosure.

[0053] As previously discussed, '111' was selected as the first data code and '000' as the second data code, and their data were converted to the third data code ('101') and the fourth data code ('001'), respectively. Additionally, when the data code is the third data code ('101') and the fourth data code ('001'), it is converted to the first data code ('111') and the second data code ('000'), respectively. This data conversion relationship is stored in a lookup table.

[0054] In the case of TLC, a total of 3 bits of data are stored in one memory cell, which means that a total of 8 data codes (1st to 8th data codes) can be used. Among them, the 1st and 2nd data codes, which have high energy consumption and a high frequency of data occurrence during read operations, are selected and converted into the 3rd and 4th data codes. Then, the original 3rd and 4th data codes are converted into the 1st and 2nd data codes, respectively, and the conversion method is not used for the remaining data codes (5th to 8th data codes).

[0055] Meanwhile, in the process of reading data after writing it to each memory cell according to the data conversion, a process of restoring the data conversion state is required. That is, by referring to a lookup table that stores the data conversion relationship, if the read data is a third data code or a fourth data code, it is restored to the corresponding first data code and second data code, respectively. As shown in FIG. 9, the third data code ('101') is restored to the first data code ('111'), and the fourth data code ('001') is restored to the second data code ('000').

[0056] FIG. 9 illustrates a method for restoring data when reading out data recorded according to a cell-first allocation method according to one embodiment of the present disclosure.

[0057] As previously discussed, in order to enhance the effectiveness of the data code conversion method, the present disclosure may use a cell-first allocation method in which data is first allocated in the column direction of the memory cell.

[0058] Accordingly, when reading data recorded in non-volatile memory using the cell-first allocation method, the data whose placement has been altered according to the cell-first allocation method is restored using the existing baseline allocation method. At this time, the restored data is divided and stored across multiple main memories (SRAM or DRAM).

[0059] For example, assuming that the first data (001 010 01), the second data (001 001 00), the third data (101 011 00), and the fourth data (110 101 01) are recorded in the column direction, each data is recorded sequentially across the first to eighth pages (page 0 to page 7) according to the data recording order.

[0060] Then, when restoring data, the data recorded in the column direction in each separated memory area is arranged sequentially in the row direction according to the reading order. For example, after reading all the data stored in the first page (page 0), it is separated and stored in each memory area (SRAM0~SRAM3). Next, after reading all the data stored in the second page (page 1), it is separated and stored in each memory area (SRAM0~SRAM3), but is stored sequentially in the row direction following the data stored first.

[0061] If this process is performed up to the last page, page 8 (page 7), it can be confirmed that data restored by the baseline allocation method is stored in each memory area.

[0062] FIG. 10 is a flowchart illustrating a data processing method according to one embodiment of the present disclosure.

[0063] First, input data to be written to a non-volatile memory device is converted into binary data and then arranged to correspond to each memory cell (S110).

[0064] In this case, the conventional baseline allocation method can be used, and to further minimize energy consumption, it is also possible to use the cell-first allocation method.

[0065] Next, the arrayed data is specified as a data code unit to be stored in each memory cell, and the preset first data code and third data code are converted into the third data code and first data code, respectively (S120).

[0066] At this time, additional steps may be performed to convert the second data code and the fourth data code into the fourth data code and the second data code, respectively.

[0067] Next, the input data is stored in a non-volatile memory device according to the converted data code (S130). Since the process of programming the data code into the non-volatile memory device itself corresponds to prior art, a detailed description thereof is omitted.

[0068] Next, data stored in a non-volatile memory device is read out (S140).

[0069] When reading data, the process of restoring the data code converted in the previous step to its original state is performed.

[0070] In addition, if cell-first allocation is performed in the preceding step (S110), a restoration step is additionally performed to arrange data according to baseline allocation, which arranges data arranged in the column direction according to cell-first allocation in the row direction.

[0071] FIG. 11 is a block diagram illustrating the configuration of an embedded processor of an SSD device according to one embodiment of the present disclosure.

[0072] The embodiments of the present disclosure described above with reference to FIGS. 1 to 10 can also be performed in an SSD device. For example, data conversion and data code restoration can be performed in an embedded processor such as FIG. 10 of an SSD device.

[0073] Referring to FIG. 11, the embedded processor may include a core processor (21), a command decoder (22), a packet manager (23), an FTL (24), a data code processing unit (25), and a NAND input / output circuit (26).

[0074] An embedded processor can control an SSD device to perform I / O requests from a host device. The embedded processor can be implemented as a microcontroller (MCU), embedded processor, or system-on-chip (SoC).

[0075] An embedded processor may be configured to control a non-volatile memory device according to commands or control from a host device. I / O requests may include writing, reading, and / or erasing user data requested by the host device to the SSD device.

[0076] The core processor (21) may be implemented as a circuit, logic, code, or a combination thereof. The core processor (21) controls the overall operation of the SSD device, including the embedded processor. When the SSD device is driven, the core processor (21) can load firmware stored in the Read Only Memory (ROM) into the working memory device and perform the overall operation of the embedded processor. The core processor (21) can load the Flash Translation Layer (FTL) (24) into the working memory and, based on the address translation result of the Flash Translation Layer (24), direct the programming of data into the non-volatile memory device and / or the reading of data from the non-volatile memory device through the NAND I / O circuit (26).

[0077] The command decoder (22) can decode commands based on the protocol that the packet manager (23) has parsed from a packet received from a host device based on the protocol of an interface agreed upon in advance (e.g., PCIe, NVMe).

[0078] The data code processing unit (25) can perform the conversion of data and the restoration of data codes as described with reference to FIGS. 1 to 10.

[0079] FIG. 12 is a drawing illustrating the division of storage areas according to one embodiment of the present disclosure.

[0080] In one embodiment, the embedded processor of the SSD device can store data by distinguishing storage areas based on the type of data and / or instructions from the host device.

[0081] For example, general data can be stored in the first storage area (SR1), and data of the artificial intelligence model (e.g., hyperparameters) can be stored in the second storage area (SR2).

[0082] In one embodiment, the first storage region (SR1) and the second storage region (SR2) may be different planes of the same non-volatile memory device. Alternatively, the first storage region (SR1) and the second storage region (SR2) may be located on different dies. The first storage region (SR1) and the second storage region (SR2) may be located on different packaged chips.

[0083] In one embodiment, the host device may transmit information indicating the type of data to be stored and / or read to the SSD device along with the data to be stored.

[0084] For example, if the host device is data of an artificial intelligence model, it transmits the storage and / or reading of the data to the SSD device along with information indicating the data, and the embedded processor of the SSD device can perform data conversion as described with reference to FIGS. 1 to 10 and then store the data of the artificial intelligence model in the second storage area (SR2).

[0085] For example, if the host device is general data, it transmits the storage and / or reading of the data to the SSD device along with information indicating this, and the embedded processor of the SSD device can store the general data in the first storage area (SR1) without performing data conversion.

[0086] Similarly, in the case of data reading, based on instructions from the host device and / or the area where data is stored, the embedded processor of the SSD device may transmit the switched data to the host device after restoring it, or in the case of general data, transmit it to the host device without restoring the data.

[0087] A method according to one embodiment of the present disclosure may also be implemented in the form of a recording medium comprising computer-executable instructions, such as program modules executed by a computer. A computer-readable medium may be any available medium accessible by a computer and includes both volatile and non-volatile media, and both removable and non-removable media. Additionally, a computer-readable medium may include a computer storage medium. A computer storage medium includes both volatile and non-volatile, removable and non-removable media implemented by any method or technique for storing information, such as computer-readable instructions, data structures, program modules, or other data.

[0088] Although the methods and systems of the present disclosure have been described in relation to specific embodiments, some or all of their components or operations may be implemented using a computer system having a general-purpose hardware architecture.

[0089] The foregoing description of the present disclosure is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present disclosure. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0090] The scope of the present disclosure is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present disclosure.

Claims

1. In a data processing device utilizing multiple level cell non-volatile memory devices, Multiple level cell non-volatile memory devices; and A host device comprising a nonvolatile memory device for storing data to be written to the nonvolatile memory device, reading data stored in the nonvolatile memory device, converting a data code to be stored in the nonvolatile memory device, and restoring the converted data code, The above host device is, A data mapping step of converting input data to be written to the non-volatile memory device into binary data and arranging them to correspond to each memory cell; a data code conversion step of specifying the arranged data as a data code unit to be stored in each memory cell and converting a preset first data code and a third data code into the third data code and the first data code, respectively; and a step of storing the input data in the non-volatile memory device according to the data codes, wherein The above-described multiple level cell-based non-volatile memory devices store N bits (N is a natural number greater than or equal to 2) of data in each memory cell, and The above data code is the above N-bit data, 2 N It includes several data codes, The above first data code is the above 2 N A data processing device that is the data code with the highest power consumption during a read operation among the data codes.

2. In Paragraph 1, The above host device is, A data processing device further performing a data reading step of reading data stored in the above-described non-volatile memory device, wherein the step includes restoring the first data code and the third data code read from each memory cell to the third data code and the first data code, respectively.

3. In Paragraph 1, The above host device is, The genital data code conversion step further performs the step of converting the preset second data code and fourth data code into the fourth data code and second data code, respectively, wherein The above second data code is the above 2 N A data processing device that is the data code with the next highest power consumption after the first data code among the data codes.

4. In Paragraph 1, The above N is 3, and The above first data code is 111, and A data processing device in which the above third data code is 101.

5. In Paragraph 3, The above N is 3, and The above first data code is 111, and The above second data code is 000, and The above third data code is 101, and A data processing device in which the above-mentioned fourth data code is 001.

6. In Paragraph 2, The above host device When performing the above data mapping step, cell-first allocation is performed to arrange data along the column direction of the non-volatile memory device, and A data processing device that, when performing the above data reading step, further performs a step of arranging data according to a baseline assignment that arranges data arranged in a row direction according to the cell first assignment before restoring each data code.

7. In Paragraph 1, The above host device is, The main memory includes data to be written to the non-volatile memory device and data read out after being stored in the non-volatile memory device, wherein A data processing device in which the above data includes weight data or input data for matrix multiplication operations of a neural network model.

8. A method for processing data in a multi-level cell-based non-volatile memory device, (a) A data mapping step of converting input data to be written to the above non-volatile memory device into binary data and arranging them to correspond to each memory cell; (b) specifying the arranged data as data code units to be stored in each memory cell, and converting the preset first data code and third data code into the third data code and first data code, respectively; and (c) a step of storing the input data in a non-volatile memory device according to the data code converted in the above step, wherein The above-described multiple level cell-based non-volatile memory devices store N bits (N is a natural number greater than or equal to 2) of data in each memory cell, and The above data code is the above N-bit data, 2 N It includes several data codes, The above first data code is the above 2 N A data processing method for a non-volatile memory device, wherein the data code that consumes the most power during a read operation is among the data codes.

9. In Paragraph 8, (a) further comprising the step of reading data stored in the non-volatile memory device, wherein the reading step is A method for processing data of a non-volatile memory device, comprising the step of restoring the first data code and the third data code read from each memory cell to the third data code and the first data code, respectively.

10. In Paragraph 8, The above step (b) It further includes the step of converting the preset second data code and fourth data code into the fourth data code and second data code, respectively, and The above second data code is the above 2 N A data processing method for a non-volatile memory device, wherein the data code is the one with the next highest power consumption after the first data code among the data codes.

11. In Paragraph 8, The above N is 3, and The above first data code is 111, and A method for processing data in a non-volatile memory device, wherein the third data code is 101.

12. In Paragraph 10, The above N is 3, and The above first data code is 111, and The above second data code is 000, and The above third data code is 101, and A method for processing data in a non-volatile memory device, wherein the above-mentioned fourth data code is 001.

13. In Paragraph 9, The above step (a) is, It is to perform cell-first allocation that arranges data along the column direction of a non-volatile memory device, and The above step (d) is, A method for processing data in a non-volatile memory device, further comprising the step of arranging data according to a baseline allocation that arranges data arranged in a column direction according to the cell-first allocation according to the above-mentioned cell-first allocation according to the row direction before restoring each data code.

14. A nonvolatile memory device comprising a plurality of nonvolatile memory cells; and It includes a processor that controls the above-mentioned non-volatile memory device, and The above processor is, In response to at least one of the write command and read command of the host device, Input data instructed to be written from the host device is converted into binary data and arranged to correspond to each memory cell, the arranged data is specified as a data code unit to be stored in each memory cell, a preset first data code and a third data code are converted into the third data code and the first data code, respectively, and the input data is transmitted to the non-volatile memory device according to the data code. The above non-volatile memory device is configured so that N bits (N is a natural number greater than or equal to 2) of data are stored in each memory cell, and The above data code is the above N-bit data, 2 N It includes several data codes, The above first data code is the above 2 N An SSD device that is the data code with the highest power consumption during a read operation among the data codes.

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