Apparatus and methods for memory page translations within die architectures
WO2026128207A1PCT designated stage Publication Date: 2026-06-18QUALCOMM INC
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- QUALCOMM INC
- Filing Date
- 2025-11-22
- Publication Date
- 2026-06-18
AI Technical Summary
⚠Technical Problem
Existing die architectures experience increased memory access latencies due to multiple memory address translations required to convert virtual addresses to physical addresses, which is particularly problematic for real-time applications like AI, AR, VR, and cloud-based applications.
⚗Method used
Incorporation of nanowalkers within die architectures to perform memory address translations, reducing the number of memory accesses needed to generate a physical address by offloading translation responsibilities from memory management units and performing translations closer to the memory.
🎯Benefits of technology
Significantly reduces memory access latencies by minimizing the number of memory accesses required, enhancing performance in real-time applications and cloud-based systems.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure US2025056760_18062026_PF_FP_ABST
Abstract
Methods and apparatuses directed to die solutions that reduce memory access latencies are described. In one example, a die includes translation control logic, and memory address translation logic electrically coupled to the translation control logic. The translation control logic receives a virtual memory address for virtual to physical address translation from a requesting device. The translation control logic transmits an address translation request to the memory address translation logic, where the address translation request includes the virtual memory address. Based on the virtual memory address, the memory address translation logic reads one or more translation tables to perform one or more memory address translations. Based on the translations, the memory address translation logic generates a physical memory address. The memory address translation logic then transmits the physical memory address to the translation control logic. The translation control logic transmits the physical memory address to the requesting device.
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