Systems and methods of determining synaptic connection strength

Abstract

Aspects of the present disclosure provide systems and methods for mapping connections across a neuronal network. Certain systems and methods provide for measurement of a connection strength for neurons across a synapse. Determining synaptic connection strength includes receiving a plurality of voltage pulses from a voltage electrode, identifying a first voltage pulse corresponding to a pre-synaptic neuron potential, identifying a second voltage pulse corresponding to a post-synaptic neuron potential, determining a sensitivity of the voltage electrode to the plurality of voltage pulses, correcting the second voltage pulse based on the determined sensitivity of the voltage electrode, and determining a synaptic connection strength based on the corrected second voltage pulse.

Description

SYSTEMS AND METHODS OF DETERMINING SYNAPTIC CONNECTION STRENGTHRELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 734,009, filed December 13, 2024, entitled “Systems and Methods of Determining Synaptic Connection Strength,” by Ham, et al., incorporated herein by reference in its entirety.FIELD OF THE INVENTION

[0002] The present disclosure relates to systems and methods for performing intracellular electrophysiology studies. More specifically, the present disclosure relates to systems and methods for determining the strength of the connection between neurons at a synapse.BACKGROUND

[0003] Understanding the connections and communications across neuronal networks is a paramount challenge in neuroscience. Conventional technologies for neuronal investigations include a patch-clamp electrode, which has been found to be useful for its ability to perform high-sensitivity intracellular recordings that are able to measure not only propagation of action potentials (“APs”) in neurons but also subthreshold events such as postsynaptic potentials (“PSPs”). Subthreshold events, the recording of which typically is not achievable by extracellular recording techniques, may be important for establishing and / or deciphering a synaptic connection map and / or for determining a connection strength between neurons.SUMMARY OF THE DISCLSOURE

[0004] Aspects of the present disclosure provide systems and methods for mapping connections across a neuronal network. Certain systems and methods provide for measurement of a connection strength for neurons across a synapse. Determining synaptic connection strength includes receiving a plurality of voltage pulses from a voltage electrode, identifying a first voltage pulse corresponding to a pre- synaptic neuron potential, identifying a second voltage pulse corresponding to a post-synaptic neuron potential, determining a sensitivity of the voltage electrode to the plurality of voltage pulses, correcting the second voltage pulse based on the determined sensitivity of the voltage electrode, and determining a synaptic connection strength based on the corrected second voltage.- 1 -#14684427vl

[0005] Aspects of the present disclosure provide systems and methods for mapping connections across a neuronal network. The systems and methods provide for measurement of a connection strength for neurons across a synapse. Determining synaptic connection strength includes receiving a plurality of voltage pulses from a voltage electrode, identifying a first voltage pulse corresponding to a pre-synaptic neuron potential, identifying a second voltage pulse corresponding to a post-synaptic neuron potential, determining a sensitivity of the voltage electrode to the plurality of voltage pulses, correcting the second voltage pulse based on the determined sensitivity of the voltage electrode, and determining a synaptic connection strength based on the corrected second voltage pulse.

[0006] Some embodiments provide for a method of determining synaptic connection strength, the method comprising: receiving a plurality of voltage pulses from a voltage electrode, wherein the plurality of voltage pulses corresponds to neuron pulses generated at a synapse between a pre-synaptic neuron and a post-synaptic neuron; identifying a first voltage pulse corresponding to a pre-synaptic neuron potential; identifying a second voltage pulse corresponding to a post-synaptic neuron potential; determining a sensitivity of the voltage electrode to the plurality of voltage pulses; correcting the second voltage pulse based on the determined sensitivity of the voltage electrode; and determining a synaptic connection strength based on the corrected second voltage pulse.

[0007] In some embodiments, identifying a first voltage pulse comprises identifying a voltage peak occurring within 20 seconds of the second voltage pulse.

[0008] In some embodiments, determining the sensitivity of the voltage electrode comprises determining an amplitude of an action potential detected within 20 seconds of the second voltage pulse.

[0009] In some embodiments, correcting the second voltage pulse based on the determined sensitivity comprises determining a correction factor proportional to a ratio between the amplitude of an action potential detected within 20 seconds of the second voltage pulse and a reference amplitude.

[0010] In some embodiments, the reference amplitude is between 60 and 130 mV.

[0011] In some embodiments, determining the synaptic connection strength comprises determining an amplitude of the corrected second voltage pulse.

[0012] In some embodiments, the voltage electrode is a first electrode of an array of electrodes, the array of electrodes being disposed on a substrate.- 2 -#14684427vl

[0013] In some embodiments, the substrate is comprised of a plurality of holes, at least some of the holes being coated with a conductive material in electrical contact with the array of electrodes.

[0014] In some embodiments, identifying a first voltage pulse comprises identifying a voltage pulse having an amplitude between 50 and 200 mV.

[0015] Some embodiments relate to a system for determining synaptic connection strength, the system comprising: an array of electrodes disposed in a substrate that is configured to contact neurons, wherein the array of electrodes includes a first electrode configured to detect voltage pulses from a neuron; at least one computer hardware processor; at least one non- transitory computer-readable storage medium storing processor executable instructions that, when executed by the at least one computer hardware processor, cause the at least one computer hardware processor to perform a method of determining a synaptic connection strength, the method comprising: controlling the array of electrodes to receive a plurality of voltage pulses; receiving a first voltage pulse from the array of electrodes, wherein the first voltage pulse is indicative of a pre-synaptic neuron potential; receiving a second voltage pulse from the array of electrodes, wherein the second voltage pulse is indicative of a post- synaptic neuron potential; determining a sensitivity of a voltage electrode, of the array of electrodes, to the plurality of voltage pulses; correcting the second voltage pulse based on the determined sensitivity of the voltage electrode; and determining a synaptic connection strength based on the corrected second voltage pulse.

[0016] In some embodiments, identifying a first voltage pulse comprises identifying a voltage peak occurring within 20 seconds of the second voltage pulse.

[0017] In some embodiments, determining the sensitivity of the voltage electrode comprises determining an amplitude of an action potential detected within 20 seconds of the second voltage pulse.

[0018] In some embodiments, correcting the second voltage pulse based on the determined sensitivity comprises determining a correction factor proportional to a ratio between the amplitude of an action potential detected within 20 seconds of the second voltage pulse and a reference amplitude.

[0019] In some embodiments, the reference amplitude is between 60 and 130 mV.In some embodiments, determining the synaptic connection strength comprises determining an amplitude of the corrected second voltage pulse.- 3 -#14684427vl

[0020] Some embodiments relate to at least one non-transitory computer-readable storage medium storing processor executable instructions that, when executed by at least one computer hardware processor, cause the at least one computer hardware processor to perform a method of determining a synaptic connection strength, the method comprising: receiving a plurality of voltage pulses from a voltage electrode, wherein the plurality of voltage pulses corresponds to neuron pulses generated at a synapse between a pre-synaptic neuron and a post-synaptic neuron; identifying a first voltage pulse corresponding to a pre-synaptic neuron potential; identifying a second voltage pulse corresponding to a post-synaptic neuron potential; determining a sensitivity of the voltage electrode to the plurality of voltage pulses; correcting the second voltage pulse based on the determined sensitivity of the voltage electrode; and determining a synaptic connection strength based on the corrected second voltage pulse.

[0021] In some embodiments, identifying a first voltage pulse comprises identifying a voltage peak occurring within 20 seconds of the second voltage pulse.

[0022] In some embodiments, determining the sensitivity of the voltage electrode comprises determining an amplitude of an action potential detected within 20 seconds of the second voltage pulse.

[0023] In some embodiments, correcting the second voltage pulse based on the determined sensitivity comprises determining a correction factor proportional to a ratio between the amplitude of an action potential detected within 20 seconds of the second voltage pulse and a reference amplitude.

[0024] In some embodiments, the reference amplitude is between 60 and 130 mV.

[0025] In some embodiments, determining the synaptic connection strength comprises determining an amplitude of the corrected second voltage pulse.

[0026] Some embodiments relate to at least one non-transitory computer-readable storage medium storing processor executable instructions that, when executed by at least one computer hardware processor, cause the at least one computer hardware processor to perform a method of determining a synaptic connection strength, the method comprising: receiving a plurality of voltage pulses from a voltage electrode, wherein the plurality of voltage pulses corresponds to neuron pulses generated at a synapse between a pre-synaptic neuron and a post-synaptic neuron; identifying a first voltage pulse corresponding to a pre-synaptic neuron potential; identifying a second voltage pulse corresponding to a post-synaptic neuron potential; determining a sensitivity of the voltage electrode to the plurality of voltage pulses;- 4 -#14684427vlcorrecting the second voltage pulse based on the determined sensitivity of the voltage electrode; and determining a synaptic connection strength based on the corrected second voltage pulse.

[0027] In some embodiments, identifying a first voltage pulse comprises identifying a voltage peak occurring within 20 seconds of the second voltage pulse.

[0028] In some embodiments, determining the sensitivity of the voltage electrode comprises determining an amplitude of an action potential detected within 20 seconds of the second voltage pulse.

[0029] In some embodiments, correcting the second voltage pulse based on the determined sensitivity comprises determining a correction factor proportional to a ratio between the amplitude of an action potential detected within 20 seconds of the second voltage pulse and a reference amplitude.

[0030] In some embodiments, the reference amplitude is between 60 and 130 mV.BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1A illustrates a microhole array 100 to be used with some embodiments of the technology described herein.

[0032] FIG. IB shows the electrode-cell interface and how membrane potential is measured, in accordance with some embodiments of the technology described herein.

[0033] FIG. 1C shows a schematic view and a corresponding micrograph of a first well and hole arrangement, in accordance with some embodiments of the technology described herein.

[0034] FIG. ID shows a schematic view and a corresponding micrograph of a second well and hole arrangement, in accordance with some embodiments of the technology described herein.

[0035] FIG. IE shows a schematic view and a corresponding micrograph of a third well and hole arrangement, in accordance with some embodiments of the technology described herein.

[0036] FIG. 2 shows a schematic interface between a cell and circuitry underneath the cell, according to some embodiments of the technology described herein.

[0037] FIG. 3 shows action potentials and corresponding voltage responses across a synapse, in accordance with some embodiments of the technology described herein.

[0038] FIG. 4 shows the variability in intracellular signal amplitudes across different electrodes, in accordance with some embodiments of the technology described herein.- 5 -#14684427vl

[0039] FIG. 5 shows the variability for an intracellular signal amplitude over time, in accordance with some embodiments of the technology described herein.

[0040] FIG. 6 shows an illustrative process 600 for determining synaptic connection strength, in accordance with some embodiments of the technology described herein.

[0041] FIG. 7 illustrates an example implementation of a computer system 700 that may be used in connection with any of the embodiments of the disclosure provided herein.DETAILED DESCRIPTION

[0042] Aspects of the present disclosure provide systems and methods for mapping connections across a neuronal network. Certain systems and methods provide for measurement of a connection strength for neurons across a synapse. As an example, by determining a sensitivity of the electrode to synaptic signals, the postsynaptic potential may be used to determine a connection strength between the post-synaptic neuron and the pre- synaptic neuron. The strength of the connection between the presynaptic and postsynaptic neurons may be quantified by normalizing PSPs of a neuron based on its action potential amplitudes. Accordingly, the measurement may be resilient to the electrode-cell interface variation.

[0043] The inventors have recognized and appreciated that when two neurons form a connection, known as a synapse, a voltage “ripple” might be triggered on the membrane of the postsynaptic neuron once the presynaptic neuron fires an action potential. This voltage ripple, referred to as the postsynaptic potential (PSP), indicates the strength of the connection. To extract the synaptic connection strength, it may be important to resolve the amplitude of PSPs and / or the timing of action potentials. Direct access to the intracellular space, such as through a patch clamp probe, would be ideal for achieving high-resolution recordings capable of resolving PSPs. However, patch clamp probes are limited in throughput, allowing simultaneous recordings from only a few neurons which is insufficient for network-level connection strength extraction.

[0044] The inventors have further recognized and appreciated that CMOS microhole arrays may overcome the throughput limitations of patch clamp probes. In particular, a CMOS microhole electrode array can be used to acquire intracellular recordings, allowing the parallelization of intracellular access to thousands of neurons. However, CMOS microhole techniques suffer from two main drawbacks: variability in intracellular signal amplitudes across different electrodes and the variation of signal amplitudes over time.- 6 -#14684427vl

[0045] As a nonlimiting explanation, the variability in signal amplitudes can be understood as a mismatch between electrodes, differences in cell-electrode adhesion, and cell type variability. Currently, no methods exist for uncovering the amplitude of PSPs from large- scale intracellular recordings. Extracting this information, along with the timing of action potentials, would allow for the evaluation of synaptic connection strength between connected neurons on a network scale, leading to the creation of more accurate neuronal network maps. Therefore, the inventors have developed certain new systems and methods to uncover the true PSP amplitudes and reveal the connection strength between neurons.

[0046] Methods described herein may utilize electrode arrays configured to measure intracellular neuronal membrane potentials. A nonlimiting example of a microhole array of electrodes is described below in connection with FIGs. 1A-2. Other electrode arrays capable of detecting membrane potentials from the intracellular space may be used. For example, nanowire or nanoneedle arrays may be used.

[0047] FIG. 1A illustrates a microhole array 100 to be used with some embodiments. Microhole array 100 includes a two-dimensional array of holes. In the example, of FIG. 1A, the two-dimensional array is a 4 x 4 array of individual holes 102. However, the two- dimensional array may have larger dimensions such as an 8 x 8 array, a 16 x 16 array, a 32 x 32 array, a 64 x 64 array, or a 128 x 128 array. While the example dimensions include arrays having a square dimensions, the two-dimensional array may also have rectangular dimensions, as aspects of the technology are not limited in this regard.

[0048] The individual holes 102 may be recessed below a main surface of an insulative passivation layer 106, and each hole 102 may be surrounded by an insulative wall 104 extending above the main surface of the passivation layer 106. Although the passivation layer 106 is schematically depicted to be a single layer, the passivation layer 106 may be comprised of a plurality of insulative layers. In some embodiments, the passivation layer 106 may be comprised of a lower layer of silicon oxide and an upper layer of silicon nitride overlaying the lower layer of silicon oxide. The wall 104 may be shaped as a square, as shown, or may be shaped as a circle, or a triangle, or any shape that surrounds the hole 102. In some embodiments, the wall 104 may be sized and shaped to permit the wall 104 to be covered by a cell. For example, in FIG. 1A, the wall 104 is sized such that a single cell 108 may cover an individual hole 102 and the wall 104, which surrounds the hole 102. The cell 108 shown in FIG. 1A is a neuron cell but it should be understood that the hole array 100 may be used with other types of cells and or non-cell organisms.- 7 -#14684427vl

[0049] According to some embodiments of the two-dimensional array, the portion of the hole array 100 comprised of wall 104 may resemble a well in the hole array 100 and therefore the wall 104 may have a depth that is limited by a thickness of the passivation layer 106. In some embodiments, the thickness of the passivation layer 106 may be greater than 2 micrometers (e.g., 2.5 micrometers or 3.0 micrometers or more), and the depth of the well 104 may be in a range of 0 micrometers to about 2 micrometers (e.g., 0.5 micrometers or 1 micrometers, or 1.5 micrometers, or 2 micrometers).

[0050] In some embodiments, the well 104 may be shaped as a square and may have a dimension of 10 micrometers on each side of the square. In some embodiments, the well may be shaped as a circle having a diameter of 10 micrometers. With a side or a diameter of 10 micrometers, the well 104 may be suitable for use with cells that typically have dimensions that are larger than 10 micrometers.

[0051] According to some embodiments, the hole 102 in the well 104 (i.e., the hole surrounded by the wall 104) may be circular and may have a diameter that is limited by the dimension of the well 104. In some embodiments, the hole 102 may have a diameter in a range of about 1.5 micrometers to less than 10 micrometers. In some embodiments, a depth of the hole 102 may be in a range of about 0.5 micrometers to about 2 micrometers (e.g., 0.5 micrometers or 1 micrometers, or 1.5 micrometers, or 2 micrometers).

[0052] According to some embodiments the present technology, the wall 104 may surround a single hole 102 or may surround a sub-array of a plurality of holes 102. FIG. 1C and FIG. ID schematically show a well 104 surrounding a single hole 102 and a micrograph of an arrangement of 10 micrometers x 10 micrometers wells and their corresponding holes. In some embodiments, adjacent 10 micrometers x 10 micrometers wells 104 may be separated by a distance of about 10 micrometers. The hole in FIG. 1C is relatively larger in diameter than the hold in FIG. ID. The larger hole 102 of FIG. 1C may provide a larger surface area for contacting the cell 108 than the smaller hole 102 of FIG. ID. A larger hole surface area that may contact the cell 108 may be associated with a lower electrical impedance or a higher conductance, which may lead to more robust signals recorded for cells. Each hole 102 may be considered an electrode or a portion of an electrode and may be a vertical extension of an electrode pad on which the hole 102 is fabricated. However, as hole size increases there is also an increased probably that the hold 102 does not get fully covered by a single cell 108. That is, the probability of the larger hole 102 in FIG. 1C being full covered by a single cell 108 is lower than a probability of the smaller hole 102 in FIG. ID being fully covered.- 8 -#14684427vlTherefore, there is a higher probability that a current injected into the cell 108 may have some leakage into a solution surrounding the cell 108 and the hole 102. As such, the larger hole 102 of FIG. 1C is not necessarily better than the smaller hole 102 of FIG. ID. In some embodiments, the hole array 100 may be comprised of a plurality of holes 102 of various dimensions, some larger, some smaller, and some in between. Such variations in dimensions for the holes 102 and / or for the walls 104 may permit a single investigation to yield recordings under a plurality of different cell-hole conditions, which may permit a determination of an optical hole structure (e.g., hole diameter, hole depth) and / or an optimal wall structure (e.g., wall (well) depth, well diameter) for a particular type of cell. FIG. IE shows a well 104 surrounding a sub-array comprised of nine holes 102 and a micrograph of an arrangement of four 10 micrometers x 10 micrometers wells each surrounding nine holes. The nine holes 102 are all connection to a same electrode pad and may be associated with a same electrode. An increase in the number of holes surrounded by the well may increase surface area for contacting the cell 108, which may lead to higher conductance than a single hole 102. In some embodiments, the hole array 100 may be comprised of a plurality of holes 102 of various dimensions and / or a plurality of sub-arrays each comprised of a plurality of holes 102. In some embodiments, some of the sub-arrays may be comprised of fewer holes while some of the sub-arrays may be comprised of smaller holes. As will be appreciated, the hole array 100 may have other combinations of individual holes and / or sub-arrays of holes not specifically described herein.

[0053] The platform in this non-limiting example is configured to measure intracellular signals from thousands of neurons. FIG. IB shows the electrode-cell interface and how membrane potential is measured, in accordance with some embodiments. The electrode voltage Veis recorded at an amplifier input while injecting a current to the electrode. Accordingly, the electrode voltage is a scaled version of the neuronal membrane potential Vm. Specifically, Ve=aVmwhere a < 1 is the coupling strength and reflects the characteristics of the cell-electrode interface. Since the electrode-cell interface varies from pixel to pixel, the coupling strength a also varies from pixel to pixel. Due to this variation of a from pixel to pixel, the absolute amplitude of the post-synaptic potential (PSP) in Vmcan be difficult to extract from the electrode voltage recording Vm. The PSP amplitude is one of the main indications of synaptic connection strength. Therefore, challenges to measuring the PSP amplitude make determinations of the synaptic connection strength difficult. Furthermore, even within a given pixel, the coupling strength a changes over time, which renders the- 9 -#14684427vlextraction of the synaptic connection strength difficult even at a given pixel. For example, the intracellular recording trace of FIG. 5 shows the gradual increase of the recorded signal in a given pixel due to the temporal increase of a.

[0054] The inventors have recognized and appreciated that a technique to estimate the timevarying a(t) for each pixel may be able to estimate the PSP amplitude and thus the synaptic connection strength. The inventors have further recognized and appreciated that the notion that while PSP amplitudes in Vmdepend on synaptic connection strengths, the AP amplitudes in Vm are more or less fixed at Ao for a given type of neuron (for example, Ao ~ 110 mV is typical). Therefore, the inventors have developed various techniques to estimate the timevarying a(t) for each pixel based on acquired potentials traces that include both action potentials (APs) and PSPs. According to some embodiments, certain techniques estimate the coupling strength by the equation a ~ Ve,Ap / Ao at a given instant of an AP measurement, where Ve,AP is the amplitude of the AP measured at the electrode. For a rough approximation, the spike-triggered averaged (STA) waveforms that include PSPs may be analyzed by removing any APs and scaling the PSPs with an averaged a. The STA PSP waveform will be captured by this relationship in expression 1. Expression 1

[0056] In expression 1, N is the total number of trace segments used for STA, Ve,k (t) is the recording trace within the k-th STA time window but with any APs removed (thus only with PSPs included), and ak, average is the averaged a obtained from all the recorded APs in a single pixel trace. For a better approximation, a time-dependent a can be estimated from the closest AP to a given PSP to account for the temporal shifts of a due to cell-electrode interface changes over time. In this case, the STA PSP waveform can be estimated by expression 2. Expression 2

[0058] The only difference between expression 1 and 2 is that ak, near is the a value obtained from the AP event nearest in time to the k-th recording trace.

[0059] While the above example method of estimating the PSP amplitude may be more effective for those traces that include both AP events and PSPs (i.e., strong or active enough chemical synaptic connections), and may be less effective when applied to a recording trace that includes only PSPs (i.e., weaker chemical synaptic connections), the former represents still an appreciable fraction of the total number of connections and these more active synaptic connections are important in understanding the function of the synaptic connectivity map.- 10 -#14684427vl

[0060] FIG. 2 shows a schematic interface between a cell and circuitry underneath the cell, according to some embodiments. Included in FIG. 2 is an insert schematically showing a circuit model for the interface. The cell 208 is shown being situated on top of hole 202. In some embodiments, the cell 208 is in a solution 200. When used with a solution, the hole 202 is also immersed in the solution 200. That is, the hole array, which includes hole 202, may be immersed in the solution 200. Accordingly, only a portion of the hole array is visible in FIG. 2. Included in contact with the solution 200 may be a counter electrode 210, which may be formed of any suitable non-reactive material (e.g., platinum).

[0061] In some embodiments, the hole may be defined within a PtB layer 230 covering surfaces of the hole 202. The PtB layer 230 may be deposited by electrodeposition techniques, which may cause a bulbous portion to be present at comers (e.g., an outer rim of the hole 202), as schematically depicted in FIG. 2. The PtB layer 230 may be electrically in contact with an electrode pad 210, such that the PtB layer 230 may be a layer of metal (e.g., aluminum). The layer of metal may be comprised of one or more integrated circuits fabricated on a same chip as the hole array. For example, the circuitry layer 212 may be comprised of stimulation circuits configured to output a stimulation current and / or a stimulation voltage to the hole 202 via the electrode pad; one or more recording or sensing circuits configured to sense a signal (e.g., a voltage) at the hole 202; and other on-chip circuitry suitable for use in investigations involving the hole array. For example, the circuitry layer 212 may be comprised of stimulation circuits configured to output a stimulation current and / or a stimulation voltage to the hole 202 via the electrode pad; one or more recording or sensing circuits configured to sense a signal (e.g., a voltage) at the hole 202; and other on- chip circuitry suitable for use in investigations involving the hole array. As noted above, the hole 202 may be recessed below a main surface of the passivation layer 206. In some embodiments, the walls 204 of the hole array may be sized to be completely or nearly completely covered by the cell 208. That is, an area bounded by the wall 204 (“wall area”) may be comparable to an area of the cell 208 so as to be covered by the cell 208. A benefit to having the wall area fit within the area of the cell 208 may be understood from the circuit model in the inset of FIG. 2.

[0062] In some embodiments, it may be desirable to measure a membrane potential, Vm, at a membrane 208m of the cell 208. According to some embodiments of the present technology, the membrane potential Vm, may be modeled according to the circuit model in the inset of FIG. 2. In FIG. 2, Rmis an impedance of the membrane 208m and Imis a current through the- 11 -#14684427vlmembrane 208m. The inventors have recognized and appreciated that it may be difficult to measure the membrane potential, Vm; however, the inventors have also recognized that a reasonable estimate of the membrane potential, Vm, may be determined by measuring a junction voltage, Vj, having a value that is closer to the membrane potential, Vm, than in the absence of such minimization.

[0063] According to some embodiments of the present technology, during a measurement process, stimulation circuitry in the circuitry layer 212 may output a known electrode current Ie, which may be injected from the PtB layer 230 to the cell 208, which may promote membrane permeabilization or electroporation of the membrane 208m. In order to promote minimization of the junction membrane impedance Rjmand / or minimization of the electrode impedance, Ze, the electrode current, Ie, may be increased to increase the amount of electroporation of the membrane 208m. Ideally, the electrode current, Ie, may equal the membrane current, Im. The inventors have recognized and appreciated that a cell current, Iceii, injected into the cell 208 may not equal the electrode current, Ie, due to a leakage current, Iieak, leaking into the solution 200. For example, the leakage current, Iieak, may arise from suboptimal contact between the cell 208 and the PtB layer 230, such that the cell 208 does not fully cover the hole 202. The inventors also have recognized that the leakage current, Iieak, may be minimized by blocking possible paths for movement of current from the PtB layer 230 into a bulk portion of the solution. The inventors have recognized that easy fluid flow from a region near a portion of the PtB layer 230 not covered by the cell 208 into the bulk of the solution 200 may be an escape path for current to dissipate easily into the solution 200 and contribute to the leakage current, Iieak, and the inventors have further recognized that by minimizing a size of this escape path the leakage current, Iieak, may be reduced or possibly even eliminated. In some embodiments, the escape path may be minimized by the wall 204, which may function to restrict or even prevent movement of the solution 200 from under the cell 208. That is, when the cell 208 sits on the wall 204 and covers all or nearly all of the wall 204, the solution 200 located with the call 204 (i.e., under the cell 208) is trapped and cannot flow freely in the bulk portion of the solution 200 outside of the wall 204. In some embodiments, even if a small part of the wall 204 is not covered by the cell 208, there may be sufficient restriction of flow of the solution 200 to reduce a magnitude of the leakage current, Iieak, relative to a magnitude of the leakage current, Iieak, when the wall 204 is not present.Thus, by minimizing the leakage current, Iieak, the cell current, Iceii, may be approximated by the electrode current, Ie. In some embodiments, the cell current, Iceii, may be used to- 12 -#14684427vlapproximate the membrane current, Im, by assuming a fixed cell impedance as current that is injected into the cell 208 travels through the cell 208. In the circuit model, the presence of wall 204 may be represented by a solution- sealing impedance, Rs, that restricts movement of the solution and 200 and thus reduces the leakage current, Iieak.

[0064] FIG. 3 shows action potentials and corresponding voltage responses across a synapse, in accordance with some embodiments. As shown in FIG. 3, synapse 300 communicatively couples presynaptic neuron 302 and postsynaptic neuron 304. Presynaptic potentials 306 are produced by presynaptic neuron 302 and postsynaptic potentials 308 are produced by postsynaptic neuron 304 in response to the presynaptic potential 306. In the illustrated example of FIG. 3, presynaptic neuron 302 generates presynaptic potentials 306a, 306b, and 306c in respective time windows Tl, T2, and T3. In response, postsynaptic neuron 304 generates postsynaptic potentials 308a, 308b, and 308c in respective time windows Tl, T2, and T3. Accordingly, potentials 306a and 308a correspond to each other; potentials 306b and 308b correspond to each other; and potentials 306c and 308c correspond to each other.

[0065] In the example of FIG. 3, the signals are shown for only two neurons. Accordingly, the bottom trace which corresponds to signals from the postsynaptic neuron 304 may include action potentials that are associated with other synapses that include neuron 304 sending signals to a different neuron. Similarly, the top trace which corresponds to signals form the presynaptic neuron 302 may include PSPs from neuron 302 in response to action potentials from a different neuron.

[0066] FIG. 4 shows the variability in intracellular signal amplitudes across different electrodes, in accordance with some embodiments. As shown in FIG. 4, the variation of signal amplitudes varies. First signal trace 400 represents the action potential and PSP signals at a first coupling strength. Second signal trace 402 represents the action potential and PSP signals at a second coupling strength. The signal amplitudes may vary between different neurons and / or may vary for a single neuron over time. For example, signal trace 400 may correspond to the signal from a first neuron and signal trace 402 may correspond to the signal from a second neuron. As another example, signal trace 400 may correspond to the signal from a neuron at a first time and signal trace 402 may correspond to the signal from the same neuron at a later second time.

[0067] FIG. 5 shows the variability for an intracellular signal amplitude over time, in accordance with some embodiments. As shown in FIG. 5, plot 500 shows traces of intracellular potentials acquired over time. At an earlier time 502, the signal amplitude is- 13 -#14684427vlsmaller, as shown in plot 506, than at a later time 504, as shown in plot 508. The contact between the neuron and the electrode varies over time. Accordingly, the signal strength varies over time, depending on the connection strength. In the illustrated example of FIG. 5, a ~ 15 / 110 -0.14 at time 1,186 s whereas a ~ 50 / 110 ~ 0.45 at time 1,682 s.

[0068] FIG. 6 shows an illustrative process 600 for determining synaptic connection strength, in accordance with some embodiments. Prior to the start of process 600, the neurons may be cultured and then disposed on an array of electrodes while immersed in a solution, as described above in connection with FIG. 2.

[0069] Process 600 starts with act 602 by receiving a plurality of voltage pulses, in accordance with some embodiments. The voltage pulses may be received from electrode pads of an array of electrodes, such as the array of electrodes described above in connection with FIG. 2. The plurality voltage pulses may include voltage pulses from multiple neurons associated with a synapse. For example, the plurality of voltage pulses may include action potentials and postsynaptic potentials produced by neurons across a synapse. The plurality of voltage pulses may include voltages produced from the same neuron or set of neurons over time. In some embodiments, the plurality of voltage pulses may include voltage pulses from multiple electrode pads in the array of electrodes. Accordingly, the plurality of voltage pulses may include voltage pulses from multiple junctions with action potentials and postsynaptic potentials.

[0070] In some embodiments, receiving the plurality of voltage pulses includes converting the voltages into digital or analog signals to be processed by a processor or processor circuitry. The voltage pulses may be processed by the electronics. For example, the signals received from the electrode pads may be amplified and / or filtered to provide signals easier for analysis.

[0071] Process 600 continues with act 604 by identifying a first voltage pulse, in accordance with some embodiments. Identifying a first voltage pulse includes identifying a potential that corresponds to a pre-synaptic neuron of a neuronal synapse. The potential being an action potential of the pre-synaptic neuron.

[0072] Identifying the first voltage pulse may include identifying from the plurality of voltage pulses a pulse having a particular voltage amplitude and / or voltage pulse profile. In some embodiments, identifying the first voltage pulse includes identifying a voltage pulse having an amplitude between 30 and 200 mV. For example, identifying the first voltage pulse may include identifying a voltage pulse having an amplitude between 30 and 200 mV, 30 and- 14 -#14684427vl150 mV, 50 and 140 mV, or 80 and 130 mV In some embodiments, regardless of the amplitude of the voltage peak, identifying the first voltage peak may include identifying a shape of the voltage pulse profile, including the duration and / or the rate of change of the voltage pulse. For example, depending on the cell type, the duration of the action potential may be a few milliseconds or hundreds of milliseconds. In some embodiments, identifying the first voltage pulse includes analyzing both the pulse amplitude and shape.

[0073] In some embodiments, identifying the first voltage may include identifying from the plurality of voltage pulses a pulse occurring within 10 seconds, 20 seconds, or 30 seconds, etc. of the second pulse.

[0074] Process 600 continues with act 606 by identifying a second voltage pulse, in accordance with some embodiments. Identifying the second voltage pulse includes identifying a voltage signal that occurs after the first voltage signal. In some embodiments, identifying the second voltage pulse includes identifying from the plurality of voltage pulses a second voltage pulse within a time window that follows the first voltage pulse. For example, the second voltage pulse may be identified from within a time window of 0.3 milliseconds to 25 milliseconds. In some embodiments, identifying the second voltage pulse may include identifying from the plurality of voltage pulses a pulse having a particular voltage amplitude relative to the first voltage pulse or relative to a noise level. In some embodiments, identifying the second voltage pulse may include identifying from the plurality of voltage pulses a pulse having a particular pulse profile.

[0075] In some embodiments, the second pulse may be identified prior to identifying the first pulse. For example, the second pulse may be identified as a first act and subsequent to identifying the second pulse, the first pulse may be identified as described in connection with act 604. In some embodiments, pulses may be identified as corresponding to pre-synaptic pulses or post-synaptic pulses as a first act. Subsequent to identifying the likely source of the pulse (e.g., pre or post synaptic) a second pulse is selected. Following selection of a second pulse, a first pulse correlated to the second pulse may be identified. For example, identification of the second pulse may include identifying a voltage that is close to the second voltage, such as within 20 seconds, within 10 seconds, within 5 seconds, or within 2 seconds of the second voltage.

[0076] Process 600 continues with act 608 by determining a sensitivity of a voltage electrode, in accordance with some embodiments. Determining the sensitivity of the voltage electrode includes comparing the received voltage pulse to a reference amplitude. The reference- 15 -#14684427vlamplitude may be representative of the action potential amplitude detected when the neuron contact with the electrode is ideal. As the contact with the electrode vary, the sensitivity of the electrode to the neuron will also vary. Therefore, the sensitivity of the electrode to the neuron may be determined by comparing the actual action potential amplitude to the reference action potential amplitude. In some embodiments, the reference amplitude is between 60 and 130 mV. For example, the reference amplitude is approximately 110 mV.

[0077] In some embodiments, determining the sensitivity of the voltage electrode includes comparing the first voltage pulse to a reference amplitude. In some embodiments, determining the sensitivity of the voltage electrode includes comparing the average voltage amplitude for multiple action potentials with the reference amplitude. For example, some or all of the action potentials received from the electrode may be averaged to obtain an average action potential amplitude which may be compared to the reference amplitude. As another example, an average action potential amplitude may be determined based on the action potentials received within a time window, such as the action potential received within 1 minute, 2 minutes, or 5 minutes. Accordingly, the time window may be a rolling window such that as the contact between the electrode and the neuron change over time, the average action potential amplitude changes.

[0078] Process 600 continues with act 610 by correcting the second voltage pulse, in accordance with some embodiments. Correcting the second voltage pulse includes using the determined sensitivity of the electrode to the neuron, determined in act 608. The sensitivity of the electrode may be expressed as a correction factor ratio of the amplitude of an action potential detected within 20 seconds of the second voltage pulse to the reference action potential. The correction factor ratio may be applied to the second voltage pulse to correct the amplitude of the second voltage pulse for the sensitivity of the electrode.

[0079] Process 600 continues with act 612 by determining a synaptic connection strength. The synaptic connection strength may be proportional to the magnitude of the response of the post-synaptic neuron to the pre-synaptic neuron action potential. Accordingly, in some embodiments, the amplitude of the corrected second neuron may be determinative of the synaptic connection.

[0080] Following act 612, process 600 concludes. Following the conclusion of process 600, the process may be repeated for other neurons such that the synaptic connection strengths for multiple neurons in a neuronal network may be mapped.- 16 -#14684427vl

[0081] FIG. 7 illustrates an example implementation of a computer system 700 that may be used in connection with any of the embodiments of the disclosure provided herein. For example, the processes described herein may be performed using computing system 700. The computing system 700 may include one or more computer hardware processors 702 and one or more non-transitory computer-readable storage media. For example, one or more volatile storage devices 710 and / or one or more non-volatile storage devices 706 (e.g., a hard disk, a flash memory, etc.) may be included with computing system 700. The hardware processor 702 may control writing data to and reading data from the volatile storage device 710 and the non-volatile storage device 706, which may serve as non-transitory computer-readable storage media storing processor-executable instructions for execution by the hardware processor 702.

[0082] Computing system 700 may be embodied in any of a number of forms, such as a rackmounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone, tablet, or any other suitable portable or fixed electronic device, as aspects of the technology described herein are not limited in this respect.

[0083] Also, a computer may have one or more input and output devices. These devices may be used, among other things, to present a user interface. Examples of output devices that may be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that may be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format.

[0084] Such computers may be interconnected by one or more networks in any suitable form, including as a local area network or a wide area network, such as an enterprise network or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks, fiber optic networks, or any suitable combination thereof. As shown in FIG. 7, computing system 700 includes network adapter(s) 704 to facilitate network connectivity.- 17 -#14684427vl

[0085] Having thus described several aspects of at least one embodiment of the technology described herein, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art.

[0086] Such alterations, modifications, and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of disclosure. Further, though advantages of the technology described herein are indicated, not every embodiment of the technology described herein will include every described advantage. Some embodiments may not implement any features described as advantageous herein and in some instances one or more of the described features may be implemented to achieve further embodiments. Accordingly, the foregoing description and drawings are by way of example only.

[0087] The above-described embodiments of the technology described herein may be implemented in any of numerous ways. For example, the embodiments may be implemented using hardware, software, or a combination thereof. When implemented in software, the software code may be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers. Such processors may be implemented as integrated circuits, with one or more processors in an integrated circuit component, including commercially available integrated circuit components known in the art by names such as CPU chips, GPU chips, microprocessor, microcontroller, or co-processor. Alternatively, a processor may be implemented in custom circuitry, such as an ASIC, or semicustom circuitry resulting from configuring a programmable logic device. As yet a further alternative, a processor may be a portion of a larger circuit or semiconductor device, whether commercially available, semi-custom or custom. As a specific example, some commercially available microprocessors have multiple cores such that one or a subset of those cores may constitute a processor. However, a processor may be implemented using circuitry in any suitable format.

[0088] Also, the various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

[0089] In this respect, some aspects of the technology described herein may be embodied as a computer readable storage medium (or multiple computer readable media) (e.g., a computer- 18 -#14684427vlmemory, one or more floppy discs, compact discs (CD), optical discs, digital video disks (DVD), magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments described above. As is apparent from the foregoing examples, a computer readable storage medium may retain information for a sufficient time to provide computer-executable instructions in a non- transitory form. Such a computer readable storage medium or media may be transportable, such that the program or programs stored thereon may be loaded onto one or more different computers or other processors to implement various aspects of the technology as described above. As used herein, the term "computer-readable storage medium" encompasses only a non-transitory computer readable medium that may be considered to be a manufacture (i.e., article of manufacture) or a machine.

[0090] The terms “program” or “software” are used herein in a generic sense to refer to any type of computer code or set of processor-executable instructions that may be employed to program a computer or other processor to implement various aspects of the technology as described above. Additionally, one or more computer programs that when executed perform methods of the technology described herein need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the technology described herein.

[0091] Processor-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed.

[0092] U.S. Provisional Patent Application Serial No. 63 / 734,009, filed December 13, 2024, entitled “Systems and Methods of Determining Synaptic Connection Strength,” by Ham, et al., is incorporated herein by reference in its entirety.

[0093] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also- 19 -#14684427vlallows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, for example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0094] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B,” when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0095] Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed. Such terms are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term).

[0096] The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” “having,” “containing,” “involving,” and variations thereof, is meant to encompass the items listed thereafter and additional items.Unless otherwise specified, the terms “approximately,” “substantially,” and “about” may be used to mean within ±10% of a target value in some embodiments. The terms “approximately,” “substantially” and “about” may include the target value.- 20 -#14684427vl

Claims

CLAIMSWhat is claimed is:

1. A method of determining synaptic connection strength, the method comprising: receiving a plurality of voltage pulses from a voltage electrode, wherein the plurality of voltage pulses corresponds to neuron pulses generated at a synapse between a pre-synaptic neuron and a post-synaptic neuron; identifying a first voltage pulse corresponding to a pre-synaptic neuron potential; identifying a second voltage pulse corresponding to a post-synaptic neuron potential; determining a sensitivity of the voltage electrode to the plurality of voltage pulses; correcting the second voltage pulse based on the determined sensitivity of the voltage electrode; and determining a synaptic connection strength based on the corrected second voltage pulse.

2. The method of claim 1, wherein identifying a first voltage pulse comprises identifying a voltage peak occurring with 20 seconds of the second voltage pulse.

3. The method of claim 2, wherein determining the sensitivity of the voltage electrode comprises determining an amplitude of the first voltage pulse.

4. The method of claim 3, wherein correcting the second voltage pulse based on the determined sensitivity comprises determining a correction factor proportional to a ratio between the amplitude of the first voltage pulse and a reference amplitude.

5. The method of claim 4, wherein the reference amplitude is between 60 and 130 mV.

6. The method of claim 1, wherein determining the synaptic connection strength comprises determining an amplitude of the corrected second voltage pulse.

7. The method of claim 1, wherein the voltage electrode is a first electrode of an array of electrodes, the array of electrodes being disposed on a substrate.- 21 -#14684427vl8. The method of claim 7, wherein the substrate is comprised of a plurality of holes, at least some of the holes being coated with a conductive material in electrical contact with the array of electrodes.

9. The method of claim 1, wherein identifying a first voltage pulse comprises identifying a voltage pulse having an amplitude between 50 and 200 mV.

10. A system for determining synaptic connection strength, the system comprising: an array of electrodes disposed in a substrate that is configured to contact neurons, wherein the array of electrodes includes a first electrode configured to detect voltage pulses from a neuron; at least one computer hardware processor; at least one non-transitory computer-readable storage medium storing processor executable instructions that, when executed by the at least one computer hardware processor, cause the at least one computer hardware processor to perform a method of determining a synaptic connection strength, the method comprising: controlling the array of electrodes to receive a plurality of voltage pulses; receiving a first voltage pulse from the array of electrodes, wherein the first voltage pulse is indicative of a pre-synaptic neuron potential; receiving a second voltage pulse from the array of electrodes, wherein the second voltage pulse is indicative of a post-synaptic neuron potential; determining a sensitivity of a voltage electrode, of the array of electrodes, to the plurality of voltage pulses; correcting the second voltage pulse based on the determined sensitivity of the voltage electrode; and determining a synaptic connection strength based on the corrected second voltage pulse.

11. The system of claim 10, wherein identifying a first voltage pulse comprises identifying a voltage peak occurring within 20 seconds the second voltage pulse.

12. The system of claim 10, wherein determining the sensitivity of the voltage electrode comprises determining an amplitude of the first voltage pulse.- 22 -#14684427vl13. The system of claim 12, wherein correcting the second voltage pulse based on the determined sensitivity comprises determining a correction factor proportional to a ratio between the amplitude of the first voltage pulse and a reference amplitude.

14. The system of claim 13, wherein the reference amplitude is between 60 and 130 mV.

15. The system of claim 10, wherein determining the synaptic connection strength comprises determining an amplitude of the corrected second voltage pulse.

16. At least one non-transitory computer-readable storage medium storing processor executable instructions that, when executed by at least one computer hardware processor, cause the at least one computer hardware processor to perform a method of determining a synaptic connection strength, the method comprising: receiving a plurality of voltage pulses from a voltage electrode, wherein the plurality of voltage pulses corresponds to neuron pulses generated at a synapse between a pre-synaptic neuron and a post-synaptic neuron; identifying a first voltage pulse corresponding to a pre-synaptic neuron potential; identifying a second voltage pulse corresponding to a post-synaptic neuron potential; determining a sensitivity of the voltage electrode to the plurality of voltage pulses; correcting the second voltage pulse based on the determined sensitivity of the voltage electrode; and determining a synaptic connection strength based on the corrected second voltage pulse.

17. The at least one non-transitory computer-readable storage medium of claim 16, wherein identifying a first voltage pulse comprises identifying a voltage peak occurring within 20 seconds the second voltage pulse.

18. The at least one non-transitory computer-readable storage medium of claim 16, wherein determining the sensitivity of the voltage electrode comprises determining an amplitude of the first voltage pulse.- 23 -#14684427vl19. The at least one non-transitory computer-readable storage medium of claim 18, wherein correcting the second voltage pulse based on the determined sensitivity comprises determining a correction factor proportional to a ratio between the amplitude of the first voltage pulse and a reference amplitude.

20. The at least one non-transitory computer-readable storage medium of claim 19, wherein the reference amplitude is between 60 and 130 mV.- 24 -#14684427vl

Images