Communication method and communication apparatus

Abstract

A communication method and a communication apparatus. The method comprises: acquiring a first information bit sequence, and performing distribution matching on a first bit sequence in the first information bit sequence on the basis of a scrambling bit sequence to determine a fourth bit sequence; and encoding an input bit sequence to obtain an encoded bit sequence. The first information bit sequence further comprises a second bit sequence, locations in the input bit sequence are arranged in an order of a first location, a second location, and a third location, the fourth bit sequence is located at the second location in the input bit sequence, and the second location corresponds to the highest-energy amplitude bit in the input bit sequence. Hence, in the method, the fourth bit sequence obtained by means of distribution matching is located at the second location in the input bit sequence, and in an encoding process, systematic bits function as amplitude bits for shaping, thereby improving probabilistic shaping performance.

Description

Communication methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202411914290.0, filed on December 20, 2024, entitled "Communication Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of wireless communication technology, and more specifically, to a communication method and a communication device. Background Technology

[0003] Higher-order modulation refers to mapping multiple bits to the same channel symbol, which can improve spectral efficiency. Common higher-order modulation schemes include quadrature amplitude modulation (QAM), such as 16QAM and 64QAM. Different symbols in higher-order modulation may have different energies; by transmitting more low-energy symbols and fewer high-energy symbols, average energy can be saved. Theoretical analysis shows that for a Gaussian white noise channel, the greatest energy saving occurs when the transmitted symbol distribution follows a Gaussian distribution. Compared to a uniform distribution, up to 1.53 dB of transmit power can be saved.

[0004] Probabilistic shaping (PS) is a common "shaping" technique. It involves cascading a precoder before the encoder to map ("shape") the information bits into a sequence following a specific distribution (the precoder is also called a distribution matcher (DM), or some kind of transformation). Then, during the encoding process, systematic coding is used, ensuring that the aforementioned sequence satisfying the specific distribution ultimately appears directly in the encoded sequence, thus shaping the final modulated symbol. Probabilistic shaping can achieve a higher probability of occurrence for low-energy symbols than for high-energy symbols.

[0005] With the introduction of probabilistic shaping, how to combine the probabilistically shaped output sequence with the systematic code encoding is currently a hot research topic. Summary of the Invention

[0006] This application provides a communication method and a communication apparatus, aiming to improve the performance of probabilistic shaping by introducing a probabilistic shaping pre-transformation before channel coding.

[0007] In a first aspect, a communication method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device is also referred to as an encoding device.

[0008] The method may include: acquiring a first information bit sequence, the first information bit sequence including a first bit sequence and a second bit sequence; performing distribution matching on the first bit sequence according to a scrambling bit sequence to determine a fourth bit sequence, the scrambling bit sequence being determined based on a third bit sequence; encoding an input bit sequence to obtain an encoded bit sequence, wherein a first part of the second bit sequence and / or a second part of the third bit sequence are located at a first position in the input bit sequence, the fourth bit sequence is located at a second position in the input bit sequence, and the remaining parts of the second bit sequence excluding the first part and the remaining parts of the third bit sequence excluding the second part are located at a third position in the input bit sequence, wherein the position order in the input bit sequence is the first position, the second position, and the third position.

[0009] It should be understood that the distribution matching in this application may also be referred to as precoding.

[0010] For example, the first part of the second bit sequence may contain 0 or a non-zero integer number of bits, and the second part of the third bit sequence may contain 0 or a non-zero integer number of bits.

[0011] For example, when there is a punched column during the encoding process, the bit at the first position is used as the bit of the punched column.

[0012] For example, the input bit sequence can be encoded using low-density parity check (LDPC) codes, or other types of encoding methods.

[0013] According to the method provided in this application, the fourth bit sequence is obtained by performing distribution matching on the first bit sequence in the first information bit sequence based on the scrambling bit sequence, and the fourth bit sequence is located at the second position in the input bit sequence. In the encoding process, the system bits are implemented to act as amplitude bit shaping, thereby improving the performance of probability shaping.

[0014] In conjunction with the first aspect, in some possible implementations, the scrambling bit sequence is determined by polar coding of the third bit sequence.

[0015] In conjunction with the first aspect, in some possible implementations, the fourth bit sequence is determined by an XOR operation between the scrambling bit sequence and the first bit sequence.

[0016] In conjunction with the first aspect, in some possible implementations, the method further includes: bit interleaving the encoded bit sequence to obtain an interleaved bit sequence, wherein the bit interleaving is combined with Q... m Related, Q m Indicates the modulation order.

[0017] In conjunction with the first aspect, in some possible implementations, the encoded bit sequence is e0, e1, e2, ... e E-1 The interleaved bit sequence is f0, f1, f2, ... f E-1 f i satisfy: Where 0≤i≤Q m -1, i and j are both integers, W(i) and Q m Related, Q m Indicates the modulation order.

[0018] For example, W(i) can be referred to as the relevant parameters of bit level interleaving.

[0019] In conjunction with the first aspect, in some possible implementations, a first portion of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, the remaining portion of the second bit sequence excluding the first portion is located in a first region at the third position, the third bit sequence is located in a second region at the third position, and the first region is located before the second region.

[0020] For example, the second bit sequence, the fourth bit sequence, and the third bit sequence can be concatenated in the following order: the first part of the second bit sequence, the fourth bit sequence, the remaining part of the second bit sequence excluding the first part, and the third bit sequence to obtain the input bit sequence.

[0021] For example, the first part of the second bit sequence is located at the punch bit, the fourth bit sequence is located at the highest energy amplitude bit, and the remaining part of the second bit sequence excluding the first part and the third bit sequence are located at the second highest energy amplitude bit, or in turn at the second highest energy amplitude bit and the sign bit.

[0022] For example, the first part of the second bit sequence can be viewed as bits placed on punched positions. The first part includes bits of length P, where the value of P can be predefined, and P is less than or equal to the length of the second bit sequence.

[0023] For example, W(i) includes Q m The values ​​of W(i) are 0 to Q. m Integers between -1 and 2a, where the 0th digit of W(i) is 2a, the 1st digit is 2a+1, and the 2nd to Qth digits are integers between -1 and 2a. m The value of -1 does not include 2a and 2a+1, and it increases from 0 to Q. m -1, where a is a positive integer.

[0024] Based on the above technical solution, the concatenation order of the second, fourth, and third bit sequences in the input bit sequence is related to the bit energy level interleaving of the input bit sequence. The fourth bit sequence is located at the second position in the input bit sequence. During the encoding process, the system bits act as amplitude bit shapers, improving the performance of probability shaping.

[0025] In conjunction with the first aspect, in some possible implementations, the second portion of the third bit sequence is located at the first position, the fourth bit sequence is located at the second position, the second bit sequence is located in the first region of the third position, the remaining portion of the third bit sequence excluding the second portion is located in the second region of the third position, and the first region is located before the second region.

[0026] For example, the second bit sequence, the fourth bit sequence, and the third bit sequence can be concatenated in the following order: the second part of the third bit sequence, the fourth bit sequence, the second bit sequence, and the remaining part of the third bit sequence excluding the second part, to obtain the input bit sequence.

[0027] For example, the second part of the third bit sequence is located at the punch bit, the fourth bit sequence is located at the highest energy amplitude bit, and the remaining parts of the second and third bit sequences, excluding the second part, are located at the second highest energy amplitude bit, or successively at the second highest energy amplitude bit and the sign bit.

[0028] For example, the second part of the third bit sequence can be viewed as bits at punched positions. The second part includes bits of length P, where the value of P can be predefined, and P is less than or equal to the length of the third bit sequence.

[0029] For example, W(i) includes Q m The values ​​of W(i) are 0 to Q. m Integers between -1 and 2a, where the 0th digit of W(i) is 2a, the 1st digit is 2a+1, and the 2nd to Qth digits are integers between -1 and 2a. m The value of -1 does not include 2a and 2a+1, and it increases from 0 to Q. m -1, where a is a positive integer.

[0030] Based on the above technical solution, the concatenation order of the second, fourth, and third bit sequences in the input bit sequence is related to the bit energy level interleaving of the input bit sequence. The fourth bit sequence is located at the second position in the input bit sequence. During the encoding process, the system bits act as amplitude bit shapers, improving the performance of probability shaping.

[0031] In conjunction with the first aspect, in some possible implementations, a first portion of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, the third bit sequence is located in a first region of the third position, and the remaining portion of the second bit sequence other than the first portion is located in a second region of the third position, with the first region preceding the second region.

[0032] For example, the second bit sequence, the fourth bit sequence, and the third bit sequence can be concatenated in the following order: the first part of the second bit sequence, the fourth bit sequence, the third bit sequence, and the remaining part of the second bit sequence excluding the first part, to obtain the input bit sequence.

[0033] For example, the first part of the second bit sequence is located at the punched bit, the fourth bit sequence is located at the highest energy amplitude bit, and the third bit sequence and the remaining parts of the second bit sequence except for the first part are located at the sign bit, or in turn at the sign bit and the second highest energy amplitude bit.

[0034] For example, the first part of the second bit sequence can be considered as bits on punched bits. The first part includes bits of length P, where the value of P can be predefined, and P is less than or equal to the length of the second bit sequence.

[0035] For example, W(i) includes Q m The values ​​of W(i) are 0 to Q. m Integers between -1 and 1, where the 0th bit of W(i) has a value of 2, the 1st bit has a value of 3, and the 2nd to Qth bits have a value of 3. m The value of -1 does not include 2 and 3, and it increases from 0 to Q. m -1.

[0036] Based on the above technical solution, the concatenation order of the second bit sequence, the fourth bit sequence, and the third bit sequence in the input bit sequence is related to the bit energy level interleaving of the input bit sequence. Among them, the fourth bit sequence is located at the second position in the input bit sequence. During the encoding process, the system bit acts as an amplitude bit shaper, which improves the performance of probability shaping.

[0037] In conjunction with the first aspect, in some possible implementations, the second portion of the third bit sequence is located at the first position, the fourth bit sequence is located at the second position, the remaining portion of the third bit sequence excluding the second portion of the third bit sequence is located in the first region of the third position, the second bit sequence is located in the second region of the third position, and the first region is located before the second region.

[0038] For example, the second bit sequence, the fourth bit sequence, and the third bit sequence can be concatenated in the following order: the second part of the third bit sequence, the fourth bit sequence, the remaining part of the third bit sequence excluding the second part of the third bit sequence, and the second bit sequence to obtain the input bit sequence.

[0039] For example, the second part of the third bit sequence is a punch bit, the fourth bit sequence is located at the highest energy amplitude bit, and the remaining part of the third bit sequence other than the second part of the third bit sequence is located at the sign bit and the second bit sequence, or in turn at the sign bit and the second highest energy amplitude bit.

[0040] For example, the second part of the third bit sequence can be viewed as bits on punched bits. The second part includes bits of length P, where the value of P can be predefined, and P is less than or equal to the length of the third bit sequence.

[0041] For example, W(i) includes Q m The values ​​of W(i) are 0 to Q. m Integers between -1 and 1, where the 0th bit of W(i) has a value of 2, the 1st bit has a value of 3, and the 2nd to Qth bits have a value of 3. m The value of -1 does not include 2 and 3, and it increases from 0 to Q. m -1.

[0042] Based on the above technical solution, the concatenation order of the second bit sequence, the fourth bit sequence, and the third bit sequence in the input bit sequence is related to the bit energy level interleaving of the input bit sequence. Among them, the fourth bit sequence is located at the second position in the input bit sequence. During the encoding process, the system bit acts as an amplitude bit shaper, which improves the performance of probability shaping.

[0043] In conjunction with the first aspect, in some possible implementations, a first portion of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, the remaining portion of the second bit sequence excluding the first portion is located in a first region at the third position, the third bit sequence is located in a second region at the third position, and the first region is located before the second region.

[0044] For example, the second bit sequence, the fourth bit sequence, and the third bit sequence can be concatenated in the following order: the first part of the second bit sequence, the fourth bit sequence, the remaining part of the second bit sequence excluding the first part, and the third bit sequence to obtain the input bit sequence.

[0045] For example, the first part of the second bit sequence is located at the lowest energy amplitude bit, the fourth bit sequence is located at the highest energy amplitude bit, and the remaining part of the second bit sequence excluding the first part and the third bit sequence are located at the second highest energy amplitude bit, or in turn at the second highest energy amplitude bit and the sign bit.

[0046] For example, in a high-throughput LDPC coding scenario, the number of punctured bits P = 0, or it can be understood that the sequence of punctured bits is an empty set.

[0047] For example, W(i) includes Q m The values ​​of W(i) are 0 to Q. m Integers between -1 and 0, where the 0th bit of W(i) has a value of Q. m -2, the value of the first digit is Q. m -1, from the 2nd to the Qth m The value of -3 does not include Q. m -2 and Q m -1, and increasing from 2 to Q m -1, Qth m The value of -2 bits is 0, and the Qth bit... m The value of the -1 bit is 1.

[0048] Based on the above technical solution, the concatenation order of the second, fourth, and third bit sequences in the input bit sequence is related to the bit energy level interleaving of the input bit sequence. The fourth bit sequence is located at the second position in the input bit sequence. During the encoding process, the system bits act as amplitude bit shapers, improving the performance of probability shaping.

[0049] In conjunction with the first aspect, in some possible implementations, the length of the first information bit sequence is K, and the length of the first bit sequence is L, where L is less than or equal to 2N. re N re The number of symbols in the modulated symbol sequence is represented by k1, where K, L and k1 are all integers.

[0050] In conjunction with the first aspect, in some possible implementations, K satisfies: K = L + k1.

[0051] In conjunction with the first aspect, in some possible implementations, the length of the first part of the second bit sequence is P, where P is an integer.

[0052] In conjunction with the first aspect, in some possible implementations, P takes the value 0, 2Z. c , or Z c Z c This represents the expansion factor.

[0053] For example, P is the number of punch holes, and the size of P can be predefined or preconfigured.

[0054] In conjunction with the first aspect, in some possible implementations, the length of the encoded bit sequence is E, where E = N. re *Q m Q m N represents the modulation order. re This indicates the number of symbols corresponding to the modulated symbol sequence.

[0055] Secondly, a communication method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). This communication device is also called a decoding device.

[0056] The method includes: acquiring information to be decoded; decoding the information to be decoded to obtain a decoded bit sequence, wherein a first part of a second bit sequence and / or a second part of a third bit sequence are located at a first position in the decoded bit sequence, a fourth bit sequence is located at a second position in the decoded bit sequence, and the remaining parts of the second bit sequence excluding the first part and the remaining parts of the third bit sequence excluding the second part are located at a third position in the decoded bit sequence, wherein the position order of the decoded bit sequence is the first position, the second position, and the third position; performing dedistribution matching based on the scrambling bit sequence and the fourth bit sequence to determine a first bit sequence, wherein the scrambling bit sequence is determined based on the third bit sequence; and determining a first information bit sequence, wherein the first information bit sequence includes the first bit sequence and the second bit sequence.

[0057] It should be understood that the second aspect corresponds to the first aspect mentioned above, and supplementary explanations and technical effects can be found in the description of the first aspect mentioned above.

[0058] In conjunction with the second aspect, in some possible implementations, the scrambling bit sequence is determined by polar coding of the third bit sequence.

[0059] In conjunction with the second aspect, in some possible implementations, the first bit sequence is determined by an XOR operation between the scrambling bit sequence and the fourth bit sequence.

[0060] In conjunction with the second aspect, in some possible implementations, decoding the information to be decoded includes: demodulating the information to be decoded to obtain a demodulated bit sequence; and deinterleaving the demodulated bit sequence to obtain a deinterleaved bit sequence, wherein the deinterleaving is combined with Q... m Related, Q m Indicates the modulation order; decodes the deinterleaved bit sequence.

[0061] In conjunction with the second aspect, in some possible implementations, the demodulated bit sequence is f0, f1, f2, ... f E-1 The deinterleaved bit sequence is e0, e1, e2, ... e E-1 e i satisfy:

[0062] Where 0≤i≤Q m -1, i and j are both integers, W(i) and Q m Related, Q m Indicates the modulation order.

[0063] In conjunction with the second aspect, in some possible implementations, a first portion of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, the remaining portion of the second bit sequence excluding the first portion is located in a first region at the third position, the third bit sequence is located in a second region at the third position, and the first region is located before the second region.

[0064] In conjunction with the second aspect, in some possible implementations, the second portion of the third bit sequence is located at the first position, the fourth bit sequence is located at the second position, the second bit sequence is located in the first region of the third position, the remaining portion of the third bit sequence excluding the second portion is located in the second region of the third position, and the first region is located before the second region.

[0065] In conjunction with the second aspect, in some possible implementations, W(i) includes Q. m The values ​​of W(i) are 0 to Q. m Integers between -1 and 2a, where the 0th digit of W(i) is 2a, the 1st digit is 2a+1, and the 2nd to Qth digits are integers between -1 and 2a. m The value of -1 does not include 2a and 2a+1, and it increases from 0 to Q. m -1, where a is a positive integer.

[0066] In conjunction with the second aspect, in some possible implementations, a first portion of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, the third bit sequence is located in a first region of the third position, and the remaining portion of the second bit sequence other than the first portion is located in a second region of the third position, with the first region preceding the second region.

[0067] In conjunction with the second aspect, in some possible implementations, W(i) includes Q. m The values ​​of W(i) are 0 to Q. m Integers between -1 and 1, where the 0th bit of W(i) has a value of 2, the 1st bit has a value of 3, and the 2nd to Qth bits have a value of 3. m The value of -1 does not include 2 and 3, and it increases from 0 to Q. m -1.

[0068] In conjunction with the second aspect, in some possible implementations, a first portion of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, the remaining portion of the second bit sequence excluding the first portion is located in a first region at the third position, the third bit sequence is located in a second region at the third position, and the first region is located before the second region.

[0069] In conjunction with the second aspect, in some possible implementations, W(i) includes Q. m The values ​​of W(i) are 0 to Q. m Integers between -1 and 0, where the 0th bit of W(i) has a value of Q. m -2, the value of the first digit is Q. m -1, from the 2nd to the Qth m The value of -3 does not include Q. m -2 and Q m -1, and increasing from 2 to Q m -1, Qth m The value of -2 bits is 0, and the Qth bit... m The value of the -1 bit is 1.

[0070] In conjunction with the second aspect, in some possible implementations, the length of the first information bit sequence is K, and the length of the first bit sequence is L, where L is less than or equal to 2N. re N re The number of symbols in the modulated symbol sequence is represented by k1, where K, L and k1 are all integers.

[0071] In conjunction with the second aspect, in some possible implementations, K satisfies: K = L + k1.

[0072] In conjunction with the second aspect, in some possible implementations, the length of the first part of the second bit sequence is P, where P is an integer.

[0073] In conjunction with the second aspect, in some possible implementations, P takes the value 0, 2Z. c , or Z c Z c This represents the expansion factor.

[0074] In conjunction with the second aspect, in some possible implementations, the length of the demodulated bit sequence is E, where E = N. re *Q m Q m N represents the modulation order. re This indicates the number of symbols corresponding to the modulated symbol sequence.

[0075] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0076] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0077] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0078] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0079] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0080] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0081] Ninth aspect, a wireless communication system is provided, including the communication device as described in the third aspect and the communication device as described in the fourth aspect. Attached Figure Description

[0082] Figure 1 shows an example of a communication system applicable to the technical solution of this application.

[0083] Figure 2 is a schematic diagram of the basic process of wireless communication.

[0084] Figure 3 is a flowchart of a plastic surgery technique.

[0085] Figure 4 is a schematic diagram of a constellation point distribution.

[0086] Figure 5 is a schematic diagram of the principle of distribution matching based on polar codes.

[0087] Figure 6 is a schematic diagram of the parity check matrix H of an LDPC.

[0088] Figure 7 is a Tanner plot of the parity-check matrix H of an LDPC.

[0089] Figure 8 is a schematic diagram of the structure of a check matrix.

[0090] Figure 9 is a schematic flowchart of a communication method provided in an embodiment of this application.

[0091] Figure 10 is a schematic block diagram of the positional distribution of the input bit sequence provided in an embodiment of this application.

[0092] Figure 11 is a schematic structural diagram of a communication device provided in this application.

[0093] Figure 12 is a schematic structural diagram of another communication device provided in this application.

[0094] Figure 13 is a schematic structural diagram of the chip provided in this application. Detailed Implementation

[0095] The technical solutions of this application can be applied to various existing and future communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, and future communication systems. Furthermore, they can also be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0096] Figure 1 illustrates an example of a communication system applicable to the technical solutions of this application. As shown in Figure 1, the communication system may include one or more transmitters and one or more receivers. Optionally, one of the transmitters and receivers may be a terminal device, and the other may be a network device. The channel coding or decoding method provided in this application is applicable to communication between the network device and the terminal device shown in Figure 1, i.e., uplink or downlink communication. For example, in downlink communication, the transmitter in this embodiment is a network device, and the receiver is a terminal device; in uplink communication, the transmitter is a terminal device, and the receiver is a network device.

[0097] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0098] In this embodiment, the device used to implement the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the terminal side and can be configured within or used in conjunction with the terminal device. The chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the corresponding functions of the terminal device.

[0099] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device performing base station functions in D2D, V2X, and M2M communications, a network device (e.g., a base station) in a future communication network, or a device performing network device functions. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0100] Base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0101] In some deployments, the network device in this application embodiment may be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network device may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0102] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0103] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0104] In this embodiment, the device used to implement the functions of the network device can be the network device itself; it can also be a device capable of supporting the network device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the network side and can be configured within or used in conjunction with the network device. In this embodiment, only the network device is used as an example to illustrate the implementation of the corresponding functions of the network device.

[0105] Figure 2 is a schematic diagram of the basic process of wireless communication. As shown in Figure 2, at the signal transmitting end, the signal source is transmitted after sequentially undergoing source coding, channel coding, and digital modulation. At the signal receiving end, the received signal is sequentially processed through digital demodulation, channel decoding, and source decoding before being output to the destination. Among these processes, channel coding and decoding is one of the core technologies in the field of wireless communication.

[0106] The channel coding or decoding methods provided in this application can be used in dedicated network devices or general-purpose devices, and can be applied to the various network devices (e.g., base stations) and the various terminal devices mentioned above. Specifically, the channel coding scheme is mainly implemented by the channel coding unit (e.g., encoder or device that supports the coding device to perform the corresponding function) in these devices; the channel decoding scheme is mainly implemented by the channel decoding unit (e.g., decoder or device that supports the decoding device to perform the corresponding function) in these devices.

[0107] Optionally, the functions of the encoding or decoding device can be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., program code in memory), or by a combination of both, without limitation.

[0108] To facilitate understanding of the embodiments provided in this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0109] 1. Modulation and demodulation

[0110] Referring to Figure 2 above, the transmitting end can also map the encoded bit sequence to a modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and obtain the sequence to be decoded through demodulation. Modulation refers to the transmitting end mapping the encoded bit sequence to a constellation based on a constellation diagram to obtain the modulation symbol sequence. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0111] For example, the encoded bit sequence can be mapped to the modulation symbol sequence by referring to a lookup table or according to a preset rule. Here, only a lookup table is used as an illustration. As shown in Table 1, it is a bit mapping relationship of 8ASK. During the modulation process, the modulation symbol x is determined according to bits b0, b1 and b2, which is used as the modulation symbol to be transmitted.

[0112] Table 1: Mapping between bit values ​​and modulation symbols

[0113] When using 8ASK modulation, the encoded bit sequence can be mapped to a modulation symbol sequence according to the bit values, referring to Table 1. When using QAM (such as 16QAM, 64QAM, etc.) modulation, the QAM constellation diagram has real and imaginary parts, which can be mapped to the modulation symbol sequence according to Table 1 or other tables, respectively. This application does not elaborate on this further.

[0114] It should be understood that different bits have different functions when mapping the encoded bit sequence to the modulation symbol sequence. For example, in Table 1, bit b0 is used to determine the quadrant of the modulation symbol, so bit b0 is also called the symbol bit. Bits b1 and b2 are used to determine the amplitude of the modulation symbol, so bits b1 and b2 are also called amplitude bits. Furthermore, the transmission reliability of bits b0, b1, and b2 decreases in that order, that is, the transmission reliability satisfies the following relationship: transmission reliability of b0 > transmission reliability of b1 > transmission reliability of b2.

[0115] It should also be understood that the values ​​of the modulation symbols in Table 1 (i.e., the magnitude of x) are only examples. In actual applications, x can be adjusted according to power consumption requirements, such as scaling up or down the multiple x values ​​shown in Table 1 by the same proportion.

[0116] 2. Distribution matching, or probability shaping.

[0117] Higher-order modulation maps multiple bits to the same modulation symbol, thereby further improving spectral efficiency. Common higher-order modulation schemes include 16QAM and 64QAM, without specific limitations. 16QAM maps 4 bits to one modulation symbol, while 64QAM maps 6 bits to one modulation symbol.

[0118] In higher-order modulation, different symbols may have different energies. As shown in Table 1 above, the energies of the modulation symbols from highest to lowest are: modulation symbol -7 (modulation symbol 7), modulation symbol -5 (modulation symbol 5), modulation symbol -3 (modulation symbol 3), and modulation symbol -1 (modulation symbol 1). Among them, modulation symbol -7 has the same energy as modulation symbol 7, modulation symbol -5 has the same energy as modulation symbol 5, modulation symbol -3 has the same energy as modulation symbol 3, and modulation symbol -1 has the same energy as modulation symbol 1.

[0119] By transmitting more low-energy symbols and fewer high-energy symbols, average energy can be saved. Theoretical analysis shows that for a Gaussian white noise channel, the information transmitted per unit energy is maximized when the transmitted symbol distribution follows a Gaussian distribution. Compared to a uniform distribution, the Gaussian distribution has the best performance, theoretically offering a performance gain of 1.53 dB.

[0120] Distribution matching, also known as probabilistic shaping or precoding, is a common shaping technique. A typical flowchart is shown in Figure 3. Figure 3 illustrates another processing flow for the source and sink. The difference between Figure 3 and Figure 2 is that in Figure 3, the transmitting device needs to perform distribution matching, and the receiving device needs to perform dedistribution matching (or deprobabilistic shaping). As shown in Figure 3, by cascading a precoder before channel coding, the information bits are mapped (or "shaped") to a bit sequence that follows a specific distribution. Therefore, the precoder is also called a distribution matcher (DM). Then, during channel coding, systematic coding is used so that the sequence satisfying the specific distribution ultimately appears directly in the coded sequence, thus shaping the final modulation symbols. As an example, the constellation point distribution after "shaping" is shown in Figure 4. It can be seen that the probability of low-energy symbols appearing is higher than that of high-energy symbols.

[0121] In this application, distribution matching can also be simply referred to as shaping, which will be explained uniformly here and will not be elaborated on later.

[0122] For example, given 500 information bits, 100 information bits are not distributed and the remaining 400 information bits are distributed to obtain a bit sequence that follows a specific distribution, which consists of 512 bits. Then, channel coding is performed on the 100 information bits and the resulting 512 bits.

[0123] For example, one implementation of distribution matching could be a distribution matching method based on polar codes.

[0124] Figure 5 is a schematic diagram illustrating the principle of distribution matching based on polar codes. The left side of Figure 5 shows the bit sequence to be encoded during the polar coding process. This bit sequence consists of two parts: one part can be called frozen bits, which are generally set to 0; the other part can be called auxiliary bits, which can be used to fill the third bit sequence and assist in shaping the scrambling bit sequence. The right side of Figure 5 shows the scrambling bit sequence, which can be considered as the bit sequence after polar code encoding. The polar code encoding process can be represented as follows: It is a bit sequence of length N to be encoded, where N is the code length of the polar code. G N It is an N×N matrix, and This is the Kronecker product of n = log N matrices F2. G N This can be called a polarization coding matrix or a polarization transformation matrix. Assume the length of the polar code's mother code is N, and the length of the scrambling bit sequence is E, where E = N. This can be found in the set of indices corresponding to the frozen bits. The indicated bit position is set to 0 (frozen bit). The third bit sequence is obtained from a portion of the bit sequence to be encoded (e.g., the first bit sequence), thus obtaining the set of indices corresponding to the auxiliary bits. The bit values ​​in the third bit sequence it carries. Among them, Including A elements, It includes S elements, S = EA. Taking E = N = 4 and A = 3 as an example, we have: Placed as a freeze position The third bit sequence is obtained from the first bit sequence (1,1,1,0) as (1). The third bit sequence u3 = 1 is filled as an auxiliary bit. Furthermore, the first scrambling sequence can be obtained from u3. For example, The fourth bit sequence (0,0,0,1) is obtained by XORing the first bit sequence and the scrambling bit sequence.

[0125] The purpose of distribution matching is to make the number of 0s in the fourth bit sequence greater than the number of 1s. For example, the technical effect of distribution matching can be achieved by increasing the number of 0s in the scrambling bit sequence from 1 to 3.

[0126] 3. LDPC code

[0127] LDPC codes are linear block codes, and their parity-check matrix (PCM) is a sparse matrix. The number of zero elements in an LDPC PC ...

[0128] In 1981, Tanner represented the codewords of LDPC using a graph, now known as a Tanner graph. Tanner graphs correspond one-to-one with parity-check matrices. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity-check nodes, representing parity-check constraints. Each parity-check node represents a parity-check constraint, as illustrated in Figures 6 and 7 below.

[0129] Figure 6 is a schematic diagram of the parity check matrix H of an LDPC.

[0130] In Figure 6, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 6, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0131] Figure 7 is a Tanner plot of the parity-check matrix H of an LDPC.

[0132] As shown in Figure 7, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices, with one vertex serving as both the start and end point, and passing through each node only once. The length of a cycle is defined as the number of connections it contains, and the circumference of the graph, also known as the size of the graph, is defined as the minimum cycle length in the graph. In Figure 7, the circumference is 4, as shown by the bolded connection. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bit in the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, then the element (i, j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge.

[0133] Furthermore, in a Tanner graph, a cycle is a closed loop consisting of variable nodes, check nodes, and connecting edges that are connected end to end.

[0134] As mentioned above, LDPC is a linear block code. A linear block code divides the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0135] 4. Quasi-cyclic low-density parity check (QC-LDPC) code

[0136] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BG An element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0137] Based on the basis matrix and the boosting value Z c (Lifting size) allows the base matrix to be expanded into a complete parity-check matrix for encoding or decoding. In this application, Z... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements in the basis matrix to a Z-shape. c ×Z c A square matrix, in which 0 is promoted to Z. c ×Z c The zero matrix is ​​promoted to an identity matrix, and then cyclically shifted based on the shifting value (SV) corresponding to the 1. This cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, 2, and 3, the cyclically shifted matrix after shifting to the right is as follows:

[0138] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0139] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0140] (3) When the translation value is 2, the corresponding cyclically shifted matrix is:

[0141] (4) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0142] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. b The elements in it can also be called QC blocks.

[0143] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0144] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the array represents a Z. c Square matrix of order Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0145] For example, As shown below:

[0146] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0147] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0148] The aforementioned exponential matrix can also be called a base graph (BG). For example, base graphs include BG1, BG2, etc. In this application, the base matrix will be used to describe the embodiments of this application. It is understood that the aforementioned exponential matrix has corresponding characteristics.

[0149] 5. Column weight and row weight

[0150] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0151] 6. Structure of the parity check matrix

[0152] Figure 8 is a schematic diagram of the structure of a parity check matrix.

[0153] As shown in Figure 8(a), a parity check matrix for an LDPC can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 8(b). Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest rate, or a parity with a degree greater than or equal to 2, or a parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 8(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 8(b). The raptor-like region can correspond to part E in Figure 8(b) and can be an identity matrix corresponding to the parity bits of the low-rate extension.

[0154] Among them, region A is the region corresponding to the high bitrate information column (or the region of the highest bitrate information column), region B is the region corresponding to the core verification of the high bitrate, region C is the zero matrix, region D is the incremental redundancy part of the verification matrix and corresponds to the low bitrate, and region E is the incremental redundancy region and is an identity matrix.

[0155] The parity-check matrix of the LDPC code shown in Figure 8 adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high code rate core matrix. In actual use, as shown in Figure 8(a), the first X rows and the first Y columns of the parity-check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0156] It should be understood that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and the schematic diagram of the basis matrix is ​​similar to that in Figure 8.

[0157] As an example, the basis matrices of the 5G LDPC code include BG1 and BG2. BG1 is a 46x68 matrix, and BG2 is a 42x52 matrix. Both BG1 and BG2 have the matrix structure shown in Figure 8(b), for example, containing multiple regions as shown in Figure 8(b). Region A corresponds to the high-rate information column (or the region with the highest code rate), region B corresponds to the core checksum of the high code rate, region C is a zero matrix, region D is the incremental redundancy part of the basis matrix and corresponds to the low code rate, and region E is the incremental redundancy region and is an identity matrix. The values ​​of the basis matrix are 0 or 1; a value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph, or the association between the checksum and the variable.

[0158] It should be understood that BG1 and BG2 are designed for the lowest bitrate. When different bitrates need to be supported, the upper left portion of BG1 or BG2 can be used. Figure 8(a) shows the matrix regions corresponding to different bitrates. The rows and columns of each dashed box region form a base matrix. As the size of the dashed box region increases, the bitrate of the corresponding base matrix gradually decreases. When rows and columns of the high bitrate region shown in Figure 8(a) are selected from BG1 or BG2 to form the base matrix, the bitrate of this base matrix is ​​the highest; therefore, this base matrix is ​​also called the highest bitrate matrix. When more rows and columns than the high bitrate region are selected from BG1 or BG2 to form the base matrix, the bitrate of this base matrix is ​​lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases.

[0159] For example, please refer to Figure 8(c), which is a schematic diagram of the high bitrate region of BG1. The high bitrate region of BG1 is a matrix region composed of region A and region B of BG1. Region A is a 4x22 matrix used to carry data information, and region B is a 4x4 matrix used to carry check information. When the first two columns are punched, the bitrate supported by the high bitrate region is 22 / (22+4-2)=11 / 12≈0.917.

[0160] Currently, BG1 or BG2 has fixed punched columns, for example, the first two columns of region A. To further improve the bitrate, while punching columns in region A, columns in region B are also punched. For example, Figure 8(d) is another schematic diagram of the high bitrate region of BG1, in which the first two columns of region A and the last column of region B can be punched.

[0161] 7. Information column and validation column

[0162] The columns of the LDPC base matrix consist of information columns and check columns.

[0163] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0164] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. Extended check columns can also be called raptor-like columns.

[0165] 8. Core rows, core columns, core matrix, and core check columns

[0166] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0167] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0168] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part composed of part A and part B.

[0169] Core check columns: N columns following the information columns in the LDPC base matrix, where N equals the number of rows corresponding to the core rows. For example, the information columns are 1 to K. b If the column is K, then the core verification column is K. b +1 to K b +N columns.

[0170] 9. Message length, code length, and code rate

[0171] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0172] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0173] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0174] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, media access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0175] It should be understood that the method provided in this application can combine probabilistic shaping with various types of encoding methods. For example, taking LDPC codes, the method provided in this application can be applied to LDPC codes, QC-LDPC codes, spatially-coupled (SC) LDPC codes, high-throughput LDPC codes, or globally coupled (GC) LDPC codes, etc. Furthermore, the method provided in this application can also combine probabilistic shaping with other types of encoding methods, which will not be listed individually here.

[0176] As discussed above, introducing probabilistic shaping into the coding process typically involves precoding before channel coding, and then using the precoded sequence as input for channel coding. Improving the performance of probabilistic shaping in this context is currently a hot research topic.

[0177] This application provides a communication method that aims to improve the performance of probabilistic shaping by introducing a probabilistic shaping pre-transformation before channel coding.

[0178] The communication method provided in this application is described in detail below.

[0179] Figure 9 is a schematic flowchart of the communication method 900 provided in this application. The method includes the following steps.

[0180] It is understood that method 900 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to perform this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0181] 901, The sending device acquires the first information bit sequence.

[0182] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, the sending device needs to first obtain the information bit sequence (e.g., the first information bit sequence) corresponding to the signal to be sent to the receiving device.

[0183] The process of the transmitting device acquiring the first information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the first information bit sequence; or, the transmitting device acquiring the first information bit sequence can also refer to: the transmitting device receiving the first information bit sequence from other communication devices. This application does not limit the specific method of acquiring the first information bit sequence.

[0184] The first information bit sequence includes a first bit sequence and a second bit sequence.

[0185] For example, the length of the first information bit sequence is K, the length of the second bit sequence is L, and the length of the third bit sequence is k1, where the length L of the first bit sequence is less than or equal to 2N. re N re N represents the number of symbols in the modulated symbol sequence. re The values ​​of are predefined or preconfigured. K, L, and k1 are all integers. The first bit sequence can be represented as: a 0,0 ,a 0,1 ,a 0,2 ,…a 0,L-1 The second bit sequence can be represented as: a 1,0 ,a 1,1 ,a 1,2 ,…a 1,k1-1 .

[0186] In one possible implementation, the length K of the first information bit sequence is equal to the sum of the lengths of the first bit sequence and the second bit sequence, i.e., K = L + k1. In this case, it can be understood that the first information bit sequence is composed of the first bit sequence and the second bit sequence, or that the first information bit sequence is divided into the first bit sequence and the second bit sequence.

[0187] 902. The transmitting device performs distribution matching on the first bit sequence based on the scrambling bit sequence to determine the fourth bit sequence.

[0188] For example, after the transmitting device obtains the first information bit sequence, it performs distribution matching on the first bit sequence in the first information bit sequence according to the scrambling bit sequence to determine the fourth bit sequence. The scrambling bit sequence is determined based on the third bit sequence. Both the scrambling bit sequence and the fourth bit sequence have a length of L, meaning their lengths are equal to the length of the first bit sequence.

[0189] For example, the third bit sequence can be represented as: a 3,0 ,a 3,1 ,a 2,2 ,…a 3,S-1 The length of the third bit sequence is S, where S is a positive integer less than or equal to L. The fourth bit sequence can be represented as: a 4,0 ,a 4,1 ,a 4,2 ,…a 4,L-1 .

[0190] For example, the scrambling bit sequence is determined by polar coding of the third bit sequence. For a detailed example of the determination method, please refer to the above introduction on probability shaping.

[0191] For example, the fourth bit sequence is determined by XORing the scrambling bit sequence and the first bit sequence. For a detailed example in Figure 5 above, please refer to the specific implementation.

[0192] 903. The transmitting device encodes the input bit sequence to obtain the encoded bit sequence.

[0193] For example, after determining the fourth bit sequence, the transmitting device determines the input bit sequence based on the fourth bit sequence. This input bit sequence includes the fourth bit sequence, the second bit sequence, and the third bit sequence. The transmitting device encodes the input bit sequence to obtain the encoded bit sequence.

[0194] It should be understood that the encoding method can be the LDPC encoding described above. For detailed encoding process, please refer to the existing description. The specific encoding process will not be elaborated in this application.

[0195] For example, the length of the encoded bit sequence is E, where E = N. re *Q m Q m This indicates the modulation order. For example, the encoded bit sequence can be represented as: e0, e1, e2, ... e E -1.

[0196] It should be understood that the input bit sequence includes a first position, a second position, and a third position. The order of these positions is: first position, second position, third position. The specific positions of the fourth bit sequence, the second bit sequence, and the third bit sequence within the input bit sequence can be: the first part of the second bit sequence and / or the second part of the third bit sequence are located at the first position, the fourth bit sequence is located at the second position, and the remaining parts of the second bit sequence (excluding the first part) and the remaining parts of the third bit sequence (excluding the second part) are located at the third position.

[0197] It should be understood that the length of the first part of the second bit sequence can be 0 or a non-zero integer; the length of the second part of the third bit sequence can be 0 or a non-zero integer.

[0198] It should also be understood that when the first part of the second bit sequence is located at the first position, the length of the first part of the second bit sequence can be P; when the second part of the third bit sequence is located at the first position, the length of the second part of the third bit sequence can be P; when the first part of the second bit sequence and the second part of the third bit sequence are both located at the first position, the sum of the lengths of the first part of the second bit sequence and the second part of the third bit sequence can be P. Here, P can be a predefined or pre-configured number of punched positions. For example, the value of P can be 0, 2Z, or higher. c , or Z c Z c This represents the expansion factor.

[0199] It should also be understood that when the first part of the second bit sequence and the second part of the third bit sequence are located in the first position, the positional relationship (e.g., sequential relationship, intersection relationship) between the first part of the second bit sequence and the second part of the third bit sequence in the first position is not limited in this application.

[0200] The following is an example of the bit sequence at a specific position in the input bit sequence.

[0201] Example 1: The first part of the second bit sequence is located in the first position, the fourth bit sequence is located in the second position, the remaining part of the second bit sequence excluding the first part is located in the first region of the third position, and the third bit sequence is located in the second region of the third position. As shown in (1) of Figure 10.

[0202] The third position comprises the first region and the second region, with the first region preceding the second region. That is, the positional order in the input bit sequence is: first position, second position, first region, second region. The size of the first region is equal to the size of the remaining portion of the second bit sequence excluding the first part, and the size of the second region is related to the size of the third bit sequence.

[0203] It should be understood that the first part of the second bit sequence is located at the first position, that is, the length of the first part of the second bit sequence is P. For example, the first part of the second bit sequence can be represented as: a 1,0 ,a 1,1 ,a 1,2 ,…a 1,P-1 , that a 1,0 ,a1,1 ,a 1,2 ,…a 1,P-1 This is merely an example; the first part could be the second bit sequence: a 1,0 ,a 1,1 ,a 1,2 ,…a 1,k1-1 Given any P bits in the second bit sequence. If the first part of the second bit sequence is located at the first position, then the length of the second part of the third bit sequence is 0, meaning the remaining part of the third bit sequence excluding the second part constitutes the third bit sequence.

[0204] It should also be understood that, as shown in (1) of Figure 10, the first position is the punched bit, the second position is the highest energy amplitude bit, and the third position includes part and all of the second highest energy amplitude bit, the sign bit, and the lowest energy amplitude bit. The remaining part of the second bit sequence excluding the first part and the third bit sequence are placed sequentially in the third position. In this embodiment, the third position shown in Figure 10 does not include the parity bit. In the input bit sequence, the position other than the first position, the second position, and the parity bit can be considered as the third position, which is located before the parity bit. The size of each position in the input bit sequence (e.g., the first position, the second position, the third position, and the parity bit) is not limited in this application. The accompanying figure shown in Figure 10 is merely an example and not a limitation.

[0205] As shown in (1) of Figure 10, the second highest energy amplitude bit is located after the highest energy amplitude bit and before the sign bit.

[0206] Suppose that the second-highest energy amplitude bit includes multiple second-highest energy amplitude bits (e.g., first high-energy amplitude bit, second high-energy amplitude bit), and the first and second high-energy amplitude bits are located in the second-highest energy amplitude bits in descending order of energy. For example, if the energy of the first high-energy amplitude bit is higher than that of the second high-energy amplitude bit, then the corresponding positions of the input bit sequence are, in order: punch bit, highest energy amplitude bit, first high-energy amplitude bit, second high-energy amplitude bit, sign bit, and lowest energy amplitude bit. The remaining part of the second bit sequence (excluding the first part) and the third bit sequence are located in the first high-energy amplitude bit, second high-energy amplitude bit, and sign bit in that order. Suppose that the sum of the lengths of the remaining part of the second bit sequence (excluding the first part) and the third bit sequence is greater than the sum of the lengths of the first and second high-energy amplitude bits, but less than the first high-energy amplitude bit, and the second high-energy amplitude bit is the sum of the lengths of the sign bit and the second high-energy amplitude bit, then the position of the sign bit (excluding the third bit sequence) can be used as a check bit.

[0207] Furthermore, assume that when there is no second-highest energy amplitude bit, i.e., the length of the second-highest energy amplitude bit is 0. The corresponding positions of this input bit sequence are, in order: punch bit, highest energy amplitude bit, sign bit, and lowest energy amplitude bit. The remaining part of the second bit sequence (excluding the first part) and the third bit sequence are located in the sign bit and lowest energy amplitude bit, respectively. Assuming that the sum of the lengths of the remaining part of the second bit sequence (excluding the first part) and the third bit sequence is greater than the length of the sign bit but less than the sum of the lengths of the sign bit and the lowest energy amplitude bit, then the remaining part of the second bit sequence (excluding the first part) and the third bit sequence are located in the sign bit and part of the lowest energy amplitude bit, respectively. The position in the lowest energy amplitude bit, excluding the third bit sequence, can be used as a parity bit.

[0208] It should be understood that the energy amplitude bits in the embodiments of this application are exemplified using the highest energy amplitude bit, the second highest energy amplitude bit, and the lowest energy amplitude bit as examples, and are not limited to or necessarily include each of the highest energy amplitude bit, the second highest energy amplitude bit, and the lowest energy amplitude bit. Those skilled in the art can combine the examples given in this application with actual application scenarios to transform or adjust the energy amplitude bits, and all such transformations are applicable to the methods provided in this application.

[0209] Example 2: The second part of the third bit sequence is located in the first position, the fourth bit sequence is located in the second position, the second bit sequence is located in the first region of the third position, and the remaining part of the third bit sequence excluding the second part is located in the second region of the third position. As shown in (2) of Figure 10.

[0210] It should be understood that the second part of the third bit sequence is located at the first position, that is, the length of the second part of the third bit sequence is P. For example, the second part of the third bit sequence can be represented as: a 3,0 ,a 3,1 ,a 3,2 ,…a 3,P-1 , where a 3,0 ,a 3,1 ,a 3,2 ,…a 3,P-1 As just one example, the second part can be any P bits in the third bit sequence. Wherein, if the second part in the third bit sequence is located at the first position, then the length of the first part in the second bit sequence is 0, that is, the remaining part of the second bit sequence excluding the first part is the second bit sequence.

[0211] It should also be understood that, as shown in (2) of 10 above, the first position is the punched bit, the second position is the highest energy amplitude bit, and the third position includes part and all of the second highest energy amplitude bit, the sign bit, and the lowest energy amplitude bit. Among them, the remaining parts of the second bit sequence and the third bit sequence, excluding the second part, are placed in the third position in sequence.

[0212] Example 3: The first part of the second bit sequence is located in the first position, the fourth bit sequence is located in the second position, the third bit sequence is located in the first region of the third position, and the remaining part of the second bit sequence excluding the first part is located in the second region of the third position. As shown in (3) of Figure 10.

[0213] It should be understood that the first part of the second bit sequence is located at the first position. Therefore, the length of the second part of the third bit sequence is 0. That is, the remaining part of the third bit sequence excluding the second part is the third bit sequence.

[0214] It should also be understood that, as shown in (3) of 10 above, the first position is the punched bit, the second position is the highest energy amplitude bit, and the third position includes part and all of the sign bit, the second highest energy amplitude bit, and the lowest energy amplitude bit. Among them, the remaining parts of the third bit sequence and the second bit sequence, excluding the first part, are placed in the third position in sequence.

[0215] Example 4: The first part of the second bit sequence is located in the first position, the fourth bit sequence is located in the second position, the remaining part of the second bit sequence excluding the first part is located in the first region of the third position, and the third bit sequence is located in the second region of the third position. As shown in (4) of Figure 10.

[0216] It should be understood that, as shown in (4) of 10 above, the first position is the lowest energy amplitude bit, the second position is the highest energy amplitude bit, and the third position includes part and all of the second highest energy amplitude bit and the sign bit. The remaining part of the second bit sequence excluding the first part and the third bit sequence are placed sequentially in the third position. The remaining part in the third position is used to place the parity bit.

[0217] It should also be understood that the input bit sequence shown in (4) of Figure 10 above has no puncture bits and can be combined with coding schemes in high-throughput scenarios, such as high-throughput LDPC codes, where the puncture bits are 0.

[0218] It should also be understood that in Examples 1 to 4 above, the correspondence between the first, second, and third positions of the input bit sequence and the energy amplitude bits (e.g., the highest energy amplitude bit, the second highest energy amplitude bit, and the lowest energy amplitude bit), the punched bit, and the sign bit is related to the bit interleaving method, which is related to the modulation order Q. m For more details, see step 904 below.

[0219] 904. The transmitting device performs bit interleaving on the encoded bit sequence to obtain the interleaved bit sequence.

[0220] For example, after receiving the encoded bit sequence, the transmitting device can also perform bit interleaving on the encoded bit sequence, wherein the bit interleaving is related to Q. m Related, Q m Indicates the modulation order.

[0221] In one possible implementation, the encoded bit sequence is e0, e1, e2, ... e E-1 The interleaved bit sequence f0, f1, f2, ... f E-1 , where f i satisfy:

[0222] Where 0≤i≤Q m -1, i and j are both integers, W(i) and Q m Related.

[0223] For example, combining the bit sequence placement order in the input bit sequence shown in Figure 10(1) and Figure 10(2) above, the transmitting device performs bit interleaving on the encoded bit sequence obtained in step 903. The rule for W(i) in this bit interleaving can be: W(i) includes Q m The values ​​of W(i) are 0 to Q. m Integers between -1 and 2a, where the 0th digit of W(i) is 2a, the 1st digit is 2a+1, and the 2nd to Qth digits are integers between -1 and 2a. m The value of -1 does not include 2a and 2a+1, and it increases from 0 to Q. m -1, where a is a positive integer.

[0224] It should be understood that the value of 'a' can be predefined or preconfigured. For example, 'a' can refer to the number of bits in the real or imaginary part of the integer part.

[0225] Assume that Q m =6, a=1, W(i)=[2,3,0,1,4,5].

[0226] For example, E = 2 * Q m =2*6=12, the corresponding bit interleaving is [4,6,0,2,8,10,5,7,1,3,9,11], that is, the interleaved bit sequence satisfies: f0=e4, f1=e6, ..., f 11 =e 11 .

[0227] And suppose that Q m =8, a=1, W(i)=[2,3,0,1,4,5,6,7]; Q m =8, a=2, W(i)=[4,5,0,1,2,3,6,7].

[0228] For example, E = 2 * Q m =2*8=16, the bit interleaving corresponding to a=1 is [4,6,0,2,8,10,12,14,5,7,1,3,9,11,13,15], that is, the interleaved bit sequence satisfies: f0=e4, f1=e6, ..., f 15 =e 15 The bit interleaving corresponding to a=2 is [8,10,0,2,4,6,12,14,9,11,1,3,5,7,13,15], that is, the interleaved bit sequence satisfies: f0=e8, f1=e 10 , ..., f 15 =e 15 .

[0229] And suppose that Q m =10, a=1, W(i)=[2,3,0,1,4,5,6,7,8,9]; Q m =10, a=2, W(i)=[4,5,0,1,2,3,6,7,8,9]; Q m =10, a=3, W(i)=[6,7,0,1,2,3,4,5,8,9].

[0230] For example, E = 2 * Q m =2*10=20, the bit interleaving corresponding to a=1 is [4,6,0,2,8,10,12,14,16,18,5,7,1,3,9,11,13,15,17,19], that is, the interleaved bit sequence satisfies: f0=e4, f1=e6, ..., f 19 =e 19 The bit interleaving corresponding to a=2 is [8,10,0,2,4,6,12,14,16,18,9,11,1,3,5,7,13,15,17,19], that is, the interleaved bit sequence satisfies: f0=e8, f1=e 10 , ..., f 19=e 19 The bit interleaving corresponding to a=3 is [12,14,0,2,4,6,8,10,16,18,13,15,1,3,5,7,9,11,17,19], that is, the interleaved bit sequence satisfies: f0=e 12 f1 = e 14 , ..., f 19 =e 19 .

[0231] And suppose that Q m =12, a=1, W(i)=[2,3,0,1,4,5,6,7,8,9,10,11]; Q m =12, a=2, W(i)=[4,5,0,1,2,3,6,7,8,9,10,11]; Q m =12, a=3, W(i)=[6,7,0,1,2,3,4,5,8,9,10,11]; Q m =12, a=4, W(i)=[8,9,0,1,2,3,4,5,6,7,10,11].

[0232] For example, E = 2 * Q m =2*12=24, the bit interleaving corresponding to a=1 is [4,6,0,2,8,10,12,14,16,18,20,22,5,7,1,3,9,11,13,15,17,19,21,23], that is, the interleaved bit sequence satisfies: f0=e4, f1=e6, ..., f 23 =e 23 The bit interleaving corresponding to a=2 is [8,10,0,2,4,6,12,14,16,18,9,11,1,3,5,7,13,15,17,19,21,23], that is, the interleaved bit sequence satisfies: f0=e8, f1=e 10 , ..., f 23 =e 23 The bit interleaving corresponding to a=3 is [12,14,0,2,4,6,8,10,16,18,13,15,1,3,5,7,9,11,17,19,21,23], that is, the interleaved bit sequence satisfies: f0=e 12 f1 = e 14 , ..., f 23 =e 23 The bit interleaving corresponding to a=4 is [16,18,0,2,4,6,8,10,12,14,20,22,17,19,1,3,5,7,9,11,13,15,21,23], that is, the interleaved bit sequence satisfies: f0=e 16 f1 = e18 , ..., f 23 =e 23 .

[0233] For example, as shown in (3) of Figure 10 above, the bit sequence in the input bit sequence is arranged in a specific order. The transmitting device performs bit interleaving on the encoded bit sequence obtained in step 903. The specific rule for W(i) in this bit interleaving can be: W(i) includes Q... m The values ​​of W(i) are 0 to Q. m Integers between -1 and 1, where the 0th bit of W(i) has a value of 2, the 1st bit has a value of 3, and the 2nd to Qth bits have a value of 3. m The value of -1 does not include 2 and 3, and it increases from 0 to Q. m -1.

[0234] Assume that Q m =6, W(i)=[2,3,0,1,4,5].

[0235] For example, E = 2 * Q m =2*6=12, the corresponding bit interleaving is [4,6,0,2,8,10,5,7,1,3,9,11], that is, the interleaved bit sequence satisfies: f0=e4, f1=e6, ..., f 11 =e 11 .

[0236] And suppose that Q m =8, W(i)=[2,3,0,1,4,5,6,7].

[0237] For example, E = 2 * Q m =2*8=16, the corresponding bit interleaving is [4,6,0,2,8,10,12,14,5,7,1,3,9,11,13,15], that is, the interleaved bit sequence satisfies: f0=e4, f1=e6, ..., f 15 =e 15 .

[0238] And suppose that Q m =10, W(i)=[2,3,0,1,4,5,6,7,8,9].

[0239] For example, E = 2 * Q m 2 * 10 = 20, corresponding to the bit interleaving [4, 6, 0, 2, 8, 10, 12, 14, 16, 18, 5, 7, 1, 3, 9, 11, 13, 15, 17, 19], that is, the interleaved bit sequence satisfies: f0 = e4, f1 = e6, ..., f 19 =e 19 .

[0240] And suppose that Q m =12, W(i)=[2,3,0,1,4,5,6,7,8,9,10,11].

[0241] For example, E = 2 * Q m 2 * 12 = 24, corresponding to the bit interleaving [4, 6, 0, 2, 8, 10, 12, 14, 16, 18, 20, 22, 5, 7, 1, 3, 9, 11, 13, 15, 17, 19, 21, 23]. That is, the interleaved bit sequence satisfies: f0 = e4, f1 = e6, ..., f 23 =e 23 .

[0242] For example, as shown in (4) of Figure 10 above, the bit sequence in the input bit sequence is arranged in a specific order. The transmitting device performs bit interleaving on the encoded bit sequence obtained in step 903. The specific rule for W(i) in this bit interleaving can be: W(i) includes Q... m The values ​​of W(i) are 0 to Q. m Integers between -1 and 0, where the 0th bit of W(i) has a value of Q. m -2, the value of the first digit is Q. m -1, from the 2nd to the Qth m The value of -3 does not include Q. m -2 and Q m -1, and increasing from 2 to Q m -1, Qth m The value of -2 bits is 0, and the Qth bit... m The value of the -1 bit is 1.

[0243] Assume that Q m =6, W(i)=[4,5,2,3,0,1].

[0244] For example, E = 2 * Q m =2*6=12, the corresponding bit interleaving is [8,10,4,6,0,2,9,11,5,7,1,3], that is, the interleaved bit sequence satisfies: f0=e8, f1=e 10 , ..., f 11 =e3.

[0245] And suppose that Q m =8, W(i)=[6,7,2,3,4,5,0,1].

[0246] For example, E = 2 * Q m=2*8=16, the corresponding bit interleaving is [12,14,8,10,4,6,0,2,13,15,9,11,5,7,1,3], that is, the interleaved bit sequence satisfies: f0=e 12 f1 = e 14 , ..., f 15 =e3.

[0247] And suppose that Q m =10, W(i)=[8,9,2,3,4,5,6,7,0,1].

[0248] For example, E = 2 * Q m =2 * 10 = 20, the corresponding bit interleaving is [16,18,12,14,8,10,4,6,0,2,17,19,13,15,9,11,5,7,1,3], that is, the interleaved bit sequence satisfies: f0 = e 16 f1 = e 18 , ..., f 19 =e3.

[0249] And suppose that Q m =12, W(i)=[10,11,2,3,4,5,6,7,8,9,0,1].

[0250] For example, E = 2 * Q m =2*12=24, the corresponding bit interleaving is [20,22,16,18,12,14,8,10,4,6,0,2,21,23,17,19,13,15,9,11,5,7,1,3], that is, the interleaved bit sequence satisfies: f0=e 20 f1 = e 22 , ..., f 23 =e3.

[0251] 905. The transmitting device modulates the interleaved bit sequence to obtain a symbol sequence, and sends one or more symbols from the symbol sequence to the receiving device.

[0252] For example, the symbol sequence can also be a rate-matched and modulated sequence. For instance, the transmitting device rate-matches the interleaved bit sequence, then modulates the rate-matched sequence to obtain the symbol sequence, and finally maps the modulated symbol sequence onto physical resources for transmission.

[0253] It should be understood that detailed descriptions of specific modulation and rate matching can be found in the existing schemes, and will not be repeated here.

[0254] 906, The receiving device obtains the information to be decoded.

[0255] It is understandable that, due to the introduction of channel noise signals during transmission, the symbol sequence #1 sent by the transmitting device and the symbol sequence #2 received by the receiving device may differ. This will be illustrated using the example of the receiving device obtaining the information to be decoded from the receiving device.

[0256] 907. The transmitting device determines the first information bit sequence based on the information to be decoded.

[0257] For example, the sending device decodes the information to be decoded to obtain a decoded bit sequence. The first part of the second bit sequence and / or the second part of the third bit sequence are located at the first position in the decoded bit sequence, the fourth bit sequence is located at the second position in the decoded bit sequence, and the remaining parts of the second bit sequence excluding the first part and the remaining parts of the third bit sequence excluding the second part are located at the third position in the decoded bit sequence. The position order of the decoded bit sequence is first position, second position, and third position.

[0258] For example, the transmitting device performs dedistribution matching based on the scrambling bit sequence and the fourth bit sequence to determine the first bit sequence. The transmitting device then determines the first information bit sequence based on the first bit sequence and the second bit sequence.

[0259] For example, the scrambling bit sequence is determined by polar coding of the third bit sequence.

[0260] For example, the first bit sequence is determined by an XOR operation between the scrambling bit sequence and the fourth bit sequence.

[0261] In one possible implementation, the transmitting device demodulates the information to be decoded to obtain a demodulated bit sequence; the transmitting device then deinterleaves the demodulated bit sequence to obtain a deinterleaved bit sequence, and finally decodes the information based on the deinterleaved bit sequence. The bit deinterleaving is related to the parameter Q in the modulation order. m Related.

[0262] For example, the length of the demodulated bit sequence is E, where E = N. re *Q m Q m N represents the modulation order. re N represents the number of symbols corresponding to the symbol sequence. re For predefined or preconfigured purposes.

[0263] For example, the demodulated bit sequence is f0, f1, f2, ... f E-1 The deinterleaved bit sequence is e0, e1, e2, ... e E-1 e i satisfy:

[0264] Where 0≤i≤Q m -1, i and j are both integers, W(i) and Q m Related, Q m Indicates the modulation order.

[0265] As an example, the first part of the second bit sequence is located in the first position, the fourth bit sequence is located in the second position, the remaining part of the second bit sequence excluding the first part is located in the first region of the third position, the third bit sequence is located in the second region of the third position, and the first region is located before the second region.

[0266] For example, during the deinterleaving process, W(i) satisfies: W(i) includes Q. m The values ​​of W(i) are 0 to Q. m Integers between -1 and 2a, where the 0th digit of W(i) is 2a, the 1st digit is 2a+1, and the 2nd to Qth digits are integers between -1 and 2a. m The value of -1 does not include 2a and 2a+1, and it increases from 0 to Q. m -1, where a is a positive integer.

[0267] It should be understood that this example corresponds to Example 1 in step 903 above.

[0268] As another example, the second part of the third bit sequence is located in the first position, the fourth bit sequence is located in the second position, the second bit sequence is located in the first region of the third position, the remaining part of the third bit sequence excluding the second part is located in the second region of the third position, and the first region is located before the second region.

[0269] For example, during the deinterleaving process, W(i) satisfies: W(i) includes Q. m The values ​​of W(i) are 0 to Q. m Integers between -1 and 2a, where the 0th digit of W(i) is 2a, the 1st digit is 2a+1, and the 2nd to Qth digits are integers between -1 and 2a. m The value of -1 does not include 2a and 2a+1, and it increases from 0 to Q. m -1, where a is a positive integer.

[0270] It should be understood that this example corresponds to Example 2 in step 903 above.

[0271] As another example, the first part of the second bit sequence is located in the first position, the fourth bit sequence is located in the second position, the third bit sequence is located in the first region of the third position, the remaining part of the second bit sequence excluding the first part is located in the second region of the third position, and the first region is located before the second region.

[0272] For example, during the deinterleaving process, W(i) satisfies: W(i) includes Q. m The values ​​of W(i) are 0 to Q. m Integers between -1 and 1, where the 0th bit of W(i) has a value of 2, the 1st bit has a value of 3, and the 2nd to Qth bits have a value of 3. m The value of -1 does not include 2 and 3, and it increases from 0 to Q. m -1.

[0273] It should be understood that this example corresponds to Example 3 in step 903 above.

[0274] As another example, the first part of the second bit sequence is located in the first position, the fourth bit sequence is located in the second position, the remaining part of the second bit sequence excluding the first part is located in the first region in the third position, the third bit sequence is located in the second region in the third position, and the first region is located before the second region.

[0275] For example, during the deinterleaving process, W(i) satisfies: W(i) includes Q. m The values ​​of W(i) are 0 to Q. m Integers between -1 and 0, where the 0th bit of W(i) has a value of Q. m -2, the value of the first digit is Q. m -1, from the 2nd to the Qth m The value of -3 does not include Q. m -2 and Q m -1, and increasing from 2 to Q m -1, Qth m The value of -2 bits is 0, and the Qth bit... m The value of the -1 bit is 1.

[0276] It should be understood that this example corresponds to Example 4 in step 903 above.

[0277] It should also be understood that the detailed processes of demodulation, rate matching, deinterleaving, and decoding at the receiving end correspond to the encoding process described above. Some details can be found in the descriptions within the encoding process and will not be repeated here. The specific decoding process and its detailed explanation can be derived from the above encoding process and existing schemes, and will not be elaborated upon here.

[0278] Based on the method provided in the embodiment of this application shown in Figure 9 above, by placing the fourth bit sequence in the highest energy amplitude bit of the input bit sequence, the system bit acts as an amplitude bit to assist in shaping during the encoding process, thereby improving the performance of probability shaping.

[0279] The above is a detailed description of the channel coding or decoding method provided in this application.

[0280] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes do not imply an order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0281] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0282] It is also understood that the methods and operations implemented by the device (transmitting device or receiving device) in the above-described method embodiments can also be implemented by components of the device (such as chips or circuits), without limitation.

[0283] The communication device provided in this application is described below.

[0284] Figure 11 is a schematic structural diagram of the communication device 1100 provided in this application. The communication device 1100 can be an encoding-side device, or a device applied to the encoding-side device and capable of implementing the corresponding functions of the encoding-side device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 1100 can be a decoding-side device, or a device applied to the decoding-side device and capable of implementing the corresponding functions of the decoding-side device in the method embodiments of this application, such as a chip, processor, or circuit.

[0285] Optionally, the communication device 1100 includes a processing module 1101, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1100 is an encoding-side device or a device applied to an encoding-side device, the processing module 1101 is used to perform probability shaping pre-transformation, channel coding, etc., based on a first table. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 1100 is a decoding-side device or a device applied to a decoding-side device, the processing module 1101 is used to perform channel decoding, de-probability shaping pre-transformation, etc., based on the first table. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0286] Optionally, the communication device 1100 further includes a communication module 1102, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 1100 is an encoding-side device or a device applied to an encoding-side device, the communication module 1102 can be used to acquire a bit sequence to be encoded and transmit the bit sequence to be encoded to the processing module 1101; and output the encoded sequence obtained by the processing module 1101. Similarly, when the communication device 1100 is a decoding-side device or a device applied to a decoding-side device, the communication module 1102 can be used to receive information to be decoded and send the information to be decoded to the processing module 1101; and output the decoded bit sequence obtained by the processing module 1101 decoding the information to be decoded. It should be understood that the aforementioned communication module and / or processing module can be implemented by virtual modules. For example, the processing module can be implemented by a software functional unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented by a physical device, such as a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., an integrated circuit, logic circuit).

[0287] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0288] Figure 12 is a schematic structural diagram of another communication device provided in this application. The communication device 1200 can be used to implement the functions of any communication device (e.g., an encoding-side device or a decoding-side device) in the communication system described in the foregoing examples. The communication device 1200 may include at least one processor 1210. Optionally, the processor 1210 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 1200 may also include at least one memory 1220. The memory 1220 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1210 may execute the computer programs, instructions, or data stored in the memory 1220 to perform the corresponding functions of the encoding-side device or decoding-side device in any of the above embodiments.

[0289] Optionally, the communication device 1200 may further include a communication interface 1230, through which the communication device 1200 can interact with other devices. For example, the communication interface 1230 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 1200 is a chip-based device or circuit, the communication interface 1230 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0290] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1210 may operate in conjunction with the memory 1220 and the communication interface 1230. This application does not limit the connection medium between the processor 1210, the memory 1220, and the communication interface 1230.

[0291] Figure 13 is a schematic structural diagram of the chip provided in this application. Chip 1330 includes circuit 1301 and communication interface 1302. Circuit 1301 can be a logic circuit, integrated circuit, etc., and communication interface 1302 can also be called an input / output circuit, input / output interface, interface circuit, etc., and can input information (or receive information) or output information (or send information). Chip 1330 can execute the methods executed by the encoding-side device or decoding-side device in the various embodiments of this application.

[0292] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by an encoding-side device or a decoding-side device in the various method embodiments of this application to be executed.

[0293] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the encoding-side device or decoding-side device in the various method embodiments of this application are executed.

[0294] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by an encoding-side device or a decoding-side device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0295] This application provides a communication system, including the encoding-side device and decoding-side device in the above method embodiments.

[0296] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0297] In the embodiments of this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for instructing A, it can be understood that the instruction information carries A, which can be a direct instruction to A or an indirect instruction to A. Indirect instruction can refer to directly instructing B through the instruction information, and the correspondence between B and A, to achieve the purpose of instructing A through the instruction information. The correspondence between B and A can be predefined by the protocol, pre-stored, or obtained through configuration between network elements.

[0298] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly embodied in the execution of the hardware processor, or executed by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0299] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0300] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0301] In the embodiments of this application, "at least one" refers to one or more items. "More than one" means two or more items. "And / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0302] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0303] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0304] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0305] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0306] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0307] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0308] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

A communication method characterized by comprising: The method comprises: obtaining a first information bit sequence, the first information bit sequence comprising a first bit sequence and a second bit sequence; distributing matching the first bit sequence according to a scrambling bit sequence, to determine a fourth bit sequence, the scrambling bit sequence being determined according to a third bit sequence; encoding an input bit sequence to obtain an encoded bit sequence, a first part of the second bit sequence and / or a second part of the third bit sequence being located at a first position in the input bit sequence, the fourth bit sequence being located at a second position in the input bit sequence, a remaining part of the second bit sequence except the first part and a remaining part of the third bit sequence except the second part being located at a third position in the input bit sequence, wherein the position sequence in the input bit sequence is the first position, the second position and the third position. The method of claim 1, wherein The scrambling bit sequence is determined by polar code encoding of the third bit sequence. The method according to claim 1 or 2, characterized in that The fourth bit sequence is determined by exclusive-OR operation of the scrambling bit sequence and the first bit sequence. The method according to any one of claims 1 to 3, characterized in that The method further comprises: The encoded bit sequence is bit-interleaved to obtain an interleaved bit sequence, wherein the bit interleaving is combined with Q. m Related, Q m Indicates the modulation order. The method according to any one of claims 1 to 4, characterized in that The first part of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, and the remaining part of the second bit sequence except the first part is located at a first area in the third position, and the third bit sequence is located at a second area in the third position, the first area being located before the second area. The method according to any one of claims 1 to 4, characterized in that The second part of the third bit sequence is located at the first position, the fourth bit sequence is located at the second position, and the second bit sequence is located at a first area in the third position, and the remaining part of the third bit sequence except the second part is located at a second area in the third position, the first area being located before the second area. The method according to claim 5 or 6, characterized in that The coded bit sequence is e0, e1, e2, … e E -1, the interleaved bit sequence is f0, f1, f2, … f E -1, f i Satisfies: where 0≤i≤Q m -1, i and j are integers, W(i) and Q m are related, Q m denotes modulation order, and the interleaved bit sequence is obtained by performing bit interleaving on the encoded bit sequence. The method according to claim 7, wherein a is a positive integer. W(i) includes Q values m W(i) values belong to 0~Q m -1, wherein the value of the 0th bit of W(i) is 2a, the value of the 1st bit is 2a+1, the values of the 2nd to Q m -1 bits of W(i) do not include 2a and 2a+1, and increase from 0 to Q m -1, The first part of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, and the third bit sequence is located at a first area in the third position, and the remaining part of the second bit sequence except the first part is located at a second area in the third position, the first area being located before the second area. The method according to any one of claims 1 to 4, characterized in that The method according to claim 10, wherein a is a positive integer. The method of claim 9, wherein The coded bit sequence is e0, e1, e2, … e E-1 The interleaved bit sequence is f0, f1, f2, … f E-1 fi satisfies: where 0≤i≤Q m -1, i and j are integers, W(i) and Q m are related, Q m denotes modulation order, and the interleaved bit sequence is obtained by performing bit interleaving on the encoded bit sequence. The first part of the second bit sequence is located at the first position, the fourth bit sequence is located at the second position, and the remaining part of the second bit sequence except the first part is located at a first area in the third position, and the third bit sequence is located at a second area in the third position, the first area being located before the second area. W(i) includes Q values m The values of W(i) belong to the integers between 0 and Q m -1, wherein the value of the 0th bit of W(i) is 2, the value of the 1st bit of W(i) is 3, the values of the 2nd to Q m -1 bits of W(i) do not include 2 and 3, and increase from 0 to Q m -1. The method according to any one of claims 1 to 4, characterized in that The method according to claim 13, comprising: The method of claim 12, wherein The coded bit sequence is e0, e1, e2, … e E-1 The interleaved bit sequence is f0, f1, f2, … f E-1 fi satisfies: where 0≤i≤Q m -1, i and j are integers, W(i) and Q m are related, Q m denotes modulation order, and the interleaved bit sequence is obtained by performing bit interleaving on the encoded bit sequence. obtaining to-be-coded information; W(i) includes Q values m values of W(i) belong to the integer between 0 and Q m -2, the value of the 0th bit in W(i) is Q m -2, the value of the 1st bit is Q m -1, the values of the 2nd to Q m -3 bits do not include Q m -2 and Q m -1, and increases from 2 to Q m -1, the value of the Q m -2th bit is 0, and the value of the Q m -1th bit is 1. The method according to any one of claims 1 to 14, characterized in that The length of the first information bit sequence is K, the length of the first bit sequence is L, and L is less than or equal to 2N re , N re represents the number of symbols of the modulated symbol sequence, and the length of the second bit sequence is k1, wherein K, L and k1 are all integers, and K=L+k1. The method according to any one of claims 1 to 15, characterized in that A first part of the second bit sequence has a length of P, P being an integer, wherein P has a value of 0, 2Z c , or Z c , Z c denotes a spreading factor. A communication method characterized by comprising: ​ ​ decoding the to-be-decoded information to obtain a decoded bit sequence, a first part of the second bit sequence and / or a second part of the third bit sequence being located at a first position in the decoded bit sequence, the fourth bit sequence being located at a second position in the decoded bit sequence, a remaining part of the second bit sequence except the first part and a remaining part of the third bit sequence except the second part being located at a third position in the decoded bit sequence, the positions of the decoded bit sequence being in the order of the first position, the second position and the third position; de-interleaving the to-be-decoded information to obtain a de-interleaved bit sequence, the de-interleaved bit sequence being obtained by performing de-interleaving on the to-be-decoded information according to the first information bit sequence and the second information bit sequence, the de-interleaved bit sequence being obtained by performing de-interleaving on the to-be-decoded information according to the first information bit sequence and the second information bit sequence, the de-interleaved bit sequence being obtained by performing de-interleaving on the to-be-decoded bit sequence according to the first information bit sequence and the second information bit sequence, the de-interleaved information being obtained by performing de-interleaving on the to-be-decoded information according to the first bit sequence and the second bit sequence, the de-interleaved information being obtained by performing de-interleaving on the de-interleaved bit sequence according to the first bit sequence and the second bit sequence, the de-interleaved information being determined by performing de-interleaving on the to-be-decoded information according to the first bit sequence, the second bit sequence and the third bit sequence, the de-interleaved information being determined by performing de-interleaving on the de-interleaved bit sequence according to the first bit, the second bit sequence and the third bit sequence, the de-interleaved information being determined according to the first bit sequence, the second bit sequence and the third bit sequence, the deinterleaved information being determined according to the first bit sequence, the second bit sequence and the third information bit sequence, the de-interleaved information being determined according to the first bit sequence, the third bit sequence and the fourth bit sequence, the de-interleaved information being determined according to the first bit sequence, the fourth bit sequence and the third information bit sequence, the de-interleaved information being determined according to a scrambling bit sequence and the fourth bit sequence, the scrambling bit sequence being determined according to the third bit sequence, the de-interleaved information being determined according to the scrambling bit sequence and the fourth bit sequence, the de-interleaved information being determined according to the scrambling bit sequence and the third information bit sequence, the de-interleaved information being determined according to an information bit sequence and the fourth bit sequence, the information bit sequence being determined according to the third information bit sequence, the de-interleaved information being determined according to the information bit sequence and the fourth bit sequence, the de-interleaved information being determined according to the information bit sequence and the third information bit sequence, the de-interleaved information being determined according to information bit sequence and the fourth bit sequence, the information bit sequence being determined according to the third bit sequence, the de-interleaved information being determined by performing de-interleaving according to the information bit sequence and the fourth bit sequence, the de-interleaved information being obtained by performing de-interleaving on the information bit sequence and the fourth bit sequence, the de-interleaved information being determined according the information bit sequence and the fourth bit sequence, the de-interleaved information being determined according a scrambling bit sequence and the fourth bit sequence, the scrambling bit sequence being determined according to the information bit sequence, the de-interleaved information being determined according to the scrambling bit sequence and the information bit sequence, the de-interleaved information being determined according to the scrambling bit sequence, the fourth bit sequence and the information bit sequence, the de-interleaved information being determined according to the information bit sequence, the fourth bit sequence and the scrambling bit sequence, the de-interleaved information being determined according to the scrambling bit sequence, the third information bit sequence and the fourth bit sequence, the de-interleaved information being determined according to a scrambling bit sequence, the third information bit sequence and the fourth bit sequence, the de-interleaving being performed according to the scrambling bit sequence, the third information bit sequence and the fourth bit sequence, the scrambling bit sequence being determined according to the third information bit sequence, the de-interleaved information being obtained by performing de-interleaving on a scrambling bit sequence and the fourth bit sequence, the scrambling bit sequence being determined according to the first information bit sequence, the second information bit sequence and the third information bit sequence, the scrambling bit sequence being determined according to the first information bit sequence, the second bit sequence and the third bit sequence, the scrambling bit sequence being determined according to the first information bit sequence, the second part of the third bit sequence and the fourth bit sequence, the scrambling bit sequence being determined according to the first information, the second part of the third bit sequence and the fourth bit sequence, the scrambling bit sequence wherein a is a positive integer. The method of claim 17, wherein wherein a is a positive integer. The method according to claim 17 or 18, characterized in that wherein a is a positive integer. The method according to any one of claims 17 to 19, characterized in that ​ The method according to any one of claims 17 to 19, characterized in that ​ The method according to any one of claims 17 to 19, characterized in that ​ The method according to any one of claims 17 to 19, characterized in that ​ The method according to any one of claims 17 to 23, characterized in that ​ ​ bit deinterleaving is performed on the demodulated bit sequence to obtain a deinterleaved bit sequence, the bit deinterleaving being associated with Q m related, Q m denotes the modulation order; ​ The method of claim 24, wherein The demodulated bit sequence is f0, f1, f2,... f E-1 The deinterleaved bit sequence is e0, e1, e2,... e E-1 e i satisfies: where 0≤i≤Q m -1, i and j are integers, W(i) is related to Q m m denotes the modulation order.​ ​ W(i) includes Q values m The values of W(i) belong to the integers between 0 and Q m The value of the 0th bit in W(i) is 2a, the value of the 1st bit is 2a+1, the values of the 2nd to Q m -1th bits do not include 2a and 2a+1, and increase from 0 to Q m -1, ​ ​ W(i) includes Q values m The values of W(i) belong to the integers between 0 and Q m -1, wherein the value of the 0th bit of W(i) is 2, the value of the 1st bit of W(i) is 3, the values of the 2nd to Q m -1 bits of W(i) do not include 2 and 3, and increase from 0 to Q m -1. ​ W(i) includes Q values m values of W(i) belong to integers between 0 and Q m -2, the value of the 0th bit in W(i) is Q m -2, the value of the 1st bit in W(i) is Q m -1, the values of the 2nd to Q m -3 bits in W(i) do not include Q m -2 and Q m -1, and increases from 2 to Q m -1, the value of the Q m -2th bit in W(i) is 0, and the value of the Q m -1th bit in W(i) is 1. The method according to any one of claims 17 to 28, characterized in that The length of the first information bit sequence is K, the length of the first bit sequence is L, L is less than or equal to 2N re , N re represents the number of symbols of the modulated symbol sequence, the length of the second bit sequence is k1, wherein K, L and k1 are all integers, and K=L+k1. The method according to any one of claims 17 to 29, characterized in that A first part of the second bit sequence has a length of P, P being an integer, wherein P has a value of 0, 2Z c , or Z c , Z c denotes a spreading factor. A communication device characterized by comprising: The communication apparatus comprises at least one processor configured to cause the method of any one of claims 1-16 to be performed by the communication apparatus, or the at least one processor is configured to cause the communication apparatus to perform the method of any one of claims 17-30. The communication apparatus according to claim 31, characterized in that, The communication apparatus further comprises a memory for storing a computer program or instructions which, when executed by the at least one processor, cause the method of any one of claims 1-16 to be performed by the communication apparatus or cause the method of any one of claims 17-30 to be performed by the communication apparatus. A chip or chip system, characterized in that The chip or chip system comprises: at least one processor and an interface for calling and running instructions from the interface, which, when executed by the at least one processor, cause the method of any one of claims A computer-readable storage medium, characterized by The computer readable storage medium has stored therein computer instructions which, when executed on a computer, implement the method of any one of claims 1-30. A computer program product, characterized by The computer program product comprises a computer program which, when executed on a computer, causes the method of any one of claims 1-16 to be performed or causes the method of any one of claims 17-30 to be performed.

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