Integrated circuit module with antenna and circuitry

Abstract

Described herein are techniques for implementing high-performance RF communication systems. Some aspects of the present disclosure are directed to an integrated circuit module incorporating components of a communication system. Some aspects of the present disclosure are directed to an improved antenna that may be included in an integrated circuit module. Some embodiments of the present disclosure exhibit improved performance, greater flexibility, a more compact footprint, and / or lower cost than distributed communication systems.

Description

[0001] Draper Ref.: CSDL.7359. WO

[0002] WGS Ref: C1756.70049WO00

[0003] INTEGRATED CIRCUIT MODULE WITH ANTENNA AND CIRCUITRY

[0004] RELATED APPLICATIONS

[0005] This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application Serial No.: 63 / 735,268, filed December 17, 2024, under Attorney Docket No.: C1756.70049US00, and entitled, “INTEGRATED CIRCUIT MODULE WITH ANTENNA AND CIRCUITRY,” which is hereby incorporated herein by reference in its entirety.

[0006] BACKGROUND

[0007] Radio-frequency (RF) communication systems typically include a transmitter and / or a receiver (e.g., a transceiver). A transmitter includes a transmit antenna and transmit circuitry that drives the transmit antenna with RF energy that the transmit antenna converts into a transmitted RF wave. A receiver includes a receive antenna and receive circuitry that obtains RF energy from a received RF wave resonating in the receive antenna. In a transmitter, a signal generator produces a signal that the transmit circuitry uses to drive the transmit antenna in order to transmit the signal in the transmitted RF wave. In a receiver, a signal processor processes the RF energy obtained by the receive circuitry to obtain information about the received RF wave.

[0008] An existing RF communication system includes a circuit board and several components mounted on the circuit board and interconnected with one another via traces in or on the circuit board. An example transmitter may be distributed across several board-mounted components such as a first integrated circuit including a signal generator, a second integrated circuit including transmit circuitry, and a transmit antenna, which may be patterned directly on the circuit board or on a dielectric component mounted on the circuit board. In other examples, the transmit antenna may take the form of an antenna array that is not mounted on the circuit board and is instead connected to the transmit circuitry by cables.

[0009] SUMMARY

[0010] Some aspects of the present disclosure relate to an integrated circuit module, comprising: a first interposer comprising a mounting interface configured for mounting to a substrate external to the integrated circuit module; a semiconductor die bonded to the first interposer and comprising communication circuitry fabricated thereon; and a second interposer bonded to the semiconductor die and comprising an antenna fabricated thereon. Draper Ref.: CSDL.7359. WO

[0011] WGS Ref: C1756.70049WO00

[0012] In some embodiments, the first interposer is selected from a group consisting of a first semiconductor interposer and a first glass interposer. In some embodiments, the second interposer is selected from a group consisting of a second semiconductor interposer and a second glass interposer.

[0013] In some embodiments, the communication circuitry comprises at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic.

[0014] In some embodiments, the semiconductor die is hybrid-bonded to the first interposer and / or to the second interposer. In some embodiments, the semiconductor die is hybrid- bonded to the first interposer and to the second interposer. In some embodiments, the communication circuitry comprises a first circuit component and a second circuit component that is hybrid-bonded to the first circuit component.

[0015] In some embodiments, the first interposer comprises a first via coupling the mounting interface to the semiconductor die. In some embodiments, the first via comprises a first via material selected from a group consisting of first semiconductor material; and first conductive material. In some embodiments, the first via material comprises polysilicon. In some embodiments, the first via material comprises copper and / or aluminum.

[0016] In some embodiments, the second interposer comprises a second via coupling the semiconductor die to the antenna. In some embodiments, the second via comprises a second via material selected from a group consisting of second semiconductor material; and second conductive material. In some embodiments, the second via material comprises polysilicon. In some embodiments, the second via material comprises copper and / or aluminum.

[0017] In some embodiments, the antenna comprises a radiating element selected from a group consisting of a patch and a dipole. In some embodiments, the antenna is configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz.

[0018] Some aspects of the present disclosure relate to an integrated circuit module comprising: a first interposer configured to route signals to and / or from a substrate external to the integrated circuit module; a semiconductor die comprising communication circuitry fabricated thereon, the communication circuitry configured to obtain signals from and / or provide signals to the first interposer; and a second interposer comprising an antenna fabricated thereon, the antenna configured to transmit signals obtained from the communication circuitry and / or provide received signals to the communication circuitry. Draper Ref.: CSDL.7359. WO

[0019] WGS Ref: C1756.70049WO00

[0020] In some embodiments, in the semiconductor die is disposed between the first interposer and the second interposer.

[0021] In some embodiments, the communication circuitry comprises an amplifier configured to obtain signals from and / or provide signals to the antenna. In some embodiments, the communication circuitry comprises a modulator configured to up-convert signals for providing to the antenna and / or a demodulator configured to down-convert signals obtained from the antenna. In some embodiments, the communication circuitry comprises a logic circuit configured to perform at least one logic operation selected from a group consisting of: generating a signal for transmitting via the antenna; and processing a signal received via the antenna. In some embodiments, the communication circuitry comprises a filter distributed over multiple layers of the semiconductor die.

[0022] In some embodiments, the first interposer comprises a first via configured to route signals between the substrate and the semiconductor die. In some embodiments, the first via comprises a first via material selected from a group consisting of: first semiconductor material; and first conductive material. In some embodiments, the first via material comprises polysilicon. In some embodiments, the first via material comprises copper and / or aluminum.

[0023] In some embodiments, the second interposer comprises a second via configured to couple signals between the semiconductor die and the antenna. In some embodiments, the second via comprises a second via material selected from a group consisting of: second semiconductor material; and second conductive material. In some embodiments, the second via material comprises polysilicon. In some embodiments, the second via material comprises copper and / or aluminum.

[0024] In some embodiments, the antenna comprises a radiating element selected from a group consisting of a patch and a dipole. In some embodiments, the antenna is configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz.

[0025] Some aspects of the present disclosure relate to an integrated circuit module comprising: a semiconductor die comprising communication circuitry fabricated thereon; and an interposer comprising an antenna fabricated thereon, the antenna being configured to transmit signals obtained from the communication circuitry and / or provide received signals to the communication circuitry, and the antenna comprising: a feed; and an array of pixels, comprising: a plurality of first pixels that comprise first conductive material coupled to the feed; and a plurality of second pixels that do not comprise the first conductive material. Draper Ref.: CSDL.7359. WO

[0026] WGS Ref: C1756.70049WO00

[0027] In some embodiments, the plurality of first pixels comprise conductive plating and the plurality of second pixels comprise voids in the conductive plating. In some embodiments, the plurality of first pixels are aperiodic within the array of pixels.

[0028] In some embodiments, the integrated circuit module further comprises: a first interposer, comprising a mounting interface, the mounting interface configured for mounting to a substrate external to the integrated circuit module, the first interposer is configured to route signals between the communication circuitry and the substrate, the interposer is a second interposer, and the semiconductor die is disposed between the first interposer and the second interposer. In some embodiments, the interposer is selected from a group consisting of a semiconductor interposer and a glass interposer.

[0029] In some embodiments, the communication circuitry comprises at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic.

[0030] In some embodiments, the semiconductor die is hybrid-bonded to the interposer.

[0031] In some embodiments, the interposer comprises a via coupling the semiconductor die to the feed of the antenna. In some embodiments, the via comprises a via material selected from a group consisting of: semiconductor material; and second conductive material. In some embodiments, the via material comprises polysilicon. In some embodiments, the via material comprises copper and / or aluminum.

[0032] In some embodiments, the antenna comprises a radiating element selected from a group consisting of a patch and a dipole. In some embodiments, the antenna is configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz.

[0033] Some aspects of the present disclosure relate to a method of manufacturing an integrated circuit module, the method comprising: fabricating a mounting interface onto a first interposer of the integrated circuit module; bonding the first interposer to a semiconductor die of the integrated circuit module, the semiconductor die comprising communication circuitry fabricated thereon; fabricating an antenna on a second interposer of the integrated circuit module; and bonding the semiconductor die to the second interposer.

[0034] In some embodiments, the method further comprises fabricating the communication circuitry onto the semiconductor die.

[0035] In some embodiments, the first interposer is selected from a group consisting of a first semiconductor interposer and a first glass interposer. In some embodiments, the second Draper Ref.: CSDL.7359. WO

[0036] WGS Ref: C1756.70049WO00 interposer is selected from a group consisting of a second semiconductor interposer and a second glass interposer.

[0037] In some embodiments, the communication circuitry comprises at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic.

[0038] In some embodiments, bonding the first interposer to the semiconductor die and / or bonding the semiconductor die to the second interposer comprises hybrid-bonding.

[0039] In some embodiments, bonding the first interposer to the semiconductor die and bonding the semiconductor die to the second interposer comprise hybrid-bonding.

[0040] In some embodiments, the method further comprises forming a first via in the first interposer coupled to the mounting interface, and bonding the first interposer to the semiconductor die couples the first via to the semiconductor die. In some embodiments, the first via comprises a first via material selected from a group consisting of: first semiconductor material; and first conductive material. In some embodiments, the first via material comprises polysilicon. In some embodiments, the first via material comprises copper and / or aluminum.

[0041] In some embodiments, the method further comprises forming a second via in the second interposer coupled to the antenna, and bonding the semiconductor die to the second interposer couples the semiconductor die to the antenna. In some embodiments, the second via comprises a second via material selected from a group consisting of: second semiconductor material; and second conductive material. In some embodiments, the second via material comprises polysilicon. In some embodiments, the second via material comprises copper and / or aluminum.

[0042] In some embodiments, the method further comprises bonding a first circuit component of the communication circuitry to a second circuit component of the communication circuitry.

[0043] In some embodiments, the antenna comprises a radiating element selected from a group consisting of a patch and a dipole.

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] Various aspects and embodiments will be described herein with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same or similar reference number in all the figures in which they appear. Draper Ref.: CSDL.7359. WO

[0046] WGS Ref: C1756.70049WO00

[0047] FIG. 1 is a side view of an example integrated circuit module, according to some embodiments.

[0048] FIG. 2 is a circuit diagram of example transmit circuitry, according to some embodiments.

[0049] FIG. 3 is a circuit diagram of example receive circuitry, according to some embodiments.

[0050] FIG. 4 is a manufacturing diagram of an example integrated circuit module, according to some embodiments.

[0051] FIG. 5 is a side view of a cross-section of an example integrated circuit module in which semiconductor interposers are hybrid-bonded to a semiconductor die using different interfacing conductive materials, according to some embodiments.

[0052] FIG. 6 is a side view of a cross-section of an example integrated circuit module in which semiconductor interposers are hybrid-bonded to a semiconductor die using same interfacing conductive materials, according to some embodiments.

[0053] FIG. 7 A is a top view of an example antenna-on-interposer configuration that may be included in an integrated circuit module, according to some embodiments.

[0054] FIG. 7B is a side view of a cross-section of the antenna-on-interposer configuration of FIG. 7A, according to some embodiments.

[0055] FIG. 8 is a graph of example return loss vs. frequency for the antenna-on-interposer configuration of FIGs. 7A-7B, according to some embodiments.

[0056] FIG. 9A is a top view of a first example antenna-on-interposer configuration including an array of pixels including conductive material patterned on an interposer that may be included in an integrated circuit module, according to some embodiments.

[0057] FIG. 9B is a top view of a second example antenna-on-interposer configuration including an array of pixels patterned on an interposer, in which some pixels include conductive material and some pixels do not include the conductive material, that may be included in an integrated circuit module, according to some embodiments.

[0058] FIG. 10A is a side view of a cross-section of a first example antenna-on-interposer configuration, according to some embodiments.

[0059] FIG. 1 OB is a top view of the first example antenna-on-interposer configuration of FIG. 10A, according to some embodiments.

[0060] FIG. IOC is a bottom view of the first example antenna-on-interposer configuration of FIG. 10A, according to some embodiments. Draper Ref.: CSDL.7359. WO

[0061] WGS Ref: C1756.70049WO00

[0062] FIG. 10D is a top view of an antenna-on-interposer fabricated according to the first example configuration of FIG. 10A, according to some embodiments.

[0063] FIG. 11A is a side view of a cross-section of a second example antenna-on-interposer configuration, according to some embodiments.

[0064] FIG. 1 IB is a top view of the second example antenna-on-interposer configuration of FIG. 11 A, according to some embodiments.

[0065] FIG. 11C is a bottom view of the second example antenna-on-interposer configuration of FIG. 11 A, according to some embodiments.

[0066] FIG. 1 ID is a top view of an antenna-on-interposer fabricated according to the second example configuration of FIG. 11 A, according to some embodiments.

[0067] FIG. 12A is a side view of a cross-section of a third example antenna-on-interposer configuration, according to some embodiments.

[0068] FIG. 12B is a top view of the third example antenna-on-interposer configuration of FIG. 12A, according to some embodiments.

[0069] FIG. 12C is a bottom view of the third example antenna-on-interposer configuration of FIG. 12 A, according to some embodiments.

[0070] FIG. 12D is a top view of an antenna-on-interposer fabricated according to the third example configuration of FIG. 12A, according to some embodiments.

[0071] FIG. 13A is a side view of a cross-section of a fourth example antenna-on-interposer configuration, according to some embodiments.

[0072] FIG. 13B is a top view of the fourth example antenna-on-interposer configuration of FIG. 13 A, according to some embodiments.

[0073] FIG. 13C is a bottom view of the fourth example antenna-on-interposer configuration of FIG. 13 A, according to some embodiments.

[0074] FIG. 13D is a top view of an antenna-on-interposer fabricated according to the fourth example configuration of FIG. 13 A, according to some embodiments.

[0075] FIG. 14A is a side view of a cross-section of a fifth example antenna-on-interposer configuration, according to some embodiments.

[0076] FIG. 14B is a top view of the fifth example antenna-on-interposer configuration of FIG. 14A, according to some embodiments.

[0077] FIG. 14C is a bottom view of the fifth example antenna-on-interposer configuration of FIG. 14A, according to some embodiments.

[0078] FIG. 14D is a top view of an antenna-on-interposer fabricated according to the fifth example configuration of FIG. 14A, according to some embodiments. Draper Ref.: CSDL.7359. WO

[0079] WGS Ref: C1756.70049WO00

[0080] FIG. 15A is a side view of a cross-section of a sixth example antenna-on-interposer configuration, according to some embodiments.

[0081] FIG. 15B is a top view of the sixth example antenna-on-interposer configuration of FIG. 15 A, according to some embodiments.

[0082] FIG. 15C is a bottom view of the sixth example antenna-on-interposer configuration of FIG. 15 A, according to some embodiments.

[0083] FIG. 15D is a top view of an antenna-on-interposer fabricated according to the sixth example configuration of FIG. 15 A, according to some embodiments.

[0084] FIG. 16A is a side view of a cross-section of a seventh example antenna-on-interposer configuration, according to some embodiments.

[0085] FIG. 16B is a top view of the seventh example antenna-on-interposer configuration of FIG. 16A, according to some embodiments.

[0086] FIG. 16C is a bottom view of the seventh example antenna-on-interposer configuration of FIG. 16 A, according to some embodiments.

[0087] FIG. 16D is a top view of an antenna-on-interposer fabricated according to the seventh example configuration of FIG. 16 A, according to some embodiments.

[0088] FIG. 17 is a perspective view of the antenna-on-interposer of FIG. 13D on a coin to demonstrate scale, according to some embodiments.

[0089] FIG. 18 is a perspective view of the antenna-on-interposer of FIG. 16D on a coin to demonstrate scale, according to some embodiments.

[0090] FIG. 19 is a perspective view of a substrate with five of the antennas-on-interposer of FIG. 11D mounted thereon, according to some embodiments.

[0091] FIG. 20 is a graph of measured return loss vs. frequency for four variants of antennas- on-interposer of FIG. 19, according to some embodiments.

[0092] FIG. 21 is a graph of measured and simulated return loss for the antennas-on- interposer of the first of the variants of FIG. 20, according to some embodiments.

[0093] DETAILED DESCRIPTION

[0094] The present disclosure provides techniques for implementing high-performance RF communication systems. Some aspects of the present disclosure are directed to an integrated circuit module incorporating components of a communication system. Some aspects of the present disclosure are directed to an improved antenna that may be included in an integrated circuit module. Draper Ref.: CSDL.7359. WO

[0095] WGS Ref: C1756.70049WO00

[0096] It is recognized that performance of existing communication systems is limited, at least in part, by the distributed and / or board-mounted nature of system components. As one example, distributing components such as signal generators, amplifiers, and filters across multiple integrated circuits that are mounted on and interconnected via a board may deteriorate the quality of signals passed between the components. For instance, high- frequency signals passed between the components may be deteriorated by interference or impedance mismatches while propagating through the board or through the interconnection between an integrated circuit and the board. Similar challenges arise in the example of passing signals from transmit circuitry to a separate transmit antenna, whether through a board or through cables to an antenna array. While a given communication system may mitigate some signal quality challenges by implementing specialized interconnections or repositioning components in the system, these solutions are application- specific rather than universal or modular and add cost and complexity to the communication system.

[0097] As another example, implementing components of a communication system in separate integrated circuits compromises the flexibility to design each component specifically for interfacing with one another. For example, in addition to potentially consuming more space, implementing an amplifier in a separate (e.g., separately packaged) integrated circuit from a filter may lead to an unacceptably high loss connection between the amplifier and filter (e.g., using wire bonding, though some embodiments may tolerate wire bonding). Similarly, filters and amplifiers implemented in separate integrated circuits for mounting on a board may be designed at the scale of the interface with the board, which may be large compared to wavelengths of high frequency signals communicated between the components.

[0098] To overcome these drawbacks, some aspects of the present disclosure provide an integrated circuit module (e.g., FIG. 1). In some embodiments, the integrated circuit module may include a first interposer comprising a mounting interface configured for mounting to a substrate external to the integrated circuit module. For example, the mounting interface may include pads for mounting onto corresponding pads on a surface of a substrate of a circuit board, such as to interconnect the integrated circuit module with other components mounted on the circuit board. In some embodiments, the integrated circuit module may further comprise a semiconductor die bonded to the first interposer and comprising communication circuitry fabricated thereon. For example, the communication circuitry may include transmit circuitry and / or receive circuitry, which may be in communication with pads that bond the semiconductor die to the first interposer. In some embodiments, the integrated circuit may further comprise a second interposer bonded to the semiconductor die and comprising an Draper Ref.: CSDL.7359. WO

[0099] WGS Ref: C1756.70049WO00 antenna fabricated thereon. For example, the antenna may be in communication with pads that bond the second interposer to the semiconductor die.

[0100] By including communication circuitry fabricated on a semiconductor die bonded between a first interposer having a mounting interface and a second interposer having an antenna fabricated thereon, an integrated circuit module according to some embodiments exhibits improved performance, greater flexibility, a more compact footprint, and lower cost than distributed communication systems. For example, in some embodiments, integrating communication circuitry on a semiconductor die bonded to an interposer having an antenna fabricated thereon maintains the quality of signals passed between components of the communication circuitry and between the communication circuitry and the antenna, such as by facilitating interconnections within the die and / or via hybrid-bonding. Moreover, fabricating components of the communication circuitry on the semiconductor die, and fabricating the antenna on the interposer bonded to the semiconductor die, may provide the flexibility to design the components to fit a specific area constraint.

[0101] Alternatively or additionally, components of the communication circuitry may be designed at the scale of the semiconductor die, which may be small compared to wavelengths of signals communicated between the components. For instance, an integrated circuit module described herein may have an area less than 25mm by 25mm, such as less than 10mm by 10mm, and / or less than 5mm by 5mm. Moreover, the integrated nature of the integrated circuit module may be implemented universally and / or modularly, such as to provide an array of integrated transmitters and / or receivers, each integrated within a respective integrated circuit module.

[0102] It should be appreciated that the communication circuitry may be fabricated on multiple semiconductor dies, such as may be bonded to one another and / or to the first interposer and / or the second interposer according to various embodiments.

[0103] In some embodiments, the semiconductor die may be hybrid-bonded to the first interposer, the second interposer, or both. Alternatively or additionally, in some embodiments, a first circuit component of the communication circuitry may be hybrid-bonded to a second circuit component of the communication circuitry. For example, hybrid-bonding between the semiconductor die and either or both interposers, and / or between circuit components fabricated on the semiconductor die(s) bonded between the interposers, may provide an efficient and high signal quality interconnect for communicating signals between, to, and / or from the communication circuitry and / or the antenna. Draper Ref.: CSDL.7359. WO

[0104] WGS Ref: C1756.70049WO00

[0105] In some embodiments, the first interposer may be selected from a group consisting of a first semiconductor interposer and a first glass interposer. In some embodiments, the second interposer may be selected from a group consisting of a second semiconductor interposer and a second glass interposer. For example, semiconductor and / or glass interposers may be amenable to hybrid-bonding, signal routing, and / or antenna fabrication according to various embodiments.

[0106] In some embodiments, the communication circuitry may comprise at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic. For example, the communication circuitry may be flexibly implemented to include any one or more of these components as part of receive circuitry, transmit circuitry, a signal generator, and / or a signal processor, any or each of which may be fabricated on the semiconductor die. According to various embodiments, the communication circuitry may alternatively or additionally include: a field programmable gate array (FPGA), application specific integrated circuit (ASIC), a microcontroller, analog-to-digital conversion (ADC) circuitry, digital-to- analog conversion (DAC) circuitry, one or more switches (e.g., micro-electromechanical system (MEMS) switches), automatic gain control (AGC) circuitry, and / or a power limiter (e.g., RF limiter).

[0107] In some embodiments, the first interposer may comprise a first via coupling the mounting interface to the semiconductor die. For example, the first via may be in communication with a component (e.g., signal generator and / or signal processor) of the semiconductor die and with a pad of the mounting interface (e.g., for communicating with a component on the board on which the first interposer may be mounted). In some embodiments, the first via may comprise a first via material selected from a group consisting of: first semiconductor material; and first conductive material. For example, the integrated circuit module may be flexibly implemented with semiconductor material (e.g., polysilicon) and / or conductive material (e.g., copper and / or aluminum), depending on the desired characteristics of the match between components.

[0108] In some embodiments, the second interposer may comprise a second via coupling the semiconductor die to the antenna. For example, the second via may be in communication with a component (e.g., amplifier) of the semiconductor die and with a portion (e.g., feed) of the antenna (e.g., for transmitting and / or receiving RF energy via the antenna). In some embodiments, the second via may comprise a second via material selected from a group Draper Ref.: CSDL.7359. WO WGS Ref: C1756.70049WO00 consisting of: second semiconductor material (e.g., polysilicon); and second conductive material (e.g., copper and / or aluminum), such as described above for the first via.

[0109] In some embodiments, the antenna may comprise a radiating element selected from a group consisting of a patch and a dipole. For example, the antenna may be implemented flexibly to include a balanced or unbalanced feed, according to various embodiments. In some embodiments, the antenna may be configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz, as applications at such ranges may benefit from high signal integrity interconnections within the integrated circuit module. It should be appreciated, however, that other frequency ranges are possible within the scope of the present disclosure. For instance, integrated circuit modules according to some embodiments may be configured for use at frequency bands contained within a range from 1 GHz to 300 GHz.

[0110] Some aspects of the present disclosure provide an integrated circuit module. In some embodiments, the integrated circuit module may comprise a first interposer configured to route signals to and / or from a substrate external to the integrated circuit module. For example, the first interposer may include a routing layer having conductive traces in communication with pads of a mounting interface of the integrated circuit module (e.g., which may be included in the first interposer as described above). In some embodiments, the integrated circuit module may further comprise a semiconductor die comprising communication circuitry fabricated thereon, the communication circuity configured to obtain signals from and / or provide signals to the first interposer. For example, the communication circuitry may include a signal generator and / or transmit circuitry configured to obtain signals from the first interposer (e.g., routed from the substrate external to the integrated circuit module) and / or a signal processor and / or receive circuitry configured to provide signals to the first interposer (e.g., routed to the substrate external to the integrated circuit module). For example, signals obtained from the first interposer may include trigger and / or clock signals used for transmitting signals, and / or signals provided to the first interposer may include intermediate frequency (IF) and / or baseband demodulations of received signals. In some embodiments, the integrated circuit module may further comprise a second interposer comprising an antenna fabricated thereon, the antenna configured to transmit signals obtained from the communication circuitry and / or provide received signals to the communication circuitry. For example, the second interposer may include an interconnection (e.g., via) to the communication circuitry (e.g., receive circuitry and / or transmit circuitry) for obtaining and / or providing the signals. Draper Ref.: CSDL.7359. WO

[0111] WGS Ref: C1756.70049WO00

[0112] By including communication circuitry fabricated on a semiconductor die, a first interposer configured to route signals to and / or from the communication circuitry, and a second interposer having an antenna fabricated thereon and configured to transmit and / or receive signals obtained from and / or provided to the communication circuitry, an integrated circuit module according to some embodiments exhibits improved performance, greater flexibility, and lower cost than distributed communication systems.

[0113] In some embodiments, the semiconductor die may be disposed between the first interposer and the second interposer, such as bonded together in a stack, which may provide the benefits described above in connection with tighter integration of components of a communication system.

[0114] In some embodiments, the communication circuitry may comprise an amplifier configured to obtain signals from and / or provide signals to the antenna. For example, the amplifier may include a power amplifier configured to drive the antenna with RF energy for transmission and / or a low noise amplifier configured to condition RF energy received by the antenna. By integrating the amplifier, fabricated on the semiconductor die, with the antenna, fabricated on the second interposer, the integrated circuit module may achieve an efficient, high signal quality interconnection between the amplifier and the antenna.

[0115] In some embodiments, the communication circuitry may comprise a modulator configured to up-convert signals for providing to the antenna and / or a demodulator configured to down-convert signals obtained from the antenna. For example, the modulator may configured to up-convert the signals from a baseband and / or IF band to a frequency range of transmission by the antenna and / or the demodulator may be configured to downconvert the signals from a frequency range of reception by the antenna to a baseband or IF band. By integrating the modulator and / or demodulator, fabricated on the semiconductor die, with the antenna, fabricated on the second interposer, the integrated circuit module may achieve an efficient, high signal quality interconnection between the modulator and / or demodulator and the antenna.

[0116] In some embodiments, the communication circuitry may comprise a logic circuit configured to perform at least one logic operation selected from a group consisting of: generating a signal for transmitting via the antenna; and processing a signal received via the antenna. For example, the logic circuit may include signal generation logic (e.g., configured to generate signals for transmission by the antenna) and / or signal processing logic (e.g., configured to process signals received by the antenna). According to various embodiments, the communication circuitry may alternatively or additionally include: an FPGA, an ASIC, a Draper Ref.: CSDL.7359. WO

[0117] WGS Ref: C1756.70049WO00 microcontroller, ADC circuitry, DAC circuitry, one or more switches (e.g., MEMS switches), AGC circuitry, and / or a power limiter (e.g., RF limiter).

[0118] In some embodiments, the communication circuitry may comprise a filter distributed over multiple layers of the semiconductor die. For example, the filter may be an RF filter configured to pass RF energy at a frequency range of transmission or reception of the antenna, and / or an IF and / or baseband filter configured to pass energy in an IF band and / or in a baseband. By distributing the filter over multiple layers of the semiconductor die, the filter may be flexibly positioned for close coupling to other components of the communication circuitry, which may improve signal quality in some embodiments.

[0119] In some embodiments, the first interposer may comprise a first via configured to route signals between the substrate and the semiconductor die. For example, the first via may be in communication with a component (e.g., signal generator and / or signal processor) of the semiconductor die and with a pad of a mounting interface of the first interposer (e.g., for communicating with a component on the board on which the first interposer may be mounted). In some embodiments, the first via may comprise a first via material selected from a group consisting of: first semiconductor material; and first conductive material. For example, the integrated circuit module may be flexibly implemented with semiconductor material (e.g., polysilicon) and / or conductive material (e.g., copper and / or aluminum), depending on the desired characteristics of the match between components.

[0120] In some embodiments, the second interposer may comprise a second via configured to couple signals between the semiconductor die and the antenna. For example, the second via may be in communication with a component (e.g., amplifier) of the semiconductor die and with a portion (e.g., feed) of the antenna (e.g., for transmitting and / or receiving RF energy via the antenna). In some embodiments, the second via may comprise a second via material selected from a group consisting of second semiconductor material (e.g., polysilicon); and second conductive material (e.g., copper and / or aluminum), such as described above for the first via.

[0121] In some embodiments, the antenna may comprise a radiating element selected from a group consisting of a patch and a dipole, such as described above. In some embodiments, the antenna may be configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz, such as described above.

[0122] Some aspects of the present disclosure provide an integrated circuit module. In some embodiments, the integrated circuit may comprise a semiconductor die comprising communication circuitry fabricated thereon (e.g., as described above). In some embodiments, Draper Ref.: CSDL.7359. WO

[0123] WGS Ref: C1756.70049WO00 the integrated circuit may further comprise an interposer comprising an antenna fabricated thereon, the antenna being configured to transmit signals obtained from the communication circuitry and / or provide received signals to the communication circuitry (e.g., as described above for the second interposer). In some embodiments, the antenna (e.g., FIG. 9B) may comprise a feed and an array of pixels, the array of pixels comprising a plurality of first pixels that comprise first conductive material coupled to the feed and a plurality of second pixels that do not comprise the first conductive material. For example, the array of pixels that comprise first conductive material coupled to the feed may be configured to radiate RF energy by conducting current in a path limited, at least in part, by the second plurality of pixels.

[0124] By including an antenna including first pixels that comprise first conductive material coupled to a feed and second pixels that do not comprise the first conductive material, the integrated circuit module may achieve high radiation performance in a compact footprint (e.g., despite potential losses in the first interposer) by facilitating fine patterning of the first pixel and second pixels. For example, the first pixels and the second pixels may be implemented based on an antenna pixelation algorithm (e.g., optimization algorithm) with high radiation performance due to the fine pixel pitch that may be achieved when patterning the antenna on the first interposer.

[0125] In some embodiments, the plurality of first pixels may comprise conductive plating and the plurality of second pixels may comprise voids in the conductive plating. For example, the voids of the second pixels may be configured to provide conductive isolation between the conductive plating of the first pixels, though the voids may couple electromagnetic energy (e.g., capacitively and / or inductively) between the conductive plating, thus contributing to radiation.

[0126] In some embodiments, the plurality of first pixels may be aperiodic within the array of pixels. For example, the first pixels may have a substantially random distribution within the array of pixels, such as may be generated using an antenna pixelization algorithm. For instance, at least some first pixels may border second pixels on three of four sides (e.g., rectangular sides in a rectangular pixel array).

[0127] In some embodiments, the integrated circuit module may further comprise a first interposer, comprising a mounting interface, the mounting interface configured for mounting to a substrate external to the integrated circuit module, the first interposer being configured to route signals between the communication circuitry and the substrate, such as described above. In some embodiments, the interposer may be a second interposer, and the semiconductor die Draper Ref.: CSDL.7359. WO

[0128] WGS Ref: C1756.70049WO00 may be disposed between the first interposer and the second interposer, such as described above.

[0129] In some embodiments, the interposer may be selected from a group consisting of a semiconductor interposer and a glass interposer. For example, semiconductor and / or glass interposers may be amenable to hybrid-bonding, signal routing, and / or antenna fabrication according to various embodiments.

[0130] In some embodiments, the communication circuitry may comprise at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic, such as described above. According to various embodiments, the communication circuitry may alternatively or additionally include: an FPGA, an ASIC, a microcontroller, ADC circuitry, DAC circuitry, one or more switches (e.g., MEMS switches), AGC circuitry, and / or a power limiter (e.g., RF limiter).

[0131] In some embodiments, the semiconductor die may be hybrid-bonded to the interposer, such as described above for the second interposer.

[0132] In some embodiments, the interposer may comprise a via coupling the semiconductor die to the feed of the antenna, such as described above for the second via. For example, the via may comprise a via material selected from a group consisting of: semiconductor material (e.g., polysilicon); and second conductive material (e.g., copper and / or aluminum).

[0133] In some embodiments, the antenna may comprise a radiating element selected from a group consisting of a patch and a dipole. For example, the patch and / or dipole may include and / or form a part of the array of pixels. In some embodiments, the antenna may be configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz, as antennas at such ranges may benefit from fine control over patterning the antenna on the interposer. It should be appreciated, however, that other frequency ranges are possible within the scope of the present disclosure.

[0134] It should be appreciated that aspects of the present disclosure may be implemented individually or in combination with other aspects.

[0135] Turning to the figures, FIG. 1 is a side view of an example integrated circuit module 100, according to some embodiments. As shown in FIG. 1, the integrated circuit module 100 includes a first interposer 110, a semiconductor die 120, and a second interposer 130. In some embodiments, the first interposer 110, semiconductor die 120, and second interposer 130 may be contained within an integrated circuit package, such as where the first interposer 110 is configured as (or the package further includes) a package substrate. According to various Draper Ref.: CSDL.7359. WO WGS Ref: C1756.70049WO00 embodiments, the integrated circuit module 100 may have an area less than 25mm by 25mm, such as less than 10mm by 10mm, and / or less than 5mm by 5mm.

[0136] In some embodiments, the first interposer 110 may be configured to route signals to and / or from a substrate external to the integrated circuit module 100. For example, as shown in FIG. 1, the first interposer 110 includes a mounting interface 112, which may be configured for mounting to the substrate external to the integrated circuit module 100. For instance, in FIG. 1, the mounting interface 112 includes conductive pads CP, which may be configured for mounting (e.g., solder-mounting) onto corresponding pads on a surface of a substrate (e.g., 1900 in FIG. 19) of a circuit board. In some embodiments, the mounting interface 112 may include a ball-grid- array (BGA) mounting interface. In some embodiments, the first interposer 110 may include routing components 114, such as conductive traces on one or more routing layers and / or vias between one or more layers of the first interposer 110, which may be configured to carry signals routed by the first interposer 110.

[0137] In some embodiments, the first interposer 110 may be a first semiconductor interposer or a first glass interposer. For example, the first interposer 110 may include bulk material that is insulative or semiconductive so as to provide isolation between electrical signals routed within the first interposer 110. For example, a first semiconductor interposer may be implemented as a silicon interposer, though other semiconductor materials may be used. It should be appreciated that semiconductor material and glass may be used in an interposer in combination without departing from the scope of the present disclosure.

[0138] In some embodiments, the semiconductor die 120 may include communication circuitry 122 fabricated thereon, such as shown in FIG. 1. For example, the communication circuitry 122 may be configured to obtain signals from and / or provide signals to the first interposer 110, such as signals routed to and / or from the substrate. In some embodiments, the communication circuitry 122 may include transmit circuitry and / or receive circuitry, such as described further herein including in connection with FIGs. 2 and 3. According to various embodiments, the communication circuitry 122 may include one or more circuit elements such as a transmit amplifier, a receive amplifier, a modulator, a demodulator, a filter, signal generator logic, and / or signal processing logic. In some embodiments, the semiconductor die 120 may include a semiconductor substrate having the communication circuitry 122 fabricated thereon, such as a bulk silicon substrate, though other semiconductor materials may be used.

[0139] In some embodiments, the second interposer 130 may include an antenna 132 fabricated thereon, such as shown in FIG. 1. For example, the antenna 132 may be configured Draper Ref.: CSDL.7359. WO WGS Ref: C1756.70049WO00 to transmit signals obtained from the communication circuitry 122 and / or provide received signals to the communication circuitry 122. For instance, the antenna may be in communication with transmit circuitry and / or receive circuitry of the communication circuitry 122 to transmit signals obtained from the transmit circuitry and / or provide received signals to the receive circuitry. In some embodiments, the second interposer 130 may include feed components configured to feed signals to and / or from the antenna 132, such as conductive traces on one or more feed layers and / or vias between one or more layers of the second interposer 130, which may be configured to carry signals between the antenna 132 and the communication circuitry 122. In some embodiments, the second interposer 130 may be a second semiconductor interposer or a second glass interposer, such as described herein for the first interposer 110.

[0140] In some embodiments, the semiconductor die 120 may be disposed between the first interposer 110 and the second interposer 130, such as shown in FIG. 1. For example, the semiconductor die 120 may be bonded to the first interposer 110 and the second interposer 130 may be bonded to the semiconductor die 120. For instance, the communication circuitry 122 may be configured to obtain signals from and / or provide signals to the first interposer 110 via bond pads that bond the semiconductor die 120 to the first interposer 110. Alternatively or additionally, the antenna 132 may be configured to obtain signals from the communication circuitry 122 and / or provide received signals to the communication circuitry 122 via bond pads that bond the second interposer 130 to the semiconductor die 120. In some embodiments, the semiconductor die 120 may be hybrid-bonded to the first interposer 110 and / or to the second interposer 130, and / or circuit components of the semiconductor die(s) 120 may be hybrid-bonded to one another, such as described further herein including in connection with FIGs. 5-6.

[0141] While a single integrated circuit module is shown in FIG. 1, it should be appreciated that multiple integrated circuit modules may be included in a communication system. For example, each integrated circuit module may include the components shown in FIG.1 for the integrated circuit module 100. For instance, the integrated circuit modules may be mounted on a circuit board and configured to transmit signals (e.g., as at least a portion of a transmit array) and / or receive signals (e.g., as at least a portion of a receive array). In some embodiments, multiple integrated circuit modules may be implemented in a beamforming arrangement by including beamforming circuitry (e.g., mounted on the circuit board) coupled to the integrated circuit modules to provide and / or obtain transmitted and / or received signals (e.g., including applying a phase shift). Draper Ref.: CSDL.7359. WO

[0142] WGS Ref: C1756.70049WO00

[0143] FIGs. 2-3 illustrate example transmit and receive circuitry that may be fabricated on the semiconductor die of the integrated circuit module of FIG. 1, according to some embodiments.

[0144] FIG. 2 is a circuit diagram of example transmit circuitry 200, according to some embodiments. FIG. 3 is a circuit diagram of example receive circuitry 300, according to some embodiments. In some embodiments, the communication circuitry 122 fabricated on the semiconductor die 120 of the integrated circuit module 100 of FIG. 1 may include the transmit circuitry 200 of FIG. 2 and / or the receive circuitry 300 of FIG. 3.

[0145] In some embodiments, the transmit circuitry 200 shown in FIG. 2 may be configured to obtain a signal via the first interposer 110 and provide a signal to the antenna 132 fabricated on the second interposer 130 for transmission. For example, in FIG. 3, the transmit circuitry 200 includes signal generator logic 202, an up-conversion modulator 204, an RF filter 206, and a transmit power amplifier (PA) 208. For instance, the signal generator logic 202 may be configured to generate a signal for transmitting via the antenna 132, the up- conversion modulator 204 may be configured to up-convert the signal from the signal generator logic 202 for providing to the antenna 132, the RF filter 206 may be configured to pass the signal to the transmit PA 208, and the transmit PA 208 may be configured to provide the signal to the antenna 132.

[0146] In some embodiments, the signal generator logic 202 may be configured to obtain a signal via the first interposer 110 (e.g., from the substrate external to the integrated circuit module) and provide a signal for transmission by the antenna 132. For example, the signal generator logic 202 may be configured to obtain a clock signal, based on which the signal generator logic 202 may be configured to generate and provide the signal for transmission by the antenna 132. In the same or another example, the signal generator logic 202 may be configured to obtain a trigger signal, in response to which the signal generator logic 202 may be configured to generate and provide the signal for transmission by the antenna 132. Alternatively or additionally, the signal generator logic 202 may be omitted and / or configured to be bypassed such that the signal transmitted by the antenna 132 is generated off-chip (e.g., by circuitry on the substrate external to the integrated circuit module 100).

[0147] In some embodiments, the up-conversion modulator 204 may be configured to obtain the signal generated by the signal generator logic 202 and up-convert the signal to a frequency range of transmission by the antenna 132. For example, the up-conversion modulator 204 may include a frequency multiplier and / or mixer. For instance, where the up- conversion modulator 204 includes a mixer, the mixer may be configured to mix the signal Draper Ref.: CSDL.7359. WO

[0148] WGS Ref: C1756.70049WO00 with a local oscillator (LO) signal, which may be obtained from the signal generator logic 202. It should be appreciated that the up-conversion modulator 204 may be alternatively or additionally configured to obtain the signal and / or LO signal from the substrate external to the integrated circuit module 100, such as in embodiments that omit the signal generator logic 202.

[0149] In some embodiments, the RF filter 206 may be configured to pass the up-converted signal from the up-conversion modulator 204 to the antenna 132. For example, the RF filter 206 may be implemented as a band-pass filter having a passband aligned at least in part with the frequency range of transmission by the antenna 132. For instance, the RF filter 206 may be configured to stop other frequencies, such as baseband, an IF band, and / or harmonics generated by the up-conversion modulator 204 outside the frequency range of transmission by the antenna 132.

[0150] In some embodiments, the transmit PA 208 may be configured to obtain the signal passed by the RF filter 206 and provide the signal to the antenna 132. For example, the transmit PA 208 may be configured to drive the antenna 132 with RF energy in the frequency range of transmission by the antenna 132, such as over at least a portion of a frequency range at which the antenna 132 is configured to transmit signals. In some embodiments, the transmit PA 208 may be implemented with compound semiconductor materials, such as using gallium arsenide (GaAs) and / or gallium nitride (GaN) transistor technologies, though it should be appreciated that other semiconductor materials are possible.

[0151] In some embodiments, the receive circuitry 300 shown in FIG. 3 may be configured to obtain a signal via the antenna 132 and provide a signal to the first interposer 110. For example, in FIG. 3, the receive circuitry 300 includes an RF filter 302, a receive low-noise amplifier (LNA) 304, a down-conversion demodulator 306, an IF and / or baseband filter 308, and signal processing logic 310. For instance, the RF filter 302 may be configured to pass a signal from the antenna 132 to the receive LNA 304, the down-conversion demodulator 306 may be configured to down-convert the signal from the antenna 132 to an IF band and / or baseband, the IF and / or baseband filter 308 may be configured to pass the down-converted signal from the down-conversion demodulator 306 to the signal processing logic3 10, and the signal processing logic 310 may be configured to process the signal and provide a signal to the first interposer 110.

[0152] In some embodiments, the RF filter 302 may be configured to obtain a signal from the antenna 132 and provide the signal to the receive LNA 304. For example, the RF filter 302 may be implemented as a band-pass filter having a passband aligned at least in part with the Draper Ref.: CSDL.7359. WO

[0153] WGS Ref: C1756.70049WO00 frequency range of reception by the antenna 132. For instance, the RF filter 302 may be configured to stop other frequencies, such as background noise outside the frequency range of reception by the antenna 132.

[0154] In some embodiments, the receive LNA 304 may be configured to obtain the signal from the RF filter 302 and provide the filtered signal to the down-conversion demodulator 306. For example, the receive LNA 304 may be configured to amplify RF energy in the signal in the frequency range of reception by the antenna 132, such as over at least a portion of a frequency range at which the antenna 132 is configured to receive signals, to mitigate at least some noise that may be introduced by the down-conversion demodulator 306. In some embodiments, the receive LNA 304 may be implemented with compound semiconductor materials, such as using GaAs and / or GaN transistor technologies, though it should be appreciated that other semiconductor materials are possible.

[0155] In some embodiments, the down-conversion demodulator 306 may be configured to obtain the conditioned signal from the receive LNA 304 and down-convert the signal to an IF band and / or baseband, such as a band in which the signal processing logic 310 may be configured to perform processing. For example, the down-conversion demodulator 306 may include a frequency divider and / or mixer. For instance, where the down-conversion demodulator 306 includes a mixer, the mixer may be configured to mix the signal with an LO signal, which may be obtained from the signal processing logic 310. It should be appreciated that the down-conversion demodulator 306 may be alternatively or additionally configured to obtain the LO signal from the substrate external to the integrated circuit module 100, and / or to down-convert the signal to an IF band and / or baseband in which circuitry on the substrate is configured to perform processing, such as in embodiments that omit the signal processing logic 310.

[0156] In some embodiments, the IF and / or baseband filter 308 may be configured to pass the down-converted signal from the down-conversion demodulator 306 to the signal processing logic 310. For example, the IF and / or baseband filter 308 may be implemented as a band-pass filter having a passband aligned at least in part with the IF band and / or baseband in which the signal processing logic is configured to perform processing. For instance, the IF band and / or baseband filter 308 may be configured to stop other frequencies, such as the frequency range of reception by the antenna 132 and / or harmonics generated by the downconversion demodulator 306 outside the frequency range of reception by the antenna 132.

[0157] In some embodiments, the signal processing logic 310 may be configured to obtain the down-converted signal via the IF and / or baseband filter 308, process the signal, and Draper Ref.: CSDL.7359. WO

[0158] WGS Ref: C1756.70049WO00 provide a signal to the first interposer 110 (e.g., for providing to the substrate external to the integrated circuit module 100). For example, the signal processing logic 310 may be configured to extract information encoded in the down-converted signal, such as a message (e.g., in an information communication system) and / or an indication of a detected object (e.g., in a detection communication system). Alternatively or additionally, the signal processing logic 310 may be omitted and / or configured to be bypassed such that the signal received by the antenna 132 is processed off-chip (e.g., by circuitry on the substrate external to the integrated circuit module 100).

[0159] In some embodiments, the signal generator logic 202 and / or signal processing logic 310 may include an FPGA, an ASIC, and / or a microcontroller. While not shown in FIGs. 2-3, some embodiments may alternatively or additionally include data conversion circuitry, such as including ADC circuitry and / or DAC circuitry. For example, ADC circuitry may be coupled between components of the receive circuitry 300 (e.g., the LNA) and the signal processing logic 310 (e.g., implemented using digital processing circuitry), and / or DAC circuitry may be coupled between the signal generator logic 202 (e.g., implemented using digital processing circuitry) and components of the transmit circuitry 200 (e.g., the PA).

[0160] In some embodiments, the transmit circuitry 200 and / or receive circuitry 300 may alternatively or additionally include one or more switches, such as RF switches, IF switches, and / or baseband switches. For example, switches may be implemented to select a transmit and / or receive path (e.g., antenna) for transmission and / or reception (e.g., in a multiple antenna element configuration), and / or to select between a transmit path and a receive path to and / or from an antenna (e.g., in a transceiver configuration). In some embodiments, switches may be implemented using MEMS technology, though other configurations are possible.

[0161] In some embodiments, the transmit circuitry 200 and / or receive circuitry 300 may alternatively or additionally include one or more power control components, such as automatic gain control (AGC) circuitry (e.g., coupled to the PA and / or LNA) and / or a power limiter (e.g., RF limiter coupled to the LNA and / or PA).

[0162] FIG. 4 is a manufacturing diagram 400 of an example integrated circuit module, according to some embodiments.

[0163] In some embodiments, an integrated circuit module may be manufactured, at least in part, as shown in FIG. 4. For example, FIG. 4 shows a first step of fabricating a mounting interface 412 onto a first interposer 410 of the integrated circuit module, a second step of bonding the first interposer 410 to a semiconductor die 420 of the integrated circuit module, a third step of fabricating an antenna 432 on a second interposer 430 of the integrated circuit Draper Ref.: CSDL.7359. WO

[0164] WGS Ref: C1756.70049WO00 module, and a fourth step of bonding the semiconductor die 420 to the second interposer 430. It should be appreciated that the first, second, third, and fourth steps need not be performed in sequential order from the first step to the second step and so on, as embodiments described herein are not so limited.

[0165] In some embodiments, the first interposer 410, semiconductor die 420, and / or second interposer 430 may be configured as described herein in connection with FIGs. 1 and 2-3. For example, the semiconductor die 420 may have communication circuitry 422 fabricated thereon. For instance, the communication circuitry 422 may include at least one circuit elements, such as a transmit amplifier, a receive amplifier, a modulator, a demodulator, a filter, signal generator logic, and signal processing logic. As another example, the first interposer 410 may be a first semiconductor interposer or a first glass interposer, and / or the second interposer 430 may be a second semiconductor interposer or a second glass interposer.

[0166] In some embodiments, the first step of fabricating the mounting interface 412 onto the first interposer may include fabricating pads CP onto a mounting interface layer of the first interposer 410. For example, the pads CP may be configured for wire bonding and / or BGA mounting, depending on the implementation.

[0167] In some embodiments, the second step of bonding the first interposer 410 to the semiconductor die 420 may include bonding an interface layer of the first interposer 410 with an interface layer of the semiconductor die 420. For example, the interface layers of the first interposer 410 and of the semiconductor die 420 may have pads that may be bonded to attach the first interposer 410 to the semiconductor die 420. For instance, the pads of the interface layer of the first interposer 410 may be coupled to the mounting interface 412 (e.g., once the mounting interface has been fabricated onto the first interposer) and the pads of the interface layer of the semiconductor die 420 may be coupled to the communication circuitry 422.

[0168] In some embodiments, the third step of fabricating the antenna 432 on the second interposer 430 may include patterning a conductive layer on an antenna layer of the second interposer 430. For example, the antenna layer may include substantially a farthest layer of the second interposer 430 from where the second interposer 430 is bonded to the semiconductor die 420 in the fourth step, such that substantially no layers of the second interposer 430 block radiation to and / or from the antenna 432. It should be appreciated that a protective layer (e.g., and / or integrated circuit packaging) may be included in the second interposer 430 after the antenna layer to protect and / or conductively isolate the antenna 432 from the external environment. Draper Ref.: CSDL.7359. WO

[0169] WGS Ref: C1756.70049WO00

[0170] In some embodiments, the fourth step of bonding the second interposer 430 to the semiconductor die 420 may include bonding an interface layer of the second interposer 430 with an interface layer of the semiconductor die 420. For example, the interface layers of the second interposer 430 and of the semiconductor die 420 may have pads that may be bonded to attach the second interposer 430 to the semiconductor die 420. For instance, the pads of the interface layer of the second interposer 430 may be coupled to the antenna 432 (e.g., once the antenna has been fabricated onto the second interposer) and the pads of the interface layer of the semiconductor die 420 may be coupled to the communication circuitry 422.

[0171] In some embodiments, the second step of bonding the first interposer 410 to the semiconductor die 420 and / or the fourth step of bonding the semiconductor die 420 to the second interposer 430 may include hybrid-bonding, such as described further herein including in connection with FIGs. 5-6.

[0172] In some embodiments, the method of manufacturing shown in FIG. 4 may further include forming a first via in the first interposer 410 coupled to the mounting interface 412, such as described further herein including in connection with FIGs. 5-6. For example, the first via may be coupled to the mounting interface 412 upon fabricating the mounting interface 412 onto the first interposer 410. In some embodiments, the second step of bonding the first interposer 410 to the semiconductor die 420 may couple the first via to the semiconductor die 420. For example, the first via may be further coupled to an interface layer of the first interposer 410 that bonds with an interface layer of the semiconductor die 420, which in turn may be coupled to the communication circuitry 422.

[0173] In some embodiments, the method of manufacturing shown in FIG. 4 may further include forming a second via in the second interposer 430 coupled to the antenna 432, such as described further herein including in connection with FIGs. 5-6. For example, the second via may be coupled to the antenna 432 upon fabricating the antenna 432 onto the second interposer 430. In some embodiments, the fourth step of bonding the second interposer 430 to the semiconductor die 420 may couple the second via to the semiconductor die 420. For example, the second via may be further coupled to an interface layer of the second interposer 430 that bonds with an interface layer of the semiconductor die 420, which in turn may be coupled to the communication circuitry 422.

[0174] In some embodiments, the method of manufacturing shown in FIG. 4 may further include a step of fabricating the communication circuitry 422 onto the semiconductor die, though other embodiments may omit such a step, such as where the communication circuitry 422 is already fabricated on the semiconductor die 420 at the time of manufacture. Draper Ref.: CSDL.7359. WO

[0175] WGS Ref: C1756.70049WO00

[0176] In some embodiments, the method of manufacturing shown in FIG. 4 may further include a step of bonding (e.g., hybrid-bonding) a first circuit component of the communication circuitry 422 to a second circuit component of the communication circuitry 422, such as including bonding (e.g., hybrid-bonding) a first semiconductor die, having the first circuit component fabricated thereon, to a second semiconductor, having the second circuit component fabricated thereon.

[0177] It should be appreciated that some embodiments may omit the third step of fabricating the antenna 432 onto the second interposer 430, such as where the antenna 432 is already fabricated on the second interposer 430 at the time of manufacture.

[0178] FIG. 5 is a side view of a cross-section of an example integrated circuit module 500 in which semiconductor interposers are hybrid-bonded to a semiconductor die using different interfacing conductive materials, according to some embodiments.

[0179] In some embodiments, the integrated circuit module 500 shown in FIG. 5 may be configured as described herein including in connection with FIGs. 1-4. For example, the integrated circuit module 500 includes a first interposer 510 including a mounting interface 512, a semiconductor die 520 including communication circuitry 522 fabricated thereon, and a second interposer 530 including an antenna 532 fabricated on an antenna layer 534. For instance, as shown in FIG. 5, the communication circuitry 522 includes an amplifier 524, logic 526, and one or more filters 528, such as described herein including in connection with FIGs. 2-3.

[0180] In some embodiments, the semiconductor die 520 may be hybrid-bonded to the first interposer 510 and / or to the second interposer 530. For example, as shown in FIG. 5, the first interposer 510 includes a first interface layer IL1 with pads IP1 that are hybrid-bonded to a second interface layer IL2 of the semiconductor die 520. For instance, the hybrid-bonds HB may include a dielectric bond between dielectric material (e.g., oxide material) proximate the pads IP1 and a conductive bond between conductive material of the pads IP1. In one nonlimiting example, each interface layer IL1, IL2 may include silicon dioxide (SiO2) dielectric material proximate the pads IP1, such as where the first interposer 510 is a silicon interposer.

[0181] Alternatively or additionally, in some embodiments, a first circuit component of the communication circuitry 522 fabricated on the semiconductor die 520 may be hybrid-bonded to a second circuit component of the communication circuitry 522 fabricated on the semiconductor die 520. For example, while not shown in FIG. 5, the illustrated filter(s) 528 may be hybrid-bonded to the amplifier 524, such as when the filter(s) 528 and amplifier 524 are fabricated on different layers and / or semiconductor dies. Draper Ref.: CSDL.7359. WO WGS Ref: C1756.70049WO00

[0182] In some embodiments, hybrid-bonds HB (e.g., between the first interposer 510 and the semiconductor die 520) may include different interfacing conductive materials. For example, as shown in FIG. 5, the pads IP1 of the first interface layer IL1 of the first interposer 510 include a different conductive material than the pads IP2 of the second interface layer IL2 of the semiconductor die 520. For instance, the pads IP1 of the first interface layer IL1 may include aluminum and the pads IP2 of the second interface layer IL2 may include copper. As another example, as shown in FIG. 5, the second interposer 530 includes a fourth interface layer IL4 with pads that are hybrid-bonded to a third interface layer IL3 of the semiconductor die 520, and the hybrid-bonds HB may be configured as described herein for the first interface layer IL1 and the second interface layer IL2. In some embodiments, the pads IP1, IP4 may be fabricated onto the first interface layer IL1 of the first interposer 510 and the fourth interface layer IL4 of the second interposer 530 using a Back End of Line (BEOL) process.

[0183] In some embodiments, the first interposer 510 may include one or more first vias coupling the mounting interface 512 to the semiconductor die 520. For example, as shown in FIG. 5, the first interposer includes a first through- silicon via TSV1 extending from the mounting interface 512 to the first interface layer. For instance, the first via TSV1 in FIG. 5 may be coupled between a pad CP on a mounting layer 514 of the mounting interface 512 and a pad IP1 of the first interface layer IL1, which in turn may be bonded to a pad IP2 of the second interface layer IL2 of the semiconductor die 520 to bring the communication circuitry 522 into communication with a substrate onto which the integrated circuit module 500 may be mounted. According to various embodiments, the first via TSV 1 may include first semiconductor material (e.g., polysilicon) or first conductive material (e.g., copper and / or aluminum). In the illustrated example, the first via TSV 1 includes first semiconductor material.

[0184] In some embodiments, the second interposer 530 may include one or more second vias coupling the antenna 532 to the semiconductor die 520. For example, as shown in FIG. 5, the second interposer 530 includes a second via TSV2 extending from the antenna 532 to the fourth interface layer IL4. For instance, the second via TSV2 in FIG. 5 may be coupled between the antenna 532 (e.g., antenna feed) and a pad IP4 of the fourth interface layer IL4, which in turn may be bonded to a pad IP3 of the third interface layer IL3 of the semiconductor die 520 to bring the communication circuitry 522 into communication with the antenna 532. According to various embodiments, the second via TSV2 may include second semiconductor material (e.g., polysilicon) or second conductive material (e.g., copper and / or Draper Ref.: CSDL.7359. WO WGS Ref: C1756.70049WO00 aluminum). In the illustrated example, the second via TSV2 includes second semiconductor material, though it should be appreciated that the first via(s) TSV1 and second via(s) TSV2 may include different materials (e.g., semiconductor and conductive material, respectively, or vice versa).

[0185] In some embodiments, the semiconductor die 520 may include one or more third vias, which may couple components of the communication circuitry 522 to the first interposer 510, the second interposer 530, one another, and / or which may bypass components of the communication circuitry 522. For example, as shown in FIG. 5, the semiconductor die 520 includes a third via TSV3 shown coupled between a pad IP2 of the second interface layer IL2 and a pad IP3 of the third interface layer IL3. For instance, according to various embodiments, the third via TSV3 may be configured to couple the amplifier 524 to the second interposer 530, the logic 526 to the first interposer 510, the logic 526 to the amplifier 524, and / or the first interposer 510 to the second interposer 530. In the illustrated example, the third via TSV3 includes third semiconductor material, though it should be appreciated that the third via(s) TSV3 may include a different material from the first via(s) TSV1 and / or the second via(s) TSV2.

[0186] In some embodiments, the semiconductor die 520 may further include routing layers with pads having different conductive materials from the pads of the interface layers of the semiconductor die 520. For example, as shown in FIG. 5, the semiconductor die 520 includes a first routing layer RL1 having pads B coupled to the third vias TSV3 with a different conductive material than the pads IP2 of the second interface layer IL2, and the semiconductor die 520 further includes a second routing layer RL2 having pads B coupled to the third vias TSV3 with a different conductive material than the pads IP3 of the third interface layer IL3. For example, the pads B of the first routing layer RL1 and of the second routing layer RL2 may include aluminum.

[0187] FIG. 6 is a side view of a cross-section of an example integrated circuit module 600 in which semiconductor interposers are hybrid-bonded to a semiconductor die using same interfacing conductive materials, according to some embodiments.

[0188] In some embodiments, the integrated circuit module 600 shown in FIG. 6 may be configured as described herein for the integrated circuit module 500 of FIG. 5. For example, the illustrated integrated circuit module 600 includes a first interposer 610 including a mounting interface 612 with pads CP on a mounting layer 614, a semiconductor die 620 including communication circuitry 622 fabricated thereon, and a second interposer 630 including an antenna 632 fabricated on an antenna layer 634. For instance, as shown in FIG. Draper Ref.: CSDL.7359. WO

[0189] WGS Ref: C1756.70049WO00

[0190] 6, the first interposer 610 is hybrid-bonded to the semiconductor die 620 and the second interposer 630 is hybrid-bonded to the semiconductor die 620. Also shown in FIG. 6, the first interposer 610 includes a first via TSV1, the second interposer 630 includes a second via TSV2, and the semiconductor die 620 includes a third via TSV3. In the illustrated example, as in FIG. 5, the communication circuitry 622 includes an amplifier 624, logic 626, and one or more filters 628.

[0191] In some embodiments, hybrid-bonds HB between the first interposer 610 and the semiconductor die 620, between the second interposer 630 and the semiconductor die 620, and / or between circuit components of the communication circuitry 622 fabricated on the semiconductor die(s) 620 may include a same conductive material. For example, as shown in FIG. 6, the pads IPF of the first interface layer ILF of the first interposer 610 include a same conductive material as the pads IP2 of the second interface layer IL2 of the semiconductor die 620, and the pads IP4’ of the fourth interface layer IL4’ of the second interposer 630 include a same conductive material as the pads IP3 of the third interface layer IL3 of the semiconductor die 620. For instance, the pads IPF of the first interface layer ILF, the second interface layer IL2, the third interface layer IL3, and the fourth interface layer IL4’ may include copper, though in each may include aluminum as embodiments described herein are not so limited.

[0192] In some embodiments, the semiconductor die 620 may further include routing layers with pads having a same conductive material as the pads of the interface layers of the semiconductor die 620. For example, as shown in FIG. 6, the semiconductor die 620 includes a first routing layer RLF having pads B’ coupled to the third vias TSV3 with a same conductive material as the pads IP2 of the second interface layer IL2, and the semiconductor die 620 further includes a second routing layer RL2’ having pads B’ coupled to the third vias TSV3 with a same conductive material as the pads IP3 of the third interface layer IL3. For example, the pads B’ of the first routing layer RL1 and of the second routing layer RL2 may include copper.

[0193] FIG. 7 A is a top view of an example antenna-on-interposer configuration 700 that may be included in an integrated circuit module, according to some embodiments. FIG. 7B is a side view of a cross-section of the antenna-on-interposer configuration 700 of FIG. 7A, according to some embodiments.

[0194] In some embodiments, the antenna-on-interposer configuration 700 shown in FIGs. 7A and 7B may be included in the integrated circuit modules of any of FIGs. 1 to 6. For Draper Ref.: CSDL.7359. WO

[0195] WGS Ref: C1756.70049WO00 example, the interposer shown in FIGs. 7 A and 7B may implement the second interposer of the integrated circuit module in some embodiments,

[0196] In some embodiments, the antenna of an integrated circuit module as described herein may include a patch or a dipole. For example, as shown in FIG. 7A, the antenna is implemented as a patch antenna 702. For instance, in the illustrated example, the patch antenna 702 has an unbalanced feed 706, which may be coupled to a via TSV (FIG. 7B) to obtain and / or provide a signal from and / or to the communication circuitry of the integrated circuit module. It should be appreciated that an antenna may be alternatively or additionally implemented as a dipole antenna (and / or other antenna configuration), such as including a balanced feed and / or a balun.

[0197] In some embodiments, the interposer 704 may include vias configured to feed the antenna. For example, as shown in FIG. 7B, the via TSV is shown coupled between the patch antenna 702 at an antenna layer and a bond pad IP at the interface layer IL. For instance, the bond pad IP at the interface layer IL may be configured to obtain and / or provide a signal from and / or to the communication circuitry of the integrated circuit module.

[0198] In some embodiments, the interposer 704 may further include a routing layer RL1 between the via TSV and the antenna layer including a different conductive material. For example, the routing layer RL1 may include tantalum and / or copper and the antenna layer may include titanium and / or aluminum. In some embodiments, the interposer 704 may further include a routing layer RL2 between the via TSV and the interface layer IL including a different conductive material. For example, the routing layer RL2 may include titanium and / or aluminum and the interface layer IL may include tantalum and / or copper. In some embodiments, the bond pads IP may include copper in a hybrid-bond configuration. In some embodiments, the conductive layers may be separated by dielectric material, such as SiO2.

[0199] While a single antenna layer is shown in the example of FIGs. 7A-7B, it should be appreciated that a multi-layer antenna-on-interposer configuration may be alternatively or additionally included in an integrated circuit module as described herein. For example, an antenna-on-interposer configuration may have antenna elements distributed over multiple antenna layers, such as having antenna elements respectively fabricated on opposing layers of an interposer (e.g., separated by an insulative or semiconductive material of the interposer) and / or on layers of multiple interposers that may be stacked (e.g., bonded) together. For instance, elements of the antenna may be configured to resonate at different frequency bands for multiband operation (e.g., sharing a common antenna feed). In the same or another example, an antenna-on-interposer configuration may include multiple antennas distributed Draper Ref.: CSDL.7359. WO

[0200] WGS Ref: C1756.70049WO00 over multiple antenna layers, such as having antennas respectively fabricated on opposing layers of an interposer and / or on layers of multiple interposer that may be stacked. For instance, antennas of the antenna configuration may be configured to resonate at different frequency bands and / or may be operated for transmission and reception, respectively, depending on the particular application.

[0201] FIG. 8 is a graph of example return loss vs. frequency for the antenna-on-interposer configuration of FIGs. 7A-7B, according to some embodiments.

[0202] In the illustrated graph, the patch antenna 702 shown in FIGs. 7A and 7B exhibits return loss of lOdB or less between 12 GHz and about 12.5 GHz, for a bandwidth of about 500 MHz and a fractional bandwidth of about 4%. It should be appreciated that the patch antenna 702 may be scaled to meet other frequency ranges. For example, the antenna may be configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz (e.g., with less than lOdB of return loss). It should be appreciated that a different degree of return loss may render an antenna suitable for a particular implementation than in the illustrated example.

[0203] FIG. 9A is a top view of a first example antenna-on-interposer configuration 900a including an array of pixels including conductive material patterned on an interposer that may be included in an integrated circuit module, according to some embodiments. FIG. 9B is a top view of a second example antenna-on-interposer configuration 900b including an array of pixels patterned on an interposer, in which some pixels include conductive material and some pixels do not include the conductive material, that may be included in an integrated circuit module, according to some embodiments.

[0204] In some embodiments, the antennas-on-interposer shown in FIGs. 9A and 9B may be included in the integrated circuit module of any of FIGs. 1-6, and / or in the manner described herein in connection with FIGs. 7A-8. For example, the interposer 904 shown in FIGs. 9A and 9B may implement the second interposer of the integrated circuit module in some embodiments.

[0205] In some embodiments, an antenna-on-interposer configuration may include a feed and an array of pixels. For example, as shown in FIGs. 9A and 9B, the illustrated antennas-on- interposer include a feed 906 and an array of pixels 910a, 910b. In the example of FIG. 9A, each pixel 910a in the array 902a includes conductive material, whereas in the example of FIG. 9B, the array 902b includes some pixels 910b including conductive material and some pixels 912 that do not include the conductive material. For instance, in the example of FIG. 9A, the array of pixels may be entirely filled with conductive material, whereas in the Draper Ref.: CSDL.7359. WO

[0206] WGS Ref: C1756.70049WO00 example of FIG. 9B, some of the pixels 910b that include conductive material are separated by pixels 912 that do not include the conductive material.

[0207] In some embodiments, some pixels of the array may include conductive material and other pixels of the array may include voids in the conductive plating. For example, in FIG. 9B, the pixels 910b including conductive material may include conductive plating fabricated on the interposer 904, and the pixels 912 that do not include the conductive material may include voids in the conductive plating. For instance, the antenna may be fabricated by selectively plating the pixels 910b shown including the conductive material, and / or by selectively etching conductive plating from the pixels 912 shown with voids in the conductive material (e.g., after plating the entire array such as shown in FIG. 9A).

[0208] In some embodiments, pixels of the array 902b including conductive material may be aperiodic within the array of pixels. For example, as shown in FIG. 9B, the pixels 910b shown including conductive material appear sporadically throughout the array as opposed to regularly. For instance, the pixels 910b including conductive materials may be implemented based on an antenna pixelization algorithm (e.g., optimization algorithm), such as may be executed to obtain a pixelated pattern with favorable radiation characteristics.

[0209] While a rectangular array is shown in FIGs. 9 A and 9B, it should be appreciated that other arrays are contemplated within the scope of the present disclosure.

[0210] FIG. 10A is a side view of a cross-section of a first example antenna-on-interposer configuration 1000, according to some embodiments. FIG. 10B is a top view of the first example antenna-on-interposer configuration 1000 of FIG. 10A, according to some embodiments. FIG. 10C is a bottom view of the first example antenna-on-interposer configuration 1000 of FIG. 10 A, according to some embodiments. FIG. 10D is a top view of an antenna-on-interposer configuration 1000’ fabricated according to the first example configuration 1000 of FIG. 10A, according to some embodiments. The cross-section of antenna-on-interposer configuration 1000 shown in FIG. 10A is identified as CS in FIGs. 10B-10C.

[0211] In some embodiments, antenna-on-interposer configurations 1000, 1000’ may be configured as described herein including in connection with FIGs. 7A-9B. For example, antenna-on-interposer configuration 1000 as shown in FIGs. 10A-10C and / or antenna-on- interposer configuration 1000’ as shown in FIG. 10D may be included in an integrated circuit module as described herein.

[0212] In some embodiments, antenna-on-interposer configuration 1000 may include a patch antenna 1002 and a ground conductor 1008. For example, in FIG. 10A, the patch antenna Draper Ref.: CSDL.7359. WO

[0213] WGS Ref: C1756.70049WO00

[0214] 1002 is on a first insulative layer 1003 on a first surface of the interposer 1004, and the ground conductor 1008 is on a second insulative layer 1003 on a second surface of the interposer 1004. In some embodiments, patch antenna 1002 may be configured to be fed at an edge. For example, as shown in FIG. 10B patch antenna 1002 is coupled to a feed 1006 terminating at one edge of the first surface. For instance, patch antenna 1002 may be fed by wire-bonding to the feed 1006, or by a conductive trace running on an outer perimeter of interposer 1004 proximate the edge (e.g., with clearance from the ground conductor 1008 as shown at the edge in FIG. 10C).

[0215] As shown in FIG. 10D, antenna-on-interposer configuration 1000’ may include further patterning in patch antenna 1002’ not shown in FIG. 10B. For example, in FIG. 10D, patch antenna 1002’ further includes slots between feed 1006’ and portions of patch antenna 1002’, and further includes slots at two edges that are not opposite feed 1006’.

[0216] In some embodiments, antenna-on-interposer configuration 1000, 1000’ may include an interposer having a height between 250 microns and 1 millimeter (mm). For example, in FIG. 10A, interposer 1004 may have a height between 250 microns and 750 microns, and / or between 400 microns and 600 microns. In some embodiments, interposer 1004 may be a semiconductor interposer, such as a silicon interposer.

[0217] In some embodiments, conductive and insulative layers of antenna-on-interposer configuration 1000, 1000’ may be less than 10 microns thick, such as less than 5 microns thick, and / or between 1-3 microns thick. In some embodiments, patch antennas 1002, 1002’ and / or ground conductors 1008 (not shown in FIG. 10D) may include aluminum. In some embodiments, insulative layers 1003 may include an oxide layer such as silicon oxide.

[0218] FIG. 11A is a side view of a cross-section of a second example antenna-on-interposer configuration 1100, according to some embodiments. FIG. 1 IB is a top view of the second example antenna-on-interposer configuration 1100 of FIG. 11 A, according to some embodiments. FIG. 11C is a bottom view of the second example antenna-on-interposer configuration 1100 of FIG. 11 A, according to some embodiments. FIG. 1 ID is a top view of an antenna-on-interposer configuration 1100’ fabricated according to the second example configuration 1100 of FIG. 11 A, according to some embodiments.

[0219] In some embodiments, antenna-on-interposer configurations 1100, 1100’ may be configured as described herein including in connection with FIGs. 10A-10D. For example, as shown in FIGs. 11A-11B, antenna-on-interposer configuration 1100 includes a patch antenna 1102 on an insulative layer 1103 on a first surface of an interposer 1104. Draper Ref.: CSDL.7359. WO

[0220] WGS Ref: C1756.70049WO00

[0221] In some embodiments, antenna-on-interposer configuration 1100 may be configured for capacitive feeding from an underlying structure. For example, as shown in FIG. 11B, antenna-on-interposer configuration 1100 does not include a ground conductor or second insulative layer as in antenna-on-interposer configuration 1000. For instance, patch antenna 1102 may be configured to capacitively couple to a feed from an underlying structure, such as a feed line provided on an upper conductive layer of a semiconductor die within an integrated circuit module. In some embodiments, the feed line may be surrounded by ground conductive material to contribute to operation of patch antenna 1102.

[0222] As described herein for antenna-on-interposer configuration 1000’, antenna-on- interposer configuration 1100’ may include further patterning in patch antenna 1102’ not shown in FIG. 11B. For example, in FIG. 11D, patch antenna 1102’ further includes slots at two opposite edges.

[0223] FIG. 12A is a side view of a cross-section of a third example antenna-on-interposer configuration 1200, according to some embodiments. FIG. 12B is a top view of the third example antenna-on-interposer configuration 1200 of FIG. 12A, according to some embodiments. FIG. 12C is a bottom view of the third example antenna-on-interposer configuration 1200 of FIG. 12 A, according to some embodiments. FIG. 12D is a top view of an antenna-on-interposer configuration 1200’ fabricated according to the third example configuration 1200 of FIG. 12 A, according to some embodiments.

[0224] In some embodiments, antenna-on-interposer configurations 1200, 1200’ may be configured as described herein including in connection with FIGs. 10A-10D. For example, a shown in FIGs. 12A-12B, antenna-on-interposer configuration 1200 includes a patch antenna 1202 on a first insulative layer 1203 on a first surface of an interposer 1204 and a ground conductor 1208 on a second insulative layer 1203 of a second surface of the interposer 1204.

[0225] In some embodiments, patch antenna 1202 may be configured to be fed at an edge, such as described herein for patch antenna 1002. In FIG. 12B, feed 1206 is located proximate a corner of patch antenna 1202. For instance, as shown in FIG. 12D, when fabricated as antenna-on-interposer configuration 1200’, slots between feed 1206’ and patch antenna 1202’ as in FIG. 10D may be omitted.

[0226] FIG. 13A is a side view of a cross-section of a fourth example antenna-on-interposer configuration 1300, according to some embodiments. FIG. 13B is a top view of the fourth example antenna-on-interposer configuration 1300 of FIG. 13A, according to some embodiments. FIG. 13C is a bottom view of the fourth example antenna-on-interposer configuration 1300 of FIG. 13A, according to some embodiments. FIG. 13D is a top view of Draper Ref.: CSDL.7359. WO

[0227] WGS Ref: C1756.70049WO00 an antenna-on-interposer configuration 1300’ fabricated according to the fourth example configuration 1300 of FIG. 13A, according to some embodiments.

[0228] In some embodiments, antenna-on-interposer configurations 1300, 1300’ may be configured as described herein including in connection with FIGs. 10A-10D. For example, a shown in FIGs. 13A-13B, antenna-on-interposer configuration 1300 includes a patch antenna 1302 on a first insulative layer 1303 on a first surface of an interposer 1304 and a ground conductor 1308 on a second insulative layer 1303 of a second surface of the interposer 1304. In some embodiments, conductive materials of patch antenna 1302 and ground conductor 1308 may be different. For example, patch antenna 1302 may include aluminum and ground conductor 1308 may include copper.

[0229] In some embodiments, patch antenna 1302 may include feed 1306 configured to be fed from an edge, such as described herein in connection with FIGs. 10A-103D. In some embodiments, when fabricated, antenna-on-interposer configuration 1300’ may be configured as described herein for antenna-on-interposer configuration 1300, such as including slots between feed 1306’ and patch antenna 1302’.

[0230] In some embodiments, antenna-on-interposer configuration 1300, 1300’ may include an interposer having a height between 50 microns and 250 microns. For example, in FIG. 13 A, interposer 1304 may have a height between 50 microns and 150 microns, and / or between 75 microns and 125 microns. In some embodiments, interposer 1304 may be a semiconductor interposer, such as a silicon interposer.

[0231] FIG. 14A is a side view of a cross-section of a fifth example antenna-on-interposer configuration 1400, according to some embodiments. FIG. 14B is a top view of the fifth example antenna-on-interposer configuration 1400 of FIG. 14A, according to some embodiments. FIG. 14C is a bottom view of the fifth example antenna-on-interposer configuration 1400 of FIG. 14A, according to some embodiments. FIG. 14D is a top view of an antenna-on-interposer configuration 1400’ fabricated according to the fifth example configuration 1400 of FIG. 14A, according to some embodiments.

[0232] In some embodiments, antenna-on-interposer configurations 1400, 1400’ may be configured as described herein including in connection with FIGs. 13A-13D. For example, as shown in FIGs. 14A-14B, antenna-on-interposer configuration 1400 includes a patch antenna 1402 on a first insulative layer 1403 on a first surface of an interposer 1404 and a ground conductor 1408 on a second insulative layer 1403 of a second surface of the interposer 1404. In some embodiments, conductive materials of patch antenna 1402 and ground conductor 1408 may be the same, such as each including copper. Draper Ref.: CSDL.7359. WO

[0233] WGS Ref: C1756.70049WO00

[0234] In some embodiments, patch antenna 1402 may be configured to be fed by a via (V) 1405. For example, as shown in FIGs. 14A-14C patch antenna 1402 is coupled to via 1405 extending between the first and second surfaces of the interposer 1404. For instance, via 1405 may be configured to couple to a signal conductor of an underlying structure, such as a semiconductor die when packaged in an integrated circuit module. As shown in FIG. 14C, ground conductor 1408 may include clearance around via 1405.

[0235] As shown in FIG. 14D, when fabricated, antenna-on-interposer configuration 1400’ may include via 1405’ at a location that is off-center from patch antenna 1402’.

[0236] FIG. 15A is a side view of a cross-section of a sixth example antenna-on-interposer configuration 1500, according to some embodiments. FIG. 15B is a top view of the sixth example antenna-on-interposer configuration 1500 of FIG. 15A, according to some embodiments. FIG. 15C is a bottom view of the sixth example antenna-on-interposer configuration 1500 of FIG. 15A, according to some embodiments. FIG. 15D is a top view of an antenna-on-interposer configuration 1500’ fabricated according to the sixth example configuration 1500 of FIG. 15A, according to some embodiments.

[0237] In some embodiments, antenna-on-interposer configurations 1500, 1500’ may be configured as described herein including in connection with FIGs. 13A-13D. For example, as shown in FIGs. 15A-15B, antenna-on-interposer configuration 1500 includes a patch antenna 1502 on a first insulative layer 1503 on a first surface of an interposer 1504.

[0238] In some embodiments, antenna-on-interposer configuration 1500 may be configured for capacitive feeding from an underlying structure, such as described herein in connection with FIGs. 11A-11D. For example, as shown in FIG. 15B, antenna-on-interposer configuration 1500 does not include a ground conductor or second insulative layer as in antenna-on-interposer configuration 1300.

[0239] As shown in FIG. 15D, when fabricated, antenna-on-interposer configuration 1500’ may include slots on opposite sides of patch antenna 1502’.

[0240] FIG. 16A is a side view of a cross-section of a seventh example antenna-on-interposer configuration 1600, according to some embodiments. FIG. 16B is a top view of the seventh example antenna-on-interposer configuration 1600 of FIG. 16A, according to some embodiments. FIG. 16C is a bottom view of the seventh example antenna-on-interposer configuration 1600 of FIG. 16 A, according to some embodiments. FIG. 16D is a top view of an antenna-on-interposer configuration 1600’ fabricated according to the seventh example configuration 1600 of FIG. 16 A, according to some embodiments. Draper Ref.: CSDL.7359. WO

[0241] WGS Ref: C1756.70049WO00

[0242] In some embodiments, antenna-on-interposer configurations 1600, 1600’ may be configured as described herein including in connection with FIGs. 13A-13D. For example, as shown in FIGs. 16A-16B, antenna-on-interposer configuration 1600 includes a patch antenna 1602 on a first insulative layer 1603 on a first surface of an interposer 1604 and a ground conductor 1608 on a second insulative layer 1603 of a second surface of the interposer 1604. As shown in FIG. 16B, patch antenna 1602 may include a pixelated conductive pattern, such as described herein including in connection with FIG. 7B.

[0243] In some embodiments, patch antenna 1602 may be configured to be fed by a via 1605, such as described herein including in connection with FIGs. 14A-14D. For example, as shown in FIGs. 16A-16C patch antenna 1602 is coupled to via 1605 extending between the first and second surfaces of the interposer 1604. For instance, via 1605 may be configured to couple to a signal conductor of an underlying structure, such as a semiconductor die when packaged in an integrated circuit module. As shown in FIG. 16C, ground conductor 1608 may include clearance around via 1605. As shown in FIG. 16D, when fabricated, via 1605’ may be surrounded by conductive pixels of patch antenna 1602’.

[0244] FIG. 17 is a perspective view of the antenna-on-interposer configuration 1300’ of FIG. 13D on a coin to demonstrate scale, according to some embodiments. FIG. 18 is a perspective view of the antenna-on-interposer configuration 1600’ of FIG. 16D on a coin to demonstrate scale, according to some embodiments. In the illustrated examples of FIGs. 17- 18, the antennas-on-interposers may have dimensions of about 5 square millimeters (mm2) by about 110 microns. The illustrated coin is a United States one-cent piece having a diameter of about 19.05 mm and thickness of about 1.52 mm.

[0245] FIG. 19 is a perspective view of a substrate 1900 with five antennas-on-interposer 1902 mounted thereon, according to some embodiments. In some embodiments, antennas-on- interposer 1902 may be configured as described herein for antenna-on-interposer configuration 1100’. As shown in FIG. 19, each antenna-on-interposer 1902 is coupled to an electrical connector 1904, which may be configured to feed the antenna-on-interposer 1902 (e.g., for measurement purposes). In other embodiments, circuitry on substrate 1900 and / or within an integrated circuit module mounted on substrate 1900 and including antenna-on- interposer 1902 may be configured to feed antenna-on-interposer 1902 as described herein.

[0246] FIG. 20 is a graph of measured return loss (Sil) vs. frequency for four variants of antennas-on-interposer 1902 of FIG. 19, according to some embodiments.

[0247] For the measurements of FIG. 20, four variants of antennas-on-interposer 1902 were fabricated using different processes. Five of each variant were fabricated and mounted on Draper Ref.: CSDL.7359. WO

[0248] WGS Ref: C1756.70049WO00 respective substrates 1900. To conduct the measurements, the electrical connectors of the substrates were fed individually, with the connectors not being fed for a given measurement terminating in matched loads. The patch antennas of the antennas-on-interposers were fed capacitively by conductive traces on the substrate 1900 underlying the patch antennas, such as described herein including in connection with FIGs. 11A-11D.

[0249] To fabricate the first variant, conductive material was deposited on the interposer using plasma-enhanced chemical vapor deposition (PECVD) and some conductive material was wet etched to form the final conductive patterns. Measurements (1, 1), (1, 2), (1, 3), (1,

[0250] 4), and (1, 5) correspond to the five antennas-on-interposer 1902 of the first variant on the same substrate.

[0251] To fabricate the second variant, conductive material was deposited on the interposer using (PECVD) and some conductive material was lifted off using an underlying sacrificial layer to form the final conductive patterns. Measurements (2, 1), (2, 2), (2, 3), (2, 4), and (2,

[0252] 5) correspond to the five antennas-on-interposer 1902 of the second variant on the same substrate.

[0253] To fabricate the third variant, conductive material was deposited on the interposer using thermal oxidation deposition and some conductive material was lifted off using an underlying sacrificial layer to form the final conductive patterns. Measurements (3, 1), (3, 2), (3, 3), (3, 4), and (3, 5) correspond to the five antennas-on-interposer 1902 of the third variant on the same substrate.

[0254] To fabricate the fourth variant, conductive material was deposited on the interposer using thermal oxidation deposition and some conductive material was wet etched to form the final conductive patterns. Measurements (4, 1), (4, 2), (4, 3), (4, 4), and (4, 5) correspond to the five antennas-on-interposer 1902 of the fourth variant on the same substrate.

[0255] FIG. 21 is a graph of measured and simulated return loss for the antennas-on- interposer of the first variants of FIG. 20, according to some embodiments.

[0256] Various inventive concepts may be embodied as one or more processes, of which examples have been provided. The acts performed as part of each process may be ordered in any suitable way. Thus, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0257] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily Draper Ref.: CSDL.7359. WO

[0258] WGS Ref: C1756.70049WO00 including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, for example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements) ;etc.

[0259] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0260] Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed. Such terms are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term). The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” “having,” “containing”, “involving”, and variations thereof, is meant to encompass the items listed thereafter and additional items.

[0261] Having described several embodiments of the techniques described herein in detail, various modifications, and improvements will readily occur to those skilled in the art. Such modifications and improvements are intended to be within the spirit and scope of the Draper Ref.: CSDL.7359. WO

[0262] WGS Ref: C1756.70049WO00 disclosure. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The techniques are limited only as defined by the following claims and the equivalents thereto.

Claims

Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO00CLAIMSWhat is claimed is:

1. An integrated circuit module, comprising: a first interposer comprising a mounting interface configured for mounting to a substrate external to the integrated circuit module; a semiconductor die bonded to the first interposer and comprising communication circuitry fabricated thereon; and a second interposer bonded to the semiconductor die and comprising an antenna fabricated thereon.

2. The integrated circuit module of claim 1, wherein the first interposer is selected from a group consisting of a first semiconductor interposer and a first glass interposer.

3. The integrated circuit module of claim 1 or 2, wherein the second interposer is selected from a group consisting of a second semiconductor interposer and a second glass interposer.

4. The integrated circuit module of any one of claims 1 to 3, wherein the communication circuitry comprises at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic.

5. The integrated circuit module of any one of claims 1 to 4, wherein the semiconductor die is hybrid-bonded to the first interposer and / or to the second interposer.

6. The integrated circuit module of claim 5, wherein the semiconductor die is hybrid- bonded to the first interposer and to the second interposer.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO007. The integrated circuit module of claim 6, wherein the communication circuitry comprises a first circuit component and a second circuit component that is hybrid-bonded to the first circuit component.

8. The integrated circuit module of any one of claims 1 to 7, wherein the first interposer comprises a first via coupling the mounting interface to the semiconductor die.

9. The integrated circuit module of claim 8, wherein the first via comprises a first via material selected from a group consisting of: first semiconductor material; and first conductive material.

10. The integrated circuit module of claim 9, wherein the first via material comprises polysilicon.

11. The integrated circuit module of claim 9, wherein the first via material comprises copper and / or aluminum.

12. The integrated circuit module of any one of claims 1 to 11, wherein the second interposer comprises a second via coupling the semiconductor die to the antenna.

13. The integrated circuit module of claim 12, wherein the second via comprises a second via material selected from a group consisting of: second semiconductor material; and second conductive material.

14. The integrated circuit module of claim 13, wherein the second via material comprises polysilicon.

15. The integrated circuit module of claim 13, wherein the second via material comprises copper and / or aluminum.

16. The integrated circuit module of any one of claims 1 to 15, wherein the antenna comprises a radiating element selected from a group consisting of a patch and a dipole.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO0017. The integrated circuit module of any one of claims 1 to 16, wherein the antenna is configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz.

18. An integrated circuit module comprising : a first interposer configured to route signals to and / or from a substrate external to the integrated circuit module; a semiconductor die comprising communication circuitry fabricated thereon, the communication circuitry configured to obtain signals from and / or provide signals to the first interposer; and a second interposer comprising an antenna fabricated thereon, the antenna configured to transmit signals obtained from the communication circuitry and / or provide received signals to the communication circuitry.

19. The integrated circuit module of claim 18, wherein the semiconductor die is disposed between the first interposer and the second interposer.

20. The integrated circuit module of claim 18 or 19, wherein the communication circuitry comprises an amplifier configured to obtain signals from and / or provide signals to the antenna.

21. The integrated circuit module of any one of claims 18 to 20, wherein the communication circuitry comprises a modulator configured to up-convert signals for providing to the antenna and / or a demodulator configured to down-convert signals obtained from the antenna.

22. The integrated circuit module of any one of claims 18 to 21, wherein the communication circuitry comprises a logic circuit configured to perform at least one logic operation selected from a group consisting of: generating a signal for transmitting via the antenna; and processing a signal received via the antenna.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO0023. The integrated circuit module of any one of claims 18 to 22, wherein the communication circuitry comprises a filter distributed over multiple layers of the semiconductor die.

24. The integrated circuit module of any one of claims 18 to 23, wherein the first interposer comprises a first via configured to route signals between the substrate and the semiconductor die.

25. The integrated circuit module of claim 24, wherein the first via comprises a first via material selected from a group consisting of: first semiconductor material; and first conductive material.

26. The integrated circuit module of claim 25, wherein the first via material comprises polysilicon.

27. The integrated circuit module of claim 25, wherein the first via material comprises copper and / or aluminum.

28. The integrated circuit module of any one of claims 18 to 27, wherein the second interposer comprises a second via configured to couple signals between the semiconductor die and the antenna.

29. The integrated circuit module of claim 28, wherein the second via comprises a second via material selected from a group consisting of: second semiconductor material; and second conductive material.

30. The integrated circuit module of claim 29, wherein the second via material comprises polysilicon.

31. The integrated circuit module of claim 29, wherein the second via material comprises copper and / or aluminum.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO0032. The integrated circuit module of any one of claims 18 to 31, wherein the antenna comprises a radiating element selected from a group consisting of a patch and a dipole.

33. The integrated circuit module of any one of claims 18 to 32, wherein the antenna is configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz.

34. An integrated circuit module comprising: a semiconductor die comprising communication circuitry fabricated thereon; and an interposer comprising an antenna fabricated thereon, the antenna being configured to transmit signals obtained from the communication circuitry and / or provide received signals to the communication circuitry, and the antenna comprising: a feed; and an array of pixels, comprising: a plurality of first pixels that comprise first conductive material coupled to the feed; and a plurality of second pixels that do not comprise the first conductive material.

35. The integrated circuit module of claim 34, wherein the plurality of first pixels comprise conductive plating and the plurality of second pixels comprise voids in the conductive plating.

36. The integrated circuit module of claim 34 or 35, wherein the plurality of first pixels are aperiodic within the array of pixels.

37. The integrated circuit module of any one of claims 34 to 36, further comprising: a first interposer, comprising a mounting interface, the mounting interface configured for mounting to a substrate external to the integrated circuit module, the first interposer being configured to route signals between the communication circuitry and the substrate, wherein the interposer is a second interposer, and wherein the semiconductor die is disposed between the first interposer and the second interposer.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO0038. The integrated circuit module of any one of claims 34 to 37, wherein the interposer is selected from a group consisting of a semiconductor interposer and a glass interposer.

39. The integrated circuit module of any one of claims 34 to 38, wherein the communication circuitry comprises at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic.

40. The integrated circuit module of any one of claims 34 to 39, wherein the semiconductor die is hybrid-bonded to the interposer.

41. The integrated circuit module of any one of claims 34 to 40, wherein the interposer comprises a via coupling the semiconductor die to the feed of the antenna.

42. The integrated circuit module of claim 41, wherein the via comprises a via material selected from a group consisting of: semiconductor material; and second conductive material.

43. The integrated circuit module of claim 42, wherein the via material comprises polysilicon.

44. The integrated circuit module of claim 43, wherein the via material comprises copper and / or aluminum.

45. The integrated circuit module of any one of claims 34 to 44, wherein the antenna comprises a radiating element selected from a group consisting of a patch and a dipole.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO0046. The integrated circuit module of any one of claims 34 to 45, wherein the antenna is configured to transmit and / or receive signals in a frequency band contained with a range from 12 GHz to 77 GHz.

47. A method of manufacturing an integrated circuit module, the method comprising: fabricating a mounting interface onto a first interposer of the integrated circuit module; bonding the first interposer to a semiconductor die of the integrated circuit module, the semiconductor die comprising communication circuitry fabricated thereon; fabricating an antenna on a second interposer of the integrated circuit module; and bonding the semiconductor die to the second interposer.

48. The method of claim 47, further comprising fabricating the communication circuitry onto the semiconductor die.

49. The method of claim 47 or 48, wherein the first interposer is selected from a group consisting of a first semiconductor interposer and a first glass interposer.

50. The method of any one of claims 47 to 49, wherein the second interposer is selected from a group consisting of a second semiconductor interposer and a second glass interposer.

51. The method of any one of claims 47 to 50, wherein the communication circuitry comprises at least one circuit element selected from a group consisting of: a transmit amplifier; a receive amplifier; a modulator; a demodulator; a filter; signal generator logic; and signal processing logic.

52. The method of any one of claims 47 to 51, wherein bonding the first interposer to the semiconductor die and / or bonding the semiconductor die to the second interposer comprises hybrid-bonding.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO0053. The method of claim 51, wherein bonding the first interposer to the semiconductor die and bonding the semiconductor die to the second interposer comprise hybrid-bonding.

54. The method of any one of claims 47 to 52, further comprising forming a first via in the first interposer coupled to the mounting interface, wherein bonding the first interposer to the semiconductor die couples the first via to the semiconductor die.

55. The method of claim 54, wherein the first via comprises a first via material selected from a group consisting of: first semiconductor material; and first conductive material.

56. The method of claim 55, wherein the first via material comprises polysilicon.

57. The method of claim 55, wherein the first via material comprises copper and / or aluminum.

58. The method of any one of claims 47 to 57, further comprising forming a second via in the second interposer coupled to the antenna, wherein bonding the semiconductor die to the second interposer couples the semiconductor die to the antenna.

59. The method of claim 58, wherein the second via comprises a second via material selected from a group consisting of: second semiconductor material; and second conductive material.

60. The method of claim 59, wherein the second via material comprises polysilicon.

61. The method of claim 59, wherein the second via material comprises copper and / or aluminum.

62. The method of any one of claims 47 to 61, further comprising bonding a first circuit component of the communication circuitry to a second circuit component of the communication circuitry.Draper Ref.: CSDL.7359. WOWGS Ref: C1756.70049WO0063. The method of any one of claims 47 to 62, wherein the antenna comprises a radiating element selected from a group consisting of a patch and a dipole.

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